JP5387493B2 - Signal processing apparatus and radio clock - Google Patents

Description

  The present invention relates to a signal processing device that converts a detection signal of a standard radio wave into digital waveform data, and a radio-controlled timepiece that includes this signal processing device.

  In a receiving device that receives a standard radio wave, it is common to detect a received signal and then shape the waveform of the detected signal into a binary signal of a high level and a low level and output it. Then, the microcomputer performs time measurement of the high level period and the low level period from the binary signal, and performs pulse determination and decoding of the time code included in the detection signal.

  As a prior art related to the present invention, Patent Document 1 discloses a technique for changing an upper reference voltage and a lower reference voltage of an AD converter in a video camera so as to be proportional to an output amplitude of an image sensor. ing.

Japanese Patent Laid-Open No. 08-181886

  The standard radio wave may have a very weak electric field strength depending on the reception environment, and a lot of external noise may be mixed in the detection signal. Therefore, if the time code is decoded only by measuring the high and low times of the binarized detection signal as described above, there is a problem that accurate decoding cannot be performed when the reception environment is not good. there were.

  In addition, in order to accurately decode the time code in an environment where the signal strength is weak and a lot of external noise is mixed, the detection signal before waveform shaping can be sampled into digital data to eliminate the influence of external noise. It is considered effective to perform pulse determination by various data processing.

  However, when the reception environment is poor, the amplitude of the detection signal also varies, and the bias point of the detection signal also varies due to individual differences in the reception circuit. Therefore, in order to be able to execute quantization that divides the signal amplitude by at least a predetermined number of bits, regardless of the range of the detection signal level, an AD converter having a high resolution and a wide dynamic range. Must be used. Further, in order to be able to distinguish a level change due to noise mixing from a signal original level change, the sampling rate needs to be relatively high.

  Since the clock microcomputer needs to have a low processing capacity in most periods such as during normal time display, a microcomputer having a relatively low processing capacity is generally applied. In addition, in a wristwatch or the like, a microcomputer having a low processing capability is generally applied to a microcomputer for a watch because of a demand for very low power consumption. Furthermore, since the number of bits of the memory address is reduced, the capacity of a RAM (Random Access Memory) and a ROM (Read Only Memory) can be reduced.

  Therefore, if the detection signal is converted into data at a relatively high sampling rate using the AD converter having a high resolution and a wide dynamic range as described above, the amount of waveform data becomes very large, and the data processing load is excessive. The problem is that the processing power required for the watch microcomputer and the power consumption required for the watch are not satisfied, such as the power consumption of the AD conversion itself increases. Occurs.

  An object of the present invention is to perform a decoding process with a small memory capacity and a small load by a signal processing apparatus capable of efficiently converting a detection signal of a standard radio wave into a data and efficient data conversion, and a reception environment is compared. It is an object of the present invention to provide a radio timepiece that can accurately decode a time code even when it is not good.

In order to achieve the above object, the present invention provides:
In a signal processing device that inputs a detection signal of a standard radio wave and converts it into digital waveform data,
A comparison voltage generation unit that generates a plurality of stages of comparison voltages that vary according to the signal level and amplitude of the detection signal;
A comparator for sequentially comparing the signal level of the detection signal and the comparison voltages of the plurality of stages;
A calculation means for summing up a predetermined number of comparison results continuous with each comparison result among a series of comparison results obtained by the comparison of the comparison unit, and multi-value each,
A signal processing apparatus.

  According to the present invention, the comparison voltage is changed in accordance with the signal level and amplitude of the detection signal, and a predetermined number of successive comparison results obtained by successive comparison with a plurality of comparison voltages are added to obtain waveform data. Therefore, it is possible to compare the effective signal level with a comparative voltage with a small number of stages with respect to the detection signal of the standard radio wave in which the amplitude and the bias point vary, and furthermore, one multi-value data is obtained for each comparison period. It is done. Therefore, it is possible to efficiently acquire waveform data useful for time code decoding.

It is a block diagram which shows the whole structure of the radio timepiece of embodiment of this invention. It is a circuit diagram which shows the detail of the digital converter of FIG. It is a time chart showing the operation | movement of each part of a digital converter, and the change of a signal. It is a time chart showing the calculation operation | movement which calculates | requires multi-value data from the reproduced value of a digital converter. It is a graph explaining the characteristic of multiple types of waveform data.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing the overall configuration of a radio timepiece according to an embodiment of the present invention.

  The radio timepiece 1 of this embodiment is a timepiece having a function of acquiring time information by receiving a standard radio wave and decoding a time code and automatically correcting the timekeeping time, an antenna 11 for receiving the standard radio wave, A receiving circuit 12 that extracts and detects a signal of a desired wave from the received signal, a digital converter 17 that performs signal processing of the previous stage for converting the detected signal into digital waveform data, and overall control of the clock A CPU (Central Processing Unit) 18 that functions as a calculation means for performing calculation processing for generating waveform data of detection signals and the like, a RAM (Random Access Memory) 19 for providing a working memory area to the CPU 18, A ROM (Read Only Memory) 20 storing a control program and control data executed by the CPU 18, a clock circuit (clocking means) 21 for clocking time, and a clock circuit 21 An oscillation circuit 22 for supplying a reference clock CLK0 to digital converter 17, and a display unit (time display means) 23 for displaying the time. Among the above configurations, the digital converter 17 and the CPU 18 constitute a signal processing device that converts the detection signal into digital waveform data.

  The receiving circuit 12 is not particularly limited, and for example, an amplifier 13 that amplifies the received signal, a filter 14 that extracts a desired wave signal from the received signal, and an amplitude-modulated signal are detected. A detector (detection means) 15 and an AGC (automatic gain control) circuit 16 that adjusts the amplification factor of the amplifier 13 so that the amplitude of the detected signal does not vary greatly are provided.

  FIG. 2 is a circuit diagram showing details of the digital converter 17.

  The digital converter 17 is a circuit that sequentially compares the signal level of the detection signal with a plurality of comparison voltages and supplies a signal Sg10 representing the comparison result to the CPU 18. The digital converter 17 includes a low-pass filter (resistor R1 and capacitor C1) 170 provided in the input stage, a peak hold circuit 171 as a first voltage holding unit that holds a maximum level voltage of the detection signal Sg2, and a detection signal. A bottom hold circuit 172 as a second voltage holding unit that holds a minimum level voltage of Sg2, a voltage dividing circuit (voltage dividing resistors R2 to R5) that divides both holding voltages Sg4 and Sg5, and a divided voltage Changeover switches S1 to S3 for selectively taking out one of Sg6 to Sg8 as a comparison voltage Sg9, a timing controller 173 as a switch control unit for turning these changeover switches S1 to S3 on and off at an appropriate timing, Comparator C as a comparison unit that compares the signal level of the detection signal Sg2 with the comparison voltage Sg9 The voltage follower 174 composed of the operational amplifier A1 that supplies the voltage of the detection signal Sg2 to the comparator Cmp1 while preventing the buffer between the circuits and the comparison voltage Sg6 to Sg8 to the comparator Cmp1 while preventing the buffer between the circuits. A voltage follower 175 including an operational amplifier A4 to be supplied is provided. Among the above-described configurations, the peak hold circuit 171, the bottom hold circuit 172, and the voltage dividing circuit constitute a comparison voltage generation unit.

  The peak hold circuit 171 includes a capacitor C2 that holds a voltage, and a diode D1 that applies a voltage to the capacitor C2 only when the voltage of the detection signal Sg2 is high and prevents a reverse flow from the capacitor C2 when the voltage of the detection signal Sg2 is low. The operational amplifier A2 supplies electric charge to the capacitor C2 when the holding voltage Sg4 of the capacitor C2 is negatively fed back and the voltage of the detection signal Sg2 is high, and the buffer B1 outputs the holding voltage Sg4 of the capacitor C2 to the voltage dividing circuit. Is done.

  The charge stored in the capacitor C2 is configured to leak little by little to the input terminal of the buffer B1 and the operational amplifier A2, etc., so that when the voltage of the detection signal Sg2 decreases, the holding voltage Sg4 of the peak hold circuit 171 It is gradually decreasing. Note that the holding voltage may be controlled to decrease with a predetermined time constant by connecting a resistor in parallel with the capacitor C2.

  The bottom hold circuit 172 includes a capacitor C3 that holds a voltage, and a diode D2 that applies a voltage to the capacitor C3 only when the voltage of the detection signal Sg2 is low and prevents backflow to the capacitor C3 when the voltage of the detection signal Sg2 is high. The operational amplifier A3 discharges charges from the capacitor C3 when the holding voltage Sg5 of the capacitor C3 is negatively fed back and the voltage of the detection signal Sg2 is low, and the buffer B2 outputs the holding voltage Sg5 of the capacitor C3 to the voltage dividing circuit. Is done.

  The electric charge stored in the capacitor C3 is configured to leak little by little to the input terminal of the buffer B2 and the operational amplifier A3. Thereby, when the voltage of the detection signal Sg2 rises, the holding voltage Sg5 of the bottom hold circuit 172 Is gradually rising. The holding voltage may be controlled to increase with a predetermined time constant by connecting a resistor in parallel with the capacitor C3.

  The timing controller 173 generates switch switching signals SP1 to SP3 that are switched at a predetermined cycle based on the reference clock CLK0 of the oscillation circuit 22, and also inputs the comparison result input timing to the CPU 18 for each comparison process of the comparator Cmp1. An operation clock CLK1 for notification is generated.

  Next, the radio timepiece 1 having the above-described configuration and the digital conversion processing operation of the detection signal will be described.

  FIG. 3 is a time chart showing the operation of each part of the digital converter 17 and changes in the signal, and FIG. 4 is a time chart showing the calculation operation for obtaining the multivalued data from the reproduction value of the digital converter 17. The horizontal axes in FIGS. 3 and 4 represent the same time axis.

  As shown in FIGS. 3E and 3F, the detection signal (detection rectification “Sg1”) input to the digital converter 17 passes through the low-pass filter 170 in the input stage, thereby reducing high-frequency noise. In addition, a detection signal (LPF output “Sg2, Sg3”) to which waveform dullness and delay are added is sent to the comparator Cmp1, the peak hold circuit 171 and the bottom hold circuit 172, respectively.

  As shown in the voltage waveform of peak hold “Sg4” in FIG. 3G, the peak hold circuit 171 holds the peak voltage of the detection signal Sg2 that has passed through the low-pass filter 170. Further, when the detection signal Sg2 becomes a low level, the holding voltage Sg4 gradually decreases due to leakage of the holding charge.

  Similarly, as shown in the voltage waveform of the bottom hold “Sg5” in FIG. 3G, the bottom hold circuit 172 holds the bottom voltage of the detection signal Sg2 that has passed through the low-pass filter 170. Further, when the detection signal Sg2 becomes a high level, the holding voltage Sg5 gradually rises due to leakage of the holding charge.

  Therefore, the three-stage comparison voltages Sg6 to Sg8 (shown by thin dotted lines in FIG. 3) obtained by dividing these voltages are voltages obtained by dividing the current (or recent) peak voltage and bottom voltage of the detection signal Sg2 into a plurality of parts. It becomes.

  In the digital converter 17 of this embodiment, the timing controller 173 generates the operation clock CLK1 (FIG. 3 (d)) having the same cycle as the waveform data sampling cycle (for example, 0.02 seconds). Then, switch switching signals SP1 to SP3 (FIGS. 3A to 3C) are generated in synchronization with the operation clock CLK1 to switch the selector switches S1 to S3. Specifically, as shown in FIGS. 3A to 3D, any one of the changeover switches S1 to S3 is turned on during one cycle of the operation clock CLK1, and the three changeover switches S1 to S3 are turned on. It is switched to turn on cyclically.

  As a result, as shown in FIG. 3G, the comparison voltage Sg9 (indicated by the thick solid line in FIG. 3G) sent to one input terminal of the comparator Cmp1 is sequentially switched to three stages of voltages. Then, the comparison voltage Sg9 and the detection signals Sg2 and Sg3 are compared by the comparator Cmp1, and a signal Sg10 (FIG. 3 (h)) representing the comparison result is supplied to the CPU 18 together with the operation clock CLK1.

  The CPU 18 acquires a binary reproduction value (FIG. 4 (i)) by taking in the signal Sg10 representing the comparison result from the digital converter 17 in synchronization with the operation clock CLK1.

  Further, the CPU 18 obtains multi-value waveform data by calculation from these series of reproduction values. There are multiple types of calculation methods as shown below.

  In the first method, as shown in FIG. 4 (j), each of a series of reproduced values (FIG. 4 (i)) is equivalent to one period (in the example of FIG. The continuous reproduction values (for three cycles of the operation clock CLK1) are added together, and this is used as the data value of the waveform data. The values in FIG. 4 (j) are obtained by adding the reproduction value at that time point and the previous and previous reproduction values for each reproduction value to obtain the data value of the waveform data at that time point.

  FIG. 4 (k) shows a curve obtained by converting the multi-value waveform data calculated by the above method into a waveform shape. In addition, curves that continuously represent the waveform shape by broken lines are superimposed. In the first method described above, since three reproduction values are added to form one data value, 2-bit waveform data of “0 to 3” is obtained, and detection is performed using this multi-value waveform data. It can be seen that waveform data according to the waveform of the signal Sg2 is obtained.

  In the second method, as shown in FIG. 4 (l), the multi-value waveform data obtained by the above calculation is subjected to further calculation, and three consecutive pieces of waveform data (for example, the current time and the previous time) And the previous three data values) are added together to obtain a new data value at that time. By this process, multi-value waveform data represented by “0-9” can be acquired.

  In the third method, as shown in FIG. 4 (m), for each of a series of reproduction values (FIG. 4 (i)), a period in which comparison with all comparison voltages is performed is one cycle, and twice that period. The continuous reproduction values for two periods (six periods of the operation clock CLK1 in the example of FIG. 2) are added together, and this is used as the data value of the waveform data. The values shown in FIG. 4 (m) are obtained by adding six consecutive reproduction values ahead from the time point for each reproduction value to obtain the data value of the waveform data at that time point.

  FIG. 4 (n) shows a curve obtained by converting the multi-value waveform data calculated by the third method into a waveform shape. Moreover, the curve which made the waveform shape continuous with the broken line is accumulated and shown. In the third method, since six reproduction values are added to form one data value, waveform data according to the waveform of the detection signal Sg2 is obtained from multi-value waveform data represented by “0 to 6”. I understand that

  In the fourth method, as shown in FIG. 4 (o), the multi-value waveform data obtained by the third method is further subjected to calculation, and 6 pieces of continuous data (for example, the waveform data) 6 consecutive data values ahead from the time point) are summed to obtain a new data value at that time point. By this processing, multi-value waveform data represented by “0 to 36” can be acquired.

  FIG. 5 shows a graph for explaining the characteristics of a plurality of types of waveform data obtained by the plurality of calculation processes.

  In FIG. 5, the dotted line indicates the detection output Sg2 that has passed through the low-pass filter 170, the square plot line indicates the reproduction value of the digital converter 17, the triangular plot line indicates the waveform data obtained by summing the reproduction values for one period (each three), and the white rhombus The plot line is the waveform data obtained by summing up the playback values for two cycles (six each), the black diamond plot line is the waveform data obtained by summing twice for one cycle, and the black circle plot line is summed twice for two cycles. The waveform data is shown with the amplitude normalized to “1”.

  As shown in FIG. 5, the four types of waveform data calculated by the first to fourth methods represent shapes according to the waveform of the detection signal Sg2 (LPF output). For example, in the reproduced value of the digital converter 17, a data value that changes in reverse to the waveform is generated at the rising portion RE1 or the falling portion RE2 of the detection signal Sg2. On the other hand, the four types of waveform data calculated by the first to fourth methods represent changes along the original waveform.

  Furthermore, in the above calculation process, when the total number of reproduction values and the total number of times are small, there are portions in which the waveform data has a small number of bits and changes stepwise. On the other hand, as the total number of reproduction values and the total number of times increase, the waveform data becomes gentle and dull and delayed as compared with the original waveform. Further, if the total number of reproduction values and the total number of reproduction values are increased, the effect of instantaneously removing external noise increases accordingly.

  Therefore, it is possible to calculate waveform data suitable for pulse determination by setting the total number of reproduction values and the total number of times to appropriate values in accordance with the time code pulse determination processing method performed thereafter. Become.

  The CPU 18 performs time code pulse determination processing based on the waveform data. Various methods can be applied to the pulse determination processing method. For example, waveform data of each pulse signal representing a plurality of types of codes constituting a time code is stored in the ROM 20 or the like as template data, and the correlation between the waveform data of the detection signal Sg2 and these template data is calculated, Various methods that can eliminate the influence of external noise, such as performing pulse determination based on the correlation value, can be applied.

  When the pulse determination of the time code is performed, the CPU 18 decodes the time code to acquire time information and the like, and corrects the time data of the time measuring circuit 21 based on this time information. Thereby, the time displayed by the display means 23 is also corrected to be accurate.

  As described above, according to the radio-controlled timepiece 1 and the signal processing device (digital converter 17 and CPU 18) that generates the waveform data of the detection signal of this embodiment, the peak hold circuit 171, the bottom hold circuit 172, and the voltage dividing resistor R2 Through R5, the plurality of stages of comparison voltages Sg6 to Sg8 change according to the signal level and amplitude of the detection signal Sg2. Further, the CPU 18 adds a predetermined number of successive reproduction values, which are the results of the successive comparison using a plurality of stages of comparison voltages Sg6 to Sg8, to form waveform data. Therefore, an effective signal level can be compared with a detection signal of a standard radio wave in which variations in amplitude and bias point occur with a small number of comparison voltages, and one multi-value data is provided for each comparison period. Waveform data can be obtained. That is, it is possible to efficiently acquire waveform data useful for time code pulse determination and decoding.

  Further, according to the radio timepiece 1 and the signal processing device (digital converter 17 and CPU 18) of this embodiment, the holding voltage Sg4 is gradually increased when the peak voltage of the detection signal Sg2 is held and the signal level of the detection signal Sg2 is low. A peak hold circuit 171 for reducing the detection signal Sg2, a bottom hold circuit 172 for holding the bottom voltage of the detection signal Sg2 and gradually increasing the hold voltage Sg5 when the signal level of the detection signal Sg2 is high, and these hold voltages Sg4, Sg5 Since the comparison voltages Sg6 to Sg8 are generated by the voltage dividing resistors R2 to R5 for dividing the signal, even when the peak voltage and the bottom voltage of the detection signal Sg2 change gently, the change can be handled. Thus, appropriate comparison voltages Sg6 to Sg8 can be generated.

  Further, in the successive comparison between the plurality of stages of comparison voltages Sg6 to Sg8 and the signal level of the detection signal Sg2, the comparison voltages Sg6 to Sg8 are sent to the comparator Cmp1 one by one under the control of the changeover switches S1 to S3 and the timing controller 173. Is easily realized.

  Further, according to the radio-controlled timepiece 1 and the signal processing device (digital converter 17 and CPU 18) of this embodiment, the detection signal Sg2 is held during the period in which the successive comparison is performed using the plurality of stages of comparison voltages Sg6 to Sg8. Rather, the signal level at each time point is sent to the comparator Cmp1 for comparison processing. As described above, multi-value data is generated by adding a plurality of reproduction values as comparison results. Therefore, unlike general successive approximation type AD converters, waveform data having one multi-value data can be obtained for each comparison period. Therefore, it is possible to reduce the power consumption for the digital conversion process and the signal processing load by setting the comparison period a little slower.

  For example, in a general successive approximation type AD converter, this voltage is compared with a plurality of stages of comparison voltages while holding the voltage to be compared, and one multi-value data is obtained from the comparison results of the plurality of stages. Therefore, in order to obtain waveform data having the same sampling rate, the period of the comparison process must be shortened by the number of comparison voltages. However, the standard radio wave detection signal Sg2 is originally a binary signal of a high level and a low level, and the signal level varies due to a decrease in radio wave intensity or mixing of external noise. The waveform data effective for pulse determination of the time code can be efficiently acquired by the waveform data generation method of the above embodiment without performing accurate AD conversion as in the case of the type AD converter.

  The present invention is not limited to the above-described embodiment, and various modifications can be made. For example, in the above embodiment, a configuration is shown in which the comparison voltages Sg6 to Sg8 that change according to the amplitude of the detection signal are generated from the peak voltage and the bottom voltage of the detection signal. Since it also appears in the output, signal processing for changing the comparison voltage in accordance with the amplitude of the detection signal may be performed based on this output.

  In addition, the low-pass filter 170 at the input stage of the digital converter 17 may be omitted, the configuration and method of the receiving circuit 12 that receives the standard radio wave, the circuit configuration of the peak hold circuit 171 and the bottom hold circuit 172, and waveform data. Details such as the sampling period, the number of comparison voltage stages, the total number and the total number of reproduction values, and the like shown in the above embodiment can be changed as appropriate without departing from the spirit of the invention.

DESCRIPTION OF SYMBOLS 1 Radio time signal 12 Receiving circuit 15 Detector 17 Digital converter 18 CPU
19 RAM
20 ROM
21 Timing circuit 23 Display means 170 Low pass filter 171 Peak hold circuit 172 Bottom hold circuit 173 Timing controller Cmp1 Comparator S1 to S3 changeover switch Sg6 to Sg8 Comparison voltage

Claims (5)

In a signal processing device that inputs a detection signal of a standard radio wave and converts it into digital waveform data,
A comparison voltage generation unit that generates a plurality of stages of comparison voltages that vary according to the signal level and amplitude of the detection signal;
A comparator for sequentially comparing the signal level of the detection signal and the comparison voltages of the plurality of stages;
A calculation means for summing up a predetermined number of comparison results continuous with each comparison result among a series of comparison results obtained by the comparison of the comparison unit, and multi-value each,
A signal processing apparatus comprising: The comparison voltage generator is
A first voltage holding unit that holds the high level voltage of the detection signal and gradually reduces the holding voltage when the signal level of the detection signal decreases;
A second voltage holding unit that holds the low level voltage of the detection signal and gradually increases the holding voltage when the signal level of the detection signal rises;
A voltage dividing resistor for dividing the holding voltage of the first voltage holding unit and the holding voltage of the second voltage holding unit into a plurality of comparison voltages;
The signal processing apparatus according to claim 1, further comprising: A plurality of changeover switches for sending or blocking the plurality of stages of comparison voltages to the input side of the comparison unit;
A switch control unit that controls the plurality of changeover switches and sequentially sends the plurality of stages of comparison voltages to the comparison unit one by one in a predetermined cycle;
That it comprises a signal processing device according to claim 1 or 2, characterized in. Any claims 1 to 3, characterized in that the signal level of the detection signal is compared with the comparison voltage of the plurality of stages is fed to the comparison unit Without being held between the sequential comparison is performed whether the signal processing device according to item 1. A time counting means for counting time;
Time display means for displaying the time;
An antenna that receives standard radio waves,
Detection means for detecting a standard radio wave received by the antenna;
The signal processing apparatus according to any one of claims 1 to 4, wherein a detection signal of the detection means is input and converted into digital waveform data.
A radio-controlled timepiece which decodes a time code based on the digital waveform data to obtain time information.

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