JP2011232067A5 - - Google Patents
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- JP2011232067A5 JP2011232067A5 JP2010100507A JP2010100507A JP2011232067A5 JP 2011232067 A5 JP2011232067 A5 JP 2011232067A5 JP 2010100507 A JP2010100507 A JP 2010100507A JP 2010100507 A JP2010100507 A JP 2010100507A JP 2011232067 A5 JP2011232067 A5 JP 2011232067A5
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- comparison
- voltage
- detection signal
- signal
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Description
上記目的を達成するため、本発明は、
標準電波の検波信号を入力してデジタルの波形データに変換する信号処理装置において、
前記検波信号の信号レベルおよび振幅に応じて変化する複数段の比較電圧を生成する比較電圧生成部と、
前記検波信号の信号レベルと前記複数段の比較電圧とを逐次比較する比較部と、
前記比較部の比較によって得られる一連の比較結果のうち各比較結果と連続する所定個の比較結果を合計してそれぞれを多値化していく算出手段と、
を備えていることを特徴とする信号処理装置である。
In order to achieve the above object, the present invention provides:
In a signal processing device that inputs a detection signal of a standard radio wave and converts it into digital waveform data,
A comparison voltage generation unit that generates a plurality of stages of comparison voltages that vary according to the signal level and amplitude of the detection signal;
A comparator for sequentially comparing the signal level of the detection signal and the comparison voltages of the plurality of stages;
A calculation means for summing up a predetermined number of comparison results continuous with each comparison result among a series of comparison results obtained by the comparison of the comparison unit, and multi-value each,
A signal processing apparatus.
Claims (5)
前記検波信号の信号レベルおよび振幅に応じて変化する複数段の比較電圧を生成する比較電圧生成部と、
前記検波信号の信号レベルと前記複数段の比較電圧とを逐次比較する比較部と、
前記比較部の比較によって得られる一連の比較結果のうち各比較結果と連続する所定個の比較結果を合計してそれぞれを多値化していく算出手段と、
を備えていることを特徴とする信号処理装置。 In a signal processing device that inputs a detection signal of a standard radio wave and converts it into digital waveform data,
A comparison voltage generation unit that generates a plurality of stages of comparison voltages that vary according to the signal level and amplitude of the detection signal;
A comparator for sequentially comparing the signal level of the detection signal and the comparison voltages of the plurality of stages;
A calculation means for summing up a predetermined number of comparison results continuous with each comparison result among a series of comparison results obtained by the comparison of the comparison unit, and multi-value each,
A signal processing apparatus comprising:
前記検波信号の高レベルの電圧を保持して前記検波信号の信号レベルが低下した場合に保持電圧を徐々に低下させる第１電圧保持部と、
前記検波信号の低レベルの電圧を保持して前記検波信号の信号レベルが上昇した場合に保持電圧を徐々に上昇させる第２電圧保持部と、
前記第１電圧保持部の保持電圧と前記第２電圧保持部の保持電圧を複数段の比較電圧に分圧する分圧抵抗と、
を備えていることを特徴とする請求項１記載の信号処理装置。 The comparison voltage generator is
A first voltage holding unit that holds the high level voltage of the detection signal and gradually reduces the holding voltage when the signal level of the detection signal decreases;
A second voltage holding unit that holds the low level voltage of the detection signal and gradually increases the holding voltage when the signal level of the detection signal rises;
A voltage dividing resistor for dividing the holding voltage of the first voltage holding unit and the holding voltage of the second voltage holding unit into a plurality of comparison voltages;
The signal processing apparatus according to claim 1, further comprising:
前記複数の切換スイッチの制御を行って所定周期で前記複数段の比較電圧を１つずつ順繰りに前記比較部へ送るスイッチ制御部と、
を備えていることを特徴とする請求項１又は２に記載の信号処理装置。 A plurality of changeover switches for sending or blocking the plurality of stages of comparison voltages to the input side of the comparison unit;
A switch control unit that controls the plurality of changeover switches and sequentially sends the plurality of stages of comparison voltages to the comparison unit one by one in a predetermined cycle;
That it comprises a signal processing device according to claim 1 or 2, characterized in.
時刻を表示する時刻表示手段と、
標準電波を受信するアンテナと、
該アンテナにより受信された標準電波を検波する検波手段と、
該検波手段の検波信号を入力してデジタルの波形データに変換する請求項１〜４の何れか１項に記載の信号処理装置とを備え、
前記デジタルの波形データに基づきタイムコードを復号して時刻情報を取得することを特徴とする電波時計。 A time counting means for counting time;
Time display means for displaying the time;
An antenna that receives standard radio waves,
Detection means for detecting a standard radio wave received by the antenna;
The signal processing apparatus according to any one of claims 1 to 4, wherein a detection signal of the detection means is input and converted into digital waveform data.
A radio-controlled timepiece which decodes a time code based on the digital waveform data to obtain time information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010100507A JP5387493B2 (en) | 2010-04-26 | 2010-04-26 | Signal processing apparatus and radio clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010100507A JP5387493B2 (en) | 2010-04-26 | 2010-04-26 | Signal processing apparatus and radio clock |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011232067A JP2011232067A (en) | 2011-11-17 |
| JP2011232067A5 true JP2011232067A5 (en) | 2013-05-23 |
| JP5387493B2 JP5387493B2 (en) | 2014-01-15 |
Family
ID=45321541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010100507A Active JP5387493B2 (en) | 2010-04-26 | 2010-04-26 | Signal processing apparatus and radio clock |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5387493B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5784445B2 (en) * | 2011-09-29 | 2015-09-24 | セイコーＮｐｃ株式会社 | Receiver circuit for radio clock |
| JP6323210B2 (en) * | 2014-06-25 | 2018-05-16 | カシオ計算機株式会社 | Standard radio receiver and radio clock |
| JP7021585B2 (en) * | 2018-03-29 | 2022-02-17 | セイコーエプソン株式会社 | Radio correction clock |
| CN110429984B (en) * | 2019-09-16 | 2022-12-27 | 广州飞瑞敖电子科技股份有限公司 | Analog optical communication system for time division duplex |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4261158B2 (en) * | 2002-11-01 | 2009-04-30 | セイコークロック株式会社 | Hold circuit, time code demodulating circuit using the hold circuit, and radio-controlled clock |
| JP4631667B2 (en) * | 2005-11-22 | 2011-02-16 | カシオ計算機株式会社 | Time receiver and radio clock |
| JP5037397B2 (en) * | 2008-03-24 | 2012-09-26 | シチズンホールディングス株式会社 | Standard radio wave receiver |
| JP4544347B2 (en) * | 2008-07-09 | 2010-09-15 | カシオ計算機株式会社 | Time information acquisition device and radio clock |
-
2010
- 2010-04-26 JP JP2010100507A patent/JP5387493B2/en active Active
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