JP6323210B2 - Standard radio receiver and radio clock - Google Patents

Description

  The present invention relates to a standard radio wave receiver and a radio timepiece that receives a standard radio wave and adjusts the date and time.

  2. Description of the Related Art Conventionally, there is an electronic timepiece (radio timepiece) having a function of receiving an external radio wave transmitting accurate date / time information and adjusting the date / time. By executing this function automatically or in response to a user operation, the radio timepiece can easily display the accurate date and time without the user manually adjusting the date and time.

  As one of such external radio waves, there is a standard radio wave using a long wavelength band radio wave. In the standard radio wave, an amplitude-modulated code signal is transmitted every second, the start timing (second sync point) of the code signal is identified, and the start (minute sync point) of each minute is determined by a format predetermined for each standard radio wave transmission station. Accurate date / time information is obtained by decoding the code sequence starting with).

  Each code signal is a combination of a large amplitude signal (also referred to as a high level signal) and a small amplitude signal or no signal having a smaller amplitude than that of the large amplitude signal (hereinafter collectively referred to as a small amplitude signal or a low level signal). The type of code is indicated by the ratio of the length of the high level signal period and the low level signal period. Therefore, the demodulated signal is binarized depending on whether it is a high-level signal, and then the code is identified. However, since the amplitude of the low-level signal is raised due to noise mixing, or the signal strength is subject to short-term fluctuations, the reference amplitude strength that is the reference value for binarization should be set as a fixed value in advance. Is difficult.

  Therefore, conventionally, a peak hold circuit that holds the maximum value (peak voltage) of the detected and rectified voltage related to the high level signal and a minimum value (bottom voltage) of the detected and rectified voltage related to the low level signal are held. There is a technology in which a bottom hold circuit is provided in parallel, the voltage held by each of them is divided, and an intermediate value (average value) is output as a reference voltage (Patent Document 1). Further, in Patent Document 1, in order to shorten the charging time for a capacitor that holds a charge amount corresponding to the maximum value in the peak hold circuit at the time of startup, when the voltage of the capacitor does not reach a predetermined voltage, A technique is disclosed in which the capacitor is connected to a predetermined voltage source to quickly bring the voltage output from the peak hold circuit close to the maximum value of the voltage related to the high level signal.

JP 2004-151055 A

  However, in the peak hold circuit and the bottom hold circuit, the charge held by the capacitor is discharged with a predetermined time constant, so that there is a problem that the peak voltage and the bottom voltage that are output along with this discharge change with time. In particular, in the standard radio wave, the duration of the voltage level related to the high level signal and the voltage level related to the low level signal changes according to the sign, so the reference voltage is close to one of the signal voltage levels according to the previous sign. There is a problem that it changes to the side.

  An object of the present invention is to provide a standard radio wave receiving apparatus and a radio timepiece that can perform binarization of a received standard radio wave signal based on a more stable reference.

In order to achieve the above object, the present invention
A receiver that receives a standard radio wave and outputs a demodulated input signal;
A binarization processing unit that binarizes the voltage of the input signal with a predetermined reference voltage;
A second synchronization identification unit for identifying the leading timing of each second in the input signal;
A high voltage period in which the input signal is always at a high level according to the received standard radio wave format, and the input signal is always at a low level with respect to the leading timing of each second identified by the second synchronization identification unit. A reference voltage output unit that defines a low voltage period and generates and outputs the reference voltage based on the input signal in the high voltage period and the low voltage period;
A standard radio wave receiving apparatus comprising:

  According to the present invention, the received standard radio wave signal can be binarized with a more stable reference.

It is a block diagram showing an embodiment of a radio timepiece of the present invention. It is a block diagram which shows the internal structure of a radio wave receiving part. It is a figure explaining the waveform of the time code signal input into a waveform shaping circuit, and the reference voltage used as the reference | standard for binarization. It is a figure explaining the signal waveform of a time code. It is a figure which shows the waveform shaping circuit of 1st Embodiment. It is a flowchart which shows the control procedure of the waveform shaping control process performed with the radio timepiece of 1st Embodiment. It is a figure which shows the change of the reference voltage in the waveform shaping circuit of 1st Embodiment, and the example of the waveform of a time code signal. It is a figure which shows the waveform shaping circuit in the radio timepiece of 2nd Embodiment. It is a flowchart which shows the control procedure of the waveform shaping control process performed with the radio timepiece of 2nd Embodiment. It is a figure which shows the change of the reference voltage in the waveform shaping circuit of 2nd Embodiment, and the example of the waveform of a time code signal. It is a figure which shows the waveform shaping circuit in the radio timepiece of 3rd Embodiment. It is a figure which shows the waveform shaping circuit in the radio timepiece of 4th Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, the radio timepiece according to the first embodiment of the present invention will be described.
FIG. 1 is a block diagram of an embodiment of a radio timepiece having a standard radio wave receiver of the present invention.

  The radio timepiece 1 of the present embodiment includes a CPU (Central Processing Unit) 11 (second synchronization identification unit, switching control unit, date correction unit), ROM (Read Only Memory) 12 (error storage unit), and RAM (Random Access). Memory) 13, power supply unit 14, operation unit 15, display unit 16 and its driver 17, oscillation circuit 18 (oscillation unit), frequency dividing circuit 19, clocking circuit 20 (clocking unit), and radio wave A receiving antenna 21 and a radio wave receiver 22 are provided.

The CPU 11 performs various arithmetic processes and controls the overall operation of the radio timepiece 1. The ROM 12 stores a control program for the radio timepiece 1 and execution programs related to various application operations. These programs are read by the CPU 11 as needed, loaded into the RAM 13 and executed. As the ROM 12, in addition to a write-once mask ROM, a rewritable flash memory and various nonvolatile memories may be used in part or in whole. The RAM 13 provides a working memory space for the CPU 11 and stores temporary data and the like.

  The power supply unit 14 supplies power to each unit such as the CPU 11 and the radio wave reception unit 22. The power supply unit 14 is, for example, a combination of solar power generation using a solar panel and a secondary battery.

  The operation unit 15 receives a user operation, converts it into an electrical signal, and outputs it to the CPU 11. The operation unit 15 includes, for example, a push button switch and a crown switch.

  The display unit 16 includes a display screen by an LCD (liquid crystal display), for example. When a control signal related to the display content is sent from the CPU 11 to the driver 17, the driver 17 outputs a drive signal to the display unit 16, and the display unit 16 displays the date and time measured, information associated therewith, and various functions. Display and menu display are performed.

The oscillation circuit 18 generates and outputs a signal having a predetermined frequency. Although not particularly limited, a crystal oscillator is used for the oscillation circuit 18, and usually a slight deviation or variation occurs in the generated frequency. The frequency dividing circuit 19 converts the frequency signal input from the oscillation circuit 18 into various frequency signals used by the CPU 11 and the time measuring circuit 20 and outputs them.
The timer circuit 20 holds the current time data by counting the frequency signal input from the frequency divider circuit 19. At this time, the frequency signal input from the frequency dividing circuit 19 to the time measuring circuit 20 uses logical steepness in order to correct a deviation or variation (error) in the frequency oscillated by the above-described crystal oscillator. The error correction data 12a (information related to the error) related to the logical slowness is inspected at a factory or the like before shipment and stored in the ROM 12 in advance. The current time data is rewritten and corrected by an instruction from the CPU 11.

The receiving antenna 21 is an antenna that receives radio waves in a long wavelength band, and is a bar antenna or the like. The radio wave receiving unit 22 tunes a radio wave received using the receiving antenna 21 to a desired standard radio frequency to which date / time information is transmitted, demodulates a time code signal (input signal) from the received radio wave, Convert to binary data, perform digital sampling, and output.
In the radio timepiece 1 of the present embodiment, the standard radio wave receiver 10 is constituted by the CPU 11, the ROM 12, the RAM 13, the oscillation circuit 18, the frequency dividing circuit 19, the receiving antenna 21, and the radio wave receiving unit 22 among the above components.

  FIG. 2 is a block diagram showing the internal configuration of the radio wave receiver 22.

The radio wave receiver 22 includes an RF amplifier 221, a mixer 222, an OSC (local frequency oscillator) 223, a BPF (narrowband filter) 224, an IF amplifier 225, a detection circuit 226, and an AGC circuit 227 (automatic gain control). Circuit), a waveform shaping circuit 228, an ADC 229 (analog-digital converter), and the like.
Received by the RF amplifier 221, the mixer 222, the OSC (local frequency oscillator) 223, the BPF (narrowband filter) 224, the IF amplifier 225, the detection circuit 226, the AGC circuit 227, the reception antenna 21, etc. The part is composed.

The RF amplifier 221 amplifies a radio wave signal having a carrier frequency input from the receiving antenna 21. As this RF amplifier 221, a high gain low noise amplifier (LNA) is used. The mixer 222 mixes the radio signal amplified by the RF amplifier 221 and the local frequency signal output from the OSC 223 and converts the mixed signal into an intermediate frequency signal.

  The BPF 224 extracts and outputs a signal in a desired frequency range including a time code signal from the intermediate frequency signal output from the mixer 222. The IF amplifier 225 amplifies the intermediate frequency band signal output from the BPF 224. Then, the detection circuit 226 demodulates the time code signal (TCO) from the signal in the intermediate frequency band.

  The AGC circuit 227 adjusts the reception gains of the RF amplifier 221 and the IF amplifier 225 based on the time code signal demodulated by the detection circuit 226. That is, the AGC circuit 227 adjusts the reception gain so that there is no significant difference between the codes in the voltage levels of the demodulated time code signal high level signal and low level signal.

  The waveform shaping circuit 228 binarizes the demodulated time code signal into either a high level signal or a low level signal based on a predetermined reference voltage (reference voltage). In the waveform shaping circuit 228, a control signal is input from the CPU 11, and an operation related to maintaining the setting of the reference voltage is performed. The ADC 229 converts the binarized analog voltage signal into digital data at a predetermined sampling frequency and outputs the digital data to the CPU 11.

Next, the operation of the time code signal waveform and its identification will be described.
3 and 4 are diagrams for explaining the waveform of the time code signal input to the waveform shaping circuit 228. FIG.

In FIG. 3A, each voltage waveform of the time code signal transmitted from the standard radio wave transmitting station is shown by a solid line. The waveform of the period C1 is a signal waveform representing a “0” code in a time code signal transmitted by a Japanese standard radio wave transmission station JJY (registered trademark). With this “0” code, the high level signal continues for 0.8 seconds from the beginning of the second, and then the low level signal that is 10% intensity (amplitude, voltage) of the high level signal continues for 0.2 seconds. The waveform of the period C2 is a signal waveform representing the “1” code in the JJY time code signal. With the “1” code, the high level signal and the low level signal each last for 0.5 seconds. The waveform of the period C3 is a signal waveform representing the “P” code in the JJY time code signal. With this “P” code, the high level signal continues for 0.2 seconds, followed by the low level signal for 0.8 seconds. That is, for any code, the leading timing of each second (hereinafter referred to as a second synchronization point) is detected by the rising of the signal level (signal strength) (timing (u1) to (u4)). Then, the type of code is determined by the duration from the second synchronization point to the fall of the signal level.
As a method for identifying the second synchronization point, any one or a combination of various known techniques is appropriately used. For example, an input signal with an arbitrary 1-second period is multi-valued or binarized at a predetermined sampling frequency, and multiple additions are performed. Can be a point. In the radio timepiece 1 of the present embodiment, these processes are executed by the CPU 11 using the digital binarized signal output from the radio wave receiver 22.

  On the other hand, in the US WWVB, UK MSF, and German DCF77, the signal level falls at the second synchronization point except for 59 seconds per minute in the DCF77 where no code is transmitted, and the arrangement and length of the subsequent low level period Any symbol is represented by. Therefore, the second synchronization point is detected by the falling edge of the signal.

Here, the reference voltage for binarization is indicated by a dotted line. The reference voltage can be, for example, an intermediate value between the high level signal and the low level signal, that is, a value obtained by dividing the reference voltage by one to one. In the radio-controlled timepiece 1, the intermediate value is not a transmission level from the standard radio wave but a value corresponding to the amplitude ratio between the high level signal and the low level signal in the actual reception radio wave, that is, when the low level signal is small. In other words, the reference voltage can be set to a middle value or a predetermined ratio including the influence of noise that increases.

  FIG. 3B shows an example of a waveform of a time code signal actually demodulated. In the radio wave receiver 22, the high-frequency component of the signal is cut by passing through the BPF 224, so that the rising and falling of the rectangular wave in the transmitted time code signal is blunt (for the sake of explanation, the blunting is greatly increased). Shown). In addition, as shown in the vibration between timings (u1) and (d1) and the increase in signal intensity between timings (d2) and (u3), short fluctuations in the input level that are not adjusted by the AGC circuit 227, burst noise, etc. May be mixed. In such a case, since the reference voltage is determined to be substantially constant, the radio timepiece 1 according to the embodiment of the present invention appropriately maintains a timing shift related to the detection of rising or falling, Prevents fluctuations in standards such as missing detections or not.

  As shown in FIG. 4, when the signal levels of the respective codes are overlapped on the basis of the second synchronization point at which the signal level rises in all codes, the interval from the second synchronization point to the third change point (originally 200 ms) is always obtained. The high level signal (voltage VH) is received (high voltage period), and the low level signal (voltage VL) is always received (low voltage period) in the section after the first change point (originally 800 ms). On the other hand, in the section from the third change point (d3) to the first change point (d1), a different signal level is shown for each code. As long as the “0” code and the “1” code are limited, the high level signal (voltage VH) is always received in the section from the second synchronization point to the second change point (d2).

Therefore, in the radio timepiece 1 of the present embodiment, a signal from the second synchronization point to the third change point (d3) and a signal from the first change point (d1) to the second synchronization point are respectively provided with separate capacitors and voltages. By inputting to the follower, the high level signal strength and the low level signal strength of the received signal are acquired and output. Then, these signal intensities are averaged and output with a predetermined weight by the resistance element, so that a reference value for binarization is generated.
Here, as described above, due to the dullness of the rising and falling waveforms of the signal, the signal level is not completely at the high level and the low level immediately after the second synchronization point and immediately after the first change point (d1), respectively. . Therefore, it may be possible to shorten the data acquisition start slightly later without acquiring all the 200 ms data. In addition, the signal level always rises at the second synchronization point, whereas the signal level may have already changed to the low level at the first change point (d1). Therefore, the reception time of both periods may be made different according to the appearance ratio of the “P” code and other codes (“P” code is 7 times per minute).

FIG. 5 is a diagram showing the waveform shaping circuit 228 of this embodiment.
The waveform shaping circuit 228 includes a reference voltage generation circuit 2289 (reference voltage generation unit) and a comparator 2280 (binarization processing unit). The reference voltage generation circuit 2289 includes a first switching element 2281a and a second switching element 2281b (switching unit), resistance elements 2282a and 2282b, a first capacitor 2283a (first voltage holding unit), and a second capacitor 2283b (first unit). 2 voltage holding unit), a first operational amplifier 2284a, a second operational amplifier 2284b, and resistance elements 2285a and 2285b. The first operational amplifier 2284a and the second operational amplifier 2284b are used as a voltage follower by returning an output to a non-inverting input.

The input voltage Vin of the input signal input from the input terminal is divided into three, one is input to the inverting input of the comparator 2280, and the other two are on the other hand the first switching element 2281a and the resistance element 2282a. Is supplied to one end of the first capacitor 2283a and the non-inverting input of the first operational amplifier 2284a of the voltage follower, and on the other hand, the second capacitor 2283b is supplied via the second switching element 2281b and the resistance element 2282b.
And the non-inverting input of the second operational amplifier 2284b of the voltage follower. The other ends of the first capacitor 2283a and the second capacitor 2283b are grounded ground ends. That is, a low-pass filter is configured by the resistance element 2282a and the first capacitor 2283a, and charges are accumulated in the first capacitor 2283a with a predetermined time constant while the first switching element 2281a is turned on. Similarly, the resistance element 2282b and the second capacitor 2283b constitute a low-pass filter, and charges are accumulated in the second capacitor 2283b with a predetermined time constant while the second switching element 2281b is turned on. That is, the first capacitor 2283a and the second capacitor 2283b hold and output a voltage obtained by allowing the change in the input voltage Vin to pass through in a predetermined band.

The output voltage of the first operational amplifier 2284a and the output voltage of the second operational amplifier 2284b are divided by the resistance elements 2285a and 2285b, input to the comparator 2280 as the reference voltage Vref (reference voltage), and compared with the input voltage Vin. The comparator 2280 outputs a high voltage or a low voltage corresponding to each of the binary values from the output terminal according to the magnitude relationship between the input voltage Vin and the reference voltage Vref.
The first operational amplifier 2284a, the second operational amplifier 2284b, and the resistance elements 2285a and 2285b constitute a reference voltage output unit.

  The first switching element 2281a and the second switching element 2281b are not particularly limited, but by using an FET, the energized state can be easily switched on and off simply by switching the voltage input as a control signal. I can do it.

  The first switching element 2281a is turned on for a period during which the high level voltage VH of the high level signal is input as the input voltage Vin, that is, the period from the second synchronization point to the third change point, and in other periods. Turned off. On the other hand, the second switching element 2281b is turned on during a period in which the low level voltage VL of the low level signal is input as the input voltage Vin, that is, from the first change point to the next second synchronization point. It is turned off in the period. Accordingly, the first capacitor 2283a is supplied with a charge corresponding to the high level voltage VH while the first switching element 2281a is on, while the charge is substantially maintained while the first switching element 2281a is off. Is done. As a result, the high level voltage VH is always output as the high level side output voltage VrefH from the first operational amplifier 2284a of the voltage follower. The second capacitor 2283b is supplied with a charge corresponding to the low level voltage VL while the second switching element 2281b is on, while the charge is substantially maintained while the second switching element 2281b is off. Is done. As a result, the low-level voltage VL is always output as the low-level output voltage VrefL from the second operational amplifier 2284b of the voltage follower.

  Here, each operation relating to the on / off of the first switching element 2281a and the second switching element 2281b cannot be performed until the second synchronization point is identified. Further, at the stage of starting reception, the first capacitor 2283a and the second capacitor 2283b do not store charges corresponding to the high level voltage VH and the low level voltage VL, respectively. Therefore, in the radio timepiece 1 of the present embodiment, the first switching element 2281a and the second switching element 2281b are always turned on until the second synchronization point is identified.

  FIG. 6 is a flowchart showing a control procedure by the CPU 11 of the waveform shaping control process executed by the radio timepiece 1 of the present embodiment.

This waveform shaping control process is a date and time acquisition process separately executed by the CPU 11, that is, a standard radio wave reception process by the radio wave receiving unit 22, a decoding process of the received time code signal, and a plurality of date and time obtained by the decoding process. This process is started in conjunction with the start of the process including the consistency check process or in the date and time acquisition process.
When the waveform shaping control process is started, the CPU 11 outputs a control signal to the first switching element 2281a and the second switching element 2281b of the waveform shaping circuit 228 to turn on any switching element (step S101).

  The CPU 11 determines whether or not the second synchronization point is identified in the second synchronization point detection process performed based on the output from the ADC 229 in the decoding process (step S102). When it is determined that the second synchronization point has not been identified (“NO” in step S102), the CPU 11 repeats the determination process in step S102.

When it is determined that the second synchronization point has been identified (“YES” in step S102), the CPU 11 turns on the first switching element 2281a and the second switching element 2281b with reference to the second synchronization point. Timing is determined, and output of a control signal related to on / off switching is started for the first switching element 2281a and the second switching element 2281b (step S103). That is, the CPU 11 outputs a control signal for turning on the first switching element 2281a only between the second synchronization point and the third change point, and the second switching element 2281b only between the first change point and the second synchronization point. A control signal for turning on is output. Further, after identifying the second synchronization point, the CPU 11 identifies the synchronization point that is the leading timing of each minute by detecting two consecutive “P” codes in the decoding process, and at the transmission timing of the “P” code, Control signal for turning on the first switching element 2281a from the second synchronization point to the second change point (d2, see FIG. 4) when discriminating between the “0” code and the “1” code at a timing that is not May be output.
Here, since the switching of the first switching element 2281a and the second switching element 2281b needs to be performed strictly in a cycle of 1 second, the CPU 11 uses the frequency dividing circuit 19 as a clock signal for acquiring the timing. For the time counting, use the one that has been corrected for logical slowness. Alternatively, the CPU 11 may independently use a high frequency signal input from the frequency dividing circuit 19 separately from the signal used by the time counting circuit 20 and perform correction based on logical slow / slow.

  In parallel with the output of the control signal started in step S103, the CPU 11 determines whether or not the reception of the standard radio wave by the radio wave receiving unit 22 has ended (step S104). The CPU 11 determines whether or not an execution instruction for the reception end process has been output in the date and time acquisition process based on whether or not the time code signal decoding process and the matching confirmation process have been normally completed. When it is determined that the execution instruction for the reception end process has not been output (“NO” in step S104), the CPU 11 repeats the determination process in step S104. If it is determined that the execution instruction for the reception end process has been output, the CPU 11 ends the waveform shaping control process.

  FIG. 7 is a diagram illustrating an example of a waveform of a time code signal and a change in the reference voltage Vref of the waveform shaping circuit 228 in the radio timepiece 1 of the present embodiment.

  At the start of reception of the standard radio wave by the radio wave receiver 22, since the first capacitor 2283a and the second capacitor 2283b are not charged, the output voltage VrefH of the first operational amplifier 2284a and the output voltage VrefL of the second operational amplifier 2284b are , Both are 0V. Therefore, the initial value of the reference voltage Vref is also “0”. When the first switching element 2281a and the second switching element 2281b are turned on, the output voltages VrefH and VrefL and the reference voltage Vref immediately change in synchronization (period T1). In JJY, as described above, the appearance frequency of the waveforms in the period C1 and the period C2 shown in FIG. 3 is relatively higher than the appearance frequency of the waveform in the period C3. The high level voltage VH is input.

  When the second synchronization point is identified, the period during which the first switching element 2281a and the second switching element 2281b are turned on is set, so that the output voltage VrefH from the first operational amplifier 2284a gradually approaches the high level voltage VH. On the other hand, the output voltage VrefL from the second operational amplifier 2284b gradually approaches the low level voltage VL (period T2). A reference voltage Vref obtained by dividing the high level voltage VH and the low level voltage VL by a predetermined ratio is input to the comparator 2280 as a substantially constant value.

As described above, the standard radio wave receiver 10 and the radio timepiece 1 of this embodiment receive the standard radio wave and output the demodulated input signal (time code signal), the receiving antenna 21, the RF amplifier 221, the mixer 222, OSC 223, BPF 224, IF amplifier 225, detection circuit 226 and AGC circuit 227, comparator 2280 for binarizing the input voltage Vin with a predetermined reference voltage Vref, and CPU 11 for identifying the second synchronization point in the input signal of the waveform shaping circuit 228 The high-voltage period during which the input signal is always at a high level (high level voltage) and the input signal is always at a low level (low level voltage) with respect to the identified second sync point The reference voltage Vref is determined based on the input signal in the high voltage period and the low voltage period. It includes a reference voltage generating circuit 2289 which forms the output, a.
Thus, since the reference voltage Vref for binarizing the time code signal of the standard radio wave is set only by the high level voltage during the high level period and the low level voltage during the low level period, fluctuations in the reference voltage Vref are suppressed. , Binarization can be performed on a more stable basis.

  In addition, the reference voltage generation circuit 2289 has a plurality of capacitors that hold a voltage corresponding to a change in the voltage of the input signal, the first capacitor 2283a and the second capacitor 2283b, and the input signal to the first capacitor 2283a and the second capacitor 2283b. First switching element 2281a and second switching element 2281b that respectively switch whether input is possible or not, and resistance elements 2285a and 2285b that generate reference voltage Vref based on voltages held by first capacitor 2283a and second capacitor 2283b. . The CPU 11 controls the switching operation of whether or not the input signal can be input by the first switching element 2281a and the second switching element 2281b, and inputs the input signal of the high voltage period to the first capacitor 2283a among the plurality of capacitors. An input signal for a low voltage period is input to the two capacitors 2283b. Further, the resistance values of the resistance elements 2285a and 2285b are set so as to generate the reference voltage Vref by combining the voltage held by the first capacitor 2283a and the voltage held by the second capacitor 2283b at a predetermined ratio. That is, since the high level voltage and the low level voltage are separately held and divided at an appropriate ratio, the time code is stored after an appropriate amount of charge is held in the first capacitor 2283a and the second capacitor 2283b. A substantially constant reference voltage Vref is generated regardless of the time change of the amplitude (voltage level) of the signal, and binarization can be determined on a stable basis.

  Further, since the output voltage from the first capacitor 2283a and the output voltage from the second capacitor 2283b are determined according to the amplitude ratio of the high level signal and the low level signal in the standard radio wave, that is, the voltage ratio, the influence of background noise An appropriate reference voltage can be set in consideration of the above. Therefore, the possibility of erroneous determination can be reduced.

  In particular, by dividing the high-level voltage and the low-level voltage on a one-to-one basis and setting the intermediate value as the reference voltage Vref, voltage changes that are not supported by the AGC circuit 227 due to short-period fluctuations in reception intensity, Stable binarization determination can be performed in consideration of the influence of the delay of the change that appears at the rise / fall of the signal in terms of the structure.

Also, resistance elements 2285a and 228 that divide a voltage corresponding to the charge held by the first capacitor 2283a and a voltage corresponding to the charge held by the second capacitor 2283b at a predetermined ratio.
Since the reference voltage Vref is generated with 5b, the reference voltage Vref can be easily generated by an analog circuit without requiring a control operation or an arithmetic operation.

  Further, until the second synchronization point is identified, the CPU 11 continues to input the voltage of the input signal (input voltage Vin) to the first capacitor 2283a and the second capacitor 2283b, and the first capacitor 2283a and the second capacitor 2283b. Capacitor 2283b retains electric charges according to the input voltage that is transmitted through the low band by combination with resistance elements 2282a and 2282b. In the time code signal, a high level signal and a low level signal are combined and output. Therefore, by continuously inputting charges during the process of identifying the second synchronization point, the high level signal and the low level signal are input in advance. It is possible to charge a charge amount corresponding to an intermediate voltage between the two. Therefore, when a capacitor having a somewhat large capacitance is used, the time required to charge the charge corresponding to the high level voltage and the low level voltage is effectively shortened, and promptly after the binarization process is started. A stable reference voltage Vref can be reached. In particular, when binarization of the time code signal is not performed in the process related to identification of the second synchronization point, the capacitor can be effectively charged during that time.

  In addition, since a capacitor provided between the input terminal of the input signal and the ground terminal is used as the voltage holding unit, the high level voltage and the low level voltage can be acquired with a simple configuration and processing.

  In addition, an oscillation circuit 18 that generates a predetermined frequency signal, and correction data relating to the logic speed for correcting the date / time counting interval in consideration of an error from the exact frequency of the frequency signal generated by the oscillation circuit 18 are stored. The reference voltage generation circuit 2289 uses the correction data to correct and determine the high voltage period and the low voltage period, so that the oscillation circuit 18 does not include an expensive compensation circuit at an accurate timing. High level voltage and low level voltage can be acquired.

  In addition, the above-described standard radio wave receiver 10, the frequency signal generated by the oscillation circuit 18, and the time counting circuit 20 that counts the current date and time based on the frequency error correction data, and the date and time acquired by receiving the standard radio wave In the radio-controlled timepiece 1 that includes a date and time correction unit that corrects the date and time counted by the timing circuit 20 based on the data, and a display unit 16 that displays the time and date that has been timed, the time code signal is displayed on a stable basis as described above. Since binarization can be performed, it is less affected by noise and the like than before, and it is possible to avoid situations such as reception failure and prolonged reception due to inconsistency of date and time data acquired a plurality of times. Therefore, accurate date and time can be displayed while effectively suppressing an increase in power consumption.

[Second Embodiment]
Next, a second embodiment of the radio timepiece of the invention will be described.

FIG. 8 is a diagram showing a waveform shaping circuit 228a in the radio timepiece 1 of the second embodiment.
The radio timepiece 1 of the second embodiment has the same configuration except that the waveform shaping circuit 228 in the radio timepiece 1 of the first embodiment is replaced by a waveform shaping circuit 228a, and the same components are the same. The description is omitted by attaching the reference numerals.

The waveform shaping circuit 228a includes a reference voltage generation circuit 2289a (reference voltage generation unit) and a comparator 2280 (binarization processing unit). The reference voltage generation circuit 2289a includes a switching element 2281c (switching unit), a resistance element 2282c, and a capacitor 2283c (voltage holding unit).
The input voltage Vin input from the input terminal to the waveform shaping circuit 228a is divided into two, one of which is the switching element 2281c and the resistance element 228 in the reference voltage generation circuit 2289a.
A voltage corresponding to the electric charge supplied to one end of the capacitor 2283c through 2c and charged in the capacitor 2283c is input to the non-inverting input of the comparator 2280. The other end of the capacitor 2283c is a grounded grounded end. The other of the two divided input voltages Vin is input to the inverting input of the comparator 2280. The resistance element 2282c and the capacitor 2283c constitute a low-pass filter, and charges corresponding to the input voltage Vin are accumulated (charged or discharged) with a predetermined time constant while the switching element 2281c is turned on. .

  In the radio-controlled timepiece 1 of this embodiment, a period in which a high level signal is always received (high voltage period) and a period in which a low level signal is always received (low voltage period) according to a control signal from the CPU 11 after identification of the second synchronization point. ) At a predetermined ratio, here, the switching element 2281c is turned on over an equal period, so that a substantially intermediate value between the high level voltage VH and the low level voltage VL is input from the capacitor 2283c to the comparator 2280 as the reference voltage Vref. . Specifically, the switching element 2281c is continuously turned on from the first change point to the third change point across the second synchronization point, thereby inputting a high level signal and a low level signal over a period of 0.2 seconds. The voltage Vin is supplied to the capacitor 2283c.

  FIG. 9 is a flowchart showing a control procedure by the CPU 11 of the waveform shaping control process executed by the radio timepiece 1 of the present embodiment.

  This waveform shaping control process is the same except that steps S101 and S103 in the waveform control process of the first embodiment have been replaced with steps S101a and S103a, respectively, and detailed description of the same processes is omitted. .

When the waveform shaping control process is started, the CPU 11 outputs a control signal for turning on the switching element 2281c (step S101a), and detects the second synchronization point while always keeping the on state.
Further, when it is determined that the second synchronization point has been identified (“YES” in step S102), the CPU 11 sets the on / off timing of the switching element 2281c and starts outputting the on / off control signal according to the setting. (Step S103a).

  FIG. 10 is a diagram showing a change in the reference voltage Vref and an example of the waveform of the time code signal in the waveform shaping circuit 228a of the present embodiment.

  In the waveform shaping circuit 228a of this embodiment, the reference voltage Vref output from the capacitor 2283c is maintained while the switching element 2281c is turned off, while the input to the capacitor 2283c is maintained while the switching element 2281c is turned on. As the voltage Vin, the low-level signal and the high-level signal are input in order of half. Therefore, while the low level signal is input, the charge of the capacitor 2283c is discharged according to the low level voltage VL lower than the intermediate value (VH + VL) / 2, the reference voltage Vref slightly decreases, and the high level signal Is input, the capacitor 2283c is charged again according to the high level voltage VH higher than the intermediate value (VH + VL) / 2, and the reference voltage Vref is recovered.

  In the waveform shaping circuit 228a of this embodiment, the charge amount corresponding to the appropriate reference voltage Vref is charged in the capacitor 2283c until the second synchronization point is identified, and the reference voltage while the switching element 2281c is on. The capacitance of the capacitor 2283c and the resistance value of the resistance element 2282c are determined so that the decrease width of Vref is within a range that does not adversely affect the binarization determination.

As described above, in the standard radio wave receiver 10 and the radio timepiece 1 of the present embodiment, the reference voltage generation circuit 2289a includes the capacitor 2283c that holds a voltage corresponding to the voltage change of the input signal that is input, and the capacitor 2283c. A switching element 2281c that switches whether or not an input signal can be input. The CPU 11 controls the switching operation of whether or not the switching element 2281c can input the capacitor 2283c. At this time, the CPU 11 inputs an input signal to the capacitor 2283c over a period including a period of a high level signal and a period of a low level signal at a predetermined ratio. The reference voltage Vref is maintained substantially constant.
Therefore, the number of resistive elements that tend to increase power consumption can be reduced, and the number of capacitors that tend to be large compared to other configurations can be reduced. Standard radio waves can be decoded by setting a reference voltage for binarization.

[Third Embodiment]
Next, the radio timepiece 1 of the third embodiment will be described.
FIG. 11 is a diagram illustrating a waveform shaping circuit 228b in the radio timepiece 1 of the third embodiment.
The radio timepiece 1 has the same configuration except that the waveform shaping circuit 228 of the radio timepiece 1 of the first embodiment is replaced by a waveform shaping circuit 228b, and the same components are denoted by the same reference numerals. The description is omitted.

  The waveform shaping circuit 228b includes resistance elements 2285c and 2285d, a comparator 2280b, and a selection switch 2286 in addition to the components of the waveform shaping circuit 228.

  The resistance elements 2285c and 2285d are provided in parallel with the resistance elements 2285a and 2285b in the reference voltage generation circuit 2289b, and reference voltage is divided between the output voltage VrefH of the first operational amplifier 2284a and the output voltage VrefL of the second operational amplifier 2284b. It outputs to the comparator 2280b as VrefD (falling reference voltage). Here, the voltage divided by the resistance elements 2285a and 2285b corresponding to the reference voltage VrefD is shown as a reference voltage VrefU (rising reference voltage).

  The resistance values of the resistance elements 2285c and 2285d are set at different ratios so that the reference voltage VrefD divided by the resistance elements 2285c and 2285d is different from the reference voltage VrefU divided by the resistance elements 2285a and 2285b. For example, in order to make the reference voltage VrefD lower than the reference voltage VrefU, the resistance values of the resistance elements 2285a and 2285c may be equalized and combined with the resistance element 2285d having a resistance value smaller than that of the resistance element 2285b.

  As described above, the comparison result between the different reference voltages VrefU and VrefD and the input voltage Vin is alternatively selected by the selection switch 2286 based on the control signal from the CPU 11 and output. In the radio timepiece 1 of the present embodiment, a comparison result between the reference voltage VrefU and the input voltage Vin used for determining the timing at which the input voltage Vin switches (rises) from the low level voltage VL to the high level voltage VH by this control signal. One of the comparison results between the reference voltage VrefD and the input voltage Vin used to determine the timing at which the input voltage Vin switches (falls) from the high level voltage VH to the low level voltage VL is output. That is, when the output voltage Vout is high, the input of the selection switch 2286 is switched to the comparator 2280b, and when the output voltage Vout is low, the input to the selection switch 2286 is changed to a signal from the comparator 2280. The CPU 11 outputs a control signal so that it can be switched.

As described above, the standard radio wave receiver 10 and the radio timepiece 1 of the present embodiment use the reference voltage VrefU for identifying the timing at which the input signal switches from the low level to the high level as the reference voltage Vref, and the input signal is high. A reference voltage VrefD for identifying the timing of switching from the level to the low level is set and used by being switched by the selection switch 2286. Then, the reference voltage generation circuit 2289b generates a voltage corresponding to the charge held by the capacitor 2283a and a voltage corresponding to the charge held by the capacitor 2283b with respect to the reference voltage VrefU at the rising time and the reference voltage VrefD at the falling time. They are generated by combining them at different ratios. Therefore, it is possible to determine more appropriate reference voltages that reflect differences in rising and falling characteristics of the input voltage Vin, differences in the influence of noise, and the like.
For example, when detecting a rising edge from a low level signal to a high level signal, the reference voltage VrefU can be set high so that a false rising edge due to burst noise or the like is not easily detected.

[Fourth Embodiment]
Next, the radio timepiece 1 of the fourth embodiment will be described.
FIG. 12 is a diagram illustrating a waveform shaping circuit 228c in the radio timepiece 1 of the fourth embodiment.
The radio timepiece 1 has the same configuration except that the waveform shaping circuit 228a of the radio timepiece 1 of the second embodiment is replaced by a waveform shaping circuit 228c, and the same components are denoted by the same reference numerals. The description is omitted.

  In this waveform shaping circuit 228c, in addition to the components in the waveform shaping circuit 228a of the second embodiment, a reference voltage generation circuit 2289c and a comparator 2280d are provided. In the reference voltage generation circuit 2289c, a switching element 2281d, a resistance element 2282d, and a capacitor 2283d (fourth voltage holding unit) are provided and connected, and the switching element 2281c, the resistance element 2282c, and the capacitor 2283c (capacitor 2283c) related to the reference voltage generation circuit 2289a are provided. The third voltage holding unit) and the comparator 2280 are connected in parallel. Further, the output signals of the comparator 2280 and the comparator 2280d are input to the selection switch 2286 as in the radio timepiece 1 of the third embodiment, and are alternatively output as the output voltage Vout.

  In the radio timepiece 1 of this embodiment, the amount of charge stored in each of the capacitors 2283c and 2283d is made different by changing the period during which the switching element 2281c and the switching element 2281d are turned on in the waveform shaping circuit 228c. That is, the reference voltage VrefU (increase reference voltage) input to the comparator 2280 and the reference voltage VrefD (decrease reference voltage) input to the comparator 2280d have different values.

  The output of the comparator 2280 and the output of the comparator 2280d are input to the selection switch 2286 that is switched by the CPU 11 based on whether the output voltage Vout is high level or low level, and either is output as the output voltage Vout.

As described above, the waveform shaping circuit 228c in the standard radio wave receiver 10 and the radio timepiece 1 according to this embodiment includes the switching elements 2281c and 2281d, the capacitors 2283c and 2283d, the comparators 2280 and 2280d, the selection switch 2286, and the like. The capacitor 2283c holds a charge corresponding to the reference voltage VrefU for identifying the timing at which the input signal switches from the low level to the high level, and the capacitor 2283d identifies the timing at which the input signal switches from the high level to the low level. The charge corresponding to the reference voltage VrefD for holding is held. The CPU 11 performs on / off control of the switching elements 2281c and 2281d at a predetermined ratio in order to cause the capacitors 2283c and 2283d to hold charges corresponding to the reference voltages VrefU and VrefD, respectively.
Therefore, like the radio timepiece 1 of the third embodiment, the reference voltage VrefU can be set high so that it is difficult to erroneously detect a false rise due to burst noise or the like.

The present invention is not limited to the above-described embodiment, and various modifications can be made.
For example, in the above embodiment, the reference voltage Vref is generated using a switching element, a capacitor, a voltage follower, and a comparator. However, digital processing may be partially included. For example, the signal level can be digitized as multi-value data at a predetermined sampling rate, an intermediate value between the high level period and the low level period can be calculated and analog output as the reference voltage Vref. Or, conversely, the reference voltage Vref and the input voltage Vin generated by the analog circuit may be converted into a multivalued digital numerical value and then compared.

  In the above embodiment, the case where the intermediate value between the high level voltage VH and the low level voltage VL is the reference voltage Vref has been described. However, other values may be used. For example, since noise is likely to be superimposed on a low level signal, even if the reference voltage Vref is set to a position slightly deviated toward the high level voltage VH, the setting is not changed during reception, and the reference is quickly made. Any configuration may be used as long as the voltage Vref approaches this value.

  In addition, as described above, in DCF77, there is no signal at the timing of 59 seconds, but since it is once in 60 times, even if the same processing is performed as it is, the influence is small. However, after the head position for each minute is identified, a process that does not turn on the switching element may be performed at the timing of 59 seconds. The operation timing of the switching element appropriate for each standard radio wave transmission station can be stored in advance as table data in the ROM 12 or the like.

  Further, in the above embodiment, the frequency error generated by a normal crystal oscillator is corrected using the setting related to the logic speed, and the high level period and the low level period are set with accurate timing, and the operation of the switching element is performed. However, when a temperature compensation circuit or the like is incorporated in the crystal oscillator and an almost accurate frequency signal is oscillated, it is not always necessary to perform correction.

  In the above embodiment, the large amplitude signal is directly used as a high level signal with a high voltage, and the small amplitude signal is described as a low level signal with a low voltage. However, the signal level is inverted during the processing of the radio wave receiver 22. The circuit may be configured such that active low, that is, a large amplitude signal is a low level signal and a small amplitude signal is a high level signal.

  In the above embodiment, the reference voltage is set by dividing the voltage by providing two capacitors, and the ON / OFF time of one capacitor is equally included in the high-level / low-level periods of the time code signal. A configuration in which a reference voltage is set by setting, and a rise detection from a low level signal to a high level signal by a configuration in which two voltage dividing resistors are provided and a configuration in which two capacitors for holding electric charges are provided The reference voltage used for the reference and the reference voltage used for detecting the fall from the high level signal to the low level signal are shown. However, four capacitors are provided and each of the two is provided for detecting the rise according to the output voltage of the capacitor. A reference voltage and a reference voltage for detecting falling may be set. Further, instead of four capacitors, one capacitor may be shared and three capacitors may be used.

In the above embodiment, the processing related to the identification of the second synchronization point and the operation timing control of the first switching element 2281a and the second switching element 2281b in the reference voltage generation circuit 2289 are performed by the CPU 11 and the ROM 12 outside the waveform shaping circuit 228. However, the waveform shaping circuit 228 and the radio wave receiver 22 may separately hold the configuration related to the control.

  In addition, the resistance element used in the above embodiment is a resistance element as a circuit component as long as it generates a resistance of a desired size and other parasitic capacitance and inductance are small enough to be ignored. Not limited.

  In the above embodiment, the low-frequency transmission filter is configured by the resistance elements 2282a and 2282b and the capacitors 2283a and 2283b to exclude the input of the high-frequency fluctuation. However, when the reference voltage Vref is calculated after conversion into digital data Alternatively, other processing such as not acquiring different values at a predetermined ratio or more with respect to the current output voltages VrefH and VrefL may be performed.

In the above-described embodiment, the digital display unit including the LCD is described as an example of the display unit 16. However, the screen for performing the digital display is not limited to the LCD, but other screens such as an organic EL ( Electro-Luminescent) display or the like may be used. Also, instead of the digital display screen, a plurality of hands provided rotatably and a drive unit that rotates these hands, such as a stepping motor and a gear train mechanism, are provided to display analog hands It may be.
In addition, specific details such as the configuration and the control procedure shown in the above embodiment can be changed as appropriate without departing from the spirit of the present invention.

Although several embodiments of the present invention have been described, the scope of the present invention is not limited to the above-described embodiments, and includes the scope of the invention described in the claims and equivalents thereof. .
The invention described in the scope of claims attached to the application of this application will be added below. The item numbers of the claims described in the appendix are as set forth in the claims attached to the application of this application.

[Appendix]
<Claim 1>
A receiver that receives a standard radio wave and outputs a demodulated input signal;
A binarization processing unit that binarizes the voltage of the input signal with a predetermined reference voltage;
A second synchronization identification unit for identifying the leading timing of each second in the input signal;
A high voltage period in which the input signal is always at a high level according to the received standard radio wave format, and the input signal is always at a low level with respect to the leading timing of each second identified by the second synchronization identification unit. Defining a low voltage period, and generating and outputting the reference voltage based on the input signal in the high voltage period and the low voltage period; and
A standard radio wave receiving apparatus comprising:
<Claim 2>
The reference voltage generator is
A plurality of voltage holding units for holding a voltage according to a voltage change of the input signal input;
A switching unit that switches whether the input signal can be input to the voltage holding unit;
A switching control unit that controls the switching operation of the input availability by the switching unit;
A reference voltage output unit that outputs the reference voltage based on the voltage held by the voltage holding unit;
With
The switching control unit causes the first voltage holding unit to input the input signal of the high voltage period among the plurality of voltage holding units, and the second voltage holding unit to input the input signal of the low voltage period. Let
The reference voltage output unit outputs the reference voltage by combining the voltage held by the first voltage holding unit and the voltage held by the second voltage holding unit at a predetermined ratio. Item 2. The standard radio wave receiver according to Item 1.
<Claim 3>
3. The standard radio wave receiver according to claim 2, wherein the predetermined ratio is determined according to an amplitude ratio between the high level input signal and the low level input signal in the standard radio wave to be received.
<Claim 4>
3. The standard radio wave receiving apparatus according to claim 2, wherein the predetermined ratio is 1: 1. <Claim 5>
The reference voltage includes a rising reference voltage for identifying a timing when the input signal switches from a low level to a high level, and a falling reference voltage for identifying a timing when the input signal switches from a high level to a low level. Included,
The reference voltage output unit generates a combination of the voltage held by the first voltage holding unit and the voltage held by the second holding unit at different ratios with respect to the rising reference voltage and the falling reference voltage. The standard radio wave receiver according to claim 2, wherein the standard radio wave receiver is output.
<Claim 6>
The reference voltage output unit includes a resistance element that divides a voltage held by the first voltage holding unit and a voltage held by the second holding unit at a predetermined ratio. The standard radio wave receiver according to any one of the above.
<Claim 7>
The reference voltage generator is
A voltage holding unit that holds a voltage according to a voltage change of the input signal that is input;
A switching unit that switches whether the input signal can be input to the voltage holding unit;
A switching control unit that controls the switching operation of the input availability by the switching unit;
With
The standard radio wave reception according to claim 1, wherein the switching control unit causes the voltage holding unit to input the input signal over a period including the high voltage period and the low voltage period at a predetermined ratio. apparatus.
<Claim 8>
The voltage holding unit includes a third voltage holding unit and a fourth voltage holding unit,
The third voltage holding unit holds a rising reference voltage for identifying the timing when the input signal switches from a low level to a high level, and the fourth voltage holding unit holds the input signal at a high level. A falling reference voltage is identified to identify when to switch from low to low,
The switching control unit causes the input signal to be input to the third voltage holding unit and the fourth voltage holding unit at the predetermined ratio corresponding to the rising reference voltage and the falling reference voltage, respectively. The standard radio wave receiver according to claim 7.
<Claim 9>
Until the start timing of each second is identified by the second synchronization identification unit,
The switching control unit continues to input the input signal to the voltage holding unit,
The standard radio wave receiver according to any one of claims 2 to 8, wherein the voltage holding unit holds a voltage obtained by transmitting a voltage change of the input signal through a low band in a predetermined band.
<Claim 10>
The voltage holding unit includes a capacitor provided between an input terminal and a ground terminal of the input signal, and holds a voltage corresponding to a charge charged in the capacitor according to a voltage change of the input signal. The standard radio wave receiver according to claim 2, wherein:
<Claim 11>
An oscillation unit that generates a predetermined frequency signal;
An error storage unit for storing information relating to an error from an accurate frequency of the predetermined frequency signal;
With
The said reference voltage production | generation part correct | amends and determines the said high voltage period and the said low voltage period based on the said error of the said predetermined frequency signal, The Claim 1 characterized by the above-mentioned. Standard radio wave receiver.
<Claim 12>
The standard radio wave receiver according to any one of claims 1 to 11,
A timer for counting the current date and time based on the predetermined frequency signal and the error;
A date and time correction unit for correcting the date and time counted by the timer unit based on date and time data acquired by the standard radio wave receiver;
A display unit for displaying the time and date counted,
A radio-controlled timepiece characterized by comprising:

1 radio time clock 10 standard radio wave receiver 11 CPU
12 ROM
12a Correction data 13 RAM
14 Power supply unit 15 Operation unit 16 Display unit 17 Driver 18 Oscillation circuit 19 Frequency division circuit 20 Timekeeping circuit 21 Reception antenna 22 Radio wave reception unit 221 RF amplifier 222 Mixer 223 OSC
224 BPF
225 IF amplifier 226 Detection circuit 227 AGC circuit 228, 228a, 228b, 228c Waveform shaping circuit 2280, 2280b, 2280d Comparator 2281a First switching element 2281b Second switching element 2281c Switching element 2281d Switching element 2282a Resistance element 2282b Resistance element 2282c Resistance element 2282d Resistance element 2283a First capacitor 2283b Second capacitor 2283c, 2283d Capacitor 2284a First operational amplifier 2284b Second operational amplifier 2285a, 2285b, 2285c, 2285d Resistance element 2286 Selection switch 2289, 2289a, 2289b, 2289c Reference voltage generation circuit 229 ADC

Claims (12)

A receiver that receives a standard radio wave and outputs a demodulated input signal;
A binarization processing unit that binarizes the voltage of the input signal with a predetermined reference voltage;
A second synchronization identification unit for identifying the leading timing of each second in the input signal;
A high voltage period in which the input signal is always at a high level according to the received standard radio wave format, and the input signal is always at a low level with respect to the leading timing of each second identified by the second synchronization identification unit. Defining a low voltage period, and generating and outputting the reference voltage based on the input signal in the high voltage period and the low voltage period; and
A standard radio wave receiving apparatus comprising: The reference voltage generator is
A plurality of voltage holding units for holding a voltage according to a voltage change of the input signal input;
A switching unit that switches whether the input signal can be input to the voltage holding unit;
A switching control unit that controls the switching operation of the input availability by the switching unit;
A reference voltage output unit that outputs the reference voltage based on the voltage held by the voltage holding unit;
With
The switching control unit causes the first voltage holding unit to input the input signal of the high voltage period among the plurality of voltage holding units, and the second voltage holding unit to input the input signal of the low voltage period. Let
The reference voltage output unit outputs the reference voltage by combining the voltage held by the first voltage holding unit and the voltage held by the second voltage holding unit at a predetermined ratio. Item 2. The standard radio wave receiver according to Item 1.   3. The standard radio wave receiver according to claim 2, wherein the predetermined ratio is determined according to an amplitude ratio between the high level input signal and the low level input signal in the standard radio wave to be received.   3. The standard radio wave receiving apparatus according to claim 2, wherein the predetermined ratio is 1: 1. The reference voltage includes a rising reference voltage for identifying a timing when the input signal switches from a low level to a high level, and a falling reference voltage for identifying a timing when the input signal switches from a high level to a low level. Included,
The reference voltage output unit generates a combination of the voltage held by the first voltage holding unit and the voltage held by the second holding unit at different ratios with respect to the rising reference voltage and the falling reference voltage. The standard radio wave receiver according to claim 2, wherein the standard radio wave receiver is output.   The reference voltage output unit includes a resistance element that divides a voltage held by the first voltage holding unit and a voltage held by the second holding unit at a predetermined ratio. The standard radio wave receiver according to any one of the above. The reference voltage generator is
A voltage holding unit that holds a voltage according to a voltage change of the input signal that is input;
A switching unit that switches whether the input signal can be input to the voltage holding unit;
A switching control unit that controls the switching operation of the input availability by the switching unit;
With
The standard radio wave reception according to claim 1, wherein the switching control unit causes the voltage holding unit to input the input signal over a period including the high voltage period and the low voltage period at a predetermined ratio. apparatus. The voltage holding unit includes a third voltage holding unit and a fourth voltage holding unit,
The third voltage holding unit holds a rising reference voltage for identifying the timing when the input signal switches from a low level to a high level, and the fourth voltage holding unit holds the input signal at a high level. A falling reference voltage is identified to identify when to switch from low to low,
The switching control unit causes the input signal to be input to the third voltage holding unit and the fourth voltage holding unit at the predetermined ratio corresponding to the rising reference voltage and the falling reference voltage, respectively. The standard radio wave receiver according to claim 7. Until the start timing of each second is identified by the second synchronization identification unit,
The switching control unit continues to input the input signal to the voltage holding unit,
The standard radio wave receiver according to any one of claims 2 to 8, wherein the voltage holding unit holds a voltage obtained by transmitting a voltage change of the input signal through a low band in a predetermined band.   The voltage holding unit includes a capacitor provided between an input terminal and a ground terminal of the input signal, and holds a voltage corresponding to a charge charged in the capacitor according to a voltage change of the input signal. The standard radio wave receiver according to claim 2, wherein: An oscillation unit that generates a predetermined frequency signal;
An error storage unit for storing information relating to an error from an accurate frequency of the predetermined frequency signal;
With
The said reference voltage production | generation part correct | amends and determines the said high voltage period and the said low voltage period based on the said error of the said predetermined frequency signal, The Claim 1 characterized by the above-mentioned. Standard radio wave receiver. The standard radio wave receiver according to any one of claims 1 to 11,
A timer for counting the current date and time based on the predetermined frequency signal and the error;
A date and time correction unit for correcting the date and time counted by the timer unit based on date and time data acquired by the standard radio wave receiver;
A display unit for displaying the time and date counted,
A radio-controlled timepiece characterized by comprising:

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