JP5384029B2 - MIS gate structure type HEMT device and method for manufacturing MIS gate structure type HEMT device - Google Patents

Description

  The present invention relates to a MIS gate structure type HEMT device, and more particularly to a normally-off type HEMT device.

  Nitride semiconductors are attracting attention as semiconductor materials for next-generation high-frequency / high-power devices because they have a high breakdown electric field and a high saturation electron velocity. In particular, the layered structure of group III nitride materials such as AlGaN / GaN and AlInN / GaN generates a high concentration of two-dimensional electron gas at the layer interface due to the large polarization effect (spontaneous polarization effect and piezoelectric polarization effect) unique to nitride materials. Can be stored. Development of a high electron mobility transistor (HEMT) using this has been actively carried out (see Non-Patent Document 1 and Non-Patent Document 2).

  In transistor elements (power transistors) used for power applications, it is desired to achieve both high breakdown voltage and low on-resistance. In addition, in order to make fail-safe and power supply circuit simpler and more compact, it is generally a normally-off type device in which main current does not flow unless a gate voltage is applied, that is, the threshold voltage is positive. Is desired.

  A technique for realizing the shift of the threshold voltage to the positive side by thinning the AlGaN barrier layer is already known (see Non-Patent Document 3 and Non-Patent Document 4).

"Highly Reliable 250W GaN High Electron Mobility Transistor Power Amplifier" Japanese Journal of Applied Physics, Vol. 44, No. 7A, 2005, pp. 4896-4901 "Design and Demonstration of High Breakdown Voltage GaN High Electron Mobility Transistor (HEMT) Using Field Plate Structure for Power Electonics Applications" Japanese Journal of Applied Physics, Vol. 43, No. 4B, 2004, pp. 2239-2242 "Non-Recessed-Gate Enhancement-Mode AlGaN / GaN High Electron Mobility Transistors with High RF Performance" Japanese Journal of Applied Physics, Vol. 43, No. 4B, 2004, pp. 2255-2258 "Enhancement-Mode AlGaN / AlN / GaN High Electron Mobility Transistor with Low On-state Resistance and High Breakdown Voltage" Japanese Journal of Applied Physics Vol. 45, No. 44, 2006, pp. L1168-L1170

  For example, when an n-channel transistor such as a GaN-based HEMT device is of a normally-off operation type, the main current does not flow unless a gate voltage is applied in the vicinity of 3 V or more, not in the vicinity of 0 V, from the viewpoint of preventing malfunction due to external noise. It is more desirable. That is, it is desirable that the threshold voltage is + 3V or higher.

  Non-Patent Document 1 and Non-Patent Document 2 only disclose GaN-based HEMT elements that are normally on and exhibit low on-resistance. Of course, there is no disclosure or suggestion of a normally-off operation type GaN HEMT device having a low on-resistance and a threshold voltage of +3 V or more.

  Further, when the HEMT device is formed by the method disclosed in Non-Patent Document 3 and Non-Patent Document 4, the piezoelectric effect is suppressed due to the thinning of the AlGaN barrier layer, and a sufficiently high two-dimensional electron gas There is a problem that the concentration cannot be secured and the on-resistance is not reduced. In addition, since a Schottky junction is used for the gate portion, a gate voltage exceeding the Schottky barrier height (about +1.2 V at the maximum) cannot be applied, and a threshold voltage of +3 V or more, which is said to be a safe operating area of the normally-off device. There is also a problem that cannot be secured.

  The present invention has been made in view of the above problems, and an object thereof is to realize a normally-off operation type HEMT element having excellent characteristics.

In order to solve the above problems, the invention of claim 1 is a MIS gate structure type HEMT device including an insulating layer between a gate electrode and a semiconductor layer, wherein the semiconductor layer has an N-type conductivity type. And a specific resistance of 1 × 10 ⁷ Ωcm or more, or a P-type conductivity type base layer made of a first group III nitride, and formed adjacent to the base layer and the insulating layer. And a barrier layer made of a second group III nitride having a band gap larger than that of the first group III nitride, so that the base layer has a two-dimensional electron gas in the vicinity of the interface with the barrier layer. And a source electrode and a drain electrode are formed on the barrier layer. In the semiconductor layer, a P-type region having a P-type conductivity is formed immediately below the insulating layer. The gate electrode from the surface side Within hiding substantially to the gate electrode when facing, Ri Sonawa to penetrate the barrier layer and the two-dimensional electron gas region, the P-type region, Mg-doped as an acceptor It is characterized by comprising a main P-type region made of GaN and a sub-P-type region which is a diffusion region of Mg contained in the main P-type region .

The invention of claim 2 is a MIS gate structure type HEMT device comprising an insulating layer between a gate electrode and a semiconductor layer, wherein the semiconductor layer has an N-type conductivity type and a specific resistance of 1 ×. A base layer made of a first group III nitride having a P type conductivity of 10 ⁷ Ωcm or more, and formed adjacent to the base layer and the insulating layer; A barrier layer made of a second group III nitride having a larger band gap than the group nitride, so that the base layer has a two-dimensional electron gas region in the vicinity of the interface with the barrier layer, and a source electrode And a drain electrode are formed on the barrier layer. In the semiconductor layer, a P-type region having a P-type conductivity is directly below the insulating layer, and the gate electrode When the game is viewed from the front side, the game Within hiding substantially to the electrode, the barrier layer Ri Sonawa with greater thickness than, the P-type region, and the main P-type region of GaN with Mg as the acceptor-doped, the main P-type And a sub-P-type region which is a diffusion region of Mg contained in the conversion region .

A third aspect of the present invention is the MIS gate structure type HEMT device according to the first or second aspect , wherein the thickness of the insulating layer is t (nm) and the ratio of the substances forming the insulating layer is When the dielectric constant is k, k / t ≦ 0.85 (nm ⁻¹ ).

A fourth aspect of the present invention is the MIS gate structure type HEMT device according to any one of the first to third aspects, wherein the second group III nitride is AlGaN.

A fifth aspect of the present invention is the MIS gate structure type HEMT device according to any one of the first to fourth aspects, wherein the base layer uses GaN as the first group III nitride and remains. It is formed as a layer having an N-type conductivity type with an electron concentration by donor of 1 × 10 ¹² / cm ³ or less.

A sixth aspect of the present invention is the MIS gate structure type HEMT device according to any one of the first to fifth aspects, wherein the base layer and the barrier layer are between 0.75 nm and 1.5 nm in length. A layer made of AlN having the following thickness is inserted.

The invention of claim 7 is a method of manufacturing a MIS gate structure type HEMT device comprising an insulating layer between a gate electrode and a semiconductor layer, and a-1) an N-type conductivity type on a predetermined substrate And forming a base layer having a specific resistance of 1 × 10 ⁷ Ωcm or more or having a P-type conductivity by doping a first group III nitride with a predetermined dopant And a-2) a barrier layer forming step of forming a barrier layer on the base layer using a second group III nitride having a band gap larger than that of the first group III nitride. Providing a two-dimensional electron gas region forming step for forming a two-dimensional electron gas region in the vicinity of the interface of the base layer with the barrier layer; and b-1) removing the barrier layer and a part of the base layer. In addition, the removed portion is buried and the upper surface is A main P-type region forming step of forming a main P-type region made of GaN while doping Mg so as to be substantially continuous with the upper surface of the layer; b-2) Mg doped in the main P-type region An activation step of performing an activation process for activation, and a P-type region comprising the main P-type region and a sub-P-type region that is a diffusion region of Mg contained in the main P-type region Forming a P-type region within a range that is substantially hidden by the gate electrode when viewed from the surface side, and c) forming the insulating layer on the upper surface of the semiconductor layer. Forming an insulating layer; and d) forming a source electrode and a drain electrode at a predetermined position on the upper surface of the barrier layer, and forming a gate electrode at a predetermined position on the upper surface of the insulating layer. It is characterized by providing.

The invention according to claim 8 is the method for manufacturing the MIS gate structure type HEMT device according to claim 7 , wherein, in the insulating layer forming step, the thickness of the insulating layer is t, and the insulating layer is formed. The insulating layer is formed so that ε / t ≦ 0.85 (nm ⁻¹ ), where k is a relative dielectric constant of the substance to be processed.

A ninth aspect of the invention is a method of manufacturing a MIS gate structure type HEMT device according to the seventh or eighth aspect of the invention, wherein the second group III nitride is AlGaN.

A tenth aspect of the present invention is a method of manufacturing a MIS gate structure type HEMT device according to any one of the seventh to ninth aspects, wherein in the base layer forming step, the base layer is the first layer. GaN is used as the group III nitride, and is formed as a layer having an N-type conductivity type with an electron concentration of 1 × 10 ¹² / cm ³ or less due to a residual donor.

The invention of claim 11 is a method for manufacturing a MIS gate structure type HEMT device according to any one of claims 7 to 10, between the barrier layer forming step and the base layer forming step, An AlN layer forming step for forming a layer made of AlN having a thickness of 0.75 nm or more and 1.5 nm or less is inserted.

The invention of claim 12 is a MIS gate structure type HEMT device, those made by any of the manufacturing methods of claims 7 to 11.

According to the first to twelfth aspects of the present invention, by forming a two-dimensional electron gas region in the vicinity of the heterojunction interface between the base layer and the barrier layer, an access site, that is, between the drain and the gate, between the gate and the source, is formed. The access resistance is sufficiently small, and a P-type region is formed immediately below the gate so as to have a so-called inversion channel type MIS transistor structure, thereby providing a normally-off type having a low on-resistance. The HEMT device can be realized.

In particular, according to the inventions of claims 3 and 8 , a normally-off HEMT element having a high threshold voltage of +3 V or more can be realized.

<First Embodiment>
<Configuration of HEMT element>
FIG. 1 is a diagram schematically showing the configuration of the HEMT device 10 according to the first embodiment. FIG. 1A is a schematic cross-sectional view of the entire configuration of the HEMT element 10. As shown in FIG. 1A, the HEMT device 10 according to the present embodiment is roughly shown on a substrate 1, a semiconductor layer 2, an insulating layer 6, a gate electrode 7, and a source electrode. 8 and a drain electrode 9. That is, the HEMT element 10 has a MIS gate structure in which the insulating layer 6 is formed between the semiconductor layer 2 and the gate electrode 7. The semiconductor layer 2 includes a base layer 3, a barrier layer 4, and a P-type region 5.

  The substrate 1 is preferably a single crystal 6H—SiC substrate, but any material can be used as long as it can form a III nitride semiconductor layer such as the base layer 3 and the barrier layer 4 with good crystallinity. There are no particular restrictions. That is, it may be appropriately selected from sapphire, SiC, Si, GaAs, spinel, MgO, ZnO, ferrite and the like.

The base layer 3 and the barrier layer 4 are laminated on the substrate 1 in this order. The base layer 3 is a high resistance layer made of group III nitride, having an N-type conductivity, and having a high specific resistance of 1 × 10 ⁷ Ωcm or more. Preferably, the base layer 3 is formed so that the electron concentration by the residual donor is 1 × 10 ¹² / cm ³ or less. Further, the base layer 3 is preferably formed to a thickness of about several μm, for example, about 3 μm. On the other hand, the barrier layer 4 is a layer having an N-type conductivity type constituted by a group III nitride having a larger band gap than the group III nitride forming the base layer 3. The barrier layer 4 is preferably formed to a thickness of about several tens of nm, for example, about 15 to 25 nm. For example, the base layer 3 is preferably made of GaN, and the barrier layer 4 is preferably made of Al _x Ga _1-x N (0 <x <1). However, in such a case, it is preferable that x ≦ 0.5. When x> 0.5, the surface state of the barrier layer 4 may be deteriorated. Or may be a manner of forming a _{In p Al q Ga r N (} 0 ≦ p ≦ 1,0 ≦ q ≦ 1,0 ≦ r <1, p + q + r = 1) barrier layer 4 at.

  In the heterojunction interface obtained by laminating the base layer 3 and the barrier layer 4 as described above, spontaneous polarization and piezo polarization occur, and this causes a few nm from the laminating interface of both layers in the base layer 3. The so-called two-dimensional electron gas is stored in a high concentration in the range of. That is, the two-dimensional electron gas region 3g is formed. Thereby, in the HEMT element 10, the access resistance, that is, the access resistance between the drain-gate and the gate-source is sufficiently small.

  For the purpose of ensuring good crystallinity in the semiconductor layer 2, a so-called buffer layer made of AlN having a thickness of about several tens of nm is formed between the substrate 1 and the semiconductor layer 2 (actually, the base layer 3). (Not shown) may be provided.

  P-type region 5 is a region formed to have a P-type conductivity type. The P-type region 5 is formed so as to penetrate the barrier layer 4 and the two-dimensional electron gas region 3g, reach the base layer 3, and have an upper surface substantially continuous with the upper surface of the barrier layer 4. . From another viewpoint, it can be said that the P-type region 5 is formed to have a thickness larger than that of the barrier layer 4.

  The P-type region 5 is below the gate electrode 7, and when the HEMT element 10 is viewed from the surface side (upper surface side), the upper surface portion of the P-type region 5 is substantially the gate electrode 7. It is formed so as to be coated.

  FIG. 1B is a schematic cross-sectional view of the HEMT element 10 in the vicinity of a portion surrounded by a circle P in FIG. However, illustration of the insulating layer 6 and the gate electrode 7 is omitted. As shown in FIG. 1B, the P-type region 5 includes a main P-type region 5a and a sub-P-type region 5b. The main P-type region 5a and the sub-P-type region 5b are common in that they have a P-type conductivity type, but their origins are different. Note that the size relationship between the main P-type region 5a and the sub-P-type region 5b shown in FIG. 1B is for convenience of illustration, and the actual ratio is different.

  The main P-type region 5a is a region made of GaN containing Mg so as to act as an acceptor on a part of the laminated structure in which the base layer 3 and the barrier layer 4 are laminated on the substrate 1. 4 is formed so as to be embedded from the upper surface side. For example, as will be described later, a barrier layer 4 and a part of the base layer 3 that have been formed once are removed by etching to form a recess, and then the recess is doped with Mg that acts as an acceptor. This is realized by growing a crystal made of GaN.

  On the other hand, the sub-P-type region 5b is a process of activation processing performed so that Mg contained in GaN constituting the main P-type region 5a acts as an acceptor after the formation of the main P-type region 5a. Mg in the main P-type region 5a diffuses into the peripheral region, that is, the region formed to have the N-type conductivity as the base layer 3 and the barrier layer 4, thereby making the region P-type. This is a region formed by doing so. In other words, the sub-P-type region 5b exists on the outer periphery of the main P-type region 5a and the peripheral region, that is, the interface on the actual structure (location indicated by the arrow AR1 in FIG. 1A). It is an area. The interface between the sub-P-type region 5b formed in this way and the outer peripheral region (the location indicated by the arrow AR2 in FIG. 1B) is a PN junction interface. The presence of the two interfaces at different positions as described above can be confirmed, for example, by analyzing the cross section of the HEMT device 10 as shown in FIG. 1 by SEM, EDX, or ToF-SIMS. Is possible.

The P-type region 5 has an Mg concentration of about 1 × 10 ¹⁸ / cm ³ to 1 × 10 ²⁰ / cm ³ , for example, 5 × 10 ¹⁹ / cm ³ , and a hole concentration of 5 × 10 ¹⁷ / cm ^{3 to} 5. It is preferable to be formed so as to be about × 10 ¹⁸ / cm ³ , for example, about 1 × 10 ¹⁸ / cm ³ .

The insulating layer 6 is a layer formed so as to cover the upper surfaces of the barrier layer 4 and the P-type region 5. The insulating layer 6 can be formed to a thickness of about several nanometers to one hundred nanometers using an insulating material such as SiO ₂ . As will be described later, since the threshold voltage in the HEMT element 10 is determined by the relationship between the film thickness of the insulating layer 6 and the relative dielectric constant of the substance forming the insulating layer 6, the film thickness and constituent materials of the insulating layer 6 are determined. Is preferably selected to achieve the desired threshold voltage.

  The gate electrode 7 is formed on the upper surface of the insulating layer 6. The source electrode 8 and the drain electrode 9 are formed so as to have an ohmic contact with the barrier layer 4 after providing a contact hole in a part of the insulating layer 6. The gate electrode 7, the source electrode 8, and the drain electrode 9 are preferably provided as multilayer electrodes made of Ti / Al / Ni / Au.

<Operation and characteristics of HEMT element>
Next, the operation of the HEMT element 10 having the above configuration will be described. FIG. 2 is a diagram illustrating an operation state of the HEMT element 10.

First, in the bias free state (the source electrode 8 is grounded (source voltage V _s = 0)) in which the gate voltage V _G and the drain voltage V _D are 0 shown in FIG. 2A, as described above, the base layer 3 A two-dimensional electron gas region 3g is formed in the vicinity of the interface with the barrier layer 4.

Next, when a bias voltage is applied to the drain electrode 9 (V _D = + V), as shown in FIG. 2B, when the gate voltage V _G is smaller than the threshold voltage V _p (V _G <V _p ). The depletion region DR extends from the P-type region 5 to the periphery, and no main current flows between the drain and source. However, as shown in FIG. 2C, when the gate voltage V _G is equal to or higher than the threshold voltage V _p (V _G ≧ V _p ), the inverted channel region 5c having a thickness of about 10 nm is formed in the vicinity of the surface of the P-type region 5. Is formed, and electrons move as indicated by an arrow AR3, so that the main current I _D flows.

  That is, the HEMT element 10 has a so-called inverted channel type MIS transistor structure.

6 and 7 are diagrams showing an example of the result of evaluating the electrical characteristics of the HEMT element 10. The result shown in FIG. 6 is that a 6H—SiC single crystal substrate is used as the substrate 1, the base layer 3 is 3 μm thick, the residual electron concentration is about 5 × 10 ¹¹ / cm ³ , and the specific resistance is 1 × 10 ⁷ Ωcm or more. A HEMT device 10 formed by forming a GaN layer, forming an Al _0.2 Ga _0.8 N layer having a thickness of 25 nm as the barrier layer 4, and varying the thickness of the SiO ₂ layer as the insulating layer 6 (implementation) Example 1). Further, the results shown in FIG. 7 are for a HEMT device 10 manufactured with various gate lengths while the thickness of the SiO ₂ layer as the insulating layer 6 is set to 5 nm. The results shown in FIG. 6 and FIG. 7 mean that a normally-off operation type HEMT device having a low on-resistance and a high threshold voltage is realized.

In particular, from the results shown in FIG. 6, when the thickness of the SiO ₂ layer (described as SiO ₂ film thickness in FIG. 6) is at least 5 nm or more, the HEMT device 10 having a threshold voltage of +3 V or more is realized. I understand that.

When the thickness of the insulating layer 6 is t (nm) and the relative dielectric constant of the material forming the insulating layer 6 is k,
k / t ≦ 0.85 (nm ⁻¹ ) (Formula 1)
It is confirmed by the inventor of the present invention that a high threshold voltage V _{p of} +3 V or higher is realized by satisfying this relationship. For example, when SiO ₂ having a relative dielectric constant of about 3.8 to 4.0 is used for the insulating layer 6, the threshold voltage V _{p of} +3 V or more is formed by forming the insulating layer 6 with a thickness of about 5 nm or more. Is feasible.

  Moreover, according to the results shown in FIGS. 6 and 7, in the HEMT device 10, the maximum current, the maximum transconductance, the on-resistance, the withstand voltage, the leakage current at the time of reverse blocking, and the like characterize the electrical characteristics of the HEMT device. Good values are also obtained for. Among these, the on-resistance is 4.5 Ωmm to 5.3 Ωmm, which is a value as small as that of the normally-on operation type. This is understood to be due to the fact that the access resistance at the access site is sufficiently reduced by forming the two-dimensional electron gas region 3g having a sufficient two-dimensional electron gas concentration.

<Method for Manufacturing HEMT Element>
Next, a manufacturing method of the HEMT device 10 according to the present embodiment that realizes the excellent characteristics as described above will be described. In addition, the manufacturing method shown below is an illustration to the last, and the manufacturing method of the HEMT element 10 which has the above characteristics is not restricted to this.

FIG. 3 is a diagram showing a flow of manufacturing the HEMT element 10. Hereinafter, a 6H-SiC single crystal substrate with a (0001) orientation is used as the substrate 1, a GaN layer is formed as the base layer 3, an Al _0.2 Ga _0.8 N layer is formed as the barrier layer 4, and SiO ₂ is formed as the insulating layer 6. A case where a layer is formed will be described as an example. In the following description, it is assumed that a large number of HEMT elements 10 are manufactured simultaneously using the substrate 1.

  The manufacturing procedure shown in FIG. 3 can be roughly described as follows. First, a heterojunction is formed by stacking the base layer 3 and the barrier layer 4, and then a part of the stacked portion is removed to form a P-type instead. An insulating layer and an electrode are formed after the region 5 is formed.

  First, the base layer 3 and the barrier layer 4 constituting the semiconductor layer 2 are sequentially epitaxially formed on the substrate 1 by MOCVD (metal organic chemical vapor deposition) which is a known technique (step S1). . Hereinafter, the laminated structure thus obtained is referred to as an element formation substrate.

For example, after the substrate 1 is placed on a susceptor in an MOCVD furnace, the base layer 3 is heated to a predetermined temperature between 1000 ° C. and 1200 ° C., for example, 1100 ° C. in a predetermined atmosphere. In the state, it can be formed by introducing TMG bubbling gas and NH ₃ gas into the MOCVD furnace. At this time, before depositing the base layer 3 on the substrate 1, a so-called buffer layer (not shown) made of GaN or AlN having a thickness of about several tens to several hundreds nm can be provided. Here, the temperature of the susceptor on which the substrate 1 is placed (set heating temperature) is referred to as the temperature of the substrate 1 (substrate temperature).

The barrier layer 4 can be formed by introducing TMA, TMG, and NH ₃ gas into the MOCVD furnace while maintaining the substrate temperature after the base layer 3 is formed as described above.

  When the element forming substrate is obtained, first, element separation processing is performed to partition the surface according to the size of each HEMT element. Such a process is not a process that is theoretically required for realizing the HEMT device according to the present embodiment, and therefore detailed description thereof is omitted. For example, a known photolithography process and RIE (reactivity) are omitted. A groove having a depth of about 400 nm may be formed at the boundary position of each element using an ion etching method.

Next, in order to form a mask pattern for forming a P-type region on the surface of the element formation substrate, a mask layer 11 is formed (step S2). As the mask layer 11, it is a preferable example to form a SiO ₂ film having a thickness of about several hundred nm. The film formation of the mask layer 11 can be realized by a vapor phase growth process such as a plasma CVD method.

  Then, by using a photolithography process, a portion that becomes the upper surface portion of the main P-type region 5a (after the gate electrode 7 is formed, the gate electrode 7 is substantially formed in a plan view from the surface side). The mask layer 11 is removed only (within a range to be hidden) (step S3). As a result, a mask pattern for forming a P-type region is obtained.

  Next, a recess 12 is formed by performing removal processing (etching) on a portion not covered with the mask layer 11 by RIE (step S4). The recess 12 needs to have a depth that penetrates at least the barrier layer 4 and the two-dimensional electron gas region 3g. As described above, the barrier layer 4 is formed with a thickness of about several tens of nm, and the two-dimensional electron gas region 3g is formed with a thickness of about several nm at most. It can be said that it is sufficient to perform processing at a depth (processing depth).

  When processing by RIE is performed in this manner, processing for forming the P-type region 5 is subsequently performed (step S5).

Specifically, first, the element forming substrate is again placed on the susceptor in the MOCVD furnace, and then heated to a predetermined temperature between 1000 ° C. and 1200 ° C., for example, 1100 ° C. in a predetermined atmosphere. Then, each bubbling gas of CP ₂ Mg and TMG and NH ₃ gas are introduced into the MOCVD furnace. Here, the SiO ₂ film used as a mask for RIE processing acts as a mask for selective epitaxial growth as it is. That is, epitaxial growth of GaN containing Mg occurs only in the recess 12 formed by RIE processing. Thereby, the main P-type region 5a is formed.

  However, since Mg does not function sufficiently as an acceptor as it is, the element forming substrate after the recess 12 is filled is heated to a predetermined temperature between 500 ° C. and 900 ° C., for example, 600 ° C. in order to activate Mg. Then, heat treatment (Mg activation treatment) is performed by heating for 10 minutes to 50 minutes, for example, 30 minutes. During the formation process of the main P-type region 5a and the Mg activation process, Mg diffuses from the main P-type region 5a to the periphery, and the sub-P-type region 5b is formed. That is, the P-type region 5 composed of the main P-type region 5a and the sub-P-type region 5b is formed. In FIG. 3, for the sake of illustration, the main P-type region 5a and the sub-P-type region 5b are not distinguished, and only the P-type region 5 is illustrated.

  After forming the P-type region 5, the mask layer 11 is removed by wet etching (step S6). For example, buffered hydrofluoric acid is preferably used as the etchant. By such wet etching, a state in which the upper surface of the P-type region 5 and the upper surface of the barrier layer 4 are substantially continuous is obtained.

Next, an SiO ₂ layer as an insulating layer 6 is formed on the P-type region 5 and the barrier layer 4 so as to cover at least the upper surface of the P-type region 5 (step S7). The formation of the SiO ₂ layer can be realized by, for example, a vapor phase growth process such as a plasma CVD method.

After forming the SiO ₂ layer, by a photolithography process, the source electrode 8 in the SiO ₂ layer, and the formation position of the drain electrode 9, a contact hole 13 and 14 (step S8).

  After the contact holes 13 and 14 are formed, the gate electrode 7, the source electrode 8, and the drain electrode 9 are formed (step S9). Specifically, first, a metal pattern made of Ti / Al / Ni / Au (film thickness is 25/75/15/100 nm, respectively) is formed at the position where each electrode is formed using a vacuum deposition method and a photolithography process. Form. Subsequently, in order to make the ohmic property of the source electrode 8 and the drain electrode 9 good, it is 20 seconds to 120 seconds at a predetermined temperature between 600 ° C. and 1000 ° C., for example, 850 ° C. in a nitrogen atmosphere. For example, heat treatment is performed for 30 seconds.

  Through the above process, the HEMT device 10 according to the present embodiment is formed.

  The semiconductor layer 2 may be formed by a technique other than the MOCVD method as long as the semiconductor layer 2 having good crystallinity can be formed. For example, a formation method appropriately selected from vapor phase growth methods such as MBE, HVPE, and LPE and liquid phase growth methods may be used, or different growth methods may be used in combination.

  As described above, according to the present embodiment, by forming a two-dimensional electron gas region in the vicinity of the heterojunction interface between the high resistance base layer and the barrier layer, an access site, that is, between the drain and gate, The access resistance between the gate and the source is made sufficiently small, and a p-type region is formed immediately below the gate so as to have a so-called inversion channel type MIS transistor structure. A Mary-off type HEMT device can be realized. Furthermore, a normally-off HEMT element having a high threshold voltage of +3 V or higher can be realized by satisfying a predetermined relationship between the relative dielectric constant and the film thickness of the insulating layer.

<Second Embodiment>
In the first embodiment described above, the base layer 3 has an N-type conductivity type and is formed as a high resistance layer having a high specific resistance of 1 × 10 ⁷ Ωcm or more. Instead of this, the base layer 3 may be made of a group III nitride having P-type conductivity. For example, the base layer 3 is composed of GaN containing Mg as an acceptor. In this case, the hole concentration at room temperature is preferably about 1 × 10 ¹⁶ / cm ³ , for example, about 2 × 10 ¹⁶ / cm ³ so that the hole concentration is about 1 × 10 ¹⁶ / cm ³ to 1 × 10 ¹⁸ / cm ^3. is there.

  Since the HEMT element 20 has the same structure as the HEMT element 10 according to the first embodiment shown in FIG. 1A as the overall structure, detailed description of each part is omitted. However, the configuration of the P-type region 5 is slightly different.

  FIG. 4 is a diagram schematically showing the configuration of the P-type region in the HEMT element 20. In the HEMT device 20, although the main P-type region 5a is formed in the same manner as the HEMT device 10 according to the first embodiment, since the base layer 3 originally has a P-type conductivity type, Mg diffusion The sub-P-type region 5b as a region is formed only between the main P-type region 5a and the barrier layer 4. In other words, a PN junction interface is formed only between the sub P-type region 5b and the barrier layer 4 (indicated by an arrow AR4 in FIG. 4).

The HEMT device 20 is manufactured by replacing the substrate 1 with a temperature between 1000 ° C. and 1200 ° C. instead of forming the base layer 3 in step S1 of the method of manufacturing the HEMT device 10 according to the first embodiment shown in FIG. It can be formed by introducing each CP ₂ Mg, TMG bubbling gas and NH ₃ gas into the MOCVD furnace in a state where the temperature is raised to a predetermined temperature of, for example, 1100 ° C. under a predetermined atmosphere.

  12 and 13 are diagrams illustrating an example of the result of evaluating the electrical characteristics of the HEMT element 20. The results shown in FIGS. 12 and 13 are for a HEMT device manufactured in the same manner as the HEMT device 10 whose characteristics are illustrated in FIGS. 6 and 7 except for the base layer 3 (see Example 2).

The results shown in FIG. 12 show that even when the base layer 3 is P-type, the threshold voltage is +3 V or more when the thickness of the SiO ₂ layer (described as SiO ₂ film thickness in FIG. 12) is at least 5 nm or more. This means that the HEMT device of FIG. Further, according to the results shown in FIGS. 12 and 13, the HEMT device 20 also has the maximum current, the maximum transconductance, the on-resistance, the withstand voltage, the leakage current at the time of blocking in the reverse direction, etc. that characterize the electrical characteristics of the HEMT device. Good values are also obtained for the evaluation values. These results show that even when the base layer 3 is P-type, a normally-off operation type HEMT device having a low on-resistance and a high threshold voltage of +3 V or more is realized. is there.

  Therefore, according to this embodiment, even when the base layer has a P-type conductivity type, the two-dimensional electron gas region is formed in the vicinity of the heterojunction interface between the base layer and the barrier layer. The access region, that is, the access resistance between the drain-gate and the gate-source is sufficiently small, and a P-type region is formed immediately below the gate so as to have a so-called inversion channel type MIS transistor structure. Thus, a normally-off type HEMT device having a low on-resistance can be realized. Furthermore, a normally-off HEMT element having a high threshold voltage of +3 V or higher can be realized by satisfying a predetermined relationship between the relative dielectric constant and the film thickness of the insulating layer.

<Third Embodiment>
FIG. 5 is a diagram schematically showing the configuration of the HEMT device 30 according to the third embodiment. In the present embodiment, the same reference numerals are given to the constituent elements having the same effects as the constituent elements of the HEMT element 10 according to the first embodiment, and the detailed description thereof is omitted. The HEMT element 30 is the same as the HEMT element 10 according to the first embodiment in that it has a MIS gate structure having the insulating layer 6 between the semiconductor layer 2 and the gate electrode 7. The difference is that an AlN layer (AlN spacer layer) 31 composed of AlN is inserted between the base layer 3 and the barrier layer 4.

  The AlN layer 31 is a layer that is inserted for the purpose of suppressing a decrease in electron mobility that occurs when the two-dimensional electron gas region 3 g is partially immersed in the barrier layer 4. Thereby, higher mobility can be obtained in the two-dimensional electron gas region 3g, and the access resistance can be further reduced. From the viewpoint of fulfilling such a purpose, the AlN layer 31 is preferably formed to a thickness of 0.75 nm or more and 1.5 nm or less.

The AlN layer 31 is formed by a TMA bubbling gas between the formation of the base layer 3 and the formation of the barrier layer 4 in step S1 of the method for manufacturing the HEMT device 10 according to the first embodiment shown in FIG. And NH ₃ gas can be realized by introducing them into the MOCVD furnace.

  14 and 15 are diagrams illustrating an example of the result of evaluating the electrical characteristics of the HEMT element 30. FIG. The results shown in FIGS. 14 and 15 are for HEMT elements manufactured in the same manner as the HEMT element 10 whose characteristics are illustrated in FIGS. 6 and 7 except that the AlN layer 31 is inserted (Example 3). Reference). These results show that the formation of the AlN layer 31 can provide a HEMT element having a high threshold voltage and further excellent characteristics as in the HEMT element 10 according to the first embodiment. ing.

  That is, according to the present embodiment, it is shown that by providing an AlN layer between the base layer and the barrier layer, a HEMT element having a high threshold voltage and superior characteristics can be obtained.

Example 1
In this example, a plurality of 2 inch diameter 6H-SiC substrates having a (0001) plane orientation are prepared as the substrate 1, and the HEMT device 10 according to the first embodiment is replaced with the thickness of the SiO ₂ film as the insulating layer 6. The gate length was made differently. The thickness of the SiO ₂ film was set to 4 levels of 2.5 nm, 5 nm, 7.5 nm, and 10 nm. For the SiO ₂ film having a thickness of 5 nm, the gate length was set to four levels of 0.1 μm, 0.2 μm, 0.5 μm, and 1 μm. For other thicknesses, the gate length was 0.2 μm. In any HEMT element 10, the gate width was 1 mm, the source-gate distance was 0.5 μm, and the gate-drain distance was 7.5 μm. The formation of the semiconductor layer 2 was performed based on conditions such as the growth rate and composition determined in a preliminary experiment performed in advance.

  First, as a process corresponding to step S1 in FIG. 3, the base layer 3 and the barrier layer 4 constituting the semiconductor layer 2 were formed by MOCVD.

  Specifically, first, the substrate 1 was placed in an MOCVD furnace and replaced with a vacuum gas. Then, an atmosphere in a hydrogen / nitrogen mixed flow state was formed, and the temperature was raised to 1100 ° C. by susceptor heating.

When the substrate temperature reached 1100 ° C., TMA bubbling gas and NH ₃ gas were introduced into the MOCVD furnace, and an AlN layer as a buffer layer was formed to a thickness of 200 nm.

Subsequently, while maintaining the substrate temperature at 1100 ° C., TMG bubbling gas and NH ₃ gas were introduced into the MOCVD, and a GaN layer as the base layer 3 was formed to a thickness of 3 μm. When a single GaN layer grown under the same conditions was examined, it was found to be an n-type semiconductor layer having a residual electron concentration at room temperature of about 5 × 10 ¹¹ / cm ³ and a specific resistance of 1 × 10 ⁷ Ωcm or more. Was confirmed.

Further, while maintaining the substrate temperature at 1100 ° C., TMA, TMG, and NH ₃ gas were introduced into the MOCVD furnace, and an Al _0.2 Ga _0.8 N layer as the barrier layer 4 was formed to a thickness of 25 nm.

  After the temperature was lowered to around room temperature, the obtained element forming substrate was taken out from the NOCVD furnace.

At this time, a part of the element forming substrate was cut and hole measurement was performed. As a result, the sheet resistance was 420 Ω / □, and the electron mobility was about 1400 cm ² / Vs.

  Subsequently, a groove portion having a depth of about 400 nm was formed at the boundary position of each element by photolithography process and RIE method as element separation processing on the obtained element formation substrate.

After the element isolation process, as a process corresponding to step S2, a SiO ₂ film as a mask layer 11 was formed to a thickness of 300 nm on the element formation substrate by plasma CVD.

After the formation of the SiO ₂ film, a portion corresponding to the upper surface portion of the main P-type region 5a (after the gate electrode 7 is formed, the gate electrode 7 is planarized from the surface side as a process corresponding to step S3 by a photolithography process. The SiO ₂ film was removed only within a range that would be substantially hidden by the gate electrode 7 when viewed. Thus, a mask pattern for forming a P-type region was obtained.

Subsequently, as a process corresponding to step S4, a recess 12 was formed in a portion not covered with the SiO ₂ film by the RIE method. Here, the RIE processing depth was about 100 nm.

  After the formation of the recess 12, a process corresponding to step S5 was performed. First, the element formation substrate was placed again on the susceptor in the MOCVD furnace, vacuum gas replacement was performed, and then the substrate was heated to 1100 ° C. by susceptor heating while forming a hydrogen / nitrogen flow mixed atmosphere.

When the substrate temperature reached 1100 ° C., Cp ₂ Mg and TMG bubbling gases and NH ₃ gas were introduced into the reactor, and the main P-type region 5 a made of Mg-doped GaN was formed in the recess 12. After the temperature was lowered to near room temperature, the element formation substrate was taken out of the MOCVD furnace, and subsequently, heat treatment was performed at 600 ° C. for 30 minutes in nitrogen as an activation treatment of Mg.

With respect to the P-type region 5 formed at this time, the results of SIMS and Hall effect measurement on the element forming substrate manufactured under the same conditions show that the Mg concentration is about 5 × 10 ¹⁹ / cm ³ and the hole concentration. Has been confirmed in advance to be about 1 × 10 ¹⁸ / cm ³ .

After the activation process, as a process corresponding to step S6, the SiO ₂ film as the mask layer 11 was removed by etching using buffered hydrofluoric acid.

Further, as a process corresponding to step S7, an SiO ₂ film (relative dielectric constant k = 4) as an insulating layer 6 was formed by plasma CVD.

After the formation of the SiO ₂ film, as a process corresponding to step S8, the SiO ₂ film at the positions where the source electrode 8 and the drain electrode 9 are formed is removed by etching using a photolithography process to form contact holes 13 and 14. .

  After the contact holes 13 and 14 were formed, an electrode formation process corresponding to step S9 was performed. First, a metal pattern made of Ti / Al / Ni / Au (film thickness is 25/75/15/100 nm, respectively) is formed on the gate electrode 7, the source electrode 8, and the drain electrode 9 using a vacuum deposition method and a photolithography process. Each electrode was obtained by performing heat treatment at 850 ° C. for 30 seconds in nitrogen in order to improve ohmic properties after forming at each formation position.

  As described above, the HEMT device 10 according to the first exemplary embodiment is obtained. Further, the fabricated HEMT device 10 was cleaved so as to be parallel to the source-drain main current path, and the fracture surface was observed by SEM and EDX. As a result, the interface was outside the main p-type region 5a. It was confirmed that a pn junction interface exists. That is, it was confirmed that the sub-P-type region 5b as the Mg diffusion region was formed.

  Further, in order to make it possible to evaluate the electrical characteristics of the HEMT device 10, a silicon nitride passivation film is formed using a CVD method and a photolithography process, and then contact holes are formed in each electrode portion and wire bonding is performed. It was.

In this state, the electrical characteristics of the HEMT element 10 were evaluated. Specifically, the threshold voltage, maximum current, maximum transconductance, on-resistance, withstand voltage, and leakage current when blocking in the reverse direction were measured. 6 and 7 are diagrams showing a list of evaluation results of the electrical characteristics. These results indicate that the HEMT element 10 is obtained as a normally-off operation type HEMT element having a low on-resistance and a positive threshold voltage. In particular, as shown in FIG. 6, when an SiO ₂ film is used as an insulating layer, a normally-off operation type HEMT device having a high threshold voltage of +3 V or more can be realized by setting the thickness of the insulating layer to 5 nm or more. I understand. Further, FIG. 7 shows that a normally-off operation type HEMT element having a high threshold voltage of +3 V or more is realized regardless of the gate length.

(Comparative Example 1)
In this comparative example, a normally-on operation type HEMT device was fabricated. FIG. 8 is a schematic cross-sectional view of the entire configuration of the normally-off operation type HEMT device 100. In general, the HEMT device 100 includes a semiconductor layer 102 on a substrate 101, and has a gate electrode 107, a source electrode 108, and a drain electrode 109 on the semiconductor layer 102. The semiconductor layer 102 is formed by stacking a base layer 103 and a barrier layer 104. A protective layer 106 is formed on a portion (access region portion) other than the electrode formation portion on the upper surface of the semiconductor layer 102.

  In manufacturing the HEMT device 100, the gate length was set to four levels of 0.1 μm, 0.2 μm, 0.5 μm, and 1 μm. In any HEMT device, the gate width was 1 mm, the source-gate distance was 0.5 μm, and the gate-drain distance was 7.5 μm.

  First, the same processes as in Example 1 were performed until the fabrication of the element formation substrate and the subsequent element separation process. That is, a 6H—SiC single crystal substrate having the same (0001) plane orientation as that of the substrate 1 of the first embodiment is used as the substrate 101, and the base layer 103 and the barrier layer 104 are respectively connected to the base layer 3 and the barrier layer 4 of the first embodiment. It produced similarly.

Thereafter, the SiO ₂ film as a mask to form a thickness of 10nm on the substrate for device formation is removed the gate electrode 107 by a photolithography process, a source electrode 108, a SiO ₂ film forming position of the drain electrode 109 by etching Thus, a mask pattern was formed.

  After the formation of the mask pattern, a SiN film as a protective layer 106 was formed to a thickness of 300 nm only in the access region portion by using a CVD method and a photolithography process.

  After the formation of the SiN film, a metal pattern made of Ti / Al / Ni / Au (film thickness is 25/75/15/100 nm, respectively) is formed between the source electrode 108 and the drain electrode 109 by a vacuum deposition method and a photolithography process. A source electrode 108 and a drain electrode 109 were obtained by performing heat treatment at 850 ° C. for 30 seconds in nitrogen in order to improve the ohmic properties of the source and drain electrodes. .

  After the source electrode 108 and the drain electrode 109 are formed, a Schottky metal pattern made of Pd / Au (film thickness is 30/100 nm, respectively) is formed at the formation position of the gate electrode 107 by using a vacuum deposition method and a photolithography process. Thus, the gate electrode 107 was obtained.

  Thereby, the HEMT device 100 was obtained. The HEMT element 100 was evaluated for electrical characteristics in the same manner as in Example 1. FIG. 9 is a diagram showing a list of evaluation results of the electrical characteristics. The results shown in FIG. 9 indicate that the HEMT element 100 is obtained as a normally-on operation type HEMT element.

(Contrast between Example 1 and Comparative Example 1)
When the HEMT element 10 according to Example 1 shown in FIG. 7 and the HEMT element 100 according to Comparative Example 1 shown in FIG. 9 are compared with respect to the same gate length, the HEMT element 10 according to Example 1 is It can be said that a threshold voltage as high as +3.2 V is realized while having characteristics similar to those of the marion-on operation type HEMT device 100.

(Comparative Example 2)
In this comparative example, the thickness of the barrier layer 104 is changed to three levels of 5, 7.5, and 10 nm, and the gate length of the barrier layer 104 having a thickness of 5 nm is made to be four levels as in the first embodiment. A HEMT device was manufactured in the same procedure as in Comparative Example 1 except that

In addition, when the element formation substrate was manufactured according to each manufacturing condition, a part of the substrate was cut and hole measurement was performed. As a result, when the thickness of the barrier layer 104 is 5, 7.5, and 10 nm, the sheet resistances are 1500, 900, and 750 Ω / □, respectively, and the electron mobilities are 940, 960, and 980 cm ² / Vs, respectively. It was about.

  The obtained HEMT device was evaluated for electric characteristics in the same manner as in Example 1. 10 and 11 are diagrams showing a list of evaluation results of the electrical characteristics. The results shown in FIGS. 10 and 11 show that only a HEMT device having a barrier layer thickness (described as an AlGaN film thickness in FIGS. 10 and 11) of 5 nm is a normally-off operation type HEMT device having a positive threshold voltage. It shows that it is obtained.

(Contrast between Example 1 and Comparative Example 2)
When the HEMT element 10 according to the first embodiment shown in FIGS. 6 and 7 and the HEMT element according to the second comparative example shown in FIGS. 10 and 11 are compared with each other having the same gate length, the HEMT according to the first embodiment is compared. It can be seen that the element has a sufficiently higher threshold voltage and a sufficiently low on-resistance than the HEMT element according to Comparative Example 2. It can also be seen that the HEMT device according to Example 1 has higher values for the maximum current and the maximum transconductance. That is, it can be said that the HEMT device 10 according to Example 1 is a normally-off operation type HEMT device having better characteristics than the HEMT device manufactured by thinning the barrier layer.

(Example 2)
In this example, the HEMT device 20 according to the second embodiment was manufactured in the same procedure as in Example 1 except that the base layer 3 was formed of a GaN layer having P-type conductivity.

In the present embodiment, the GaN layer as the base layer 3 is formed by raising the temperature of the substrate 1 to 1100 ° C. in the same manner as in the first embodiment, and then bubbling each gas of Cp ₂ Mg, TMG and NH ₃ gas into the reactor. Done by introducing. The thickness of the GaN layer was 1.5 μm. When a single-layer GaN layer grown under the same conditions was examined, it was confirmed that the hole concentration at room temperature was about 2 × 10 ¹⁶ / cm ³ .

In addition, about the element formation board | substrate obtained by forming the base layer 3 and the barrier layer 4, the part was cut | disconnected and hole measurement was performed before performing the process of a back | latter stage. The sheet resistance was 1500Ω / □, and the electron mobility was about 800 cm ² / Vs.

  The finally obtained HEMT device 20 was cleaved so as to be parallel to the source-drain main current path, and its fracture surface was observed with SEM and EDX. It was confirmed that a pn junction interface exists outside the interface of the region 5a. That is, it was confirmed that the sub-P-type region 5b as the Mg diffusion region was formed.

The obtained HEMT device 20 was evaluated for electrical characteristics in the same manner as in Example 1. 12 and 13 are diagrams showing a list of evaluation results of the electrical characteristics. These results indicate that the HEMT element 20 is obtained as a normally-off operation type HEMT element having a positive threshold voltage. In particular, as shown in FIG. 12, even when the base layer 3 has a P-type conductivity, as in the case of Example 1, if the SiO ₂ film is used as an insulating layer, the thickness of the insulating layer is at least 5 nm. By doing so, it is understood that a normally-off operation type HEMT device having a high threshold voltage of +3 V or more is realized. Further, FIG. 13 shows that a normally-off operation type HEMT element having a high threshold voltage of +3 V or more is realized regardless of the gate length.

(Contrast between Example 2 and Comparative Example 2)
When the HEMT device 20 according to the second embodiment shown in FIGS. 12 and 13 and the HEMT device according to the second comparative example shown in FIGS. 10 and 11 are compared with each other having the same gate length, the HEMT according to the second embodiment is compared. The element 20 is inferior in terms of maximum current and maximum transconductance. This is understood to be caused by the low electron mobility. However, the HEMT device according to Example 2 has a sufficiently higher threshold voltage than the HEMT device according to Comparative Example 2. Therefore, it can be said that the HEMT device 20 according to Example 2 is superior from the viewpoint of operation stability and reliability.

(Example 3)
A HEMT device 30 according to the third embodiment was manufactured in the same procedure as in Example 1, except that the AlN layer 31 was formed between the formation of the base layer 3 and the barrier layer 4. . The AlN layer 31 was formed by introducing TMA bubbling gas and NH ₃ gas into the MOCVD furnace while maintaining the substrate temperature at 1100 ° C. after forming the GaN layer as the base layer 3. The thickness of the AlN layer 31 was 1 nm.

Moreover, about the element formation board | substrate obtained by forming the base layer 3, the AlN layer 31, and the barrier layer 4, the part was cut | disconnected and hole measurement was performed before performing the latter process. As a result, the sheet resistance was 250Ω / □, and the electron mobility was about 2200 cm ² / Vs.

  The obtained HEMT device 30 was cleaved so as to be parallel to the source-drain main current path, and its fracture surface was observed with SEM and EDX. It was confirmed that a bonding interface exists. That is, it was confirmed that the sub-P-type region 5b as the Mg diffusion region was formed.

  Further, the electrical characteristics of the HEMT element 30 were evaluated in the same manner as in Example 1. 14 and 15 are diagrams showing a list of evaluation results of the electrical characteristics.

  The HEMT device 30 has a high threshold voltage equivalent to that of the HEMT device 10 according to the first embodiment that does not include the AlN layer 31, and the on-resistance is slightly smaller than that of the HEMT device 10. Further, the maximum current and the maximum transconductance are slightly larger than those of the HEMT element 10. That is, it can be said that the HEMT element 30 according to the present example is superior in characteristics to the HEMT element 10 according to the first embodiment.

Example 4
In this example, the HEMT device 10 according to the first exemplary embodiment was manufactured in the same procedure as in Example 1 except that the composition of the barrier layer 4 and the thickness thereof were different. However, the thickness of the SiO ₂ film as the insulating layer 6 was 5 nm and the gate length was 0.2 μm. At that time, the sheet resistance of the element forming substrate obtained by forming the base layer 3 and the barrier layer 4 is also measured.

The obtained HEMT device 10 was evaluated for electrical characteristics in the same manner as in Example 1. FIG. 16 is a table showing the evaluation results of the electrical characteristics together with the composition, film thickness, and sheet resistance of the barrier layer 4 of each HEMT device 10. FIG. 16 also shows the evaluation results of the HEMT device 10 manufactured in Example 1 having the same SiO ₂ film thickness and gate length.

  From FIG. 16, if the barrier layer 4 is formed of group III nitride, the on-resistance is small and high as +3 V or higher, as in Example 1, even if the composition and film thickness are variously changed. It can be seen that the HEMT device 10 having the threshold voltage is realized. It can also be seen that the characteristics of the HEMT element depend on the sheet resistance because the maximum current and the maximum transconductance increase as the sheet resistance decreases.

(Example 5)
In this example, a HEMT device 10 was fabricated in the same manner as in Example 1 except that the type of material constituting the insulating layer 6 (hereinafter also referred to as insulating film type) and the thickness thereof were different. There are four types of insulating films: SiO ₂ film, SiN _x film, Al ₂ O ₃ film, and HfO ₂ film. In either case, the gate length was 0.2 μm. FIG. 17 is a table showing a list of insulating film types, film forming methods, relative dielectric constants, and minimum film thicknesses (rounded to the second decimal place) for satisfying Equation 1.

  About the obtained HEMT element 10, the threshold voltage was evaluated. FIG. 18 is a diagram showing the relationship between the thickness of the insulating layer 6 and the threshold voltage for the HEMT element 10 in which the insulating layer 6 is configured by each insulating film type.

  FIG. 18 shows that the threshold voltage increases as the thickness of the insulating layer 6 increases regardless of the type of insulating film. Then, by forming the insulating layer 6 with a thickness equal to or larger than the minimum film thickness shown in FIG. 17, a normally-off operation type HEMT device having a high threshold voltage of +3 V or higher is realized regardless of the type of insulating film. I understand that.

It is a figure which shows schematically the structure of the HEMT element 10 which concerns on 1st Embodiment. FIG. 3 is a diagram showing an operating state of the HEMT element 10. 3 is a diagram showing a flow of manufacturing the HEMT element 10. FIG. It is a figure which shows typically the structure of the P-type-ized area | region in the HEMT element 20 which concerns on 2nd Embodiment. It is a figure which shows schematically the structure of the HEMT element 30 which concerns on 3rd Embodiment. FIG. 6 is a diagram showing evaluation results of electrical characteristics of the HEMT device according to Example 1. FIG. 6 is a diagram showing evaluation results of electrical characteristics of the HEMT device according to Example 1. 6 is a schematic cross-sectional view of the entire configuration of a normally-off operation type HEMT device according to Comparative Example 1. FIG. It is a figure which shows the evaluation result of the electrical property of the HEMT element which concerns on the comparative example 1. FIG. It is a figure which shows the evaluation result of the electrical property of the HEMT element which concerns on the comparative example 2. FIG. It is a figure which shows the evaluation result of the electrical property of the HEMT element which concerns on the comparative example 2. FIG. It is a figure which shows the evaluation result of the electrical property of the HEMT element which concerns on Example 2. FIG. It is a figure which shows the evaluation result of the electrical property of the HEMT element which concerns on Example 2. FIG. It is a figure which shows the evaluation result of the electrical property of the HEMT element which concerns on Example 3. FIG. It is a figure which shows the evaluation result of the electrical property of the HEMT element which concerns on Example 3. FIG. It is a figure which shows the evaluation result of the electrical property of the HEMT element which concerns on Example 4. FIG. FIG. 10 is a diagram showing conditions for forming an insulating layer in a HEMT device according to Example 5. It is a figure which shows the relationship between the thickness of the insulating layer of the HEMT element which concerns on Example 5, and threshold voltage.

Explanation of symbols

1, 101 Substrate 2, 102 Semiconductor layer 3, 103 Base layer 3g Two-dimensional electron gas region 4, 104 Barrier layer 5 P-type region 5a Main P-type region 5b Sub-P-type region 5c Inverted channel region 6 Insulating layer 7 107 gate electrode 8, 108 source electrode 9, 109 drain electrode 10, 20, 30, 100 HEMT element 11 mask layer 12 recess 13, 14 contact hole 106 protective layer DR depletion region

Claims (12)

A MIS gate structure type HEMT device including an insulating layer between a gate electrode and a semiconductor layer,
The semiconductor layer is
A base layer made of a first group III nitride having an N-type conductivity type and a specific resistance of 1 × 10 ⁷ Ωcm or more, or a P-type conductivity type;
A barrier layer made of a second group III nitride formed adjacent to the base layer and the insulating layer and having a larger band gap than the first group III nitride;
The base layer has a two-dimensional electron gas region in the vicinity of the interface with the barrier layer,
A source electrode and a drain electrode are formed on the barrier layer;
In the semiconductor layer,
A P-type region having a P-type conductivity is located immediately below the insulating layer and within a range substantially hidden by the gate electrode when the gate electrode is viewed from the surface side. Ri Sonawa to pass through the two-dimensional electron gas region,
The P-type region includes a main P-type region made of GaN doped with Mg as an acceptor, and a sub-P-type region that is a diffusion region of Mg contained in the main P-type region.
A MIS gate structure type HEMT device characterized by the above. A MIS gate structure type HEMT device including an insulating layer between a gate electrode and a semiconductor layer,
The semiconductor layer is
A base layer made of a first group III nitride having an N-type conductivity type and a specific resistance of 1 × 10 ⁷ Ωcm or more, or a P-type conductivity type;
A barrier layer made of a second group III nitride formed adjacent to the base layer and the insulating layer and having a larger band gap than the first group III nitride;
The base layer has a two-dimensional electron gas region in the vicinity of the interface with the barrier layer,
A source electrode and a drain electrode are formed on the barrier layer;
In the semiconductor layer,
A P-type region having a P-type conductivity is located immediately below the insulating layer and within a range that is substantially hidden by the gate electrode when the gate electrode is viewed from the surface side. also Ri Sonawa a large thickness,
The P-type region includes a main P-type region made of GaN doped with Mg as an acceptor, and a sub-P-type region that is a diffusion region of Mg contained in the main P-type region.
A MIS gate structure type HEMT device characterized by the above. A MIS gate structure type HEMT device according to claim 1 or 2,
When the thickness of the insulating layer is t (nm) and the relative dielectric constant of the material forming the insulating layer is k,
k / t ≦ 0.85 (nm ⁻¹ )
MIS gate structure type HEMT device, characterized in that at. A MIS gate structure type HEMT device according to any one of claims 1 to 3,
MIS gate structure type HEMT device, wherein the second group III nitride is AlGaN . A MIS gate structure type HEMT device according to any one of claims 1 to 4,
The base layer is formed as a layer having an N-type conductivity type using GaN as the first group III nitride and having an electron concentration due to a residual donor of 1 × 10 ¹² / cm ³ or less.
A MIS gate structure type HEMT device characterized by the above. A MIS gate structure type HEMT device according to any one of claims 1 to 5,
A layer made of AlN having a thickness of 0.75 nm or more and 1.5 nm or less is inserted between the base layer and the barrier layer.
A MIS gate structure type HEMT device characterized by the above. A method of manufacturing a MIS gate structure type HEMT device including an insulating layer between a gate electrode and a semiconductor layer,
a-1) On a predetermined substrate, a base layer having an N-type conductivity and having a specific resistance of 1 × 10 ⁷ Ωcm or more or having a P-type conductivity is formed on the first group III Forming a base layer by doping a nitride with a predetermined dopant; and
a-2) a barrier layer forming step of forming a barrier layer on the base layer using a second group III nitride having a band gap larger than that of the first group III nitride;
A two-dimensional electron gas region forming step of forming a two-dimensional electron gas region in the vicinity of the interface between the base layer and the barrier layer,
b-1) While removing part of the barrier layer and the base layer, while doping Mg so that the removed part is buried and the upper surface is substantially continuous with the upper surface of the barrier layer A main P-type region forming step for forming a main P-type region made of GaN;
b-2) an activation process for performing an activation treatment for activating Mg doped in the main P-type region;
A P-type region composed of the main P-type region and a sub-P-type region that is a diffusion region of Mg contained in the main P-type region when the gate electrode is viewed in plan from the surface side Forming a P-type region in a range that is substantially hidden by the gate electrode;
c) an insulating layer forming step of forming the insulating layer on the upper surface of the semiconductor layer;
d) an electrode forming step of forming a source electrode and a drain electrode at a predetermined position on the upper surface of the barrier layer, and forming a gate electrode at a predetermined position on the upper surface of the insulating layer;
A method of manufacturing a MIS gate structure type HEMT device characterized by comprising : A manufacturing method of a MIS gate structure type HEMT device according to claim 7 ,
In the insulating layer forming step, when the film thickness of the insulating layer is t and the relative dielectric constant of the material forming the insulating layer is k,
k / t ≦ 0.85 (nm ⁻¹ )
A method of manufacturing a MIS gate structure type HEMT device , wherein the insulating layer is formed as follows . A method for manufacturing a MIS gate structure type HEMT device according to claim 7 , wherein:
A method of manufacturing a MIS gate structure type HEMT device, wherein the second group III nitride is AlGaN . We claim 7 A manufacturing method of a MIS gate structure type HEMT device according to any one of claims 9,
In the base layer forming step, the base layer is made of GaN as the first group III nitride, and has an N-type conductivity type with an electron concentration by a residual donor of 1 × 10 ¹² / cm ³ or less. Form,
A method of manufacturing a MIS gate structure type HEMT device characterized by the above. A method for manufacturing a MIS gate structure type HEMT device according to any one of claims 7 to 10,
Between the base layer forming step and the barrier layer forming step, an AlN layer forming step for forming a layer made of AlN having a thickness of 0.75 nm to 1.5 nm is inserted.
A method of manufacturing a MIS gate structure type HEMT device characterized by the above. 7. to MIS gate structure type HEMT element produced by the method for manufacturing a MIS gate structure type HEMT device according to any one of claims 11.

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