JP5382503B2 - Branching program machine and parallel processor - Google Patents

Description

  In the present invention, a branching program machine (BM) and a branching program machine capable of performing operations that simulate a multiple-valued decision diagram (MDD) are connected in parallel. The present invention relates to a multistage branching program machine (multistage branching program machine) and a parallel processor in which multistage branching program machines are connected in parallel.

  A branching program machine that simulates a binary decision graph (hereinafter referred to as “BDD (Binary Decision Diagram)”) is a processor having two types of instructions, a branch instruction and an output instruction (see Non-Patent Documents 1 and 2). ). Thus, the branching program machine has a simpler architecture than a general purpose processor. In addition, conditional branches that are often used in control circuits and the like are executed by dedicated instructions, so that a specific application can perform processing at a higher speed than a general-purpose processor. Examples of branching program machine applications include control circuits, circuit simulators, network device routing tables, packet classification, and pattern matching. As a conventional branching program machine, one that simulates BDD for a binary input variable is known (see Non-Patent Documents 1 and 2).

P. C. Baracos, R. D. Hudson, L. J. Vroomen, and P. J. A. Zsombor-Murray, "Advances in binary decision based programmable controllers," IEEE Transactions on Industrial Electornics, Vol. 35, No. 3, pp. 417-425, Aug., 1988. R. T. Boute, "The binary-decision machine as programmable controller," Euromicro Newsletter, Vol. 1, No. 2, pp. 16-22, 1976. R. E. Bryant, "Graph-based algorithms for boolean function manipulation," IEEE Trans. Comput., Vol. C-35, No. 8, pp. 677-691, Aug. 1986. Y. Iguchi, T. Sasao, and M. Matsuura, "Evaluation of multiple-output logic functions," Asia and South Pacific Design Automation Conference'2003, Kitakyushu, Japan, pp. 312-315, Jan. 21-24, 2003 . T. Kam, T. Villa, RK Brayton, and AL Sagiovanni-Vincentelli, "Multi-valued decision diagrams: Theory and Applications," Multiple-Valued Logic, Vol. 4, No. 1-2, pp. 9-62, 1998. Y. Iguchi, T. Sasao, and M. Matsuura, "Implementation of multiple-output functions using PROMDDs," 30th International Symposium on Mulitple-Valued Logic, Portland, Oreon, USA, pp. 199-205, May 23-25 2000 . S. Nagayama, T. Sasao, Y. Iguchi, and M. Matsuura, "Area-time complexities of multi-valued decision diagrams," IEICE Transactions on Fundamentals of Electronics, Vol. E87-A, No. 5, pp. 1020 -1028, May 2004. S. Nagayama, and T. Sasao, "On the optimization of heterogeneous MDDs," IEEE Transactions on CAD, Vol. 24, No. 11, pp. 1645-1659, Nov. 2005.

  An arbitrary n-input logical function can be expressed by BDD (Non-patent Document 3). A BDD representing a multi-output logic function is called an MTBDD (multi-terminal binary decision diagram), and multiple outputs can be evaluated simultaneously with at most n table references (Non-patent Document 4). FIG. 1 shows an example of MTBDD. The average value of the number of table references is called the average path length. The BDD evaluation time is proportional to the average path length.

By the way, as a method for further reducing the BDD evaluation time, a method using a multi-valued logic decision graph (hereinafter referred to as “MDD (Multiple-valued Decision Diagram)”) is known (see Non-Patent Document 5). In MDD, an input variable is divided into a set of k binary variables. A set of ^k binary variables becomes a super variable of 2 ^k values. The decision diagram representing a super variable 2 ^k values referred to MDD (k). BDD is equivalent to MDD (1).

  Since MDD (2) has four branches at each node, MDD (2) is referred to as QDD (Quaternary Decision Diagram) in this paper. An MDD in which the number of binary variables in each group when the input variables are grouped is the same as a “homogeneous MDD”. On the other hand, an MDD in which the number of binary variables in each group is not all equal is referred to as “heterogeneous MDD”.

  Heterogeneous MDD can reduce the number of table references and the number of nodes compared to homogeneous MDD by devising variable grouping (grouping) (see Non-Patent Document 8). Hereinafter, in this paper, heterogeneous MTQDD (multi-terminal quaternary decision diagram) is simply referred to as QDD. FIG. 2 shows a QDD obtained by converting the MTBDD of FIG. In the QDD of FIG. 2, only the highest node has two branches, and the other nodes have four branches.

When a logical function is expressed in MDD (k), the number of memory references can often be reduced to 1 / k compared to when expressed in BDD (Non-patent Document 6). Therefore, when k is increased, the logical function evaluation time can be shortened. However, the amount of memory required to represent one node increases in the order of 2 ^k. Therefore, in many benchmark functions, the total memory amount of MDD (k) when k = 2 is minimized (see Non-Patent Document 7). Therefore, it can be said that QDD is more suitable than BDD in evaluating logical functions.

  Therefore, an object of the present invention is to provide a branching program machine capable of executing an operation that simulates such QDD. Another object of the present invention is to provide a multistage branching program machine in which branching program machines are connected in parallel and a parallel processor in which multistage branching program machines are connected in parallel for further speeding up. There is to do.

A branching program machine according to the present invention includes a variable input bus to which a plurality of input variables are input,
An input selector for selecting an input variable from the variable input bus;
An input register in which an input variable selected by the input selector is temporarily set;
An output register in which the output variable is set;
A variable output bus to which an output variable set in the output register is output;
An instruction memory in which each instruction to be executed in the program is stored;
An instruction register in which instructions sequentially read from the instruction memory are temporarily set;
An instruction decoder that executes the instruction based on an input variable read from the input register and an instruction read from the instruction register;
A program counter for storing address information in an instruction memory of an instruction to be read next;
A branching program machine with
The instruction memory includes (1) an index of an input variable to be referred to, address information of an instruction memory to be jumped when the input variable is 0, and address information of an instruction memory to be jumped to when the input variable is 1. (2) The index of the input variable to be referenced, the address information of the instruction memory to jump to when the input variable is the first value, and the jump when the input variable is the second value The address information of the previous instruction memory, the 3-address 4-branch instruction including the address information of the previous instruction memory to jump when the input variable is the third value, and (3) the address information of the output register of the output destination, And an instruction series including at least three types of output instructions including output data are stored, and according to the address information set in the program counter, And outputs a command stored in the address commanded dress information in the instruction register,
When the instruction set in the instruction register is the 2-address 2-branch instruction or the 3-address 4-branch instruction, the instruction decoder is input by the input selector based on an index of an input variable designated by the instruction. Select a variable and set it in the input register. Based on the value of the input variable set in the input register, select the address information of the instruction memory to jump specified by the instruction and set it in the program counter. (B) When the instruction set in the instruction register is the output instruction, the address of the output register instructed by the address information according to the address information of the output register specified by the instruction is A process for setting output data specified by the instruction is executed.

  With this configuration, it is possible to execute an operation that simulates QDD.

  In the present invention, the 3-address 4-branch instruction stored in the instruction memory includes an index of an input variable to be referred to, a function selection flag for designating a combination of a branch destination address with respect to the value of the input variable, and an input variable. The address information ADDR0 of the instruction memory to jump to when the value is the first value, the address information ADDR1 of the instruction memory to jump to when the input variable is the second value, and the address information ADDR1 to the jump value when the input variable is the third value Including the address information ADDR2 of the instruction memory to jump to, and when the instruction set in the instruction register is the 3-address 4-branch instruction, the instruction decoder is based on the index of the input variable specified by the instruction. An input variable is selected by the input selector and set in the input register, and the value of the input variable set in the input register is the first, second, second In the case of the value of, the address information ADDR0, ADDR1, ADDR2 of the instruction memory to be jumped designated by the instruction is selected, and the values of the input variables set in the input register are the first and second values, respectively. If the value is other than the third value, the address information of the address (P + 1) next to the address P of the current instruction can be selected and set in the program counter.

  In the multistage branching program machine according to the present invention, the branching program machine is connected in series, and at least part of the variable input bus of the branching program machine at the subsequent stage includes the preceding stage at the preceding stage. The variable output bus of the branching program machine is connected, and input variables are input to the remaining variable input buses.

  By thus connecting the branching program machines in multiple stages in series, a larger logical function can be calculated.

  In the present invention, the variable output bus of each branching program machine is connected to the variable input bus of a subsequent branching program machine via a programmable routing box. can do.

  As a result, the order of the output variables of the branching program machine at each stage can be freely rearranged and input as input variables of the subsequent branching program machine. Therefore, it is easy to code the instructions of the branching program machine at each stage for realizing the sequential circuit.

A parallel processor according to the present invention includes a plurality of branching program machines described above connected in parallel,
A plurality of selection input nodes and a plurality of selection output nodes, each variable output bus of each multi-stage branching program machine is connected to each selection input node, and at least a part of the selection output nodes A programmable interconnection circuit connected to a part of a variable input bus of a multistage branching program machine and capable of recombining the connection between each selected input node and each selected output node, To do.

  Thereby, parallel calculation becomes possible, and the calculation speed of the logical function can be further increased.

  As described above, according to the branching program machine of the present invention, it is possible to execute an operation that simulates QDD. In addition, according to the multistage branching program machine of the present invention, it is possible to perform a larger logical function operation by multistage. Further, according to the parallel processor of the present invention, the operation speed of the logical function can be further increased by parallel operation.

It is an example of MTBDD. It is QDD obtained by converting MTBDD of FIG. It is a block diagram showing the structure of the branching program machine which concerns on Example 1 of this invention. It is a figure which shows the double rank flip-flop which comprises the output register of FIG. It is a figure which shows the mnemonic of each instruction, and memory internal representation. It is a figure which shows the combination of the branch destination address in four types of 3 address 4 branch instructions. This is the result of assigning the addresses of each 3-address 4-branch instruction (Q_BRANCH) by the code of the instruction set in FIG. FIG. 6 is a block diagram illustrating a configuration of a multistage branching program machine according to a second embodiment. FIG. 10 is a block diagram illustrating a configuration of a parallel processor 30 according to a third embodiment.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  FIG. 3 is a diagram illustrating a configuration of a branching program machine (hereinafter, referred to as “BM” for short) according to the first embodiment of the present invention.

  The BM 1 includes a variable input bus 2, an input selector 3, an input register 4, a register file 5, a variable output bus 6, an instruction memory 7, an instruction register 8, an instruction decoder 9, a program counter 10, and a flag output bus 11. Yes.

  The variable input bus 2 is a bus to which a plurality of input variables are input from an external circuit such as an MPU. The input selector 3 is a selector that selects an input variable input from the variable input bus 2. As the input selector 3, a shifter, a crossbar switch, a multiplexer or the like is used. The input register 4 is a register in which an input variable selected by the input selector 3 is temporarily set.

  The instruction memory 7 is a memory in which each instruction to be executed in the program is stored. In this embodiment, the instruction memory 7 can store 256 BM instructions having a word length of 32 bits. The instruction register 8 is a register in which instructions sequentially read from the instruction memory 7 are temporarily set. The instruction decoder 9 is a decoder that interprets and executes an instruction read from the instruction memory 7 to the instruction register 8. The instruction decoder 9 executes the instruction based on the input variable set in the input register 4 and the instruction set in the instruction register 8. The program counter 10 stores address information in the instruction memory 7 of an instruction to be read next.

  Here, the instruction memory 7 includes four types of instruction sets: a 2-address 2-branch instruction (B_BRANCH), a 3-address 4-branch instruction (Q_BRANCH), a data set instruction (output instruction) (DATASET), and an unconditional jump instruction. An instruction sequence is stored. The 2-address 2-branch instruction (B_BRANCH), 3-address 4-branch instruction (Q_BRANCH), and unconditional jump instruction are instructions for evaluating the non-terminal node of MTBDD or QDD, and the data set instruction (DATASET) is the terminal node of QDD. An instruction to evaluate. FIG. 5 shows the mnemonics of each instruction and the internal representation of the memory.

  In order to reduce the length of one instruction, a one-address two-branch instruction that replaces a two-address two-branch instruction (B_BRANCH) has also been proposed (see, for example, Non-Patent Document 2). Execution time often increases. Therefore, in the present invention, a 2-branch instruction using the 2-address method is employed.

  In QDD, an instruction that simultaneously evaluates two variables can be realized by a 4-address 4-branch instruction. The 4-address 4-branch instruction can reduce the evaluation time in half compared to the 2-branch instruction. However, the 4-address 4-branch instruction requires a long instruction word and is not suitable for the standard word length (32 bits) of the current embedded processor. Therefore, in the present invention, a 3-address 4-branch instruction (Q_BRANCH) is employed instead of the 4-address 4-branch instruction.

  FIG. 5A shows a 2-address 2-branch instruction (B_BRANCH). The 2-address 2-branch instruction (B_BRANCH) is an instruction that jumps to one of the two branch destination addresses. The 2-address 2-branch instruction is the index of the input variable to be referenced (INDEX), the address information of the instruction memory to jump to when the input variable is 0 (ADDR0), and the instruction to jump to when the input variable is 1 Contains memory address information (ADDR1). If the value of the variable designated by the index (INDEX) is 0, the program jumps to the address designated by the address information (ADDR0), otherwise jumps to the address designated by the address information (ADDR1). In this embodiment, as shown in FIG. 5A, the address information (ADDR0) and (ADDR1) are expressed by 8 bits, and the input variable index (INDEX) is expressed by 6 bits. The code “111” stored in bits 29-31 in the memory internal representation of the 2-address 2-branch instruction (B_BRANCH) is an instruction identification code indicating that this instruction is a 2-address 2-branch instruction (B_BRANCH). .

  FIG. 5B shows a data set instruction (DATASET). The data set instruction (DATASET) is an instruction for outputting specified data to a specified output register. The data set instruction (DATASET) includes output destination address register address information (REG), output data (DATA), and destination instruction memory address information (ADDR) to be jumped to after execution of the instruction. In this embodiment, as shown in FIG. 5B, the output data (DATA) is expressed by 16 bits, the address information (ADDR) is expressed by 8 bits, and the address information (REG) of the output register is expressed by 6 bits. The code “10” stored in bits 30 to 31 in the internal representation of the data set instruction (DATASET) is an instruction identification code indicating that this instruction is a data set instruction (DATASET).

  FIG. 5C shows a 3-address 4-branch instruction (Q_BRANCH). The 3-address 4-branch instruction (Q_BRANCH) is an instruction that jumps to one of the four branch destination addresses. The 3-address 4-branch instruction (Q_BRANCH) is the index of the input variable to be referenced (INDEX), the function selection flag (SEL) that specifies the combination of the branch destination address for the value of the input variable, and when the input variable is the first value Address information (ADDR0) of the instruction memory to jump to, address information (ADDR1) of the instruction memory to jump to when the input variable is the second value, and destination to jump when the input variable is the third value Instruction memory address information (ADDR2). In this embodiment, as shown in FIG. 5C, the address information (ADDR0), (ADDR1), (ADDR2) is 8 bits, the input variable index (INDEX) is 5 bits, and the function selection flag (SEL) is It is expressed by a total of 31 bits of 2 bits. The code “0” stored in 31 bits in the internal memory representation of the 3-address 4-branch instruction (Q_BRANCH) is an instruction identification code indicating that this instruction is a 3-address 4-branch instruction (Q_BRANCH).

  In the 3-address 4-branch instruction (Q_BRANCH), three of the four branch destination addresses are specified by address information (ADDR0, ADDR1, ADDR2). The remaining one branch destination address is the address (PC + 1) next to the address (PC) of the current instruction.

  In the present invention, four types of 3-address 4-branch instructions as shown in FIG. 6 are used to reduce the evaluation time and the number of steps. The function selection flag (SEL) in the 3-address 4-branch instruction (Q_BRANCH) is a flag for designating one of four types of 3-address 4-branch instructions. Assuming that the variable designated by the index (INDEX) of the input variable is i, jump to the next address (PC + 1) when SEL = i. By devising the address assignment, the number of steps and the execution time can be optimized.

  When using a 3-address 4-branch instruction (Q_BRANCH), the address (PC + 1) next to the current instruction address (PC) conflicts with PC + 1 of another 3-address 4-branch instruction (Q_BRANCH). Cases arise. Therefore, an unconditional jump instruction is required to avoid such contention. The unconditional jump instruction is an instruction for forcibly jumping to a designated address. This unconditional jump instruction is realized by using the above-described 2-address 2-branch instruction (B_BRANCH). In the case of an unconditional jump instruction, an invalid value (for example, “0”) is set in the index (INDEX), and the same jump destination address is set in the address information (ADDR0) and address information (ADDR1). As a result, when the unconditional jump instruction is executed, it jumps unconditionally to the address set in the address information (ADDR0) and (ADDR1) without evaluating the value of the input variable.

  When the instruction set in the instruction register 8 is a 2-address 2-branch instruction (B_BRANCH) or a 3-address 4-branch instruction (Q_BRANCH), the instruction decoder 9 in FIG. Based on the input variable is selected and set in the input register 4 based on the value of the input variable ({0, 1} or {00, 01, 10, 11}) set in the input register 4 The address information ((ADDR0), (ADDR1), (ADDR2)) of the jump destination instruction memory specified by the instruction is selected and set in the program counter 10. When the instruction set in the instruction register 8 is a data set instruction (DATASET), the instruction is stored in the output register in the register file 5 instructed by the address information (REG) of the output register specified by the instruction. A process for setting the output data (DATA) designated by the instruction is executed, the address information (ADDR) of the instruction memory to be jumped designated by the instruction is selected, and a process for setting the program counter 10 is executed.

  The register file 5 in FIG. 3 includes registers called “output registers” and “status registers”, and “input selection registers” and “flag registers”. The output register and the status register are registers in which output variables are set. The output register and the status register are constituted by double rank flip-flops as shown in FIG.

  In FIG. 4, L1 and L2 are D latches. The output register and status register are updated by a data set instruction, but the value of this data set instruction can be updated only every 16 bits. Therefore, when evaluating a circuit having an output or state variable having a larger number of bits than 16 bits, there is a problem that the values of the previous and subsequent states are mixed. Therefore, this double rank flip-flop is used to update the value at a time when the state transition signal (S_Clock) is High.

  An input selection signal (ISR) for selecting a variable set in the input register 4 by the input selector 3 is set in the input selection register.

The flag register is a special register that specifies the operation of BM1. The flag register has “RUN bit”, “IRQ bit”, “RCOPY bit”, “ACT bit”, and “FETCH bit”, and each bit has a specific role as follows.
(1) Only when the “RUN bit” is 1, the program counter 10 of the BM 1 is updated.
(2) When the “IRQ bit” is 1, an interrupt signal is sent to the outside.
(3) When the “RCOPY bit” is 1, data transfer of the double rank flip-flop is performed.
(4) When the “ACT bit” is 1, it activates a circuit for connecting BM1 described later.
(5) When the “FETCH bit” is 1, the value is taken into the input register 4.

  The variable output bus 6 is a bus through which output variables and state variables set in the output registers and state registers in the register file 5 are output. The flag output bus 11 is a bus to which each flag set in the flag register in the register file 5 is output.

  The BM 1 can realize a sequential circuit by feeding back the output variable set in the output register to the input register 4. In the input register 4, these fed back values, external inputs, and output variables sent from the adjacent BM 1 are set. These are selected by the input selector 3 using the value of the input selection register.

  The operation of the BM 1 according to this embodiment configured as described above will be described below. Here, as a simple specific example, the case of executing MTBDD shown in FIG. 1 and the case of executing QDD shown in FIG. 2 will be described and the operation of BM1 will be described.

(1) When the MTBDD shown in FIG. 1 is executed When the MTBDD shown in FIG. 1 is executed, the code of the instruction set stored in the instruction memory 7 is as shown in the following table.

  First, in the initial state, A0 is set in the program counter 10 as address information.

  When the execution of the program is started, first, the instruction memory 7 refers to the address information A0 of the program counter 10 and outputs the instruction B_BRANCH (A1, A7), x0 stored at the address A0 to the instruction register 8. Set. The instruction decoder 9 refers to the instruction B_BRANCH (A1, A7), x0 set in the instruction register 8, and decodes and executes it. In this case, since it is a 2-address 2-branch instruction, first, the index (INDEX) of the input variable is set to the “input selection register” in the register file 5 and the “FETCH bit” of the “flag register” in the register file 5 Is set to 1 for a certain period. When the “FETCH bit” is set to 1, the input selector 3 selects and selects one of the lines of the variable input bus 2 according to the index (INDEX) of the input variable x0 set in the “input selection register”. The input variable x0 input from the line thus set is set in the input register 4. Next, the instruction decoder 9 refers to the value of the input variable x0 set in the input register 4. When x0 is 0, the address A1 is set in the program counter 10, and when x0 is 1, the address A7 is set. Is set in the program counter 10.

  Here, as an example, it is assumed that x0 = 1. In this case, the address A7 is set in the program counter 10.

  Next, the instruction memory 7 refers to the address information A7 of the program counter 10, and outputs and sets the instruction B_BRANCH (A3, A8), x1 stored in the address A7 to the instruction register 8. The instruction decoder 9 reads and decodes and executes the instruction B_BRANCH (A3, A8), x1 set in the instruction register 8. In this case, since it is a 2-address 2-branch instruction, first, the index (INDEX) of the input variable x1 is set in the “input selection register” in the register file 5 and the “FETCH bit” in the “flag register” in the register file 5 is set. Is set to 1 for a certain period. When the “FETCH bit” is set to 1, the input selector 3 selects and selects one of the lines of the variable input bus 2 according to the index (INDEX) of the input variable x1 set in the “input selection register”. The input variable x1 input from the line thus set is set in the input register 4. Next, the instruction decoder 9 refers to the value of the input variable x1 set in the input register 4. When x1 is 0, the address A3 is set in the program counter 10, and when x1 is 1, the address A8 is set in the program counter 10. To do.

  Here, as an example, it is assumed that x1 = 0. In this case, the address A3 is set in the program counter 10.

  Next, the instruction memory 7 refers to the address information A3 of the program counter 10 and outputs and sets the instruction B_BRANCH (A4, A5), x2 stored at the address A3 to the instruction register 8. The instruction decoder 9 refers to the instruction B_BRANCH (A4, A5), x2 set in the instruction register 8, and decodes and executes it. In this case, since it is a 2-address 2-branch instruction, first, the index (INDEX) of the input variable x2 is set in the “input selection register” in the register file 5 and the “FETCH bit” in the “flag register” in the register file 5 is set. Is set to 1 for a certain period. When the “FETCH bit” is set to 1, the input selector 3 selects and selects one of the lines of the variable input bus 2 according to the index (INDEX) of the input variable x2 set in the “input selection register”. The input variable x2 input from the line thus set is set in the input register 4. Next, the instruction decoder 9 refers to the value of the input variable x2 set in the input register 4. When x2 is 0, the address A4 is set in the program counter 10, and when x2 is 1, the address A5 is set in the program counter 10. To do.

  Here, as an example, it is assumed that x2 = 0. In this case, the address A4 is set in the program counter 10.

  Next, the instruction memory 7 refers to the address information A4 of the program counter 10 and outputs and sets the instructions DATASET 10, 0, A0 stored in the address A4 to the instruction register 8. The instruction decoder 9 refers to the instruction DATASET 10, 0, A0 set in the instruction register 8 and decodes and executes it. In this case, since it is a data set instruction, first, output data “10” is set to “output register” at address 0 in register file 5. Then, the instruction decoder 9 sets the address A0 in the program counter 10 and then terminates the program execution because it is a terminal node.

(2) When the QDD shown in FIG. 2 is executed The code of the instruction set stored in the instruction memory 7 when the QDD shown in FIG. 2 is executed is as shown in the following table.

  FIG. 7 shows the result of assigning the addresses of each 3-address 4-branch instruction (Q_BRANCH) by this instruction set code.

  First, in the initial state, A0 is set in the program counter 10 as address information.

  When execution of the program is started, first, the instruction memory 7 refers to the address information A0 of the program counter 10 and stores the instruction Q_BRANCH (A2, A2, A5), X0,00 stored at the address A0 in the instruction register. Output to 8 and set. The instruction decoder 9 refers to the instruction Q_BRANCH (A2, A2, A5), X0,00 set in the instruction register 8, and decodes and executes it. In this case, since it is a 3-address 4-branch instruction (Q_BRANCH), first, the index (INDEX) of the input variable x0 is set to the “input selection register” in the register file 5, and the “flag register” in the register file 5 is set. The “FETCH bit” is set to 1 for a certain period. When the “FETCH bit” is set to 1, the input selector 3 selects and selects one of the lines of the variable input bus 2 according to the index (INDEX) of the input variable x0 set in the “input selection register”. The input variable x0 input from the line thus set is set in the input register 4. Next, the instruction decoder 9 refers to the value of the input variable x0 set in the input register 4, and since the function selection flag (SEL) is “00”, when x0 is “00”, the instruction decoder 9 has the current address A0. The next address A1 is set in the program counter 10 when x0 is “01”, the address A2 is set when x0 is “10”, and the address A5 is set when x0 is “11”. .

  Here, as an example, it is assumed that x0 = 11. In this case, the address A5 is set in the program counter 10.

  Next, the instruction memory 7 refers to the address information A5 of the program counter 10 and outputs and sets the instructions Q_BRANCH (A4, A4, A4), X1, 10 stored in the address A5 to the instruction register 8. The instruction decoder 9 refers to the instructions Q_BRANCH (A4, A4, A4), X1, 10 set in the instruction register 8, and decodes and executes them. In this case, since it is a 3-address 4-branch instruction (Q_BRANCH), first, the index (INDEX) of the input variable x1 is set to the “input selection register” in the register file 5, and the “flag register” in the register file 5 is set. The “FETCH bit” is set to 1 for a certain period. When the “FETCH bit” is set to 1, the input selector 3 selects and selects one of the lines of the variable input bus 2 according to the index (INDEX) of the input variable x1 set in the “input selection register”. The input variable x1 input from the line thus set is set in the input register 4. Next, the instruction decoder 9 refers to the value of the input variable x1 set in the input register 4, and since the function selection flag (SEL) is “10”, the address A4 is set to x0 when x1 is “00”. When the address is “01”, the address A4 is set in the program counter 10 when x1 is “10”, the address A6 next to the current address A5 is set, and when the address x4 is “11”, the address A4 is set. .

  Here, as an example, it is assumed that x1 = 10. In this case, the address A6 is set in the program counter 10.

  Next, the instruction memory 7 refers to the address information A6 of the program counter 10, and outputs and sets the instruction B_BRANCH (A3, A3),-stored in the address A6 to the instruction register 8. The instruction decoder 9 refers to the instruction B_BRANCH (A3, A3),-set in the instruction register 8, and decodes and executes it. In this case, the type of instruction code is a two-address two-branch instruction (B_BRANCH), but since the two specified jump destination addresses are equal, it does not depend on the value of the input variable and becomes an unconditional jump instruction. Therefore, the instruction decoder 9 sets the designated address A3 in the program counter 10.

  Next, the instruction memory 7 refers to the address information A3 of the program counter 10 and outputs and sets the instructions DATASET 10, 0, A0 stored in the address A3 to the instruction register 8. The instruction decoder 9 refers to the instruction DATASET 10, 0, A0 set in the instruction register 8 and decodes and executes it. In this case, since it is a data set instruction (DATASET), first, output data “10” is set to “output register” at address “0” in register file 5. Then, the instruction decoder 9 sets the address A0 in the program counter 10 and then terminates the program execution because it is a terminal node.

  In the present embodiment, a multistage branching program machine (hereinafter referred to as “multistage BM”) in which eight BM1 described in the first embodiment are connected in series will be described.

  FIG. 8 is a block diagram illustrating a configuration of a multistage BM according to the second embodiment. 8, the BM 1, the variable input bus 2, the input selector 3, the input register 4, the register file 5, the variable output bus 6, the instruction memory 7, the instruction register 8, the instruction decoder 9, and the program counter 10 are the same as those shown in FIG. It is the same thing.

The multi-stage BM 20 of the present embodiment has a configuration in which eight BM1 (BM _{0 to} BM ₇ ) are cascade-connected.

The variable output bus 6 of each BM _n is connected via the programmable routing box 22 to the variable input bus 2 of the subsequent BM _{n + 1} or the programmable routing box 22 or the output register 24 of the subsequent stage. The flag output bus 11 of each BM _n is connected to the variable input bus 2 of the subsequent BM _{n + 1} , the programmable routing box 21 of the subsequent stage, or the flag register 23 via the programmable routing box 21. The external output bus r_out of the output register 24 is connected to an external circuit, and is connected to a programmable routing box 22 that is branched and cascade-connected to the input bus of the BM ₁ at the foremost stage. The external output bus f_out of the flag register 23 is connected to an external circuit and connected to a programmable routing box 21 that is branched and cascade-connected to the input bus of the BM ₁ at the foremost stage.

  Each of the programmable routing boxes 21 and 22 is a connection circuit that rearranges the connection between the input wiring and the output wiring so as to be reconfigurable. Each of the programmable routing boxes 21 and 22 includes a crossbar switch, a multiplexer, and the like.

  Each programmable routing box 21 and 22 can perform bitwise AND or bitwise OR operation of the output of the previous BM1 and the output of the current BM by changing the configuration. Constant output is also possible. When performing a bitwise AND operation, a constant 1 is generated in the programmable routing boxes 21 and 22 at the ends (portions indicated by hatching in FIG. 8). On the other hand, when a bitwise OR operation is performed, a constant 0 is generated in the programmable routing boxes 21 and 22 at the ends (portions indicated by hatching in FIG. 8).

As a result, the output variable set in each output register and each status register in the register file 5 as the operation result in each BM _n and each flag set in the flag register are cascaded in the programmable routing box. The data is temporarily stored in the output register 24 and the flag register 23 via 22 and 21. The values stored in the output register 24 and the flag register 23 are hooded back and sent to the input variable bus 2 of each BM again.

In addition, external input buses f_in and r_in from an external circuit are also connected to the programmable routing boxes 21 and 22 cascade-connected to the input bus of the BM ₁ at the front stage. Accordingly, external inputs input via these external input buses f_in and r_in are also broadcast to each BM 1 via each programmable routing box 21 and 22.

  Further, the output of the multistage BM 20 can be fed back and referred to by each BM 1. Therefore, each BM1 can be operated independently.

  In this multi-stage BM 20, the communication time between the BMs 1 passes through one register (flag register 23 or output register 24), and can be referred to after one clock after writing a value in the register. BM1 uses two clocks for processing one instruction, and there is no instruction level communication time delay within the multistage BM20.

  In the present embodiment, a parallel processor 30 using 128 BM1 described in the first embodiment will be described. When 128 BM1s are connected in multiple stages in cascade as in the second embodiment and can communicate with each other, the connection circuits (programmable routing boxes 21 and 22) become very large, which is not realistic. Therefore, a hierarchical connection circuit is used in this embodiment. In the present embodiment, as described in the second embodiment, a multi-stage BM 20 in which eight BMs 1 are cascade-connected is set as one unit, and 16 multi-stage BMs 20 are arranged to form a hierarchical structure.

  When simulating a sequential circuit, another multi-stage BM 20 is referred to in order to make a state transition. At this time, the programmable connection circuit 31 is used for the connection between the multistage BMs 20. As described above, communication between the BMs 1 in each multistage BM 20 can be performed in one clock. On the other hand, communication between different multistage BMs 20 requires 4 clocks.

  FIG. 9 is a block diagram illustrating the configuration of the parallel processor 30 according to the third embodiment. The parallel processor 30 includes 16 multi-stage BMs 20 (8-BM_0 to 8-BM_15), a programmable connection circuit 31, a bitwise AND / OR circuit 32, and an ACT product operation circuit 33.

  The external output bus r_out of the output register 24 of each multistage BM 20 is connected to the input side of the programmable connection circuit 31. The external input bus r_in of the programmable routing box 22 at the forefront of each multi-stage BM 20 is connected to the output side of the programmable connection circuit 31.

  The programmable connection circuit 31 is a connection circuit that switches the connection order of each wiring of the bus connected to the input side and each wiring of the bus connected to the output side so as to be reconfigurable. The programmable connection circuit 31 includes a multi-stage multiplexer in order to perform complicated signal selection. Therefore, in a simple configuration, the programmable connection circuit 31 becomes a critical path, and the operating frequency of the entire parallel processor 30 is extremely reduced. Therefore, a pipeline register is inserted in the programmable connection circuit 31 so as to improve the operating frequency. However, since a pipeline register is inserted, four clocks are required to determine the output of the programmable connection circuit 31. Since the parallel processor 30 uses two clocks per instruction, it is necessary to wait for two instructions to transfer data through the programmable connection circuit 31.

  The external output bus f_out of the flag register 23 of each multistage BM 20 is connected to the input side of the bitwise AND / OR circuit 32. The external input bus f_in of the programmable routing box 21 at the forefront of each multi-stage BM 20 is connected to the output side of the bitwise AND / OR circuit 32.

  The bitwise AND / OR circuit 32 switches the connection order between each wiring of the bus connected to the input side and each wiring of the bus connected to the output side in a reconfigurable manner, and by changing the configuration, This is a connection circuit configured to perform bitwise AND and bitwise OR operations between flags output from the multistage BM20.

  The output line f_out [12] in the external output bus f_out of the flag register 23 of each multi-stage BM 20 is used as an ACT flag that activates the programmable connection circuit 31. The output line f_out [12] of each multi-stage BM 20 is connected to the ACT product operation circuit 33. The ACT product operation circuit 33 performs an AND operation of these ACT flags to generate an ACT signal. This ACT signal is input to the ACT input terminal of the programmable connection circuit 31. The programmable connection circuit 31 is activated when the ACT signal is 1, and holds the value determined at the previous activation.

DESCRIPTION OF SYMBOLS 1 Branching program machine 2 Variable input bus 3 Input selector 4 Input register 5 Register file 6 Variable output bus 7 Instruction memory 8 Instruction register 9 Instruction decoder 10 Program counter 11 Flag output bus 20 Multistage branching program machine 21 Programmable routing box 22 Programmable routing box 23 Flag register 24 Output register 30 Parallel processor 31 Programmable connection circuit 32 Bitwise AND / OR circuit 33 ACT product operation circuit

Claims (5)

A variable input bus to which multiple input variables are input;
An input selection register;
An input selector for selecting an input variable from the variable input bus according to a set value of the input selection register ;
An input register in which an input variable selected by the input selector is temporarily set;
An output register in which the output variable is set;
A variable output bus to which an output variable set in the output register is output;
An instruction memory in which each instruction to be executed in the program is stored;
An instruction register in which instructions sequentially read from the instruction memory are temporarily set;
An instruction decoder that executes the instruction based on an input variable read from the input register and an instruction read from the instruction register;
A program counter for storing address information in an instruction memory of an instruction to be read next;
Equipped with a,
The instruction memory includes (1) an index of an input variable to be referred to, address information of an instruction memory to be jumped when the input variable is 0, and address information of an instruction memory to be jumped to when the input variable is 1. (2) The index of the input variable to be referenced, the address information of the instruction memory to jump to when the input variable is the first value, and the jump when the input variable is the second value The address information of the previous instruction memory, the 3-address 4-branch instruction including the address information of the previous instruction memory to jump when the input variable is the third value, and (3) the address information of the output register of the output destination, And an instruction series including at least three types of output instructions including output data are stored, and according to the address information set in the program counter, And outputs a command stored in the address commanded dress information in the instruction register,
When the instruction set in the instruction register is the 2-address 2-branch instruction or the 3-address 4-branch instruction, the instruction decoder stores in the input selection register based on an index of an input variable designated by the instruction. A value is set, an input variable is selected by the input selector and set in the input register, and based on the value of the input variable set in the input register, the jump destination instruction memory specified by the instruction is stored. (B) When the instruction set in the instruction register is the output instruction, the address information is selected according to the address information of the output register specified by the instruction. Execute the process of setting the output data specified by the instruction to the address of the output register commanded by Branching program machines that feature.


The 3-address 4-branch instruction stored in the instruction memory jumps when the index of the input variable to be referred to, a function selection flag that specifies a combination of the branch destination address with respect to the value of the input variable, and the input variable is the first value. Address information ADDR0 of the previous instruction memory, address information ADDR1 of the destination instruction memory that jumps when the input variable is the second value, and address information of the destination instruction memory that jumps when the input variable is the third value Including ADDR2,
When the instruction set in the instruction register is the 3-address 4-branch instruction, the instruction decoder selects an input variable by the input selector based on an index of the input variable specified by the instruction, and the input register When the value of the input variable set in the input register is the first, second, and third values, the address information ADDR0, When ADDR1 or ADDR2 is selected and the value of the input variable set in the input register is other than the first, second, or third value, the address (P + 1) next to the address P of the current instruction The branching program machine according to claim 1, wherein the address information is selected and set in the program counter.   A plurality of branching program machines according to claim 1 or 2 are cascade-connected, and at least a part of a variable input bus of the subsequent branching program machine includes the branching program machine in the previous stage. A multi-stage branching program machine, wherein the variable output bus of the machine is connected, and input variables are input to the remaining variable input buses.   4. The variable output bus of each branching program machine is connected to the variable input bus of a subsequent branching program machine via a programmable routing box. Multi-stage branching program machine. A multi-stage branching program machine according to claim 3 or 4 connected in parallel.
A plurality of selection input nodes and a plurality of selection output nodes, each variable output bus of each multi-stage branching program machine is connected to each selection input node, and at least a part of the selection output nodes A programmable interconnection circuit connected to a part of a variable input bus of a multi-stage branching program machine and capable of recombining the connection between each selected input node and each selected output node;
A parallel processor characterized by comprising:

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