JPH09148998A - Programmable pcm /tdm demultiplexer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize a demultiplexer by separating the multiplexing cancel conversion into a frame alignment function unit and a decommutation function unit. SOLUTION: A frame alignment function unit includes a frame alignment logical device which is controlled by a programmable frame alignment controller. On the other hand, a decommutation function unit contains the output logical device hardware which is controlled by the next sequence instruction NSI of the output of a programmable decommutator sequencer controller and the control word signal CW that is outputted from the decommutator sequencer at the speed of a bit clock signal BCLK. Then every input PCM/DTM is decommutated while passing through the decommutation function. Therefore, only a compact memory that operates at the speed of the signal BCLK is needed. Thus the demultiplexer can be miniaturized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to pulse code modulation / time division multiplexed data communication, and more particularly to an apparatus for performing high frequency demultiplexing.

[0002]

2. Description of the Related Art FIG. 1 shows local oscillators (CLKa), (CLKb), (CLK
c), the pulse code modulation (PCM) data signal is input to the input of the conventional time division multiplexer (TDM MUX) via the input branch lines (ITa, ITb, ITc) and the input speed RATEa, RATE.
Individual electronic data sources Ia, Ib, I transmitted at b, RATEc
c is shown. The time division multiplexer (TDM MUX) is
Driven by the transmitter-oscillator master clock (MCLK), the branches are sampled in a selected order at a rate faster than the total allowable input rate, and then as a higher frequency converted data bit signal, a PCM / TDM signal stream. Multiplex time slots. This signal stream is a PCM / TDM demultiplexer.
Received by TDM DEMUX and demultiplexed. This PCM /
The TDM demultiplexer produces individual output data streams on the output branches OTa, OTb and OTc for the output devices Oa, Ob, Oc. The clock recovery unit CLKR is a bit clock signal from the PCM / TDM signal stream for use by the TDM DEMUX.
CLK). After clock recovery is done, the demultiplexing process includes the additional steps of frame alignment, dejustification and decommutation.

Frame Alignment FIG. 2 shows an example of a PCM / TDM signal stream of data bits (Da), (Db), (Dc) grouped into octets during a frame interval. The frame spacing format is traditionally defined by frame alignment (FA) words and multi-frame alignment (MFA) words that consist of frame alignment bit (F) patterns inserted either continuously at frame boundaries or periodically between frame boundaries. Stipulated in. When a PCM / TDM signal stream is received, the MCLK timing is recovered as a renamed BCLK signal so that the bits associated with the signal stream are sorted by the inverse process of demultiplexing. The bits containing the FA word are then searched from the bitstream assembled by the demultiplexer. The candidate FA word pattern is compared with the reference FA word pattern until it matches.
Unless simulated FA words confuse the search
Continuous F-bit pattern synchronization is achieved at one frame intervals.

More generally, the bits F may be distributed along the frame as illustrated in FIG. In this case, frame synchronization requires assembling candidate bits starting from each possible position for the FA word within one frame or multiple frames.

Assembling a candidate FA word from exactly one bit position in each BCLK cycle will not achieve frame synchronization until the candidate FA word is assembled from each possible start position bit. The probability of achieving frame synchronization is proportional to all possible start positions at which FA candidate bits are tested during a given cycle. This is the corresponding number of candidate FAs
Requires memory capacity for pattern words.

Multi-frame boundaries coincide with frame boundaries. After FA synchronization, there is only one possible start position in each frame for the candidate multiframe (MF) bits. In the absence of bit errors, MF synchronization is achieved later in another MF interval.

In the justification near-synchronous communication, I
The signals from a, Ib, and Ic have an accuracy of about a predetermined tolerance, and the signals are uncertain within the tolerance. Therefore, the input branch signal timing deviation is preferably contained within the justification (J) bit timeslot (FIG. 3), during which compensation bits can be inserted or erased. The Justification Control (JC) word bit value indicates the justification action to be taken. Each justifiable tributary requires a JC word and a J-bit time slot. Of frames within a multi-frame
TDM grouping allows a common control word to be used to justify different branch lines within each frame. In this way, the JC word does not need to be tested for each branch in each frame.

In positive justification, the PCM / TDM style bit clock exceeds the nominal branch bit clock speed. Occasionally, a source data bit occupying a data slot is not available and the multiplexer transmits a "stuff" bit in the J bit time slot and also sets a valid justification control (JC) bit for the corresponding branch line. .

Negative justification can be used when the branch bit clock speed can exceed the nominal speed of the PCM / TDM stream. J-bit timeslots are initially empty and are sometimes used to pull in excess bit inputs from the faster branch lines. In this case, the corresponding justification control bit is activated.

Positive / zero / negative justification uses positive and negative J slots to accelerate, decelerate, or not adjust the data bit rate received from the input branch.

The bits JC are arranged consecutively or distributedly in the frame to form the JC word. JC words are interpreted in a conventional manner by odd majority voting or pattern matching. When a positive justified branch line frame is received and an active bit JC word is detected, the stuff bit is deleted from the J slot. When a negative justified stream is received and an active bit JC word is detected, the data bit is held in slot J. Zero dejustification removes the stuff bit from positive slot J and keeps the data bit in negative slot J.

[0012] decommutation data stream is once justification release, bits, they are Routing to the appropriate branch according to the sample format in the multiplexer.

Conventional Features and Characteristics The conventional form of the MPX-100 demultiplexer was generally implemented in ICs with field programmable working memory using down-loaded software to decommutate the TDM format. . The MPX-100 working memory is required to cycle at the BCLK speed of the multiplexed stream. Any programmable demultiplexer that relies on the programmable working memory to cycle on BCLK encounters substantially one dilemma at the IC. Memory speed is inversely proportional to their size. IC memory capacity must be balanced with access speed. This provides a compromise between functional and programming advantages. With that memory size, MPX-
The 100 did not work at 50 Mbit / s.

In particular applications, it enables very fast de-communication of TDM signals, practically any TDM signal.
Multiplexers are desirable because they are small and reprogrammable to the format.

US Pat. No. 4,377,861 to Huffmann provides data bits to each branch by using individual channel units which are provided with real-time framing information by a state controller and branch branching selectivity by a macro processor. A demultiplexer for redistributing is disclosed.

In Hubbard US Pat. No. 4,430,730, multiple digital voice channels are demultiplexed and added together to set up a conference call.
Voice data is stored in the buffer memory and extracted by the microprocessor.

[0017]

Therefore, branch-like data in the telecommunications field from a wide variety of TDM formats that can operate at the highest achievable data rates and can be implemented in the current state of the art IC technology. There is a need for a programmable decommutator that can decommutate streams.

[0018]

SUMMARY OF THE INVENTION The present invention is a PCM / TDM that can operate with a fast input bit clock and is reprogrammable for various types and levels of hierarchical demultiplexing operations.
I will provide a. The present invention is suitable for implementation in two and preferably only one degree of IC.

Memory size and access latency are minimized by separating the demultiplexing transformation into separate FA functional units and decommutation and dejustification (DEC) functional units that operate in an integrated manner. To be done.

The memory size and access delay time are further controlled by a non-branching sequence controller operating in the DEC functional unit, preferably at the BCLK speed,
It is preferably minimized by isolating into a branching sequence controller that operates at a fraction of BCLK.

Memory size and access time are further further minimized by separating the control memory of the branching controller contained within the FA and DEC functional units into address and instruction segments.

The demultiplexer architecture according to the present invention comprises a programmable frame alignment controller (P
FAC) Output logic hardware controlled by programmable decommutator sequencer (PDS) with FA functional unit including frame alignment logic controlled by programmable decommutator sequencer controller (PDSC) With a DEC functional unit containing (OLH).

Unlike the Hubbard patent, the present invention does not require a frame buffer memory. The invention has the advantage that it is not necessary to record the entire frame of the bit signal. The data bits are decolated one by one while the TDM stream is undergoing the decommutation function.
The present invention, unlike the Huffman patent, enhances the implementation efficiency, and especially the programmability, of the state controller.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings. The present invention includes individual integrated FA and DEC functions as shown in FIG.
Provides an architecture for PCM / TDM demultiplexers. The present invention minimizes the dependence on programmable memories that cycle at BCLK speeds, which can be as high as 50 MHz in current technology. The balance between hard-wired and programmable logic keeps demultiplexing and programming quirky.

The candidate FA pattern word assembling and matching steps of the frame alignment circuit FA function must be kept at the same pace as BCLK and are therefore implemented by the hardwired logic unit FAL. Referring to FIG. 5, FAL is controlled by PFAC, which is programmed with a short microcode sequence and does this at the rate of one microinstruction per BCLK unit cycle. PFAC preferably depending only on the current state stored in the F AL state address memory (FSMEM) segments and F AL instructions (FIMEM) has a control memory which is partitioned into segments and status register (SREG) Next A branching programmable state machine with instruction output (NI) output may be provided. Each memory segment is small enough to be accessed with a reasonable design margin that is faster than the fastest specified BCLK speed. FSMEM is P F
Apply AC next state address (FNSA) signal to SREG. Sequential FN
SA is latched on successive cycles of BCLK and provided on the FSMEM and FIMEM address lines as the P F AC current state address (FCSA) signal. Therefore, FIMEM produces the NI signal. The next cycle of BCLK advances the signal NI in the instruction register (IREG) to appear as the current instruction signal (CI). CI is fed to the P F AC state multiplexer (FSMUX) to select the input F AL condition state line (FCSL). this is,
It is preferable that one address line of FSMEM has a selected bit.
Used as (SSB) to facilitate program branching in controller PFAC. An example FSMEM is
It can store 64 states, each of which can branch into two paths. This can provide up to 128 addresses. The CI is received by the FAL via the FAL instruction decoder (FDEC). FAL is also a serial / parallel FAL shift register (F
SR), Interleave pattern RAM (IPR), Initializable address counter (ADDCT), Reference FAL pattern register (FPR), FAL mask register (FMR), FAL masked bit comparator (FMBC), FAL detection (all comparisons are true. Circuit) (FDCT), FAL flip-flop (FF)
F) and a series (preferably 8) of programmable counters (PRCTR). In this example, the PFAC control memory data is organized as follows.

[0026]

[Table 1]

Distributed during a frame of specific duration
The speed target for sync lock on the FA signal is related to the IPR size. FALs embodied in ICs preferably use memory areas economically by allowing slow FA searches. An IPR that can store 1/4 of all potential candidate FA pattern bits means that it sometimes requires as long as 4 frames to achieve FA synchronization. To achieve FA synchronization, IPR performs the following iterations. That is, 1. Shift the 4th received PCM / TDM bit to FSR to assemble with the candidate FA pattern bits loaded in step 4, thereby updating the set of candidate FA
Produces a pattern bit. 2. Write the updated candidate FA pattern bits to their respective positions in the IPR. 3. Increment ADDCT by 4. 4. In preparation for step 1, load the newly addressed contents of the IPR into the FSR in parallel.

The FDCT senses the output from the FMBC. FMR
The FDCT produces a logical true signal only when there is a match between the IPR and FPR at the bit position pointed to by. Programs in PFAC usually use counters in PRCTR
Follow the progress in analyzing the signal flow. The program increments, resets, and tests the counters to detect when they are at their final count. When the program in PFAC senses that a set of 4th addressed bit patterns has been collected without finding a match, the program increments ADDCT by 1 and continues until the next match is found. It may operate to iterate the search for a set of fourth addresses.

The FAL of FIG. 5 may test the distributed bits for FA words starting in any of the 64 time slots in each frame.

1 for the start bit in each frame
To check only timeslots, IPR and ADDCT can be omitted in an alternative to FAL. Also,
A continuous bit FA pattern search that shifts bits into BSR in FSR does not require IPR.

Frame Alignment Process The PCM / TDM signal is received via a circuit that recovers the MCLK (FIG. 1) timing signal as BCLK, which is
With the PCM / TDM stream bits reaching the demultiplexer of FIG. The received PCM / TDM signal stream expected to have non-contiguous FA bits is searched for possible start bits at multiple locations. Each time a 1-bit assembly completes a candidate FA pattern, the assembled pattern word is masked with FMR and compared with the reference FA pattern stored in FPR in FMBC. Normally, on the first match, the FA is used to tag the identified frame boundaries.
L emits a frame sync pulse (P). Loss of FA sync pulse is usually not admitted until a few comparison failures. Preferably, the FA loss threshold is PRCTR by the PFAC program.
It is programmable by monitoring the comparison result in a counter such as (FIG. 5).

Achieving FA in some TDM formats then involves searching for MF boundaries in some multiframe pattern. MF boundaries have a planned relationship with respect to a single frame boundary. Therefore, MFA
The word search only needs to compare a limited number of positions for potential MFA word start bits and does not require IPR.

Dejustification and Decomiation
In decommutating the received PCM / TDM signal stream, various short structured bit sequences are iteratively manipulated in a predetermined manner in a particular PCM / TDM multiplex format so that the data bits are Distribute to their respective output branches. Dejustification is
This is a change in decommutation operation. Justification control bits contained in the signal stream are detected and, depending on their interpretation in the particular multiplexing format, certain bits from the signal stream are sent to the output branch, modified, sent or deleted. obtain.

The conventional form of the MPX-100 used a one-state machine to directly control its dejustification and its decommutation OLH. The current state state or condition input could cause the state machine used in the MPX-100 to immediately change its output. However, analysis of the MPX-100 confirms that the decommutation process can be successfully performed by a state machine whose output depends only on prior states and conditions. This is the response presented by the branching state machine of the type used in the present invention. This kind of machine cycles faster than the equivalent machine of the type used in the MPX-100.

The TDM decommutation and dejustification control functions according to the present invention are implemented on a combination of two machines. One is a branching state machine, which preferably runs slower than BCLK, and BC
Control a second, preferably small, simple non-branching state machine operating at LK speed.

FIG. 4 illustrates the decommutation and dejustification function according to the invention consisting of OLH, PDS and PDSC. The OLH receives a short control word (CW) signal from the PDS as a result of the PDS receiving a specific next sequence instruction (NSI) from the PDSC. Each short CW signal sequence normally controls the OLH and decommutates a repeating sequence of bit formats within the frame. TDS outputs CW at BCLK speed. The TDS is preferably a non-branching sequencer, controlled by a counter, which causes the PDS to start executing the CW addressed by the NSI and then reach the CW with the sequencer Dunn (SDONE) bit turned on. Up to CW cyclically. At this point, the sequencer decrements the sequence repeat number (SRN) from the NSI and either signals an instruction (IDONE) or is addressed by the NSI if the SRN reaches the limit count.
Resume at CW and start CW execution. IDONE signal is PDSC
Cycle state machine to PDS new NSI signal
, And the process repeats. The PDSC sequence generation control process can be made conditional by testing the FA sync lock line P, or the OLH conditional status line DCSL. The representative condition status signal represents the status of the justification control operation and is the final count value of the counter.

The single branching state machine in the conventional type MPX 100 has a single segment control memory,
The memory then cycles at the BCLK rate to limit the BCLK rate. The memory was large compared to the present invention. This is because each location contains storage for states and instructions, as well as other states and instructions.

In contrast, the present invention uses only a relatively small memory SPM operating at the BCLK speed. Large DMEM
Preferably operates at 1/4 BCLK speed and is smaller than conventional MPX-100 memory due to the different structure of the branching controller PDSC. The PDSC is a form of controller whose output depends only on the current state and not on the current input, and therefore stores alternative instructions and states at each location as the MPX-100 controller's memory does. I don't need it. Together, these improvements allow PDS and PDSC memory to take up 30% less total area than MPX-100 memory while maintaining comparable performance. Conditional PDSC instructions are supported for branching to other parts of the program, or to call subroutines in the usual overview of computational controllers. When the NSI is a procedure CALL, the Subroutine Control (SUBC) bit causes the Next State Logic (NSL) Subroutine-Return Register (SRR) (detailed in Figure 10) to be the value of the normal Decommutator Next State Address (DNSA). Is incremented and then stored. When the body of the subroutine is completed, the RETURN instruction will generate a SUBC field bit, which will cause the SRR to become the decommutator current state address (DCS
A) Indicate as a source for a ward.

The "IF ---- THEN GOTO" instruction can be looped and further incorporated by incrementing and testing the OLH similar to PRCTR in FIG. FIG.
For conditioning instructions, the branch condition select (IF) bit directs the state multiplexer (DSMUX) to select the OLH conditional state line (DCSL) or line P for testing, which causes the PDSC output to go out. Affect the next cycle.

The generic PDSC of FIG. 6 is shown in the alternative embodiment of FIGS. 7, 8, 9 and 10, each of which partitions the DMEM differently. The PDSC in the embodiment of FIGS. 7 and 8 is a decommutator state memory (DSME
M) Segments a and b (DSMEMa and DSMEMb, respectively)
, And decommutator instruction memory (DIMEM) DM divided into segments a and b (DIMEM and DIMEMb, respectively)
Have EM. In FIG. 7, DNSA is output from DSMEM when addressed together by the DCSA bit and the DCSL bit selected by the IF signal. The 256-word x 7-bit DSMEMa in Figure 7 is a 128-word x 14-bit DSMEMa in Figure 8.
It can be replaced with MEMb. DSMEMb in Figure 8 outputs two parallel bitfields, the next state address word (NSAW)
And the next state branch address word (NSBAW) to the next state multiplexer (NSMUX)
(NUMUS), and the multiplexer selects either NSAW or NSBAW as DNSA.

FIG. 9 shows that the state address and instruction memory are the decommutator instruction and state memory unit c (DISME
The PDSC as the third concrete example collected in Mc) is shown. This decommutator instruction and state memory unit c is equivalent in total capacity to the DSWEM + DIMEM of FIG. Examples of these three DMEMs (DMEMa, DMEMb and
All DMEMc) have an equivalent storage capacity of 3456 bits.

FIG. 10 shows the memory requirements shown in FIG.
10 shows a further improvement over the embodiment of FIGS. 8 and 9. Decommutator instruction and status memory unit (DIS
The MEMd) area, and thus the access time, is reduced by almost half in the embodiment shown in FIG. This implementation has the advantage that PDSC programs are mainly inline configurable and branching is rare.

In the embodiment of FIG. 10, the next state address is generated by simply incrementing DCSA. each
IDONE signal, decommutator sequencer status register
(DSSR) stores the incremented DCSA, which is then selected as the DCSA.

The CALL and GOTO instructions are executed in two access cycles of DISMEMd. Conditional instructions can use either the decommutator branch status register (DBSR) or DSSR.
Performed by selecting the input to DSMUX to select as the source for DCSA. By placing the branch state address (BSA) in DISMEMd immediately after the Call or GOTO instruction, the second DISMEMd access causes the DB
Output BSA instead of NSI and BSA as input to SR. The DBSR output is therefore selected as the new DCSA.

The subsequent DCSA is generated by incrementing DCSA and storing it in DSSR. The return is performed by storing the return address in the SRR in all the examples of FIGS.

The TDSC may be implemented as illustrated in FIG. Standard or non-standard format PCM / TD
Most M decommutator programs are executed using the 128-word Decommutator Instruction Memory (DIMEM). The memory, therefore, contains fields for subroutine control (SUBC) in bits 11-12, branching control (IF) in bits 8-10, and next sequence instruction (NSI) field for PDS in bits 0-7. The NSI is further divided into a sequence repetition number (SRN) of bits 4-7 and a current scan sequence (CSS) of bits 0-3.

[0047]

[Table 2]

The PDS performs a "scan sequence" of microinstructions to manipulate the input PCM / TDM signal bits.
The particular scan sequence and the number of repetitions thereof is dictated by the NSI. When the PDS executes the previously loaded NSI, the PDSC sets the next NSI. Upon completion of the last cycle of the scan sequence, the PDS will generate an IDONE signal, which loads the NSI waiting for this signal into the PDS and the PDSC
Cycle to select the subsequent NSI. Thus, the PDSC cycles through its state at the IDONE rate or twice the IDONE rate for CALL or GOTO instructions. The maximum PDSC design cycle speed can be adjusted by limiting the length of the shortest (fastest) scan sequence that the PDS will perform. The practical limitation allows the PDSC to cycle at less than 1/4 the PDS speed, which cycles at the BCLK speed.

The PDS is a sequence program memory (SP
M) and the sequence control logic unit (SCL) are shown in FIG. Thus, the sequence control logic unit includes a sequence control register (SCR), a sequence cycle counter (SCC), a terminal logic unit (TL) and a sequence program counter (SPC). The SPM has a capacity of 256 words, preferably 8 bits, each writable in a data field defining a microinstruction as follows.

[0050]

[Table 3]

SPM Output CW microinstruction is a scan sequence (any of 16) executed in response to an NSI.
, Preferably used as steps in (4-16) clock cycles.

Assuming the PDS has already returned the IDONE signal, the NSI waiting to be input to SCL (as shown in FIG. 11) is latched by SCR and then SP
Outputs in parallel as 4-MSB Current Scan Sequence (CSS), which indicates the start address of the scan sequence at N, and as 4-LSB, which indicates the SRN of the number of times to repeat the scan sequence addressing of the SPM. LSB is initialized and BCLK increments LSB via SPN address and outputs CW bits (0: 6) to OLH.

The SPM scan sequence ends when the CW contains a "1" in bit No. 7 (SDONE). This increments SCC, resets SPC, and restarts execution of the current scan sequence.

The PDSC sets the subsequent NSI while the current sequence instruction is re-executed until the final iteration of the current scan sequence instruction has been completed by the PDS.

When the SCC reaches its final count value = SRN, the TL issues an IDONE signal on SDONE. This signal is SC
Strobe R and latch other NSI. Referring again to FIG. 6, the IDONE signal strobes NSL simultaneously and latches the other DNSA as a new DCSA for feedback. The additional NSI can be used to extend the number of iterations of a given sequence to 32 or more.

An example of a scanning sequence consists of eight CWs so that the OLH decommutates the data signal into eight branches in the selected order. The CW signal is equivalent to an inline code string, and it repeatedly calls the "hardware subroutine", OLH in FIG. 12, to perform justification or decommutation operations.

[0057] Data output logic hardware de controller for commutation - PLC - architecture according to the present invention for the hardware is sufficiently adapted to Dejustification signals in synchronization and / near synchronous multiplexing environment To be done.

Conditional data signal manipulations, such as dejustification, are performed in the hardwired logic by the OLH rather than letting the PDSC select the justification control program sequence so that this purpose is exercised in the PDS. It

OKH is a dejustification control logic unit (DJL) and a decommutation control logic unit.
(DCL) is included. Output interface logic unit (OIL)
In addition to the data signal, is also controlled by the decommutator data field decoder DDEC to provide a "data valid / ready" signal.

FIG. 12 represents DJL hardware for assembling and interpreting justification control words from JC bits, as described for the example of FIG. DJL is a justification data field decoder and data selection unit (JDEC), shift logic unit (SL), dejustification shift register (D
SR), dejustification pattern register (D
PR), dejustification mask register (DM
R), dejustification masked-bit comparator (DMBC), justification detection (when all bits compare registers) register (DDCT), and flip-flop (DFF).

Received PC that is a candidate as bit JC
The M / TDM stream bits are single-shifted to one of the 8DSRs selected by the CW branch select bits (0: 2).

The bits JC may be contiguous within a frame or distributed within a frame or across multiple frames. The bit JC shift is controlled by the CW input to JDEC, so DJL can assemble bits from any format. The contents of the dejustifier shift register (DSR) are the mask and reference retrieved by the dejustifier masked bit comparator (DMBC) from the corresponding register dejustifier mask register (DMR) and dejustifier pattern register (DPR). Compared to the pattern. Dejustifier detection (for all bit comparison) circuit (DDCT)
Produces a true signal if all unmasked compare bits match. Once the justification control word is DS
Once assembled in R, JDEC enable comparison (R
The ESET) signal latches the DDCT output into one of the eight DFFs.

The initialization procedure preferably configures DJL with rules for specific justifications. For example, a common JC word is an odd number of strings of "1" s, and the rule for this is to ensure that most of the bits in the JC are "1" s. In this example, the initialization procedure configures SL to shift only "1". The DMBC then tests for (n / 2) + multiple "1" strings. Where "n"
Is the number of "1" in the JC word. Thus, for five "1" (11111) JC words, the DMBC will test for a majority string of five, such as at least three "1", eg 111xx.

FIG. 12 illustrates the DCL, which is
Includes DDEC, Data Selector (DS), a set of 16 FFs and OILs. The CW, with its bits (3: 6) normally set equal to 0, causes the DC to select the current PCM / TDM data signal as the data source. However, as a result of dejustification, the CW bits (3: 6) should be equal to 1 to let DC select the PCM / TDM data bit complement, or equal to 4 to select a logical 1 or Equal to 3 to force a logic 0 to be selected. DS output data bit and DDEC data valid / ready set the FF pair indicated by the tributary selection bit of CW.

Returning to FIG. 12, the justification control signal test result is output to the PDSC as DCSL. At the estimated time to perform the justification action, the PDSC was conditioned to the DCSL state.
This produces NSI. The NSI then controls the PDS and outputs the CW, which causes the DCL (Fig. 5) to control the data valid / ready bit, thereby performing the justification operation, as described above. It is a thing. If the current time slot contains data bits, a data valid / ready signal is generated to indicate that tributary data is being output. Conversely, if the current time slot contains no data bits, no data valid signal occurs.

In FIG. 12, OIL outputs bit serial data and data-valid signals from up to eight branches. Other implementations of OIL could output word serial or word parallel data signals from each possible branch. OIL
Contains sufficient registers and logic for some applications to create word-parallel data output from multiple branch lines and to prepare a ready signal for each branch line.

[Initialization] The present invention has separate functions.
Although it is convenient to facilitate initialization by (INIT), FIG. 4 shows this as off-line configuration control. From the controller, at power-up and / or reconfiguration, configuration and initialization information is input via the serial port and various demultiplexer variants via conventional additional data paths not shown in FIGS. Should be transmitted to the elements of. The initialization signal is downloaded, first load the microprogram into both controller states and instruction memory, and second,
Load the scan sequencer microprogram into SPM,
Third, configure the FAL, DJL and DCL output logic hardware, and fourth, load the end count into the OLH counter,
Finally, load the OLH correlation pattern into the pattern register and the mask into the mask register. The MPX-100 performed the initialization function within the state machine, but still required an offline download of its state memory control store. The combination of memory for download and configuration hardware in the present invention significantly reduces the control store size required at a reasonable cost of additional hardware. This is a good compromise to minimize the control store size.

The present invention is a method where PCM / wherein constraints must be maintained with respect to the total amount of logic that can be used.
It relates to a device for optimizing the speed and variability of multiplexers in TDM, and as the technology of logic device realization improves, the individual disclosed techniques are more rapid and more compact embodiments of the present invention. It will be apparent to those skilled in the art that it can be used to give examples. Moreover, it will be apparent that other functional elements not disclosed herein, such as a feedthrough descrambler, may be included within the structure of the preferred embodiment.

[Brief description of the drawings]

FIG. 1 is a block diagram representing a simplified PCM / TDM communication link.

FIG. 2 is a diagram showing an example of a PCM / TDM format having continuous F bits.

[Fig. 3] Distributed F bit, justification control
It is a diagram which shows an example of PCM / TDM which has a JC bit and a justification J bit.

FIG. 4 is a block diagram representing the basic architecture of a preferred embodiment of a PCM / TDM demultiplexer according to the present invention.

FIG. 5 is a block diagram showing FA functions performed by FAL and PFAC.

FIG. 6 is a block diagram showing an overall PDSC architecture.

FIG. 7 is a block diagram showing a first specific example of PDSC.

FIG. 8 is a block diagram showing a second specific example of PDSC.

FIG. 9 is a block diagram showing a third specific example of PDSC.

FIG. 10 is a block diagram showing a fourth specific example of PDSC.

FIG. 11: Preferred Sequence Program Memory (SPM)
FIG. 3 is a block diagram illustrating a PDS embodied in the elements of a Sequence Control Logic Unit (SCL).

FIG. 12: Dejustification Logic Unit (DJL)
And in decommutation logic unit (DCL) circuits
It is a block diagram which shows OLH hard wired.

FIG. 13: FA function of FIG. 5 and DEC of FIGS.
It is a block diagram which combines a function as one example.

[Explanation of symbols]

FAL Frame Alignment Logic BCLK Bit Clock Signal CI Current Command Signal F Frame Alignment Signal P Frame Sync Signal FCSL Frame Alignment Status Signal PFAC Programmable Frame Alignment Controller DEC Dejustification and Decommutation Functional Unit CW Control Word DCSL Dejustification Fification status signal PDS Programmable sequencer NSI Next sequence instruction OLH Output logical unit IDONE instruction Dan signal PDSC Programmable sequencer controller

Claims (11)

[Claims] 1. An apparatus for demultiplexing a PCM / TDM input data signal, comprising: The PCM / TDM input data signal, the bit clock signal (BCLK) recovered from the input data signal, and the current command signal are received, and the frame alignment signal (F) present in the PCM / TDM input data signal is detected. A frame sync signal in response to detection of frame boundaries in the input data signal
A frame alignment logic means for generating (P),
Further, a frame alignment logic unit that operates to generate a frame alignment status signal (FCSL), receives the bit clock signal (BCLK) and the frame alignment status signal (FCSL), and generates the current command signal (CI). Then
Frame aligning means including programmable frame aligning controller means (PFAC) for controlling the frame aligning logic means (FAL); Receives the bit clock signal (BCLK), the input data signal (PCM / TDM), and the control word (CW), and outputs one or more output branch signals, a data valid signal, and a dejustification status signal. Output logic means (OLH) for generating (DCSL), the bit clock signal (BCLK) and the next sequence instruction (NS
I), generates the control word (CW) for controlling the output logic means (OLH), and outputs the command signal (IW).
Programmable sequencer means (PDS) for generating DONE), the frame sync signal (P), the dejustification status signal (DCSL), and the instruction download signal (IDONE)
A programmable sequencer controller means (PDSC) for receiving a signal and generating the next sequence instruction (NSI) to control the programmable sequencer means (PDS), the output logic means (OLH) ) And the programmable sequencer means (PDS) are operated with the bit clock (BCLK), and the programmable sequencer controller means (PDSC) is a fraction of the bit clock (BCLK) speed. A demultiplexing and decommutation means (DEC) capable of being operated at the speed of. 2. The programmable frame alignment controller means (PFAC) is a control memory means (FSMEM, FIMEM).
And the control memory means is the bit clock
State segment memory means for storing address information (FNSA), cycled at the (BCLK) signal frequency
2. The demultiplexing device according to claim 1, which is divided into (FSMEM) and instruction segment memory means (FIMEM) for storing instruction information. 3. The frame alignment logic means (FAL) comprises the programmable frame alignment controller means (PFA).
C) receives the instruction (CI), decodes the instruction (CI), interleaf pattern memory means (IPR), shift register means (FSR), address counter means (ADDCT), flip-flop means (FFF) and An instruction decoder means (FDEC) for generating a control signal for controlling a programmable counter means (PRCTR), wherein the shift register means (FSR) serially inputs the input data signal (PCM / TDM). Responsive to the control signal by operating the candidate frame alignment pattern words in parallel and receiving the control signal and combining the input data signal (PCM / TDM) with the candidate frame alignment pattern word. An instruction decoder means (FDEC) operable to form an updated candidate frame alignment pattern, address means for receiving an interleaf pattern memory address signal, An interface comprising control means for receiving a control signal and input / output means for receiving the updated candidate frame alignment pattern word and outputting the candidate frame alignment pattern word to the shift register means (FSR). Leaf pattern memory means (IP
R), an address counter means (ADDCT) for receiving the control signal and the bit block signal (BCLK), and generating the interleaf pattern memory address signal, and storing a predetermined frame alignment pattern word, A pattern register means (FPR) for outputting, a mask register means (FMR) for storing and outputting a scheduled frame alignment pattern comparison mask word, the scheduled frame alignment pattern word, and The candidate frame alignment pattern word and the expected frame alignment pattern word that receive the expected frame alignment pattern comparison mask word and the candidate frame alignment pattern word and are in accordance with the expected frame alignment pattern comparison mask word. Generate a comparison result signal for each bit position of A masked bit comparison means for receiving the comparison result signal, and a detection means (FDCT) for generating an equivalent signal in response to a true result in all the comparison result signals, and the detection means ( Flip-flop means (F) for storing the equivalent signal generated by the FDCT) and generating the frame synchronization signal (P) for instructing the detection of the frame boundary.
FF) and programmable counter means (PRCTR) for receiving the control signal and for generating the frame alignment status signal (FSCL) for testing by the programmable frame alignment controller means (PFAC). Item 3. The demultiplexing device according to item 2. 4. The instruction dan signal (IDONE) is used as a clock which operates at a frequency lower than that of the bit clock signal and causes the programmable sequencer controller means (PDSC) to execute the next instruction,
Programmable Sequencer Controller (PDSC)
However, the next state address signal (DNSA) and the command signal (INON
E) and a subroutine control signal (SUBL) are received, and the programmable sequencer controller clock signal (I
DONE) signal, the next state logic means (NSL) for storing and outputting the current state address signal (DSCA), the current state address signal (DSCA), and the command dan signal
(IDONE), the output logic means status signal (DCSL), and the frame synchronization signal (P) are received to generate the next-state address information and the next sequence command information, and the next-state address signal (DNSA) is generated. ) And next sequence command signal (NSI)
Memory means having addressing means for generating, said next sequence command signal (NSA) controlling said programmable sequencer means (PDS) and changing only when said current state address signal (DCSA) changes The demultiplexing device according to claim 1. 5. The memory means (DMEM) of the programmable sequencer controller (PDSC) receives the current state address signal (DCSA) and stores data including the next sequence instruction information (NSI), An instruction memory means (DIMEMa,
DIMEMb), the current state address signal (DCSA), and at least one of the output logic means state signal (DCSA) and the frame synchronization signal (P), and receives the data including the next state address information (DNSA). 5. Demultiplexing device according to claim 4, characterized in that it comprises next state address memory means (DSMEMa, DSMEMb) with address means for storing and outputting. 6. The memory means (DMEM) of the programmable sequencer controller (PDSC) receives the current state address signal (DCSA) and outputs next state address information, next state branch address information and next sequence instruction information. (NS
Demultiplexer according to claim 4, comprising instructions having address means and address memory means for storing and outputting I) simultaneously. 7. The memory means (DMEM) of the programmable sequencer controller (PDSC) receives the current state address signal, the next state branch address information (NBSA) and the next sequence instruction information.
Next instruction and next branch address memory (DISMEM) having address means for alternately storing and outputting (NSI)
d) means, receiving the next state branch address information (NBSA), one of the output logic means state signal (DSCL) and the frame synchronization signal (P), the next state branch address information (NBSA)
From the next state address signal (DCS
Logic means DBS for generating said next state address signal (DNSA) from the result of performing algebraic operation (Σ + 1) on A)
R, NSMUX, NSMUX). 8. The programmable sequencer (PDS)
Receives the current scan sequence signal (CSS) and the sequence program counter (SPC) output signal, stores the control word (CW) and outputs the control word used to control the output logic means (OLH) Sequence program memory means (SPM) having address means for
The control word information is the sequence program memory.
The control word occupying one storage location in (SPM)
A sequence program containing a plurality of sequences of (CW) and having a final step signal means for supplying a final step signal (SDONE) when the last control word (CW) of a series of control words is output. Memory means (SPM)
And, receiving the next sequence command information (NSI), the bit clock signal (BCLK) and the final step signal (SDONE),
5. A sequence control logic means (SCL) for receiving said current scan sequence signal (CSS) and said sequence program counter (SPC) output signal and cyclically selecting successive steps of said sequence. Demultiplexer. 9. The sequence control logic means (SCL) receives the next sequence command (NSI) information and outputs sequence address information to the sequence program memory (SPM).
And sequence control register means (SCR) for supplying sequence repetition information, and storing the sequence repetition information from the sequence control register (SCR), counting in response to the final step signal (SDONE). , A sequence cycle counter means (SCC) for outputting a cycle completion signal when the step sequence is repeated according to the sequence repetition information.
Receiving the bit clock signal (BCLK), the final step signal (SDONE), and the cycle completion signal, loading the sequence control register (SCR) and loading the current sequence into the programmable sequencer controller (PDSC). A termination logic means (TL) for outputting a signal (IDONE) indicating that the sequence is terminated, and the bit clock signal which is reset to a predetermined value in response to the final step signal (SDONE). A sequence program counter (SPC) that operates in response to (BCLK) and supplies the addresses of successive steps of the sequence to the sequence program memory means (SPM).
The demultiplexing device according to claim 8, further comprising: 10. The programmable sequencer (PD
S) is a control word used to receive the current scan sequence signal (CSS) and the sequence program counter (SPC) output signal, store the control word (CW) and control the output logic means (OLH). Sequence program memory means (SPM) having address means for outputting
The control word information is the sequence program memory.
The control word occupying one storage location in (SPM)
A sequence program including a plurality of sequences of (CW) and having a final step signal means for supplying a final step signal (SDONE) when the last control word of a series of control words (CW) is output. Memory means (SOM)
Receiving the next sequence command information (NSI), the bit clock signal (BCLK) and the final step signal (SDONE), receiving the current scan sequence signal (CSS) and the sequence program counter output signal (SPC) 8. The demultiplexer of claim 7, further comprising sequence control logic (SCL) for periodically selecting successive steps of the sequence. 11. The sequence control logic means (SCL)
Receives the next sequence command (NSI) information and sends the sequence address information to the sequence program memory (SPM).
And sequence control register means (SCR) for supplying sequence repetition information, and storing the sequence repetition information from the sequence control register (SCR), counting in response to the final step signal (SDONE). , A sequence cycle counter means (SCC) for outputting a cycle completion signal when the step sequence is repeated according to the sequence repetition information.
Receiving the bit clock signal (BCLK), the final step signal (SDONE) and the cycle completion signal, loading the sequence control register (SCR) and storing the programmable sequencer controller (PDSC) A signal (IDO
End logic means (TL) for outputting NE), reset to a predetermined value in response to the final step signal (SDONE), counting and in response to the bit clock signal (BCLK). Sequence program counter (SPC) which operates to supply the address of the sequential steps to the sequence program memory means (SPM)
The demultiplexing device according to claim 10, further comprising: