JP2010218178A - Sort processing apparatus and sort processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve sort processing whose processing speed is higher than conventional bubble sort when sort frequency is large, in a system in which area constraint is strict and the number of sort object data is small. <P>SOLUTION: This sort processing apparatus is configured to perform processing for determining the maximum value data to all sort object data by using a comparison/exchange means 103 configured of comparison/exchange arithmetic units 111 and 113 including comparison/exchange arithmetic units of binary to be executed in parallel for reading m pieces (m>2) comparison/exchange object data in sort object data from a storage means 101 and a register 112 for a pipe line, and to repeat the similar processing even to the residual sort object data by determining the sequence of the (m-1) pieces of data. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

      The present invention relates to a sort processing apparatus and a sort processing method capable of significantly improving the processing speed as compared with a conventional bubble sort.

    Bubble sort is a sorting method in which the maximum or minimum number is determined one by one by repeatedly comparing and exchanging data. Bubble sort is classified as a slow sorting method because the worst calculation time requires (n + ... + 2 + 1) comparisons and exchanges with the number of data n and is proportional to the square of the number of data. Is simple and does not use a complex arithmetic unit, and is therefore suitable for a system with a strict area restriction and a small number of data to be sorted.

  Bubble sort consists of double loops. In the inner loop, two pieces of data whose order is indefinite are sequentially selected, compared and exchanged, and the minimum value is selected. The inner loop is repeated until one minimum value is selected. In the outer loop, the range of data whose order is indefinite is updated, and the process returns to the inner loop. The outer loop is repeated until the ranking of all data is established.

Japanese Patent Application Laid-Open No. 2002-229772

However, even in a system where the area restriction is strict and the number of data to be sorted is small, when the number of times of sorting is large, the conventional bubble sorting method has a problem that the processing speed is slow.
In order to solve such a conventional problem, the present invention expands and improves the bubble sort method, adds a dedicated arithmetic unit, and makes the sort apparatus and sort faster than the conventional bubble sort apparatus by pipelining. It aims to provide a method.

The sort processing method according to the present invention includes a first step in which a plurality of input data is used as the first sort target data, and m pieces of data (m is an integer of 3 or more) from the sort target data. The second step of determining the data to be compared and exchanged as the target data and the data of the maximum value in the case of sort in ascending order and the data of the minimum value in the case of sort in descending order as the decision data, and the determined decision data among the data to be compared and exchanged Compare the process of determining new decision data by comparing and exchanging m-1 data excluding, and one of the sort target data that has never been compared and replaced as new comparison data The third step that repeats up to the last m pieces of data to be exchanged data, and the order of the m-1 data remaining in the third step are determined, and the order of the sort target data A fourth step in which data excluding only m-1 data is set as new sort target data, and the second step, the third step, and the fourth step This is repeated until all rankings are finalized.
A sort processing apparatus according to the present invention includes a storage unit that stores a plurality of input data, a first register group that stores data within a range of sort target data in the storage unit as comparison / exchange target data, Comparison and exchange operations of each data stored in one register group are pipelined at multiple stages, and the maximum value data is selected as the decision data in the ascending order and the minimum value data is determined as the decision data in the descending order sort An exchange unit, a second register group for storing data to be subjected to a comparison / exchange operation at each stage of the comparison / exchange unit, corresponding to each stage, a storage unit, a first register group, a comparison / exchange unit, A control unit that controls the two register groups, and reads m pieces of data (m is an integer of 3 or more) within the range of data to be sorted from the storage means and stores them in the first register group After the first processing is performed, the comparison / exchange target data is read from the first register group, and the comparison / exchange unit selects the maximum value data in the descending order when the comparison / exchange data is sorted in the ascending order. A process for determining the minimum value data as decision data, a process for writing the decision data determined by the comparison / exchange means back to the storage means, and m−1 pieces of data excluding the determined decision data of the comparison / exchange target data And one of the data that has never become comparison / exchange target data within the range of the data to be sorted stored in the storage means, and stores the data as new comparison target data in the first register group; Are repeated until the last m pieces of data to be compared and exchanged, the third process for determining the rank of the remaining m-1 pieces of data is performed, and the sort pair A fourth process is performed in which data other than the remaining m−1 data among the data is set as a new range of data to be sorted, and the first process is performed until all ranks of the plurality of input data are determined. The second process, the third process, and the fourth process are repeated.

In the sort processing method of the present invention (hereinafter referred to as the expanded bubble sort method), the worst calculation time order is proportional to the square of the number of data as in the bubble sort. Can reduce the execution time.
For example, if the number of data to be compared at a time is 4, the worst number of comparison exchanges is approximately (n +... + 2 + 1) / 3. Furthermore, the number of execution cycles is further reduced by reducing the number of memory accesses.

  The sort processing apparatus of the present invention can suppress the amount of hardware to a slight increase compared to the conventional bubble sort, and can be applied not only to a system with a large area constraint, but also to a computing unit that uses the conventional bubble sort. Sorting can be performed at high speed.

Configuration diagram of sort processing apparatus according to Embodiment 1 of the present invention The flowchart which shows the processing method of the sort processing apparatus by Embodiment 1 of this invention. The block diagram of the sort processing apparatus which is an Example in the case of m = 4 by Embodiment 1 of this invention The figure which shows the description of the block which comprises the processor of FIG. 3, its kind and name, content, or operation | movement Explanatory drawing of a structure and operation | movement of the comparison exchange means of the Example of this invention The flowchart which shows the processing method of the sort processing apparatus in the Example of this invention. Measurement result of evaluation experiment of sort processing apparatus in an embodiment of the present invention

  An embodiment of the present invention will be described.

  FIG. 1 is a block diagram showing a sort processing apparatus according to Embodiment 1 of the present invention.

In FIG. 1, the sort processing apparatus includes a data memory 101 (storage means) for storing a plurality of input data, and m pieces of data within the range of data to be sorted in the data memory 101 (m is an integer of 3 or more). ) In the case of sorting in ascending order by comparison exchange operation of each data stored in the dedicated register 102 (first register group) stored as read comparison exchange target data, the maximum value data is determined and sorting in descending order In this case, a comparison / exchange unit 103 for determining a minimum value and a control unit 104 are provided. Further, the comparison / exchange unit 103 performs comparison / exchange operations of a plurality of stages, so that the comparison / exchange operation unit 111 that performs comparison operation on the data read from the dedicated register 102 and the comparison / output unit 111 output the comparison of the next stage. A register 112 (second register group) for storing data to be operated is provided, and a comparison / exchange operation unit 112 for performing a comparison operation on data read from the register 112 in the next stage. The control unit 104 controls input / output of the data memory 101 and the dedicated register 102 and output of the output of the comparison / exchange means to the dedicated register 102 and the data memory 101.
If the comparison / exchange means 103 has three or more stages, a register may be added between the stages. For example, when m> 4, the comparison / exchange means 103 has log (2) m (logarithm with base 2 and rounded up to the next decimal point) comparison / exchange arithmetic units and log (2) m−1 It is configured by a register, and the register is sandwiched between comparison / exchange arithmetic units. When m is large, in order to realize a plurality of comparison / exchange operations in one cycle, it is not necessary to put a register between all the comparison / exchange operations, but depending on the delay of other operation units and the delay constraint of the system. It is possible to adopt a configuration in which an increase in the number of pipeline stages is suppressed by interposing one register between the comparison / exchange operation units.

  Next, the operation of the sort processing device will be described.

  FIG. 2 is a flowchart showing the processing method of the sort processing apparatus according to the first embodiment of the present invention for sorting in ascending order. First, the range of data to be sorted in the data memory 101 is initialized (step S1). Next, it is determined whether or not there is data to be sorted (step S2). If there is no data to be sorted, the process ends with all the rankings being completed. In step S3, predetermined m pieces of data (m is an integer of 3 or more) within the range of the sort target data are read from the data memory 101 as comparison exchange target data. Next, the comparison / exchange target data is written to the dedicated register 102 (step S4), the comparison / exchange means 103 determines the maximum value of the comparison / exchange target data (step S5), and the determined maximum value data is stored in the data memory 101. (Step S6). Next, it is determined whether all data to be sorted have been compared and exchanged (step S7). If not, the comparison / exchange target data within the range of the m−1 data excluding the determined maximum value data of the comparison / exchange target data and the sort target data stored in the data memory 101 One of the data that has never been read is read out and used as new comparison target data (step S8), and the process returns to step S4. The repetition of steps S4 to S8 is called an inner loop. When the processing of the inner loop is completed up to the last m pieces of data to be compared and exchanged in the range of sort target data, and all the data to be sorted has been compared and exchanged, the rank of the remaining m-1 data Is determined and written back to the data memory 101 (step S9). Here, whether the processing of the inner loop so far and whether or not the exchange has been performed in step S9 is held in the exchange occurrence flag, for example, whether or not the exchange has never occurred. It is determined whether sorting is completed during the process (step S10). If no exchange has occurred, the process ends as the sorting is completed. When the exchange occurs even once, the data other than the m-1 data remaining at the end of the inner loop among the sort target data is set as a new sort target data range (step 11), and the process returns to step S2 to newly Will carry out a comparative exchange. This loop is called the outer loop.

  Here, the sort is performed from a small value (ascending order), but when the sort is performed from the large value (descending order), “maximum value” is referred to as “minimum value” in the above description of the processing method of the route processing apparatus. You can replace it.

  FIG. 3 shows an example of the case of m = 4 according to the first embodiment of the present invention, and shows a sort processing device incorporated in a processor. FIG. 4 shows the notation of the blocks constituting the processor in FIG. 3, their types, names, contents, and operations.

  The processor shown in FIG. 3 has a four-stage pipeline and is divided into three pipeline registers 320, 312, and 322 in order to reduce delay time. The pipeline stage includes an IF stage up to the pipeline register 320 that performs instruction fetch, an ID stage up to the pipeline register 312 that decodes the instruction, an EXE stage up to the pipeline register 322 that executes the operation, It consists of four WB stages that read and write data memory after the pipeline register 322 and write to the register. The comparison exchange calculator 311 corresponds to the comparison exchange calculator 111 of FIG. 1 and is included in the ID stage. The comparison exchange calculator 313 corresponds to the comparison exchange calculator 113 of FIG. 1 and is included in the EXE stage. The comparison exchange calculator 311, the comparison exchange calculator 313, and the pipeline register 312 constitute a comparison exchange unit 103 that determines the maximum value data in the case of sorting in ascending order by comparison exchange operation. The data memory 301 corresponds to the data memory 101 of FIG. 1, stores a plurality of input data, and inputs / outputs data in the middle of processing and stores data after all ranking has been completed. The dedicated register 302 corresponds to the dedicated register 102 in FIG. 1, and in addition to the SPR0, SPR1, SPR2 and SPR3 for storing the four comparison exchange target data, the ID stage and EXE stage comparison exchange calculator 311 or the comparison exchange operation It comprises an exchange flag register XF for storing an exchange occurrence flag indicating whether or not exchange has occurred even once in the device 313.

  FIG. 5 is a detailed explanatory diagram of the comparison / exchange means 103. Four comparison / exchange target data are read from the SPR 0 to 3 of the dedicated register 102 into the comparison / exchange arithmetic unit 311. The comparison / exchange operation unit 311 is composed of two comparison / exchange operation units CMPX0 and CMPX1 that compare the input binary values and output the divided values as a larger value and a smaller value. Similarly, the comparison / exchange operation unit 313 is composed of two comparison / exchange operation units CMPX2 and CMPX3 that compare the input two values and output the divided value as a larger value and a smaller value. In the comparison and exchange computing unit 311, the two larger values stored in the pipeline register 312 are input and compared and exchanged. In the comparison and exchange computing unit CMPX3, the comparison and exchange computing unit 311 outputs and enters the pipeline register 412. The two smaller values stored are input and compared. Accordingly, the data having the maximum value and the data having the minimum value among the four comparison exchange target data are determined and stored in SPR3 and SPR2 of the dedicated register 102, respectively. On the other hand, when exchange occurs in the comparison exchange arithmetic units CMPX0 and CMPX1, 1 is output so that the value of the exchange flag register XF is ORed with the OR arithmetic unit 501, and is output to the pipeline register 412. And the comparison / exchange arithmetic units CMPX2 and CMPX3 output the logical OR in the OR arithmetic unit 501 so as to output 1 when the exchange occurs, and output the result to the exchange flag register XF. The exchange flag register XF1 can be set to 1 when any one of the devices CMPX0, CMPX1, CMPX2, and CMPX3 has exchanged data.

Next, the operation of the sort processing apparatus in the present embodiment will be described.
FIG. 6 is a flowchart showing the processing method of the sort processing apparatus according to the present embodiment for sorting in ascending order. First, the value of the exchange flag register XF is cleared to 0, and the start address x and the end address y of the sort target data in the data memory 301 are set to initialize the range of the sort target data (step S61). Next, it is determined whether or not the data to be sorted exists by comparing the value of x and the value of y (step S62). If x> y, the process proceeds to the next step assuming that the data exists, otherwise Ends. When there is data, x is substituted for t representing the start address of unsorted data (step S63), and ternary data from address t to address t + 2 is selected and read from the data memory 301 (step S63). In step S64, the selected ternary data is read into SPR0 to SPR2 of the dedicated register 102 (step S65). Next, the value of the data at address t + 3 of the address of the data memory 301 is read into SPR3 (step S66), and the four values of the data values of SPR0 to SPR3 are compared and exchanged by the comparison and exchange means 103, and the data having the maximum value and the minimum value are compared. The data having a value and the value of the exchange flag register XF are determined (step S67), the value of the SPR3 data in which the maximum value is stored is written to the address t (step S68), and all the data in the range to be sorted are included. Whether or not the data has been compared and exchanged is determined by comparing the value of t + 3 with y (step S69). If t + 3> y, the comparison exchange is not completed and t + 1 is newly set as the value of t and the process returns to step S66. (Step S70) When t + 3 = y, it is determined that the comparison has been exchanged and the process proceeds to the next Step S71. Since all the data in the range of the data to be sorted has been compared and exchanged, three of the values in the range of the data to be sorted are determined from the smaller value, and the minimum value of the three is stored in SPR2. In S71, the data values of SPR0 and SPR1 whose order is indeterminate are compared and exchanged using one of the binary comparison exchanges CMPX0, CMPX1, CMPX2, and CMPX3, the smaller one is stored in SPR1, and the larger one is stored in SPR0. Store and determine the value of the exchange flag register XF. Next, the data of SPR0, SPR1 and SPR2 are stored at the addresses t + 1, t + 2 and t + 3 of the address of the data memory 301 (step S72), and all of the range of data to be sorted depends on whether the value of the exchange flag register XF is 0 or not. It is determined whether or not the data has never been exchanged (step S73). When the value of the exchange flag register XF is 0, the process is terminated as the sorting is completed during the process, and the value of the exchange flag register XF is determined. When 1 is 1, in order to exclude data whose order has been determined, the value of y-3 is newly set to y, and the value of the exchange flag register XF is cleared to 0 (step S74), and then the process returns to step S62.
Here, the case where the sorting is performed from a small value (ascending order) has been described. However, when the sorting is performed from the larger value (descending order), the data having the maximum value and the data having the minimum value in the sort processing device of FIG. After the determination, it is assumed that they are stored in SPR2 and SPR3 of the dedicated register 102, respectively. In the explanation of the processing method of the sort processing device, “maximum value” is “minimum value” and “maximum value” is “minimum value”. In step S71, “smaller” should be read as “larger” and “larger” should be read as “smaller”.

(Evaluation experiment)
In the processor of the present embodiment, the conventional bubble sort method and the extended bubble sort method of the present invention were compared. The number n of data to be sorted is 8, 16, and 32, and the number of cycles until the end of the operation by each method was measured by simulation of hardware description language (HDL). The measurement results are shown in FIG. By the extended bubble sort method, the sort is completed in about one-fourth the number of execution cycles of the conventional bubble sort method.

  Also, as a result of synthesizing the circuit from HDL under delay priority conditions with the TSMC 0.18 micron design rule, the area ratio of the comparison switch, dedicated register and additional pipeline register added for expanded bubble sort as the circuit scale is the whole Of 13%.

  Therefore, it has been found that a significant improvement in processing speed can be obtained as compared with the conventional bubble sorting method, and an increase in the amount of hardware can be suppressed to about 13%.

101 Data Memory 102 Dedicated Register 103 Comparison Exchange Means 104 Control Unit 111 Comparison Exchange Calculator 112 Register 113 Comparison Exchange Calculator

Claims (2)

A sorting method for rearranging a plurality of input data in ascending or descending order, wherein the first plurality of input data is used as the first sort target data, and m (m Is a second step of comparing and exchanging data as the first comparison exchange target data, and determining the maximum value data in the ascending order and the minimum value data in the descending order as the decision data. , M-1 data excluding the determined decision data in the comparison exchange target data and one of the data that has never become comparison exchange target data in the sort target data are newly added. A third step of repeating the process of comparing and exchanging as comparison object data and determining new decision data up to the last m pieces of data to be compared and exchanged data; A fourth step of determining the rank of the remaining m−1 data in the step and setting the data other than the remaining m−1 data in the sorting target data as new sorting target data. A sort processing method comprising: repeating the second step, the third step, and the fourth step until all ranks of the plurality of input data are determined.
A sort processing device for rearranging a plurality of input data in ascending or descending order, wherein the storage means for storing the plurality of input data and the data within the range of data to be sorted in the storage means are compared and exchanged The first register group to be stored as target data and the comparison / exchange operation of each data stored in the first register group are pipeline-processed in a plurality of stages, and in the case of ascending order sorting, the maximum value data is in descending order. In the case of sorting, comparison exchange means for determining the minimum value data as decision data, and a second register group for storing data to be subjected to comparison exchange operation at each stage of the comparison exchange means corresponding to each stage; And a control unit for controlling the storage means, the first register group, the comparison / exchange means, and the second register group. After the first processing of reading out m pieces of data (m is an integer of 3 or more) within the range and storing the data in the first register group, the comparison / exchange target data is read out from the first register group, and In the comparison and exchange means, in the case of sort in ascending order among the data to be compared and exchanged, the process of determining the maximum value data as the decision data in the case of sort in descending order, and the above-mentioned data determined by the comparison and exchange means A process of writing the decision data back to the storage means, a range of m-1 data excluding the decided decision data in the comparison exchange target data, and a range of the sort target data stored in the storage means Processing for reading out one of the data that has never become comparison / exchange target data and storing it as new comparison target data in the first register group. A second process that repeats up to the last m pieces of data, and a third process for determining the rank of the remaining m-1 pieces of data, and the remaining m-1 of the sort target data. Performing a fourth process in which data other than the number of data is set as a range of new data to be sorted, and the first process and the second process until all ranks of the plurality of input data are determined. A sort processing apparatus that repeats the third process and the fourth process.