JP5379810B2 - グラフィックスパイプラインのための効率的な状態管理 - Google Patents

グラフィックスパイプラインのための効率的な状態管理 Download PDF

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JP5379810B2
JP5379810B2 JP2010540662A JP2010540662A JP5379810B2 JP 5379810 B2 JP5379810 B2 JP 5379810B2 JP 2010540662 A JP2010540662 A JP 2010540662A JP 2010540662 A JP2010540662 A JP 2010540662A JP 5379810 B2 JP5379810 B2 JP 5379810B2
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processing
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JP2011508338A (ja
JP2011508338A5 (enExample
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マントール マイケル
エルドン マックラリー レックス
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Graphics (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Generation (AREA)
  • Image Processing (AREA)
  • Advance Control (AREA)
JP2010540662A 2007-12-26 2008-12-23 グラフィックスパイプラインのための効率的な状態管理 Active JP5379810B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US1674607P 2007-12-26 2007-12-26
US61/016,746 2007-12-26
US12/341,028 US8826294B2 (en) 2007-12-26 2008-12-22 Efficient state management system
US12/341,028 2008-12-22
PCT/US2008/014011 WO2009085264A1 (en) 2007-12-26 2008-12-23 Efficient state management for a graphics pipeline

Publications (3)

Publication Number Publication Date
JP2011508338A JP2011508338A (ja) 2011-03-10
JP2011508338A5 JP2011508338A5 (enExample) 2012-02-16
JP5379810B2 true JP5379810B2 (ja) 2013-12-25

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ID=40800308

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JP2010540662A Active JP5379810B2 (ja) 2007-12-26 2008-12-23 グラフィックスパイプラインのための効率的な状態管理

Country Status (6)

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US (1) US8826294B2 (enExample)
EP (1) EP2232447B1 (enExample)
JP (1) JP5379810B2 (enExample)
KR (1) KR101574275B1 (enExample)
CN (1) CN101918982B (enExample)
WO (1) WO2009085264A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9147224B2 (en) * 2011-11-11 2015-09-29 Nvidia Corporation Method for handling state transitions in a network of virtual processing nodes
CN104484173B (zh) * 2014-12-12 2017-10-27 北京国双科技有限公司 基于TPL Dataflow的状态监控方法及装置
CN106921646B (zh) * 2016-07-26 2020-11-20 创新先进技术有限公司 业务处理方法及装置
US10430990B2 (en) * 2017-09-20 2019-10-01 Intel Corporation Pixel compression mechanism
US20240378790A1 (en) * 2023-05-09 2024-11-14 Advanced Micro Devices, Inc. Pipelined graphics state management

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69635066T2 (de) 1995-06-06 2006-07-20 Hewlett-Packard Development Co., L.P., Houston Unterbrechungsschema zum Aktualisieren eines Lokalspeichers
US6343309B1 (en) 1996-09-30 2002-01-29 International Business Machines Corporaton Method and apparatus for parallelizing a graphics pipeline
US5920326A (en) * 1997-05-30 1999-07-06 Hewlett Packard Company Caching and coherency control of multiple geometry accelerators in a computer graphics system
US6091422A (en) * 1998-04-03 2000-07-18 Avid Technology, Inc. System for editing complex visual data providing a continuously updated rendering
JP3338673B2 (ja) 1999-09-07 2002-10-28 株式会社マルチターム ３次元仮想空間共有マルチユーザーシステム
US6411301B1 (en) * 1999-10-28 2002-06-25 Nintendo Co., Ltd. Graphics system interface
US6452600B1 (en) * 1999-10-28 2002-09-17 Nintendo Co., Ltd. Graphics system interface
US6462743B1 (en) * 1999-12-21 2002-10-08 Ati International Srl Pipeline processing system and method
JP2001236221A (ja) 2000-02-21 2001-08-31 Keisuke Shindo マルチスレッドを利用するパイプライン並列プロセッサ
US7162716B2 (en) 2001-06-08 2007-01-09 Nvidia Corporation Software emulator for optimizing application-programmable vertex processing
GB0425204D0 (en) 2004-11-15 2004-12-15 Falanx Microsystems As Processing of 3-dimensional graphics
US7586492B2 (en) 2004-12-20 2009-09-08 Nvidia Corporation Real-time display post-processing using programmable hardware
US7580040B2 (en) * 2005-11-10 2009-08-25 Via Technologies, Inc. Interruptible GPU and method for processing multiple contexts and runlists

Also Published As

Publication number Publication date
CN101918982B (zh) 2015-01-21
JP2011508338A (ja) 2011-03-10
EP2232447A1 (en) 2010-09-29
KR101574275B1 (ko) 2015-12-04
WO2009085264A1 (en) 2009-07-09
CN101918982A (zh) 2010-12-15
KR20100102176A (ko) 2010-09-20
EP2232447B1 (en) 2019-05-08
US8826294B2 (en) 2014-09-02
US20090172677A1 (en) 2009-07-02

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