JP5373567B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of adjusting the operation margin of a memory cell to an appropriate value even though a power source voltage supplied to a peripheral circuit is changed. <P>SOLUTION: The semiconductor device 100 is equipped with: an SRAM 200 including a memory cell array 201 and a peripheral circuit 202; and a memory cell voltage generating section 300 in which the memory cell voltage VMM of &alpha; times (&alpha;&gt;1) of a core power source voltage VDD is generated in accordance with the change of the core power source voltage VDD supplied to the peripheral circuit 202, and the memory cell voltage VMM is supplied to the memory cell array 201. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device on which an SRAM (Static Random Access Memory) is mounted.

  Patent Document 1 describes a semiconductor device using a voltage higher than a core power supply voltage supplied to a peripheral circuit as a power supply voltage of a memory cell in order to ensure a static noise margin. 12 and 13 show the configuration of the semiconductor device described in Patent Document 1. FIG.

  In the example shown in FIG. 12, the power supply voltage Vddm supplied to the memory cell array 30 is generated by the booster circuit 21. The booster circuit 21 uses the core power supply voltage Vdd supplied to the memory cell peripheral circuit 25 to generate a power supply voltage Vddm higher than the core power supply voltage Vdd.

  In the example shown in FIG. 13, the power supply voltage Vddm supplied to the memory cell array 30 is generated by the step-down circuit 22. The step-down circuit 22 uses the IO high-voltage power supply voltage Vddio to generate a power supply voltage Vddm that is lower than the IO high-voltage power supply voltage Vddio and higher than the core power supply voltage Vdd.

  In recent years, depending on the type of application, the core power supply voltage supplied to the peripheral circuit may be changed. When the core power supply voltage Vdd changes, an operation margin such as a static noise margin and a write margin indicating the performance of the memory cell changes, and there is a possibility that it may not become an optimum value.

  Although Patent Document 1 describes that a static noise margin is ensured with the power supply voltage Vddm being higher than the core power supply voltage Vdd, the operation margin of the memory cell changes when the core power supply voltage Vdd changes. Is not considered.

JP 2008-135169 A

  As described above, the semiconductor device described in Patent Document 1 has a problem that the operation margin of the memory cell cannot be adjusted to an appropriate value when the core power supply voltage changes.

A semiconductor device according to one embodiment of the present invention includes an SRAM including a memory cell and a peripheral circuit, and α times (α>) the first power supply voltage in accordance with a change in the first power supply voltage supplied to the peripheral circuit. generates a memory cell voltage of 1), wherein the supply to the memory cell a memory cell voltage generating unit, a semiconductor device in which example Bei a second power supply voltage is applied to the memory cell voltage generating unit, the memory The cell voltage generation unit includes a first resistance element and a second resistance element connected in series, and a resistance ratio between the first resistance element and the second resistance element is (α-1): 1. A first reference voltage as a first reference voltage, a voltage between the first resistance element and the second resistance element as a second reference voltage, and the first reference voltage and the second reference voltage. A first differential amplifier that operates to eliminate the voltage difference between A first active element to which the second power supply voltage is supplied, the resistor circuit is connected to the other end, and a load changes according to the output of the first differential amplifier, and the memory cell voltage generation The unit outputs the voltage between the resistance circuit and the first active element as the memory cell voltage through a buffer circuit.

  Thereby, even if the power supply voltage supplied to the peripheral circuit changes, the memory cell power supply voltage supplied to the memory cell can always be kept α times the power supply voltage. Therefore, a change in the operation margin of the memory cell due to a change in the ratio α between the power supply voltage and the memory cell voltage can be suppressed, and the operation margin of the memory cell can be adjusted to an appropriate value.

  According to the present invention, it is possible to provide a semiconductor device capable of adjusting an operation margin of a memory cell to an appropriate value even when a power supply voltage supplied to a peripheral circuit changes.

1 is a diagram showing a configuration of a semiconductor device according to a first embodiment. 1 is a diagram showing a configuration of an SRAM in a semiconductor device according to a first embodiment. 2 is a diagram showing a configuration of an SRAM cell in the semiconductor device according to the first embodiment. FIG. 4 is a diagram showing a configuration of a memory cell voltage generation unit in the semiconductor device according to the first embodiment. FIG. 6 is a diagram illustrating an example of input / output transfer characteristics during a read operation of an inverter that constitutes a memory cell of the semiconductor device according to the first embodiment; FIG. FIG. 6 is a diagram showing an example of input / output transfer characteristics during a write operation of an inverter constituting the memory cell of the semiconductor device according to the first embodiment. It is a figure which shows the change of the operation margin with respect to (alpha) (= VMM / VDD). FIG. 4 is a diagram showing a configuration of a semiconductor device according to a second embodiment. FIG. 10 is a diagram illustrating a configuration of a memory cell voltage generation unit used in a semiconductor device according to a third embodiment. FIG. 10 is a diagram showing a configuration of a memory cell voltage generation unit used in a semiconductor device according to a fourth embodiment. It is a figure which shows the other example of the SRAM cell used for the semiconductor device which concerns on this invention. 1 is a diagram illustrating a configuration of a semiconductor device described in Patent Document 1. FIG. 1 is a diagram illustrating a configuration of a semiconductor device described in Patent Document 1. FIG.

Embodiment 1 FIG.
A semiconductor device according to Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a diagram schematically showing a configuration of a semiconductor device 100 according to the present embodiment. As illustrated in FIG. 1, the semiconductor device 100 includes an SRAM (Static Random Access Memory) 200, a memory cell voltage generation unit 300, and a logic circuit 400. The SRAM 200 includes a memory cell array 201 and a peripheral circuit 202.

  A core power supply block 10, an I / O block 20, and an I / O power supply block 30 are formed on the periphery of the semiconductor device 100. The core power supply block 10 is provided to supply the core power supply voltage VDD input from the outside of the semiconductor device 100 to the logic circuit 400, the peripheral circuit 202, and the memory cell voltage generation unit 300.

  The I / O block 20 is provided to input / output various signals input / output to / from the SRAM 200, the logic circuit 400, and the like. The I / O power supply block 30 is provided to supply the I / O power supply voltage VCC supplied from the outside to the I / O block 20 and the memory cell voltage generation unit 300. Generally, the I / O power supply voltage VCC is higher than the core power supply voltage VDD.

  Here, the configuration of the SRAM 200 will be described in detail with reference to FIGS. FIG. 2 is a diagram illustrating an example of the configuration of the SRAM 200. FIG. 3 is a circuit diagram showing an example of the configuration of one SRAM cell 220 in the memory cell array 201.

  As shown in FIG. 2, the memory cell array 201 of the SRAM 200 includes word lines WL0 to WLi, bit lines (True bit lines: BL0 to BLj, Bar bit lines: / BL0 to / BLj), and SRAM cells 220. . The word lines WL0 to WLi extend in the left-right direction in FIG. 2 and are arranged in parallel to each other.

  The bit lines BL0 to BLj and / BL0 to / BLj extend in the vertical direction in FIG. 2 and are arranged in parallel to each other. The word lines WL0 to WLi and the bit lines BL0 to BLj, / BL0 to / BLj are arranged so as to intersect with each other.

  The plurality of SRAM cells 220 are arranged in a matrix. The SRAM cell 220 is connected to one of the word lines WL0 to WLi and one of the bit line pairs BL0− / BL0 to BLj− / BLj, respectively. The memory cell voltage VMM is supplied from the memory cell voltage generator 300 to the SRAM cell 220. This will be described in detail later.

  The memory cell array 201 includes a control circuit 203, an address buffer 204, an X-decoder and word line driver 205, a Y-decoder 206, a Y-select switch 207, a precharge circuit 208, a write data buffer 209, a write driver 210, and a sense amplifier 211. , An output buffer 212 is provided.

  The control circuit 203 performs overall control of the SRAM 200. For example, the control circuit 203 generates an internal clock and switches between a write operation and a read operation. The address buffer 204 generates an X address signal and a Y address signal based on an address signal input from the outside, and supplies the generated signals to the X-decoder and the word line driver 205 and the Y-decoder 206, respectively.

  The X-decoder and word line driver 205 designates the X address of the memory cell array 201 according to the X address signal and selects any word line WL0 to WLi. The Y-decoder 206 designates the Y address of the memory cell array 201 according to the Y address signal and supplies the designation signal to the Y-select switch 207. The Y-select switch 207 selects an arbitrary bit line pair BL0− / BL0 to BLj− / BLj in accordance with a designation signal.

  The precharge circuit 208 precharges the bit lines BL0 to BLj, / BL0 to / BLj. The write data buffer 209 holds data to be written to the SRAM cell 220 and supplies it to the write driver 210. The write driver 210 writes data to the selected SRAM cell 220.

  The sense amplifier 211 senses and amplifies data read from the SRAM cell 220 selected by the X-decoder and word line driver 205 and the Y-decoder 206. The output buffer 212 holds the data amplified by the sense amplifier 211. The peripheral circuit 202 is supplied with the core power supply voltage VDD. Each part constituting the memory cell array 201 operates with the memory cell voltage VMM.

  The configuration of the SRAM cell 220 will be described with reference to FIG. As shown in FIG. 3, the SRAM cell 220 includes load transistors MP41 and MP42 made of PMOS, drive transistors MN41 and MN42 made of NMOS, and access transistors MN43 and MN44 made of NMOS.

  The load transistor MP41 and the drive transistor MN41 constitute an inverter INV41. The load transistor MP42 and the drive transistor MN42 constitute an inverter INV42.

  The gate of the load transistor MP41 is connected to the gate of the drive transistor MN41. The drain of the load transistor MP41 is connected to the drain of the drive transistor MN41. A connection point between the load transistor MP41 and the drive transistor MN41 is a contact A.

  The gate of the load transistor MP42 is connected to the gate of the drive transistor MN42. The drain of the load transistor MP42 is connected to the drain of the drive transistor MN42. A connection point between the load transistor MP42 and the drive transistor MN42 is a contact B.

  The contact A is connected to the gates of the load transistor MP42 and the drive transistor MN42. The contact B is connected to the gates of the load transistor MP41 and the drive transistor MN41. This constitutes a flip-flop. This flip-flop stores and holds data.

  The access transistor MN43 has a source connected to the True bit line BL, a drain connected to the contact A, and a gate connected to the word line WL. The access transistor MN44 has a source connected to the Bar bit line / BL, a drain connected to the contact B, and a gate connected to the word line WL.

  Here, the configuration of the memory cell voltage generation unit 300 will be described with reference to FIG. FIG. 4 is a diagram illustrating an example of the configuration of the memory cell voltage generation unit in the semiconductor device 100. The memory cell voltage generator 300 generates a memory cell voltage VMM and supplies it to the memory cell array 201.

  The memory cell voltage generator 300 uses the I / O power supply voltage VCC, which is the second power supply voltage, as the power supply, and α times (α) the core power supply voltage VDD in accordance with a change in the core power supply voltage VDD, which is the first power supply voltage. The memory cell voltage VMM of> 1) is generated.

  The memory cell voltage generation unit 300 includes a resistance circuit, a first differential amplifier, and a first active element. The resistance circuit has two resistance elements connected in series with a resistance ratio of (α-1): 1. In the example illustrated in FIG. 4, the resistor R <b> 11 is provided as the first resistance element, and the second resistance element is provided.

  The first differential amplifier uses the core power supply voltage VDD, which is the first power supply voltage, as the first reference voltage, and the voltage between the two resistors R11 and R12 of the resistor circuit as the second reference voltage. 2 The operation is performed so that the voltage difference from the reference voltage is eliminated.

  The first differential amplifier has MP21 and MP22 made of PMOS, and MN21, MN22, and MN23 made of NMOS. The I / O power supply voltage VCC is supplied to the sources of MP21 and MP22. The gate of MP21 and the gate of MP22 are connected. The connection point between the gates of MP21 and MP22 and the drain of MP22 are connected.

  The drain of MN21 is connected to the drain of MP21, and the drain of MN22 is connected to the drain of MP22. A core power supply voltage VDD is supplied to the gate of MN21 as the first reference voltage. In addition, MN23 is connected to the sources of MN21 and MN22. The I / O power supply voltage VCC is supplied to the gate of MN23.

  The connection point between MP21 and MN21 is connected to the gate of MP23 made of PMOS, which is the first active element. The I / O power supply voltage VCC, which is the second power supply voltage, is supplied to the source of the MP23. Resistors R11 and R12 are connected in series to the drain of MP23. In MP23, the load changes according to the output of the first differential amplifier. A connection point between MP23 and the resistor R11 is defined as a contact N21. The other end of the resistor R12 is grounded.

  A connection point between the resistor R11 and the resistor R12 is a contact N22. The contact N22 is connected to the gate of MN22. That is, the voltage between the two resistors R11 and R12 is supplied to the gate of MN22 as the second reference voltage. Here, R11 = (α−1) R and R12 = R. Resistors R11 and R12 constitute a resistance circuit. The resistors R11 and R12 can be formed of polysilicon, a diffusion layer, or a well in consideration of the resistance value, the value of current flowing through the resistor, the area, and the like.

  Due to the resistors R11 and R12, the potential of the contact N21 becomes α times the core power supply voltage VDD (αVDD). Further, the potential of the contact N22 becomes equal to the core power supply voltage VDD. The gate of the MN22 is connected to the contact N22 and is supplied with the core power supply voltage VDD.

  The voltage αVDD between the resistance circuit and the one active element MP23 is output as a memory cell voltage VMM through the buffer circuit. The buffer circuit includes a second differential amplifier and a second active element. The second differential amplifier uses a voltage between the resistor circuit and the first active element MP23 as a third reference voltage, and outputs a memory cell voltage as a fourth reference voltage. The third reference voltage and the fourth reference voltage It operates so as to eliminate the voltage difference.

  The second differential amplifier has MP24 and MP25 made of PMOS and MN24, MN25 and MN26 made of NMOS. The I / O power supply voltage VCC is supplied to the sources of MP24 and MP25. The gate of MP24 and the gate of MP25 are connected. The connection point between the gates of MP24 and MP25 and the drain of MP25 are connected.

  The drain of MN24 is connected to the drain of MP24, and the drain of MN25 is connected to the drain of MP25. A voltage αVDD between the resistance circuit and the first active element MP23 is supplied to the gate of the MN24 as a third reference voltage. Further, the MN 26 is connected to the sources of the MN 24 and the MN 25. The I / O power supply voltage VCC is supplied to the gate of MN26.

  The connection point between MP24 and MN24 is connected to the gate of MP26 made of PMOS, which is the second active element. The I / O power supply voltage VCC, which is the second power supply voltage, is supplied to the source of the MP26. The MP 26 outputs αVDD which is α times the core power supply voltage VDD as the memory cell voltage VMM. In MP26, the load changes according to the output of the second differential amplifier. Further, the output memory cell voltage VMM (αVDD) is supplied to the gate of MN25 as the fourth reference voltage. The second differential amplifier operates so that the voltage difference between the third reference voltage and the fourth reference voltage is eliminated.

  With the circuit configuration as described above, the memory cell voltage VMM can always be maintained at α times the core power supply voltage VDD regardless of changes in the I / O power supply voltage VCC. For example, when the I / O power supply voltage VCC is 2.5V ± 0.2V, the core power supply voltage VDD is 1.0V ± 0.1V, and α = 1.2, VCC swings to 2.7V or 2.3V. VMM = 1.2VDD. Since α is determined by the resistance ratio between the resistors R11 and R12, it is not affected by changes in the I / O power supply voltage VCC or the core power supply voltage VDD.

  An operation margin of the semiconductor device 100 according to the present embodiment will be described with reference to FIGS. FIG. 5 shows the input / output transmission characteristics of the inverters INV41 and 42 at the time of reading, and FIG. 6 shows the input / output transmission characteristics of the inverters INV41 and 42 at the time of writing. The input / output transfer characteristic is an output of the contact A when the contact B is input in the INV41, and an output of the contact B when the contact A is input in the inverter INV42.

  5 and 6, the horizontal axis represents the voltage of the contact A, and the vertical axis represents the voltage of the contact B. Further, the input / output transmission characteristics when the dotted line α is 1.0, the solid line α is 1.2, and the alternate long and short dash line α is 1.4 are shown. 5 and 6, it is assumed that the core power supply voltage VDD is 1.0V.

  The indexes representing the performance of the SRAM 200 include a static noise margin (Static Noise Margin: SNM) indicating the stability of memory data and a write margin (Write Margin: WM) for determining the performance at the time of writing. The SNM can be determined from the length of one side of the inscribed square in the characteristic curves of the two inverters INV41 and INV42 at the time of reading.

  As shown in FIG. 5, at the start of the read operation or the write operation, the voltages of the word line WL and the bit lines BL and / BL are approximately VDD. At this time, the SNM becomes the smallest.

  As can be seen from FIG. 5, by increasing α (= VMM / VDD) from 1.0 to 1.4, the area surrounded by the characteristic curves of the two inverters INV41 and 42 is expanded. That is, as the memory cell voltage VMM is made higher than the core power supply voltage VDD, the length of one side of the inscribed square can be increased. Thereby, SNM can be improved.

  On the other hand, the WM of the SRAM cell 220 is a characteristic curve of the two inverters INV41 and INV42 when one of the bit line pair (BL, / BL) is set to the ground potential (0.0V), that is, when "1" is written. It is defined as the length of one side of the smallest square in between.

  As can be seen from FIG. 6, the VMM = 1.2V (α = 1.2) is smaller than the VMM = 1.0V (α = 1.0). That is, contrary to SNM, WM decreases as α (memory cell voltage VMM) increases.

  When the memory cell voltage VMM (α) increases, the current capability of MP42 shown in FIG. 3 increases, but the current capability of MN44 does not change. For this reason, the voltage at the intersection of the characteristic of INV42 in FIG. 6 with the Y-axis (voltage determined by the current capability ratio of MP42 and MN44 in FIG. 3) is raised. As a result, the characteristic curves of INV41 and INV42 approach and the WM (one side length of the inscribed square) becomes smaller.

  FIG. 7 shows how SNM and WM change with respect to α when the core power supply voltage VDD is 0.8V, 1.0V, and 1.2V. As can be seen from FIG. 7, the SNM increases as α increases, and the WM decreases as α increases. It can also be seen that there is always an α in which SNM and WM are equal.

  In the example shown in FIG. 7, when α = 1.2, SNM and WM are substantially equal. The operation margin of the SRAM cell 220 is determined by the smaller of SNM or WM. Therefore, in order to maximize the operation margin of the SRAM cell 220, both SNM and WM need to have the same value.

  As shown in FIG. 7, when the core power supply voltage VDD is changed, both SNM and WM change in the vertical direction in the same manner. For this reason, the value of α at the intersection of SNM and WM hardly changes. That is, if α (= VMM / VDD) is set to an optimum value, SNM and WM can always be made substantially equal even when the core power supply voltage VDD changes. In the example shown in FIG. 7, by setting α = 1.2, SNM and WM can be set to substantially the same value.

  Patent Document 1 does not take into consideration that the operation margin of the memory cell changes when the core power supply voltage Vdd changes. Therefore, in order to ensure a static noise margin, for example, it is conceivable that the fixed value ΔV is added to the core power supply voltage VDD to make the memory cell voltage VMM higher than the core power supply voltage VDD.

In this case, for example, when VDD1 = 1.0V and the fixed value ΔV to be added is 0.2V,
α1 = (VDD1 + ΔV) /VDD1=1.2/1.0=1.2
It becomes. In this case, SNM and WM are substantially equal values.

However, if the core power supply voltage VDD changes to VDD2 = 0.8V, the fixed value 0.2V does not change.
α2 = (VDD2 + ΔV) /VDD2=1.0/0.8=1.25
It becomes. In this case, the WM is lower than when α1. As described above, when the core power supply voltage VDD changes, the value of α changes, and there is a problem that the operation margin of the SRAM cell 220 is reduced.

  However, according to the present invention, the memory cell voltage VMM can always be kept α times the core power supply voltage VDD in accordance with the change of the core power supply voltage VDD. Thereby, even if the core power supply voltage VDD changes, the operation margin of the SRAM cell 220 can be adjusted to an appropriate value.

  In addition, the memory cell voltage generation unit 300 steps down the I / O power supply voltage VCC higher than the core power supply voltage VDD to generate a memory cell voltage VMM that is α times VDD. As described above, since the memory cell voltage VMM can be generated without using the booster circuit, it is possible to suppress the complexity of the circuit, the increase in area, the increase in power consumption, and the like.

Embodiment 2. FIG.
A semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 8 is a diagram showing a configuration of the semiconductor device 101 according to the present embodiment. In FIG. 8, the same components as those in FIG.

  The semiconductor device 101 according to the present embodiment has a plurality of SRAMs 200. In the example shown in FIG. 8, two SRAMs 200 are provided. As in the first embodiment, the memory cell voltage generation unit 300 generates a memory cell voltage VMM that is α times (α> 1) the core power supply voltage VDD.

  In the semiconductor device 101, the memory cell voltage VMM generated by one memory cell voltage generation unit 300 is used as a power source for the plurality of SRAMs 200. In this way, as described above, an appropriate operation margin can be ensured even if the core power supply voltage VDD changes, and the chip area of the semiconductor device can be reduced.

Embodiment 3 FIG.
A semiconductor device according to Embodiment 3 of the present invention will be described with reference to FIG. FIG. 9 is a diagram showing a configuration of the memory cell voltage generation unit 301 used in the semiconductor device according to the present embodiment. The memory cell voltage generation unit 301 is used in place of the memory cell voltage generation unit 300 shown in FIGS. 9, the same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.

  The memory cell voltage generator 301 shown in FIG. 9 is different from the memory cell voltage generator 300 shown in FIG. 4 in that a PMOS transistor MP11 and an NMOS transistor MN12 are added to a resistor circuit made up of resistors R11 and R12. It is. That is, in the example shown in FIG. 9, the first resistance element includes resistors R11 and MP11, and the second resistance element includes resistors R12 and MN12.

  MP11 and MN12 are substantially the same transistors as the PMOS and NMOS constituting the SRAM cell 220. That is, MP11 is implanted with the same impurities as the PMOS constituting the SRAM cell 220. Further, the same impurity as that of the NMOS constituting the SRAM cell 220 is implanted into MN12. For example, MP11 and MN12 are manufactured simultaneously with the SRAM cell 220.

  The source of MP11 is connected to the contact N21, and one end of a resistor R11 is connected to the drain of MP11. The gate of MP11 is connected to GND. For this reason, MP11 is always ON. The resistance between the source and the drain of MP11 in the normally on state is R11P.

  Further, one end of the resistor R12 is connected to the drain of the MN12, and the source of the MN12 is grounded. The gate of MN12 is connected to the core power supply voltage VDD. For this reason, the MN 12 is always on. The source-drain resistance of the MN 12 in the normally on state is R12N.

  In the specific resistance circuit, each resistance value is set such that R11 + R11P = (α−1) × (R12 + R12N). Thereby, the same effect as Embodiment 1 is acquired. Furthermore, in the present embodiment, a transistor that is substantially the same as the transistor of the SRAM cell 220 is added to the resistor circuit. For this reason, in the manufacturing process, when the transistor characteristics of the SRAM cell 220 vary, the resistance value of the resistance circuit follows this, and the effect of correcting the value of α is obtained.

Embodiment 4 FIG.
The configuration of the semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 10 is a diagram showing a configuration of the memory cell voltage generation unit 302 used in the semiconductor device according to the present embodiment. The memory cell voltage generation unit 302 is used in place of the memory cell voltage generation unit 300 shown in FIGS. 10, the same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.

  The memory cell voltage generator 302 shown in FIG. 10 is different from the memory cell voltage generator 300 shown in FIG. 4 in that a booster circuit 303 is provided. The booster circuit 303 boosts the core power supply voltage VDD, which is the first power supply voltage, to generate a boosted voltage VPP. In the memory cell voltage generation unit 302, the boosted voltage VPP is used as the second power supply voltage instead of the I / O power supply voltage VCC of FIG.

  Memory cell voltage generation unit 302 generates memory cell voltage VMM using boosted voltage VPP. Even in such a case, as in the first embodiment, even if the core power supply voltage VDD changes, the operation margin of the SRAM cell 220 can be adjusted to an appropriate value.

  As described above, according to the present invention, when I (= VMM / VDD) is set so that SNM and WM are substantially equal, the I / O power supply voltage VCC or VDD changes. However, the optimum operation margin of the SRAM cell 220 can be maintained.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, in the above-described example, the example of the single-port type SRAM cell 220 is shown, but the present invention is not limited to this. For example, as shown in FIG. 11, the present invention can be applied to a dual port type SRAM cell 220.

  It is also possible to use transistors that are always ON instead of the resistors R11 and R12 of the memory cell voltage generator 300. In this case, it is preferable to use the same type of transistor as PMOS or NMOS. Thereby, complication of a circuit configuration can be suppressed.

10 Core Power Supply Block 20 I / O Block 30 I / O Power Supply Block 100 Semiconductor Device 200 SRAM
201 memory cell array 202 peripheral circuit 203 control circuit 204 address buffer 205 X-decoder and word line driver 206 Y-decoder 207 Y-select switch 208 precharge circuit 209 write data buffer 210 write driver 211 sense amplifier 212 output buffer 220 SRAM cell 300 Memory cell voltage generator 303 Boost circuit 400 Logic circuit VDD Core power supply voltage VCC I / O power supply voltage VMM Memory cell voltage

Claims (7)

An SRAM having memory cells and peripheral circuits;
A memory cell voltage generator that generates a memory cell voltage that is α times (α> 1) the first power supply voltage in response to a change in the first power supply voltage supplied to the peripheral circuit, and supplies the memory cell voltage to the memory cell; ,
A semiconductor device in which example Bei a,
It said second power supply voltage is applied to the memory cell voltage generating unit,
The memory cell voltage generator is
Having a first resistor element and a second resistive element connected in series, the resistance ratio between the first resistor element and the second resistive element (alpha-1): a resistor circuit is 1,
A voltage difference between the first reference voltage and the second reference voltage, where the first power supply voltage is a first reference voltage and a voltage between the first resistance element and the second resistance element is a second reference voltage. A first differential amplifier that operates to eliminate
The second power supply voltage is supplied to one end, the resistor circuit is connected to the other end, and a first active element whose load changes according to the output of the first differential amplifier ,
Said memory cell voltage generating unit, as the memory cell voltage a voltage between said resistor circuit and said first active element, you output through the buffer circuit
Semiconductor device comprising a call. The buffer circuit is
A voltage difference between the third reference voltage and the fourth reference voltage, where the voltage between the resistance circuit and the first active element is a third reference voltage, and the output memory cell voltage is a fourth reference voltage. A second differential amplifier that operates to eliminate
A second active element having one end supplied with the second power supply voltage and outputting the memory cell voltage from the other end, the load changing according to the output of the second differential amplifier;
A semiconductor device according to claim 1 . It said first resistive element and said second resistive element is a polysilicon semiconductor device according to claim 1 or 2, characterized in that it is formed by any one of the diffusion layer or well. 3. The semiconductor device according to claim 1, wherein the first resistance element and the second resistance element are formed of a transistor that is always on. 4. 5. The semiconductor device according to claim 1 , wherein the first resistance element and the second resistance element include substantially the same transistor as the memory cell. Said memory cell voltage generating unit, a semiconductor device according to any one of claims 1 to 5, wherein the use of I / O power supply as said second power supply voltage. The memory cell voltage generator is
The first boosts the power supply voltage, the semiconductor device according to any one of claims 1 to 6, characterized in that it comprises a booster circuit for generating the second power supply voltage.

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