JP5340398B2 - 半導体コンポーネント用の担体、半導体コンポーネントおよび担体の製造方法 - Google Patents
半導体コンポーネント用の担体、半導体コンポーネントおよび担体の製造方法 Download PDFInfo
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- JP5340398B2 JP5340398B2 JP2011533536A JP2011533536A JP5340398B2 JP 5340398 B2 JP5340398 B2 JP 5340398B2 JP 2011533536 A JP2011533536 A JP 2011533536A JP 2011533536 A JP2011533536 A JP 2011533536A JP 5340398 B2 JP5340398 B2 JP 5340398B2
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Description
Claims (14)
- 半導体コンポーネント用の担体であって、
導電性導体層と接続層とを有しており、
当該導体層と接続層は、向かい合っている主要面を介して相互に接続されており、
前記接続層が完全に導電性であり、少なくとも前記導体層の部分に対して電気的に絶縁されているか、
または、
前記接続層が少なくとも部分的に電気的に絶縁性であり、
前記導体層および前記接続層はそれぞれ少なくとも1つの薄い領域を有しており、当該薄い領域において、各層の層厚は自身の最大層厚よりも薄く、
前記担体および前記導体層および前記接続層は、自己支持形の部材であり、
前記担体は第1の面を有しており、当該第1の面ではカプセル封入用質量体が、導体層および接続層に一体成形され、当該カプセル封入用質量体はシリコーンを含んでおり、
前記導体層の前記薄い領域は、ラテラル方向で、前記接続層の薄い領域と重なっており、
前記重なっている導体層の薄い領域と接続層の薄い領域との間にすき間があり、当該すき間は前記カプセル封入用質量体によって充填されている、
ことを特徴とする半導体コンポーネント用の担体。 - 前記シリコーンは、屈折率が1.41〜1.57の場合、A=20〜D=90のショア硬さを有している、請求項1記載の担体。
- 第2の面を有しており、当該第2の面は前記第1の面に対向しており、
前記第1の面でカプセル封入用質量体が導体層に一体成形されている領域において、前記導体層は当該第2の面で少なくとも部分的にカプセル封入用質量体および電気的絶縁性材料を有していない、請求項1または2記載の担体。 - 前記導体層は少なくとも2つの、電気的に相互に絶縁されている部分を有しており、当該2つの部分は半導体コンポーネント用の第1の接続導体および第2の接続導体を形成し、接続層の少なくとも1つの部分によって相互に機械的に接続されている、請求項1から3までのいずれか1項記載の担体。
- 前記導体層は第1のリードフレームの部分であり、前記接続層は第2のリードフレームの部分であり、当該2つのリードフレームは電気的に絶縁して相互に接続されている、請求項1から4までのいずれか1項記載の担体。
- 前記接続層および/または導体層は貫通部および薄い領域を有しており、当該薄い領域は前記貫通部に接している、請求項1から5までのいずれか1項記載の担体。
- 前記接続層は貫通部を有しており、前記導体層は薄い領域を有しており、前記貫通部はラテラル方向で、前記導体層の薄い領域と重なっている、請求項1から6までのいずれか1項記載の担体。
- 前記接続層は貫通部と、当該貫通部に接している部分とを有しており、当該部分は、導体層の部分にラテラル方向で張り出しており、
これらの領域の間の領域には、担体の材料は設けられていない、請求項1から7までのいずれか1項記載の担体。 - 1つの縁部に接続層の部分が設けられており、当該部分は導体層の部分にラテラル方向で張り出しており、これらの部分の間の領域には担体の材料は設けられていない、請求項1から8までのいずれか1項記載の担体。
- チップ取り付け領域が、導体層部分上に設けられており、当該チップ取り付け領域の面において接続層は導体層の後方に配置されており、
殊に、少なくとも1つの内壁が設けられており、当該内壁の主要延在面は、前記担体または電気的接続導体の接続層の主要延在面に対して傾斜して延在しており、当該主要延在面と比較して、チップ取り付け領域の方に傾いている、請求項1から9までのいずれか1項記載の担体。 - 前記導体層および接続層は接続手段によって相互接続されている、請求項1から10までのいずれか1項記載の担体。
- 請求項1から11までのいずれか1項に記載された担体を備えた半導体コンポーネントであって、
前記導体層には、第1の面で、半導体チップおよび前記カプセル封入用質量体が設けられており、前記カプセル封入用質量体は前記半導体チップを取り囲んでおり、前記担体に一体成形されている、
ことを特徴とする半導体コンポーネント。 - 前記導体層は、前記第1の面に対向している第2の面で、ラテラル方向で、カプセル封入用質量体および/またはカプセル封入用質量体および半導体チップと重なっている領域において、カプセル封入用質量体および電気的絶縁性材料を有していない、請求項12記載の半導体コンポーネント。
- 担体の製造方法であって:
それぞれ、相互に反している2つの主要面を有している導体層と接続層とを供給するステップと;
前記導体層と接続層を自身の2つの主要面を介して、当該主要面が向かい合うように接続するステップとを有し、ここで
前記接続層は導電性であり、前記導体層に対して電気的に絶縁されているか、
または、
前記接続層は電気的に絶縁性であり;
少なくとも1つの薄い領域を、前記導体層および前記接続層内に形成し、当該薄い領域において、各層の層厚は、自身の最大層厚よりも薄く、ここで前記担体および前記導体層および前記接続層は自己支持形の部材であり、前記導体層の前記薄い領域は、ラテラル方向で、前記接続層の薄い領域と重なっており、
カプセル封入用質量体を、前記担体の第1の面に一体成形し、ここで当該カプセル封入用質量体を、前記導体層および接続層に一体成形し、当該カプセル封入用質量体はシリコーンを含んでおり、前記重なっている、前記導体層の薄い領域と前記接続層の薄い領域との間にすき間があり、当該すき間を前記カプセル封入用質量体によって充填する、
ことを特徴とする、担体を製造する方法。
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DE102008053489A DE102008053489A1 (de) | 2008-10-28 | 2008-10-28 | Trägerkörper für ein Halbleiterbauelement, Halbleiterbauelement und Verfahren zur Herstellung eines Trägerkörpers |
PCT/DE2009/001484 WO2010048926A1 (de) | 2008-10-28 | 2009-10-22 | Trägerkörper für ein halbleiterbauelement, halbleiterbauelement und verfahren zur herstellung eines trägerkörpers |
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DE102010027313A1 (de) | 2010-07-16 | 2012-01-19 | Osram Opto Semiconductors Gmbh | Trägervorrichtung für einen Halbleiterchip, elektronisches Bauelement mit einer Trägervorrichtung und optoelektronisches Bauelement mit einer Trägervorrichtung |
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DE102015112757A1 (de) * | 2015-08-04 | 2017-02-09 | Osram Opto Semiconductors Gmbh | Verfahren zum Herstellen eines optoelektronischen Bauelements und optoelektronisches Bauelement |
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WO2010048926A1 (de) | 2010-05-06 |
EP2345074A1 (de) | 2011-07-20 |
KR20110081306A (ko) | 2011-07-13 |
EP2345074B1 (de) | 2016-08-24 |
DE102008053489A1 (de) | 2010-04-29 |
CN102203940B (zh) | 2013-12-25 |
JP2012507157A (ja) | 2012-03-22 |
US20120098110A1 (en) | 2012-04-26 |
TWI389268B (zh) | 2013-03-11 |
US8629549B2 (en) | 2014-01-14 |
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CN102203940A (zh) | 2011-09-28 |
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