JP5338490B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device that grinds the back surface of a semiconductor wafer while leaving an outer edge portion, and more particularly to a method for manufacturing a semiconductor device that can improve the yield when manufacturing semiconductor elements.

  The thinning of semiconductor wafers has become an indispensable technique for improving the characteristics of semiconductor elements. The semiconductor wafer is thinned by a method of forming a semiconductor element on the surface of the semiconductor wafer and then grinding the semiconductor wafer from the back surface to obtain a desired thickness. In this method, when the semiconductor wafer is simply ground from the back surface, the mechanical strength of the semiconductor wafer is reduced and the semiconductor wafer is easily cracked. Also, the semiconductor wafer is likely to warp due to internal stress in the layer due to the electrodes formed on the surface of the semiconductor wafer. As a result, for example, when a semiconductor wafer having a diameter of 6 inches is thinned to a thickness of 100 μm or less, the defect rate of the semiconductor wafer due to cracking or warping increases rapidly.

  A method called a TAIKO process is known as means for preventing an increase in the defect rate of a semiconductor wafer due to the above-described cracks and warpage (see, for example, Patent Document 1). In the TAIKO process, the back surface of the semiconductor wafer is ground while leaving a few mm of the outer edge portion, the inside of the outer edge portion of the semiconductor wafer is thinned, and a recess is formed inside the outer edge portion. When the TAIKO process is applied, the outer edge portion of the semiconductor wafer is not ground and the original thickness is maintained, so that the mechanical strength of the semiconductor wafer is not lowered. For this reason, cracks and warpage of the semiconductor wafer are reduced.

JP 2007-335659 A

  When a power semiconductor device is manufactured by applying the TAIKO process, a circuit pattern may be further formed on the bottom surface of the recess after the recess is formed inside the outer edge of the back surface of the semiconductor wafer. In this case, a resist is applied to the bottom surface of the recess by spin coating, and a resist pattern is formed on the bottom surface of the recess. When the resist is applied to the bottom surface of the recess by spin coating, the resist applied to the bottom surface of the recess is blocked by the outer edge portion and collected near the outer edge portion. As a result, a thick resist film is formed in the vicinity of the outer edge of the recess. Thereby, when forming a resist pattern, an opening defect occurs in the resist film near the outer edge. For this reason, the yield at the time of manufacturing a power semiconductor device is lowered.

  In the TAIKO process, when the back surface of the semiconductor wafer is mechanically ground, the bottom surface of the recess may be wet-etched by a spin method in order to remove a crushed layer generated by the mechanical grinding. In this case, the etching solution dropped on the bottom surface of the recess is blocked by the outer edge portion and remains in the vicinity of the outer edge portion. As a result, the semiconductor wafer is etched and thinned near the outer edge of the recess. Thereby, a breakdown voltage defect occurs in the semiconductor element formed on the surface of the semiconductor wafer. For this reason, the yield at the time of manufacturing a semiconductor element falls.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device capable of improving the yield when manufacturing a semiconductor element.

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a semiconductor element on a surface of a semiconductor wafer; and grinding the back surface of the semiconductor wafer while leaving the outer edge portion after forming the semiconductor element. A step of forming a recess on the inner side, a step of grinding a part of the outer edge portion to form a groove portion that leads from the inner side to the outer side of the outer edge portion, and after forming the groove portion, the resist is formed by spin coating. A plurality of groove portions are formed as the groove portions, and the total length of the outer circumference of the semiconductor wafer and the width of the plurality of groove portions is R1 and R2, respectively. The value of -R2) / R1 is in the range of 0.2 to 0.8 .

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a step of forming a semiconductor element on a surface of a semiconductor wafer; and after forming the semiconductor element, the rear surface of the semiconductor wafer is ground to leave the outer edge portion. A step of forming a recess on the inside, a step of grinding a part of the outer edge to form a groove that leads from the inside to the outside of the outer edge, and after forming the groove, the bottom surface of the recess is formed by a spin method. Wet etching , forming a plurality of groove portions as the groove portions, and assuming that the total value of the length of the outer circumference of the semiconductor wafer and the width of the plurality of groove portions is R1 and R2, respectively (R1-R2 ) / R1 is in the range of 0.2 to 0.8 .

  According to the present invention, the yield at the time of manufacturing a semiconductor element can be improved.

FIG. 5 is a process diagram illustrating the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 5 is a process diagram illustrating the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 5 is a process diagram illustrating the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 5 is a process diagram illustrating the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 5 is a process diagram illustrating the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 5 is a process diagram illustrating the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 5 is a process diagram illustrating the method for manufacturing the power semiconductor device according to the first embodiment. It is process drawing which shows the principal part of the manufacturing method of the power semiconductor device which concerns on a comparative example. It is process drawing which shows the principal part of the manufacturing method of the power semiconductor device which concerns on a comparative example. FIG. 10 is a process diagram showing a groove on the back surface of the semiconductor wafer according to a modification of the first embodiment. FIG. 10 is a process diagram illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process diagram illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process diagram illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process diagram illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process diagram illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process diagram illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 11 is a process diagram showing a groove on the back surface of a semiconductor wafer according to a modification of the second embodiment. 10 is a graph showing the relationship between the thickness of a semiconductor wafer and the amount of warpage according to the third embodiment. FIG. 10 is a process diagram showing a groove on the back surface of a semiconductor wafer according to a fourth embodiment. 14 is a graph showing the relationship between the width W1 of the groove portion of the semiconductor wafer and the amount of warpage according to the fourth embodiment. 14 is a graph showing the relationship between the width W1 of the groove of the semiconductor wafer according to the fourth embodiment and the thickness of the resist film near the outer edge of the recess. FIG. 10 is a process diagram showing the back surface of the semiconductor wafer according to the fifth embodiment. 10 is a graph showing the relationship between the value of (R1-R2) / R1 and the amount of warpage of a semiconductor wafer according to a fifth embodiment. 14 is a graph showing the relationship between the value of (R1-R2) / R1 of a semiconductor wafer according to a fifth embodiment and the thickness of a resist film near the outer edge of a recess. FIG. 10 is a process diagram showing the back surface of the semiconductor wafer according to the sixth embodiment. FIG. 26 is a process diagram illustrating the back surface of a semiconductor wafer according to a modification of the sixth embodiment.

Embodiment 1 FIG.
A method for manufacturing the power semiconductor device according to the first embodiment will be described below. A TAIKO process is applied to this manufacturing method. 1 to 7 are process diagrams showing the method for manufacturing the power semiconductor device according to the first embodiment. 1, 2, 5, and 7 are cross-sectional process diagrams showing a cross section of a semiconductor wafer. 3 and 4 are process diagrams showing the back surface of the semiconductor wafer. FIG. 6 is a process diagram showing a groove on the back surface of the semiconductor wafer.

  First, as shown in FIG. 1, a power semiconductor element 14 having an aluminum electrode 12 is formed on the surface of a semiconductor wafer 10.

  Next, as shown in FIG. 2, the surface of the semiconductor wafer 10 is attached to a protective substrate 16 in order to protect the power semiconductor element 14. At this time, the semiconductor wafer 10 is not thinned, and its thickness is about 725 μm.

  Next, as shown in FIG. 3, a resist pattern 20 is formed on the outer edge portion 18 on the back surface of the semiconductor wafer 10. At this time, the outer edge 18 is provided with a gap 22 where the resist pattern 20 is not formed.

  Next, dry etching is performed on a portion of the back surface of the semiconductor wafer 10 where the resist pattern 20 is not formed. As a result, as shown in FIGS. 4 and 5, the back surface of the semiconductor wafer 10 is ground leaving the outer edge portion 18 having a width of about 2 mm, and the inner side of the outer edge portion 18 is thinned to the inner side of the outer edge portion 18. A recess 24 is formed.

  And the clearance gap 22 of the outer edge part 18 is also ground simultaneously, and the groove part 26 which leads outside from the inner side of the outer edge part 18 is formed. When forming the groove part 26, as shown in FIG. 6, the corner | angular corner part 28 by the side of the recessed part 24 of the outer edge part 18 is rounded off.

  Next, as shown in FIG. 7, in order to form a circuit pattern on the bottom surface of the recess 24, a resist 30 is applied to the bottom surface of the recess 24 by spin coating.

  The effects of the first embodiment will be described in comparison with a comparative example. 8 and 9 are process diagrams showing the main part of the method for manufacturing the power semiconductor device according to the comparative example. FIG. 8 is a process diagram showing the back surface of the semiconductor wafer. FIG. 9 is a sectional process diagram showing a section of the semiconductor wafer.

  In the comparative example, as shown in FIG. 8, when the recess 24 is formed inside the outer edge portion 18 by grinding the back surface of the semiconductor wafer 10, the groove portion 26 that communicates from the inside to the outside of the outer edge portion 18 is not formed. For this reason, as shown in FIG. 9, when the resist 30 is applied to the bottom surface of the recess 24 by spin coating, the resist 30 accumulates in the vicinity of the outer edge portion 18 of the recess 24. As a result, a thick resist film is formed in the vicinity of the outer edge portion 18 of the recess 24, and an opening defect occurs.

  On the other hand, in the first embodiment, when the back surface of the semiconductor wafer 10 is ground, the groove portion 26 communicating from the inner side to the outer side of the outer edge portion 18 is formed. For this reason, when the resist 30 is applied to the bottom surface of the recess 24 by spin coating, the excess resist 30 is discharged to the outside of the semiconductor wafer 10 through the groove 26. Further, since the corner portion 28 is rounded, excess resist 30 is easily discharged through the groove portion 26.

  For this reason, it is possible to prevent the resist 30 from accumulating near the outer edge portion 18 of the recess 24. Accordingly, it is possible to prevent the occurrence of defective opening in the resist film formed in the vicinity of the outer edge portion 18 of the recess 24, and to improve the yield when manufacturing the power semiconductor element 14.

  A modification of the first embodiment will be described. FIG. 10 is a process diagram showing the groove on the back surface of the semiconductor wafer according to the modification of the first embodiment. In this modification, instead of rounding the corner portion 28 when forming the groove portion 26, the direction of the boundary between the outer edge portion 18 and the groove portion 26 on the back surface of the semiconductor wafer 10 and from the outside of the outer edge portion 18 toward the inside a The angle α in the b direction opposite to the direction and the direction in which the groove 26 moves when the resist is applied is made larger than 90 degrees. This makes it easy for excess resist 30 to be discharged to the outside of the semiconductor wafer 10 through the groove 26. For this reason, it is possible to prevent the resist 30 from accumulating in the vicinity of the outer edge portion 18 of the recess 24 and to improve the yield.

  In the first embodiment, the angle α may not be larger than 90 degrees without rounding the corner portion 28. Also in this case, excess resist 30 can be discharged to the outside of the semiconductor wafer 10 through the groove 26. For this reason, it is possible to prevent the resist 30 from accumulating in the vicinity of the outer edge portion 18 of the recess 24 and to improve the yield.

  Moreover, although the recessed part 24 and the groove part 26 were formed by applying dry etching, wet etching may be applied. In the case of applying wet etching, the resist pattern may be used as a mask for etching with hydrofluoric acid, or the oxide film may be used as a mask for etching with potassium hydroxide. Alternatively, etching may be performed using a seal packing provided in the etching pot as a mask. Moreover, you may form the recessed part 24 and the groove part 26 by applying mechanical grinding instead of dry etching or wet etching. Even if it takes any method, the same effect is acquired.

Embodiment 2. FIG.
A method for manufacturing the semiconductor device according to the second embodiment will be described below. A TAIKO process is applied to this manufacturing method. 11 to 16 are process diagrams showing the method for manufacturing the semiconductor device according to the second embodiment. 11, FIG. 12, FIG. 14 and FIG. 16 are cross-sectional process diagrams showing a cross section of a semiconductor wafer. FIG. 13 is a process diagram showing the back surface of the semiconductor wafer. FIG. 15 is a process diagram showing a groove on the back surface of the semiconductor wafer.

  First, as shown in FIG. 11, the semiconductor element 32 having the aluminum electrode 12 is formed on the surface of the semiconductor wafer 10.

  Next, as shown in FIG. 12, the surface of the semiconductor wafer 10 is attached to the protective substrate 16 in order to protect the semiconductor element 32.

  Next, as shown in FIGS. 13 and 14, the back surface of the semiconductor wafer 10 is mechanically ground leaving the outer edge portion 18 having a width of about 2 mm, and the inner side of the outer edge portion 18 of the semiconductor wafer 10 is thinned to form an outer edge. A recess 24 is formed inside the portion 18.

  A part of the outer edge 18 is also mechanically ground at the same time to form a groove 26 that leads from the inside to the outside of the outer edge 18. At this time, as shown in FIG. 15, the corner portion 28 on the concave portion 24 side of the outer edge portion 18 is rounded.

  Next, as shown in FIG. 16, in order to remove the crushed layer generated by the mechanical grinding, the bottom surface of the recess 24 is wet-etched by a spin method using an etching solution 34.

  The effect of the second embodiment will be described. When the back surface of the semiconductor wafer 10 is mechanically ground, a groove portion 26 that leads from the inside to the outside of the outer edge portion 18 is formed. For this reason, when the bottom surface of the recess 24 is wet-etched by the spin method, excess etching solution 34 is discharged to the outside of the semiconductor wafer 10 through the groove 26. Further, since the corner portion 28 on the concave portion 24 side of the outer edge portion 18 is rounded, the excess etching solution 34 is easily discharged.

  For this reason, it is possible to prevent the etching liquid 34 from collecting near the outer edge portion 18 on the bottom surface of the concave portion 24 and grinding the vicinity of the outer edge portion 18 on the bottom surface of the concave portion 24 more than necessary. Therefore, it is possible to prevent a breakdown voltage failure from occurring in the semiconductor element 32 and improve the yield when manufacturing the semiconductor element 32.

  A modification of the second embodiment will be described. FIG. 17 is a process diagram showing a groove on the back surface of the semiconductor wafer according to a modification of the second embodiment. In this modification, instead of rounding the corner portion 28 when forming the groove portion 26, the direction of the boundary between the outer edge portion 18 and the groove portion 26 on the back surface of the semiconductor wafer 10 and from the outside of the outer edge portion 18 toward the inside a The angle α in the b direction opposite to the direction and the direction in which the groove 26 moves when the bottom surface of the recess 24 is wet-etched is set to be greater than 90 degrees. As a result, excess etching liquid 34 is easily discharged to the outside of the semiconductor wafer 10 through the groove 26. For this reason, it is possible to effectively prevent the etching liquid 34 from accumulating in the vicinity of the outer edge portion 18 of the concave portion 24 and improve the yield.

Embodiment 3 FIG.
Only the differences from the first embodiment of the method for manufacturing a power semiconductor device according to the third embodiment will be described below. In the third embodiment, the semiconductor wafer 10 having a diameter of 6 inches is used. And when forming the recessed part 24 inside the outer edge part 18, the thickness of the semiconductor wafer 10 in the recessed part 24 shall be 80 micrometers.

  FIG. 18 is a graph showing the relationship between the thickness of the semiconductor wafer and the warpage amount according to the third embodiment. In the semiconductor wafer 10 having a diameter of 6 inches, when the thickness is 130 μm or less, the amount of warpage increases rapidly, and cracks due to warpage tend to occur. In the third embodiment, the thickness of the semiconductor wafer 10 in the recess 24 is 80 μm. Therefore, as compared with the first embodiment, the resist 30 can be prevented from accumulating near the outer edge portion 18 of the recess 24 and the yield can be improved while preventing the warpage of the semiconductor wafer 10 more effectively.

  In the third embodiment, even if the thickness of the semiconductor wafer 10 in the recess 24 is not 80 μm, the same effect can be obtained as long as it is 130 μm or less.

Embodiment 4 FIG.
Only the points of the method for manufacturing the power semiconductor device according to the fourth embodiment that are different from the first embodiment will be described below. FIG. 19 is a plan view showing a groove on the back surface of the semiconductor wafer according to the fourth embodiment. In the fourth embodiment, a semiconductor wafer 10 having a diameter of 6 inches is used. When forming the groove 26, the width W1 of the groove 26 in the outer peripheral direction of the semiconductor wafer 10 is set to 9 mm.

  FIG. 20 is a graph showing the relationship between the width W1 of the groove of the semiconductor wafer according to the fourth embodiment and the amount of warpage. FIG. 21 is a graph showing the relationship between the width W1 of the groove of the semiconductor wafer according to the fourth embodiment and the thickness of the resist film near the outer edge of the recess. FIG. 20 shows a relative value with respect to the warping amount when the groove 26 is not provided in the outer edge portion 18. FIG. 21 shows a relative value with respect to the thickness of the resist film when the entire back surface 00 is ground and the outer edge portion 18 is not provided. As shown in FIG. 20, when the width W1 of the groove part 26 becomes larger than 10 mm, the amount of warpage increases. As shown in FIG. 21, when the width W1 of the groove 26 is smaller than 1 mm, the thickness of the resist film increases.

  In the fourth embodiment, the width W1 of the groove 26 is 9 mm. For this reason, the amount of warpage does not increase compared to when the outer edge 18 is not provided with the groove 26, and the thickness of the resist film does not increase compared to when the outer edge 18 is not provided. That is, the warpage of the semiconductor wafer 10 can be prevented more effectively than in the first embodiment, and the resist can be prevented from collecting near the outer edge 18 of the recess 24, thereby improving the yield.

  In the fourth embodiment, even if the width W1 of the groove portion 26 in the outer peripheral direction of the semiconductor wafer 10 is not 9 mm, the same effect can be obtained if the width W1 is in the range of 1 mm to 10 mm.

Embodiment 5 FIG.
In the following, the method of manufacturing the power semiconductor device according to the fifth embodiment will be described while referring to differences from the fourth embodiment. FIG. 22 is a process diagram showing the back surface of the semiconductor wafer according to the fifth embodiment. In the fifth embodiment, similar to the fourth embodiment, the semiconductor wafer 10 having a diameter of 6 inches is used, and the width W1 of the groove 26 in the outer peripheral direction of the semiconductor wafer 10 is set to 9 mm. Then, 15 groove portions 26 are formed as the groove portions 26. As a result, when the total length of the outer peripheral length of the semiconductor wafer 10 and the width W1 of the 15 groove portions 26 is R1 and R2, respectively, the value of (R1-R2) / R1 is set to 0.718.

  FIG. 23 is a graph showing the relationship between the value of (R1-R2) / R1 and the amount of warpage of the semiconductor wafer according to the fifth embodiment. FIG. 24 is a graph showing the relationship between the value of (R1-R2) / R1 of the semiconductor wafer according to the fifth embodiment and the thickness of the resist film near the outer edge of the recess. FIG. 23 shows a relative value with respect to the warp amount when the outer edge 18 is not provided with the groove 26. FIG. 24 shows a relative value with respect to the thickness of the resist film when the entire back surface of the semiconductor wafer 10 is ground and the outer edge portion 18 is not provided. As shown in FIG. 23, when the value of (R1-R2) / R1 becomes smaller than 0.2, the amount of warpage increases rapidly. Further, as shown in FIG. 24, when the value of (R1-R2) / R1 becomes larger than 0.8, the thickness of the resist film near the outer edge 18 increases rapidly.

  In the fifth embodiment, 15 groove portions 26 having a width W1 of 9 mm are formed, and the value of (R1-R2) / R1 is 0.718. For this reason, the amount of warpage does not increase so much as compared with the case where the groove 26 is not provided in the outer edge portion 18, and the thickness of the resist film does not increase so much as compared with the case where the outer edge portion 18 is not provided. That is, the warpage of the semiconductor wafer 10 can be prevented more effectively than in the fourth embodiment, and the resist can be prevented from accumulating in the vicinity of the outer edge portion 18 of the recess 24, thereby improving the yield.

  In the fifth embodiment, even if the value of (R1-R2) / R1 is not set to 0.718, the same effect can be obtained by setting the value within the range of 0.2 to 0.8.

Embodiment 6 FIG.
In the following, the method of manufacturing a semiconductor device according to the sixth embodiment will be described while referring to differences from the first embodiment. FIG. 25 is a process diagram showing the back surface of the semiconductor wafer according to the sixth embodiment. In the sixth embodiment, the notch region 36 cut out from the front surface to the back surface of the semiconductor wafer 10 is formed before the recess 24 is formed by grinding the back surface of the semiconductor wafer 10. Since the groove portion 26 is formed in the notch region 36, the thinned groove portion 26 can be prevented from contacting when the semiconductor wafer 10 is transported in the carrier storage container or the process apparatus. For this reason, it is possible to prevent the semiconductor wafer 10 from being broken and to improve the yield.

  A modification of the sixth embodiment will be described. FIG. 26 is a process diagram showing the back surface of the semiconductor wafer according to the modification of the sixth embodiment. In this modification, a cutout region 38 cut out from the front surface to the back surface of the semiconductor wafer 10 is formed separately from the notch region 36, and the groove 26 is also formed in the cutout region 38. For this reason, when the resist 30 is applied to the bottom surface of the recess 24, the excess resist 30 is discharged to the outside of the semiconductor wafer 10 through the plurality of grooves 26. Therefore, it is possible to prevent the resist 30 from accumulating more effectively than in the sixth embodiment, thereby improving the yield and preventing the semiconductor wafer 10 from cracking.

DESCRIPTION OF SYMBOLS 10 Semiconductor wafer 14 Power semiconductor element 18 Outer edge part 24 Recessed part 26 Groove part 28 Corner part 30 Resist 32 Semiconductor element 34 Etching solution 36 Notch area

Claims (7)

Forming a semiconductor element on the surface of the semiconductor wafer;
After forming the semiconductor element, the step of grinding the back surface of the semiconductor wafer leaving an outer edge portion to form a recess inside the outer edge portion;
Grinding a part of the outer edge to form a groove that leads from the inside to the outside of the outer edge; and
After forming the groove, applying a resist to the bottom surface of the recess by spin coating ,
When a plurality of groove portions are formed as the groove portions, and the total value of the length of the outer circumference of the semiconductor wafer and the width of the plurality of groove portions is R1 and R2, respectively, the value of (R1-R2) / R1 is 0.2. A method for manufacturing a semiconductor device, characterized in that the range is in the range of -0.8 . Forming a semiconductor element on the surface of the semiconductor wafer;
After forming the semiconductor element, the step of grinding the back surface of the semiconductor wafer leaving an outer edge portion to form a recess inside the outer edge portion;
Grinding a part of the outer edge to form a groove that leads from the inside to the outside of the outer edge; and
A step of performing wet etching on the bottom surface of the concave portion by a spin method after forming the groove portion , and
When a plurality of groove portions are formed as the groove portions, and the total value of the length of the outer circumference of the semiconductor wafer and the width of the plurality of groove portions is R1 and R2, respectively, the value of (R1-R2) / R1 is 0.2. A method for manufacturing a semiconductor device, characterized in that the range is in the range of -0.8 . The semiconductor wafer has a diameter of 6 inches;
2. The method of manufacturing a semiconductor device according to claim 1, wherein when the groove portion is formed, a width of the groove portion in the outer peripheral direction of the semiconductor wafer is in a range of 1 mm to 10 mm.   3. The method of manufacturing a semiconductor device according to claim 1, wherein when forming the groove portion, a corner portion on the concave portion side of the outer edge portion is rounded. 4.   When forming the groove portion, the direction of the boundary between the outer edge portion and the groove portion on the back surface of the semiconductor wafer and from the outside to the inside of the outer edge portion, and the direction in which the groove portion moves when the resist is applied The method of manufacturing a semiconductor device according to claim 1, wherein an angle with a direction opposite to the direction is larger than 90 degrees.   When forming the groove portion, the groove portion moves when wet etching is performed on the bottom surface of the concave portion in the direction of the boundary between the outer edge portion and the groove portion on the back surface of the semiconductor wafer and from the outside to the inside of the outer edge portion. 3. The method of manufacturing a semiconductor device according to claim 2, wherein an angle with a direction opposite to the direction in which the direction is made is greater than 90 degrees.   3. The method according to claim 1, further comprising a step of forming a notch region cut out from the surface of the semiconductor wafer to the back surface of the semiconductor wafer before forming the recess, and forming the groove in the notch region. The manufacturing method of the semiconductor device of description.

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