JP2005123425A - Semiconductor substrate manufacturing method, semiconductor substrate and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor substrate manufacturing method having high processing accuracy and suited to mass production, semiconductor substrates manufactured by the method, and a method for manufacturing semiconductor devices. <P>SOLUTION: The semiconductor substrate manufacturing method is provided with a first process for thinning an element 1b which is the element forming area of a semiconductor substrate 1 by blast and/or etching, and a second process for further thinning the thinned element 1b by polishing. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device for power, for example, a semiconductor substrate used therefor, and a method for manufacturing the same.

In a vertical semiconductor device, the substrate is made thinner in order to reduce the on-resistance and reduce the loss. However, if the substrate thickness is reduced, cracks during handling and deformation during heat treatment occur. For this reason, a technique has been proposed in which a concave groove is locally provided by sandblasting only in a portion serving as a conductive region of each element, and the substantial substrate thickness is reduced to 215 μm (see, for example, Patent Document 1). .
Japanese Patent Laid-Open No. 10-50718

  In recent years, thinning has progressed, and a substrate thickness of 100 μm or less is required. In such a thin substrate, the substrate strength is further reduced and stress deformation occurs. For example, in a uniformly processed wafer having a substrate diameter of 150 mm and a substrate thickness of 100 μm, warpage of 4 mm or more occurs due to film stress on the substrate. . When the thickness is further reduced to 60 μm, the warpage is expected to exceed 10 mm. In such a thin substrate, a method of thinning only the element portion is considered effective.

  On the other hand, as a conventional thinning method, dry etching is generally used in addition to the above-described sandblasting. This is a technique of performing masking and removing only necessary portions by embrittlement removal or etching. However, according to these methods, a processing variation of 10% or more of the thickness to be removed occurs.

  For example, when the substrate thickness is 625 μm and the element thickness is reduced to 50 μm, the removed thickness is 575 μm, and when the variation is 10%, the actual element thickness is 50 ± 28.8 μm. End up. In a vertical semiconductor device for electric power or the like, the element portion thickness determines the withstand voltage characteristic, and therefore it is necessary for practical use to be within ± 3 μm, and there is a problem that these thinning methods cannot cope.

  Polishing is an example of a technique for suppressing the variation. As shown in a top view in FIG. 9 and a cross-sectional view in FIG. 10, the polishing head 4 smaller than the processing diameter is revolved on the semiconductor substrate 1 to thin only the element portion 1b. The variation can be controlled to about ± 2 μm or less regardless of the processing thickness. However, the processing speed is 3 μm / min or less, and the processing time for one sheet is about 200 minutes, which is not suitable for mass production. Further, there is a problem that the polishing head comes into contact with the edge portion of the element portion and cracks and chipping occur on the substrate.

  Therefore, an object of the present invention is to provide a semiconductor substrate manufacturing method, a semiconductor substrate manufacturing method, and a semiconductor device manufacturing method that eliminate conventional problems, have high processing accuracy, and are suitable for mass production.

  According to one aspect of the present invention, a first step of thinning an element portion that is an element formation region of a semiconductor substrate by blasting and / or etching, and the thinned element portion is further thinned by polishing. There is provided a method for manufacturing a semiconductor substrate, comprising a second step of performing chemical processing.

  In addition, according to one embodiment of the present invention, there is provided a semiconductor substrate having a recess on at least one surface and having an inner surface tapered.

  According to one aspect of the present invention, the first element region is formed on the main surface of the semiconductor substrate, and the back surface of the first element region is thinned by blasting and / or etching. 1 thinning step, a second thinning step of further thinning the thinned back surface of the first element region by polishing, and a second element on the back surface of the first element region A method for manufacturing a semiconductor device is provided, which includes a step of forming a region.

  According to one embodiment of the present invention, it is possible to provide a method for manufacturing a semiconductor substrate, a semiconductor substrate, and a method for manufacturing a semiconductor device that have high processing accuracy and are suitable for mass production.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a top view of a semiconductor substrate in the present embodiment, and FIG. As shown in the figure, a semiconductor substrate (silicon substrate) 1 has a concave shape in which a peripheral portion 1a is thick and a central element portion 1b is thin, and an inner wall 1c has a taper. A first element region (surface element) 2 is formed on the side opposite to the surface where the recess is formed.

  Such a semiconductor substrate is formed as follows. That is, first, as shown in FIG. 3, using a semiconductor substrate having a thickness of, for example, 625 μm in which the first element region is formed, masking 3 is applied to the peripheral portion of the semiconductor substrate as shown in FIG. Is used to thin the element portion 1b (primary processing). At this time, by controlling the abrasive spray pressure and making the abrasive grain size uniform, the variation in processing thickness is kept within ± 5% of the processing thickness, and the surface crushing layer generated by processing is reduced to 5 μm or less. Suppress.

  By such blasting, as shown in FIG. 5, the primary processing thickness is 542 μm, that is, the element thickness is 83 μm ± 27 μm (56 to 110 μm), and a taper of about 70 ° is formed. At this time, a normal silicon layer without a crushed layer is at least 51 to 105 μm.

  Next, as shown in FIG. 6, secondary processing is performed using a polishing apparatus having a polishing head 4 smaller than the processing diameter, and the element portion is thinned until the thickness becomes 50 μm. Due to variations in blast processing, the maximum processing amount is 55 μm, but the minimum processing amount is 1 μm. Therefore, partial thinning may be performed, and the apparent processing speed is about twice that of the conventional processing speed.

  The element thickness of the semiconductor substrate thinned as shown in FIG. 1 through such steps is 50 ± 2 μm, and a semiconductor substrate with high processing accuracy and sufficiently suitable for practical use can be obtained.

  Further, a second element region is formed in the element portion (recessed portion) of the semiconductor substrate thus obtained. Then, for example, through an electrode formation process on each element region (each main surface) and a subsequent process, for example, current flows from one electrode to the other electrode through the pn junction formed in each element area of the semiconductor substrate. A vertical semiconductor device or the like for power flowing through is formed.

In the present embodiment, primary processing is performed by blasting, but etching can also be used. In this case, dry etching is preferable. For example, the etching gas is CF ₄ or SF _6, and RIE (Reactive Ion Etching) or ICP (Inductive Coupled Plasma) etching can be used.

  Further, it is preferable to provide a taper on the inner surface, and by providing the taper, the polishing head comes into contact with the edge part of the element part during the secondary processing by the polishing apparatus, and cracks and chipping occur on the substrate. Can be suppressed. Further, since there are no acute angle portions, it is possible to suppress cracking and warping of the substrate. Such a taper is provided at the time of blasting, and the angle is preferably about 70 ± 3 ° depending on the processing characteristics.

  Furthermore, the element part (concave part) is not limited to one place, and a plurality of small parts may be formed as shown in a top view in FIG. 7 and a sectional view in FIG. With such a structure, a thick portion of the substrate is also formed inside the substrate, so that the substrate strength is improved. However, if the size is too small, it is necessary to reduce the size of the polishing head, and the processing ability decreases. Moreover, you may form not only on one side but on both surfaces.

  In addition, this invention is not limited to embodiment mentioned above. Various other modifications can be made without departing from the scope of the invention.

The figure which shows the semiconductor substrate by one Embodiment of this invention. The figure which shows the semiconductor substrate by one Embodiment of this invention. The figure which shows the manufacturing process of the semiconductor substrate by one Embodiment of this invention. The figure which shows the manufacturing process of the semiconductor substrate by one Embodiment of this invention. The figure which shows the manufacturing process of the semiconductor substrate by one Embodiment of this invention. The figure which shows the manufacturing process of the semiconductor substrate by one Embodiment of this invention. The figure which shows the semiconductor substrate by one Embodiment of this invention. The figure which shows the semiconductor substrate by one Embodiment of this invention. The figure which shows the manufacturing process of the conventional semiconductor substrate. The figure which shows the manufacturing process of the conventional semiconductor substrate.

Explanation of symbols

1 Semiconductor substrate (silicon substrate)
DESCRIPTION OF SYMBOLS 1a Peripheral part 1b Element part 1c Inner side wall 2 First element area 3 Mask 4 Polishing head

Claims (5)

A first step of thinning an element portion which is an element formation region of a semiconductor substrate by blasting and / or etching;
A method of manufacturing a semiconductor substrate, comprising: a second step of further thinning the thinned element portion by polishing.   The method of manufacturing a semiconductor substrate according to claim 1, wherein the thinned inner side surface of the semiconductor substrate has a taper.   A semiconductor substrate having a recess on at least one surface, the inner surface having a taper. Forming a first element region on a main surface of a semiconductor substrate;
A first thinning step of thinning the back surface of the first element region by blasting and / or etching;
A second thinning step of further thinning the thinned back surface of the first element region by polishing;
A method of manufacturing a semiconductor device, comprising: forming a second element region on a back surface of the first element region.   The semiconductor device has at least one pn junction between two opposing main surfaces of a semiconductor substrate, and a main current is passed through the pn junction from one electrode on the main surface of the semiconductor substrate. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is made to flow through the electrode on the main surface.

Images