JP5335440B2 - オペランドの早期の条件付き選択 - Google Patents

オペランドの早期の条件付き選択 Download PDF

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Publication number
JP5335440B2
JP5335440B2 JP2008551563A JP2008551563A JP5335440B2 JP 5335440 B2 JP5335440 B2 JP 5335440B2 JP 2008551563 A JP2008551563 A JP 2008551563A JP 2008551563 A JP2008551563 A JP 2008551563A JP 5335440 B2 JP5335440 B2 JP 5335440B2
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Japan
Prior art keywords
operand
instruction
operands
pipeline
execution
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Expired - Fee Related
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JP2008551563A
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English (en)
Japanese (ja)
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JP2009524167A5 (enExample
JP2009524167A (ja
Inventor
ディーフェンダーファー、ジェームズ・ノリス
ブリッジス、ジェフリー・トッド
マクイルバイン、マイケル・スコット
サートリウス、トマス・アンドリュー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
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Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of JP2009524167A publication Critical patent/JP2009524167A/ja
Publication of JP2009524167A5 publication Critical patent/JP2009524167A5/ja
Application granted granted Critical
Publication of JP5335440B2 publication Critical patent/JP5335440B2/ja
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Anticipated expiration legal-status Critical

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
JP2008551563A 2006-01-20 2007-01-22 オペランドの早期の条件付き選択 Expired - Fee Related JP5335440B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/336,357 2006-01-20
US11/336,357 US9710269B2 (en) 2006-01-20 2006-01-20 Early conditional selection of an operand
PCT/US2007/060814 WO2007085010A2 (en) 2006-01-20 2007-01-22 Early conditional selection of an operand

Publications (3)

Publication Number Publication Date
JP2009524167A JP2009524167A (ja) 2009-06-25
JP2009524167A5 JP2009524167A5 (enExample) 2012-03-01
JP5335440B2 true JP5335440B2 (ja) 2013-11-06

Family

ID=38286963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008551563A Expired - Fee Related JP5335440B2 (ja) 2006-01-20 2007-01-22 オペランドの早期の条件付き選択

Country Status (6)

Country Link
US (1) US9710269B2 (enExample)
EP (2) EP2461246B1 (enExample)
JP (1) JP5335440B2 (enExample)
KR (1) KR100986375B1 (enExample)
CN (1) CN101371223B (enExample)
WO (1) WO2007085010A2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5739055B2 (ja) 2011-04-01 2015-06-24 インテル コーポレイション ベクトルフレンドリ命令フォーマット及びその実行
CN104011670B (zh) 2011-12-22 2016-12-28 英特尔公司 用于基于向量写掩码的内容而在通用寄存器中存储两个标量常数之一的指令
US9280344B2 (en) * 2012-09-27 2016-03-08 Texas Instruments Incorporated Repeated execution of instruction with field indicating trigger event, additional instruction, or trigger signal destination
KR101711388B1 (ko) 2013-01-28 2017-03-02 삼성전자주식회사 파이프라인에서 블럭을 스케줄하는 컴파일 방법 및 장치
US10459727B2 (en) 2015-12-31 2019-10-29 Microsoft Technology Licensing, Llc Loop code processor optimizations
US10592252B2 (en) 2015-12-31 2020-03-17 Microsoft Technology Licensing, Llc Efficient instruction processing for sparse data
US11385897B2 (en) * 2019-10-01 2022-07-12 Marvell Asia Pte, Ltd. Merge execution unit for microinstructions
US12430127B1 (en) 2024-03-27 2025-09-30 International Business Machines Corporation Vector test decimal instruction for validity testing

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US5150469A (en) * 1988-12-12 1992-09-22 Digital Equipment Corporation System and method for processor pipeline control by selective signal deassertion
GB2228597A (en) * 1989-02-27 1990-08-29 Ibm Data processor with conditional instructions
JP3082944B2 (ja) 1990-12-20 2000-09-04 富士通株式会社 パイプライン処理装置
GB2291515B (en) 1994-07-14 1998-11-18 Advanced Risc Mach Ltd Data processing using multiply-accumulate instructions
US5699537A (en) * 1995-12-22 1997-12-16 Intel Corporation Processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions
TW325552B (en) 1996-09-23 1998-01-21 Advanced Risc Mach Ltd Data processing condition code flags
GB2317466B (en) 1996-09-23 2000-11-08 Advanced Risc Mach Ltd Data processing condition code flags
TW343318B (en) 1996-09-23 1998-10-21 Advanced Risc Mach Ltd Register addressing in a data processing apparatus
GB2317464A (en) 1996-09-23 1998-03-25 Advanced Risc Mach Ltd Register addressing in a data processing apparatus
US6173393B1 (en) * 1998-03-31 2001-01-09 Intel Corporation System for writing select non-contiguous bytes of data with single instruction having operand identifying byte mask corresponding to respective blocks of packed data
JP2000020309A (ja) * 1998-06-30 2000-01-21 Toshiba Microelectronics Corp デジタルシグナルプロセッサ
JP2001051845A (ja) 1999-08-12 2001-02-23 Hitachi Ltd アウトオブオーダー実行方式
US6633971B2 (en) * 1999-10-01 2003-10-14 Hitachi, Ltd. Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipeline
US20050188182A1 (en) * 1999-12-30 2005-08-25 Texas Instruments Incorporated Microprocessor having a set of byte intermingling instructions
US6604192B1 (en) 2000-01-24 2003-08-05 Hewlett-Packard Development Company, L.P. System and method for utilizing instruction attributes to detect data hazards
JP2001216275A (ja) 2000-02-01 2001-08-10 Sony Corp 画像処理装置および画像処理方法
WO2002042907A2 (en) 2000-11-27 2002-05-30 Koninklijke Philips Electronics N.V. Data processing apparatus with multi-operand instructions
JP4220722B2 (ja) 2001-05-02 2009-02-04 パイオニア株式会社 情報記録媒体および情報読取装置
US7028171B2 (en) * 2002-03-28 2006-04-11 Intel Corporation Multi-way select instructions using accumulated condition codes
JP2004062401A (ja) 2002-07-26 2004-02-26 Matsushita Electric Ind Co Ltd 演算プロセッサおよび当該演算プロセッサを用いたカメラ装置
US6944747B2 (en) * 2002-12-09 2005-09-13 Gemtech Systems, Llc Apparatus and method for matrix data processing
US7636837B2 (en) * 2003-05-28 2009-12-22 Fujitsu Limited Apparatus and method for controlling instructions at time of failure of branch prediction
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Also Published As

Publication number Publication date
EP1974254A2 (en) 2008-10-01
CN101371223B (zh) 2015-07-15
WO2007085010A2 (en) 2007-07-26
KR20080087171A (ko) 2008-09-30
CN101371223A (zh) 2009-02-18
JP2009524167A (ja) 2009-06-25
US9710269B2 (en) 2017-07-18
EP2461246A1 (en) 2012-06-06
US20070174592A1 (en) 2007-07-26
EP1974254B1 (en) 2012-06-06
EP2461246B1 (en) 2017-03-29
KR100986375B1 (ko) 2010-10-08
WO2007085010A3 (en) 2007-12-13

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