JP5307992B2 - Display device production method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a production system of a display device equipped with a TFT (thin film transistor) of high performance neither impairing productivity nor increasing a production cost steeply. <P>SOLUTION: The production system of the display device includes a film forming device, an etching device, a resist applying/developing device and an exposure device which are respectively connected by a process-to-process conveying mechanism or an in-process conveying mechanism. The production system is constituted to be capable of carrying out a process for forming the thin film transistor. The film forming device in the production system has a plasma CVD device for forming a microcrystal semiconductor film, and a laser processing device added to irradiate the microcrystal semiconductor film formed by the plasma CVD device, with laser beams. A substrate to be processed is moved between the plasma CVD device and the laser processing device by a conveying mechanism, the in-process conveying mechanism or the process-to-process conveying mechanism. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

The present invention relates to a display device production system, and more particularly to a display device production system in which a thin film transistor (hereinafter also referred to as “TFT”) is used.

The glass substrate size for producing the liquid crystal panel is from 300 mm × 400 mm called the first generation, to the third generation 550 mm × 650 mm, the fourth generation 730 mm × 920 mm, the fifth generation 1000 mm × 1200 mm, the sixth generation The size is increased to 24500 mm × 1850 mm, the seventh generation 1870 mm × 2200 mm, and the eighth generation 200 mm × 2400 mm. In the future, glass substrate sizes of 9th generation 2400 mm × 2800 mm, 10th generation 2880 mm × 3080 mm, etc. are planned. Such an increase in the size of the glass substrate is based on a cost minimum design.

Of course, the development of the liquid crystal panel not only increases the size of the glass substrate, but also strives to improve the characteristics of amorphous silicon TFTs without reducing the number of masks to increase productivity and without impairing productivity. (For example, refer to Patent Documents 1 and 2).

Here, the amorphous silicon TFT used in the liquid crystal panel has a problem that the writing time to the pixel is insufficient due to an increase in the panel size and the density of the pixel. Until now, since the polycrystalline silicon TFT has higher field effect mobility than the amorphous silicon TFT, it has been expected to solve the above-mentioned problems (for example, see Patent Document 3).
JP 2007-047516 A JP 2007-059560 A JP 2000-150888 A

However, polycrystalline silicon requires excimer laser annealing, and the production line completed with amorphous silicon TFTs has to be significantly changed. Therefore, since new capital investment is required, it has not been possible to compete with the conventional amorphous silicon TFT panel in terms of production cost. In addition, the excimer laser annealing has a problem that the display quality of a large screen panel is impaired due to crystallization variations.

Accordingly, an object of the present invention is to provide a production system for a display device on which high-performance TFTs are mounted without impairing productivity and without significantly increasing production costs.

A display apparatus production system includes a film forming apparatus, an etching apparatus, a resist coating / developing apparatus, and an exposure apparatus, and each apparatus is connected by an inter-process transfer mechanism or an in-process transfer mechanism. The production system is configured to perform a process of forming a thin film transistor. Among the production systems, a plasma CVD apparatus for forming a microcrystalline semiconductor film is formed as a film forming apparatus, a laser processing apparatus for irradiating a microcrystalline semiconductor film formed by the plasma CVD apparatus with laser light is added, and plasma is added. The substrate to be processed is transported between the CVD apparatus and the laser processing apparatus by an in-apparatus transport mechanism, an in-process transport mechanism, or an inter-process transport mechanism.

This production system makes it possible to configure the channel formation region of the TFT with a microcrystalline semiconductor, and has a function of modifying the crystallinity of the microcrystalline semiconductor. In other words, providing a production system for display devices equipped with new TFTs that exceed the performance of conventional amorphous silicon TFTs by adding minimum production facilities without making major changes to the conventional production line can do.

By forming the channel formation region using a microcrystalline semiconductor, fluctuations in threshold voltage are suppressed, field effect mobility is improved, and a subthreshold coefficient (S value) is also reduced. Can be achieved. As a result, the drive frequency of the display device can be increased, and it is possible to sufficiently cope with an increase in panel size and an increase in pixel density. Furthermore, since no significant production line change is required, it is possible to suppress the increase in capital investment and production cost while improving the performance of the TFT.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. In the structure of the present invention described below, the same reference numerals are used in common in different drawings. In addition, arrangement | positioning of each apparatus in the production system shown by the following embodiment shows an example, and if it is arrangement | positioning which has the same effect, it should not be limitedly interpreted to what is illustrated.

(Embodiment 1)
FIG. 1 shows a display device production system to which the bay production method is applied. In the bay production method, a glass substrate transfer line is composed of an inter-process transfer mechanism 10 and an in-process transfer mechanism 11. The inter-process transport mechanism 10 and the in-process transport mechanism 11 transport in-process products in the production system. The timing of the inter-process transport mechanism 10 and the intra-process transport mechanism 11 can be adjusted by storing a glass substrate (or a cassette containing a glass substrate) in the stocker 12.

The inter-process transport mechanism 10 transports a cassette containing a plurality of work-in-process glass substrates on a transport cart such as an OHV (Over Head Vehicle). The in-process transport mechanism 11 mounts a cassette on an AGV (Automated Guided Vehicle) or RGV (Rail Guided Vehicle) and transports the cassette to each processing apparatus. In each processing apparatus, the substrate transfer robot takes out the glass substrate from the cassette for each sheet, and performs processing in each processing apparatus. Thereafter, the substrate transfer robot accommodates the glass substrate in the cassette again and moves to the next processing apparatus by a transfer carriage such as AGV or stores the cassette in the stocker 12.

Since conveyance between processes and within a process is performed in units of cassettes, such a conveyance system is called a “cassette conveyance method”.

The processing apparatus constituting the production system shown in FIG. 1 includes a film forming apparatus, an etching apparatus, a resist coating / developing apparatus, and an exposure apparatus, and each processing apparatus is connected by an inter-process transfer mechanism or an in-process transfer mechanism. This production system is configured such that a process of forming a thin film transistor can be performed.

As the film forming apparatus, a plasma CVD apparatus 13 and a sputtering apparatus 14 are included. As the etching apparatus, a dry etching apparatus 15 and a wet etching apparatus 16 are included. The resist coating / developing device 17 is disposed in the same process area as the exposure device 18. In addition, as an additional element, the production system includes a peeling device 19, a cleaning device 20, an inspection device 21, and the like.

In a display device using a conventional amorphous silicon TFT, an amorphous silicon layer is deposited in a plasma CVD apparatus. This amorphous silicon layer is a region for forming the channel of the TFT. In this embodiment, a function of forming a microcrystalline semiconductor layer in the plasma CVD apparatus 13 and modifying the crystallinity of the microcrystalline semiconductor layer is added. Typically, microcrystalline silicon is used as the microcrystalline semiconductor layer.

As a method for modifying the crystallinity of the microcrystalline semiconductor layer, means for irradiating an energy beam is applied, and a laser processing apparatus for irradiating laser light is typically added to the plasma CVD apparatus. A glass substrate over which a microcrystalline semiconductor layer is formed employs a structure in which a substrate to be processed moves between a plasma CVD apparatus and the laser processing apparatus by a transport mechanism.

FIG. 2 shows the configuration of the plasma CVD apparatus 13. A glass substrate in process is inserted into a substrate carry-in / out chamber 26 by a substrate transport robot 25 from a cassette 22 carried by a transport carriage such as AGV. The first processing chamber 27 to the fifth processing chamber 31 are chambers for forming a thin film by a plasma CVD method, and are connected to the transfer chamber 32 so that individual film formation can be performed in each processing chamber. . The glass substrate in the apparatus is transferred to each processing chamber by the substrate transfer robot 25 in the transfer chamber 32. In such a multi-chamber structure, in the TFT process, a stacked interface such as a gate insulating layer, a semiconductor layer that forms a channel, and an impurity semiconductor layer that forms a source and a drain is continuously formed without being exposed to the atmosphere. Suitable for doing.

The laser processing chamber 33 is preferably connected to any one of the processing chambers for film formation. FIG. 2 shows a configuration connected to the third processing chamber 29. The glass substrate on which the microcrystalline semiconductor is deposited in the third processing chamber 29 is moved to the laser processing chamber 33 by the transport mechanism in the apparatus, and laser processing is performed. The laser processing chamber 33 is provided with a light introduction window 35 so that the laser light from the laser light source 34 is irradiated onto the microcrystalline semiconductor layer of the glass substrate. In this way, by carrying in the apparatus, laser treatment for modifying crystallinity can be performed without exposing the surface of the microcrystalline semiconductor layer to the atmosphere. The transport mechanism can have a simple configuration that only moves the glass substrate in parallel. By not exposing the microcrystalline semiconductor layer to the atmosphere, the partial crystal semiconductor can be prevented from being oxidized, and contamination by other impurities can be prevented, so that it is a good quality semiconductor layer for forming a TFT channel. You can get things.

As shown in FIG. 2, the laser processing chamber 33 may be connected to one processing chamber in the plasma CVD apparatus 13, so that no major modification of the apparatus is required. Further, since the floor area does not increase, it can be easily incorporated into an existing production line.

FIG. 3 shows an in-line configuration in which one processing chamber is provided for one substrate loading / unloading chamber as the configuration of the plasma CVD apparatus 13. The glass substrate of the cassette 22 is loaded into the substrate carry-in / out chamber 26 by the substrate transfer robot 25. A transfer chamber 32 is provided between the substrate carry-in / out chamber 26 and the first processing chamber 27. A laser processing chamber 33 is connected to the first processing chamber, and a glass substrate can be carried in and out by a transport mechanism. By only depositing the microcrystalline semiconductor layer in the first treatment chamber 27, deposition and laser treatment can be performed continuously. In addition, after the microcrystalline semiconductor layer is formed in the first treatment chamber 27, laser treatment is performed in the laser treatment chamber 33, and the glass substrate is returned to the first treatment chamber 27 again to protect the microcrystalline semiconductor layer. A layer may be formed.

FIG. 3 shows a configuration in which a plurality of units in which such chambers are connected in series are arranged. By operating each unit independently, the throughput can be increased.

According to this embodiment, there is provided a production system for a display device in which a new TFT exceeding the performance of a conventional amorphous silicon TFT is mounted by adding a minimum production facility without requiring significant modification. Can do. When the channel formation region is formed using a microcrystalline semiconductor, variation in threshold voltage is suppressed, field-effect mobility is improved, and an S value is reduced, so that high performance of the TFT can be achieved. As a result, the drive frequency of the display device can be increased, and it is possible to sufficiently cope with an increase in panel size and an increase in pixel density. Furthermore, since no significant production line change is required, it is possible to suppress the increase in capital investment and production cost while improving the performance of the TFT.

(Embodiment 2)
The display device production system shown in FIG. 4 shows an application of the bay production method as in FIG. In this embodiment, a configuration in which the plasma CVD apparatus 13 and the laser processing apparatus 23 are juxtaposed in the process is shown. In this configuration, after the microcrystalline semiconductor layer is formed by the plasma CVD apparatus 13, the glass substrate is once taken out from the plasma CVD apparatus 13 and moved to the laser processing apparatus 23 by the transport mechanism.

FIG. 5 shows the configuration of the plasma CVD apparatus 13 and the laser processing apparatus 23. The plasma CVD apparatus 13 has an in-line configuration, and the substrate carry-in / out chamber 26, the transfer chamber 32, and the first processing chamber 27 are connected in series. In the laser processing apparatus 23, the substrate carry-in / out chamber 26 and the laser processing chamber 33 are connected. The plasma CVD apparatus 13 and the laser processing apparatus 23 share the substrate transfer robot 25 to facilitate the transfer of the glass substrate. In this way, the plasma CVD apparatus 13 and the laser processing apparatus 23 are juxtaposed, and the substrate transport robot 25 is shared, so that the cost of the equipment can be reduced. The surface of the microcrystalline semiconductor layer that has been subjected to the laser treatment is subjected to the next step after the surface oxide film is removed by a cleaning device.

In this production system, a part of the plasma CVD apparatus may be replaced with a laser processing apparatus in the plasma CVD process, so that it is not necessary to increase the floor area for installing the apparatus. Since the microcrystalline semiconductor layer can be formed and laser treatment can be performed in parallel, throughput can be improved. Other configurations are the same as those of the first embodiment, and the same effects are obtained.

(Embodiment 3)
The display device production system shown in FIG. 6 applies the bay production method as in FIG. 1, and shows a configuration in which the plasma CVD device 13 and the laser processing device 23 are juxtaposed in the same process as in FIG. . In this configuration, after the microcrystalline semiconductor layer is formed by the plasma CVD apparatus 13, the glass substrate is once taken out from the plasma CVD apparatus 13 and moved to the laser processing apparatus 23 by the in-process transport mechanism 11.

FIG. 7 shows the configuration of the plasma CVD apparatus 13 and the laser processing apparatus 23 in this embodiment. The plasma CVD apparatus 13 has an in-line configuration, and the substrate carry-in / out chamber 26, the transfer chamber 32, and the first processing chamber 27 are connected in series. In the laser processing apparatus 23, the substrate carry-in / out chamber 26 and the laser processing chamber 33 are connected. The plasma CVD apparatus 13 and the laser processing apparatus 23 each have a substrate transfer robot 25 and transfer the glass substrate loaded in the cassette 22 to the substrate carry-in / out chamber 26. A gap between the plasma CVD apparatus 13 and the laser processing apparatus 23 is performed by a transport carriage 24 such as an AGV equipped with a cassette 22 that moves the in-process transport mechanism 11.

In this embodiment, the plasma CVD apparatus 13 and the laser processing apparatus 23 do not necessarily have to be installed adjacent to each other, so that the arrangement of facilities is flexible. Further, by arranging the plasma CVD apparatus 13 and the laser processing apparatus 23 within the range of the in-process transport mechanism 11, it is not necessary to use the inter-process transport mechanism 10, and the film deposited on the stocker 12 by the plasma CVD apparatus 13 can be used. There is no need to store a glass substrate with a crystalline semiconductor layer. Accordingly, the process residence time between the formation of the microcrystalline semiconductor layer and the laser treatment can be shortened. Further, since the microcrystalline semiconductor layer can be formed and laser treatment can be performed in parallel, throughput can be improved. Other configurations are the same as those in the first and second embodiments, and the same effects are obtained.

(Embodiment 4)
The display device production system shown in FIG. 8 applies the bay production method as in FIG. In the production system of this embodiment, the plasma CVD apparatus 13 and the laser processing apparatus 23 are installed in different process areas. In this configuration, after the microcrystalline semiconductor layer is formed by the plasma CVD apparatus 13, the glass substrate is once taken out from the plasma CVD apparatus 13 and moved to the laser processing apparatus 23 by the intra-process transport mechanism 11 and the inter-process transport mechanism 10. is there.

In this embodiment, the plasma CVD apparatus 13 and the laser processing apparatus 23 do not necessarily have to be installed adjacent to each other, so that the arrangement of facilities is flexible and the layout of the production system does not need to be significantly changed. For example, in consideration of the balance of the entire production system, it can be replaced with a laser processing apparatus 23 that newly introduces a part of surplus equipment. Since the laser processing device 23 does not require special reaction gas, waste liquid recovery, or detoxification equipment, it can be replaced with one of the surplus equipment. Therefore, since it is not necessary to significantly change the production line, it is possible to suppress the increase in capital investment and production cost while improving the performance of the TFT.

(Embodiment 5)
FIG. 9 shows an example of a production system adopting a so-called “single-wafer conveyance method” in which a glass substrate is conveyed between processes and within the process in a single-wafer type. When the size of the glass substrate is increased, the size of the cassette for storing the glass substrate is also increased, and the weight is increased. Since the glass substrate itself is also bent, it is necessary to increase the distance between the glass substrates in order to stably hold the glass substrate. For example, if an 8th generation glass substrate is to be transported in the same cassette as in the prior art, its weight will be about 1 ton. Therefore, when handling a glass substrate of the sixth generation or later, a method of carrying a single wafer between processes and within a process is suitable.

The production system to which the single wafer transfer system shown in FIG. 9 is applied includes a film forming apparatus, an etching apparatus, a resist coating / developing apparatus, and an exposure apparatus, and each processing apparatus is connected by an inter-process transfer mechanism or an in-process transfer mechanism. Yes. This production system is configured such that a process of forming a thin film transistor can be performed. The inter-process transport mechanism 10 and the in-process transport mechanism 11 transport the glass substrate one by one. The transfer is performed by a transfer carriage such as OHV, AGV, or RGV, and has a configuration in which the substrates are mounted and transferred one by one. In each processing apparatus, the substrate transfer robot takes out the glass substrate from the transfer carriage for each sheet, and performs processing in each processing apparatus. Thereafter, the substrate transfer robot transfers the glass substrate to the transfer carriage again and moves to the next processing apparatus or stores the glass substrate in the stocker 12.

In the single wafer transfer method, since the transfer is performed in units of substrates, it is possible to apply a penetrating layout in which the entrance and exit of the glass substrate are different in some processes. By adopting the through layout, the transport distance of the glass substrate can be shortened, and the tact time can be shortened.

FIG. 10 shows the configuration of the plasma CVD apparatus 13 corresponding to the through layout. A first processing chamber 27 for forming a semiconductor layer is connected to the substrate carry-in / out chamber 26. A laser processing chamber 33 is connected to the first processing chamber 27 so that laser processing can be continuously performed after the microcrystalline semiconductor layer is formed. A gas supply unit 37 and a high frequency power source 38 are connected to the first processing chamber 27. The exhaust means 36 is configured so that the exhaust flow flows in a direction parallel to the glass substrate, and is configured so that the gas flow does not stay. A substrate carry-in / out chamber 26 is connected to the laser processing chamber 33, and the glass substrate after the laser processing is moved there. Thus, by carrying out in-line type in-apparatus conveyance in which the glass substrate sequentially moves in each chamber, the structure of the conveyance mechanism can be simplified.

Note that the cluster type multi-chamber plasma CVD apparatus shown in FIG. 2 can also be applied to the production system of this embodiment. In any case, it is possible to provide a production system for a display device in which a new TFT exceeding the performance of the conventional amorphous silicon TFT is mounted by adding a minimum production facility without requiring a major modification. it can. When the channel formation region is formed using a microcrystalline semiconductor, variation in threshold voltage is suppressed, field-effect mobility is improved, and an S value is reduced, so that high performance of the TFT can be achieved. As a result, the drive frequency of the display device can be increased, and it is possible to sufficiently cope with an increase in panel size and an increase in pixel density. Furthermore, since no significant production line change is required, it is possible to suppress the increase in capital investment and production cost while improving the performance of the TFT.

(Embodiment 6)
An example of the manufacturing process of the display device applied in the display device production system shown in Embodiment Modes 1 to 5 will be described with reference to FIG. FIG. 11 shows a flowchart of the manufacturing process.

The glass substrate is cleaned by a cleaning device (S01), and a conductive film for forming a gate electrode is formed by a sputtering device (S02). The mask pattern of the gate electrode is transferred to the surface of the power transmission film by the resist coating / developing device and the exposure device (S03). Using this mask pattern, the conductive film is etched by a dry etching apparatus or a wet etching apparatus to form a gate electrode (S05).

Thereafter, the mask pattern is peeled off (S05), and a gate insulating layer is formed by a plasma CVD apparatus (S06). A microcrystalline silicon layer is formed on the gate insulating layer by a plasma CVD method (S07), and laser treatment is performed (S08). The processing from S06 to S08 shown here can also be performed continuously.

The surface of the microcrystalline silicon layer after the laser treatment is preferably subjected to surface oxide film removal treatment (S09, not essential), and a buffer layer is formed (S10, not essential), and an impurity semiconductor layer is formed. (S11) is performed by a plasma CVD apparatus. Thereafter, the mask pattern of the semiconductor layer is transferred to the surface of the conductive film by the resist coating / developing apparatus and the exposure apparatus (S12). Using this mask pattern, the semiconductor layer is etched by a dry etching apparatus to form an island-shaped semiconductor layer that matches the TFT arrangement (S13).

Thereafter, the mask pattern is peeled off (S014), and a conductive film for forming wiring is formed by a sputtering apparatus (S15). Thereafter, the mask pattern of the wiring layer is transferred to the surface of the conductive film by the resist coating / developing apparatus and the exposure apparatus (S16). Using this mask pattern, the conductive film is etched by a dry etching apparatus to form a wiring (S17). Furthermore, the process which etches the impurity semiconductor layer in the uppermost layer of an island-like semiconductor layer is performed (S18).

The mask pattern is removed (S19), and a passivation film is formed by a plasma CVD apparatus (S20). A mask pattern for opening a contact hole is transferred to the surface of the passivation film by the resist coating / developing apparatus and the exposure apparatus (S21). Using this mask pattern, the passivation film is etched by a dry etching apparatus to form a contact hole (S22).

The mask pattern of the contact hole is peeled off (S23), and a conductive film for forming a pixel electrode is formed by a sputtering apparatus (S24). The mask pattern of the pixel electrode is transferred to the surface of the conductive film by the resist coating / developing device and the exposure device (S25). Using this mask pattern, the conductive film is etched by a dry etching apparatus or a wet etching apparatus to form a pixel electrode (S26). Then, the mask pattern is peeled off (S27).

Thus, according to the display device production system shown in the first to fifth embodiments, a display device can be produced. Hereinafter, an example of the manufacturing process will be described in detail.

(Embodiment 7)
In this embodiment, an example of a manufacturing process of a display device produced by the display device production system shown in Embodiments 1 to 6 will be described with reference to FIGS. FIGS. 12 to 14 and FIGS. 17 to 19 are cross-sectional views showing a manufacturing process of a TFT, and FIGS. 15 and 20 are top views of a connection region between a TFT and a pixel electrode in one pixel.

A TFT having a microcrystalline semiconductor film as a channel formation region is more suitable for use in a driver circuit because the n-channel type has higher mobility than the p-channel type. It is desirable that all TFTs formed on the same substrate have the same polarity in order to reduce the number of steps. Here, description is made using an n-channel TFT.

As shown in FIG. 12A, a gate electrode 51 is formed over a substrate 50 by a sputtering apparatus. The substrate 50 is a heat-resistant material that can withstand the processing temperature in this manufacturing process, in addition to a non-alkali glass substrate manufactured by a fusion method or a float method, such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass, or a ceramic substrate. A plastic substrate or the like having the above can be used. Alternatively, a substrate in which an insulating film is provided on the surface of a metal substrate such as a stainless alloy may be used.

The gate electrode 51 is formed using a metal material such as titanium, molybdenum, chromium, tantalum, tungsten, aluminum, or copper, or an alloy material thereof (aluminum-neodymium alloy, aluminum-selenium alloy, or the like). The gate electrode 51 is formed by forming a conductive film on the substrate 50 using a sputtering apparatus, and forming a mask pattern on the conductive film using a resist coating / developing apparatus and an exposure apparatus. The gate electrode 51 is formed by etching the conductive film using the mask pattern. The structure of the gate electrode 51 includes molybdenum and aluminum stacks, titanium and aluminum stacks, titanium nitride and aluminum stacks, tantalum nitride and aluminum stacks, molybdenum and copper stacks, titanium nitride and copper stacks, tantalum nitride and There are copper layers.

In this embodiment mode, a molybdenum film is formed as a conductive film over the substrate 50 by a sputtering method, and the conductive film formed over the substrate 50 is etched using a mask pattern formed using the first photomask. An electrode is formed.

The gate electrode 51 is formed with a thickness of 50 nm to 300 nm. By setting the thickness of the gate electrode 51 to 50 nm or more and 100 nm or less, it is possible to prevent disconnection of a semiconductor film or a wiring to be formed later. In addition, by setting the thickness of the gate electrode 51 to 150 nm or more and 300 nm or less, the resistance of the gate electrode 51 can be reduced, and the area can be increased.

Next, gate insulating layers 52a and 52b and a microcrystalline semiconductor film 53a are formed over the gate electrode 51 by a plasma CVD apparatus.

The gate insulating layers 52a and 52b can be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. In this embodiment, a silicon nitride film or a silicon nitride oxide film is formed as the gate insulating layer 52a, and a silicon oxide film or a silicon oxynitride film is formed and stacked as the gate insulating layer 52b. Note that the gate insulating layer can be formed as a single layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film, without using two gate insulating layers.

Note that the silicon oxynitride film has a higher oxygen content than nitrogen. For example, the concentration range is oxygen of 55 to 65 atomic%, nitrogen of 1 to 20 atomic%, and Si of 25 to 35 atomic%. , Hydrogen (and / or OH group) is contained in the range of 0.1 to 10 atomic%. The silicon nitride oxide film has a nitrogen content higher than that of oxygen as a composition. For example, the concentration ranges from 15 to 30 atomic% for oxygen, 20 to 35 atomic% for nitrogen, and 25 to 25 for Si. 35 atom%, and hydrogen (and / or OH group) means what is contained in the range of 15 to 25 atom%.

Further, as shown in FIG. 16, the gate insulating layers 52a to 52c are formed, a silicon nitride film or a silicon nitride oxide film is formed as the gate insulating layer 52a, and a silicon oxide film or an oxynitride is formed as the gate insulating layer 52b. A silicon film can be formed, and a silicon nitride film or a silicon nitride oxide film can be formed as the gate insulating layer 52c. Note that the gate insulating layer 52c may be formed as thin as about 1 nm to 5 nm in thickness. In the case where the gate insulating layer 52b is a silicon oxide film or a silicon oxynitride film, a silicon nitride film having a thickness of 1 nm to 5 nm is formed on the surface of the gate insulating layer 52b, whereby a microcrystalline semiconductor film to be formed later is formed. When the laser beam is irradiated, the surface of the microcrystalline semiconductor film can be prevented from being oxidized at the interface between the microcrystalline semiconductor film and the gate insulating layer 52b.

The silicon nitride film can be formed by a plasma CVD apparatus or a sputtering apparatus. Alternatively, the gate insulating layer 52b can be nitrided by plasma treatment to form a nitrogen silicon layer on the surface of the gate insulating layer 52b. The plasma treatment is generated by using microwaves, for example 2.45 GHz. Using such high-density plasma, nitrogen (or a gas containing nitrogen) is activated by plasma excitation, and these are reacted with the gate insulating layer 52b. Since high-density plasma characterized by low electron temperature has low kinetic energy of active species, it is possible to form a layer with less plasma damage and fewer defects than conventional plasma treatment. In addition, when high-density plasma is used, the surface roughness of the gate insulating layer 52b can be reduced, so that carrier mobility can be increased. Furthermore, it becomes easy to align the organic semiconductor material constituting the semiconductor layer formed on the gate insulating layer 52b.

When the gate insulating layer 52a is formed using a silicon nitride film or a silicon nitride oxide film, the adhesion between the substrate 50 and the gate insulating layer 52a is increased. When a glass substrate is used as the substrate 50, impurities from the substrate 50 Can be prevented from diffusing into the microcrystalline semiconductor film, and the gate electrode 51 can be prevented from being oxidized. That is, film peeling can be prevented and electrical characteristics of a TFT formed later can be improved. In addition, it is preferable that the gate insulating layers 52a and 52b have a thickness of 50 nm or more because reduction in coverage due to unevenness of the gate electrode 51 can be reduced.

The microcrystalline semiconductor film 53a is described as being in a metastable state between amorphous and single crystal according to Gibbs free energy. That is, it is a semiconductor having a third state that is stable in terms of free energy, and has a short-range order and lattice distortion. Columnar or needle-like crystals grow in the normal direction with respect to the substrate surface. Microcrystalline silicon which is a typical example of a microcrystalline semiconductor has a Raman spectrum shifted to a lower frequency side than 520 cm ⁻¹ indicating single crystal silicon. That is, the peak of the Raman spectrum of microcrystalline silicon is between 520 cm ⁻¹ indicating single crystal silicon and 480 cm ⁻¹ indicating amorphous silicon. In addition, at least 1 atomic% or more of hydrogen or halogen is contained to terminate dangling bonds (dangling bonds). Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability can be improved and a good microcrystalline semiconductor film can be obtained.

This microcrystalline semiconductor film can be formed by a high-frequency plasma CVD method with a frequency of several tens to several hundreds of MHz or a microwave plasma CVD apparatus with a frequency of 1 GHz or more. Typically, silicon hydride such as SiH ₄ or Si ₂ H ₆ can be formed by diluting with hydrogen. In addition to silicon hydride and hydrogen, the microcrystalline semiconductor film can be formed by dilution with one or more kinds of rare gas elements selected from helium, argon, krypton, and neon. The flow rate ratio of hydrogen to silicon hydride at these times is 12 to 1000 times, preferably 50 to 200 times, and more preferably 100 times. Note that SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like can be used instead of silicon hydride.

In addition, since the microcrystalline semiconductor film exhibits weak n-type conductivity when an impurity element for the purpose of valence electron control is not intentionally added, the microcrystalline semiconductor film functions as a TFT channel formation region. Thus, the threshold value can be controlled by adding an impurity element imparting p-type at the same time as film formation or after film formation. The impurity element imparting p-type is typically boron, and an impurity gas such as B ₂ H ₆ or BF ₃ may be mixed into silicon hydride at a rate of 1 ppm to 1000 ppm, preferably 1 to 100 ppm. . The boron concentration is preferably 1 × 10 ^{14 to} 6 × 10 ¹⁶ atoms / cm ³ , for example.

In addition, the oxygen concentration of the microcrystalline semiconductor film is 5 × 10 ¹⁹ atoms / cm ³ or less, 1 × 10 ¹⁹ atoms / cm ³ or less, and the nitrogen and carbon concentrations are 3 × 10 ¹⁸ atoms / cm ³ or less. Is preferred. By reducing the concentration of oxygen, nitrogen, and carbon in the microcrystalline semiconductor film, the microcrystalline semiconductor film can be prevented from becoming n-type.

The microcrystalline semiconductor film 53a is formed with a thickness of 1 nm to 200 nm, preferably 1 nm to 100 nm, preferably 1 nm to 50 nm, preferably 1 nm to 30 nm, preferably 1 nm to 20 nm, preferably 1 nm to less than 15 nm. . The microcrystalline semiconductor film 53a functions as a channel formation region of a TFT to be formed later. When the thickness of the microcrystalline semiconductor film 53a is greater than or equal to 1 nm and less than or equal to 50 nm, TFTs to be formed later are completely depleted. Further, since the deposition rate of the microcrystalline semiconductor film 53a is as low as 1/10 to 1/100 that of the amorphous semiconductor film, the throughput can be improved by reducing the thickness.

Next, the laser beam 57 is irradiated to the microcrystalline semiconductor film 53a by an LP apparatus. The energy of the laser beam 57 is applied so that the microcrystalline semiconductor film does not melt. That is, laser processing (hereinafter referred to as “LP”) according to this embodiment is based on solid-phase crystal growth performed without melting the microcrystalline semiconductor film 53a by radiation heating. In other words, the deposited microcrystalline semiconductor film 53a uses a critical region where the liquid phase does not enter a liquid phase, and can be referred to as “critical growth” in that sense.

The laser beam 57 can be applied to the interface between the microcrystalline semiconductor film 53a and the gate insulating layer 52b. Thus, using the crystal on the surface side of the microcrystalline semiconductor film 53a as a seed, solid-phase crystal growth can be performed from the surface at the interface of the gate insulating layer to form a microcrystalline semiconductor film with improved crystallinity (FIG. 12 (B)). In this specification, a microcrystalline semiconductor film obtained by performing LP treatment on the microcrystalline semiconductor film 53a after deposition is referred to as an LPSAS (Laser Process Semi-Amorphous Semiconductor) film.

Solid phase crystal growth by LP treatment does not increase the crystal grain size, but rather improves the crystallinity in the thickness direction of the film. That is, the LP treatment improves the crystallinity of the interface region of the gate insulating layer and improves the electrical characteristics of the TFT having the bottom gate structure. In such critical growth, the surface irregularities (convex bodies called ridges) found in conventional low-temperature polysilicon are not formed, and the surface of the LPSAS film 53b is maintained smooth. is there. As in this embodiment mode, a crystalline semiconductor film obtained by directly applying a laser beam 57 to a microcrystalline semiconductor film 53a after film formation is a conventional microcrystalline semiconductor film that has been deposited. The growth mechanism and film quality are clearly different from the modified microcrystalline semiconductor film (in Non-Patent Document 1).

Further, since the LPSAS film 53b is made of microcrystals, its resistance is lower than that of an amorphous semiconductor film. For this reason, in the TFT using the LPSAS film 53b, the slope of the rising portion of the curve indicating the current-voltage characteristics is steep, and the response as a switching element is excellent, and high-speed operation is possible. Further, by using the LPSAS film 53b in the TFT channel formation region, it is possible to suppress fluctuations in the TFT threshold. Therefore, a display device with little variation in electrical characteristics can be manufactured.

Further, the LPSAS film 53b has a higher mobility than the amorphous semiconductor film. For this reason, the area of the channel formation region, that is, the area of the TFT can be reduced by using the TFT in which the channel formation amount region is formed of the LPSAS film 53b for switching the display element. For this reason, the area of the TFT shown per pixel is reduced, and the aperture ratio of the pixel can be increased. As a result, a display device with high resolution can be manufactured.

When an excimer laser is used as the laser beam 57, the pulse oscillation frequency is 1 Hz or more and less than 10 MHz, preferably 100 Hz to 10 kHz, and the laser energy is 0.2 to 0.35 J / cm ² (typically 0.2 to 0. 0. 3 J / cm ² ). When a YAG laser is used, the third harmonic is used and the pulse oscillation frequency is set to 1 Hz or more and less than 10 MHz, and the laser energy is set to 0.2 to 0.35 J / cm ² (typically 0.2 to 0.3 J). / Cm ² ).

As a laser oscillator that oscillates the laser beam 57, a laser oscillator capable of pulse oscillation or continuous oscillation can be used. The laser wavelength is in the visible to ultraviolet region (800 nm or less), preferably in the ultraviolet region (400 nm or less) so that the semiconductor film can efficiently absorb the laser beam. By irradiation with a laser beam in the ultraviolet region with a wavelength of 300 nm to 400 nm, the microcrystalline semiconductor film is efficiently absorbed. As the laser oscillator, KrF, ArF, XeCl, excimer laser oscillator such as _{XeF, N 2, He, He} -Cd, Ar, He-Ne, HF, gas laser oscillator such as _{CO 2, YAG, GdVO 4,} YVO 4 , YLF, YAlO ₃ , ScO ₃ , Lu ₂ O ₃ , Y ₂ O _3, etc., a solid-state laser oscillator using a crystal doped with Cr, Nd, Er, Ho, Ce, Co, Ti, Yb, or Tm A solid-state laser such as a KGW laser, a KYW laser, an alexandrite laser, a Ti: sapphire laser, a metal vapor laser oscillator such as a helium cadmium laser, or the like can be used. In the solid-state laser oscillator, it is preferable to apply the second to fifth harmonics of the fundamental wave.

Typically, an excimer laser beam having a wavelength of 400 nm or less, typically 308 nm, or the third harmonic (355 nm) of a YAG laser is used as the laser beam 57.

The LP process is performed by condensing the rectangular shape into a linear laser beam, so that the microcrystalline semiconductor film 53a on a glass substrate of, for example, 730 mm × 920 mm can be processed by one laser beam scan. In this case, the linear laser beam overlapping ratio (overlap ratio) is set to 0 to 95% (preferably 0 to 67%). Thereby, the substrate processing time per sheet can be shortened, and productivity can be improved. The shape of the laser beam is not limited to a linear shape, and it can be similarly processed even if it is a planar shape. Further, the present LP treatment is not limited to the size of the glass substrate, and can be applied to various things.

When a continuous wave laser beam is used as the laser beam 57, a throughput of LP processing can be improved by providing a polygon mirror or a galvano mirror between the oscillator and the substrate and scanning the laser beam at a high speed. For example, it is possible to perform LP processing on a microcrystalline semiconductor film formed on a glass substrate of 730 mm × 920 mm or a glass substrate larger than that.

Note that the microcrystalline semiconductor film 53a may be irradiated with the laser beam 57 in an argon atmosphere, a hydrogen atmosphere, an argon and hydrogen atmosphere, a nitrogen atmosphere, or the like. In this manner, by irradiating the microcrystalline semiconductor film 53a with a laser beam in an inert atmosphere, an oxide film is hardly formed on the surface of the LPSAS film 53b.

In addition, by cleaning the surface of the microcrystalline semiconductor film 53 a before irradiating the microcrystalline semiconductor film 53 a with the laser beam 57, impurities attached to the surface of the microcrystalline semiconductor film 53 a are irradiated with the laser beam 57. Mixing in the semiconductor film can be prevented.

Alternatively, the microcrystalline semiconductor film 53a may be irradiated with the laser beam 57 and the microcrystalline semiconductor film 53a may be heated. Typically, the crystallinity of the microcrystalline semiconductor film 53a can be increased by irradiating the laser beam 57 while heating the substrate 50 at 300 ° C. to 400 ° C. Alternatively, the temperature of the microcrystalline semiconductor film 53a may be instantaneously increased by irradiating the microcrystalline semiconductor film 53a with a laser beam and irradiating strong light. As a representative example of strong light, infrared light, particularly infrared light having a peak at 1 μm to 2 μm (preferably halogen light (1.3 μm)) can be used.

Note that in the case where an oxide film is formed on the surface of the LPSAS film 53b, the oxide film is preferably removed by a cleaning apparatus or a wet etching apparatus. As a result, it is possible to reduce inhibition of carrier movement by the insulating film formed at the interface between the LPSAS film 53b and the buffer layer 54.

Next, as illustrated in FIG. 12C, a buffer layer 54 and an impurity semiconductor film 55 to which an impurity imparting one conductivity type is added are formed over the LPSAS film 53b. Next, a mask pattern 56 is formed on the impurity semiconductor film 55.

The buffer layer 54 can be formed by a plasma CVD method using silicon hydride such as SiH ₄ or Si ₂ H ₆ . Further, the silicon hydride can be diluted with one or more kinds of rare gas elements selected from helium, argon, krypton, and neon to form an amorphous semiconductor film. An amorphous semiconductor film containing hydrogen can be formed using hydrogen with a flow rate of 1 to 10 times, more preferably 1 to 5 times the flow rate of silicon hydride. In addition, by using the silicon hydride and nitrogen or ammonia, an amorphous semiconductor film containing nitrogen can be formed.

The buffer layer 54 may be partially etched in a later formation process of the source region and the drain region, but it is preferable to form the buffer layer 54 with such a thickness that a part of the buffer layer 54 remains at that time. Typically, it is preferably formed with a thickness of 100 nm to 500 nm, preferably 200 nm to 300 nm. In a display device with a high applied voltage of TFT (for example, about 15 V), typically a liquid crystal display device, when the thickness of the buffer layer 54 is increased as shown in the above range, the withstand voltage increases, and a high voltage is applied to the TFT. Even if it is applied, it is possible to avoid deterioration of the TFT.

Note that the buffer layer 54 is preferably not added with an impurity imparting one conductivity type, such as phosphorus or boron. In particular, it is preferable that boron contained in the LPSAS film 53b or phosphorus contained in the semiconductor film to which an impurity imparting one conductivity type is added to control the threshold is not mixed in the buffer layer. As a result, the leakage current can be reduced by eliminating the leakage current generation region due to the PN junction. In addition, an amorphous semiconductor film to which an impurity imparting one conductivity type such as phosphorus or boron is not added is formed between the semiconductor film to which an impurity imparting one conductivity type is added and the LPSAS film 53b. It is possible to prevent the impurities contained in the LPSAS film 53b and the source and drain regions from diffusing. In addition, after the LPSAS film 53b is formed, the buffer layer 54 is preferably formed at a temperature of 300 ° C. to 400 ° C. by plasma CVD. By this film formation process, hydrogen is supplied to the LPSAS film 53b, and an effect equivalent to that obtained by hydrogenating the LPSAS film 53b is obtained. That is, by depositing the buffer layer 54 on the LPSAS film 53b, hydrogen can be diffused into the LPSAS film 53b to terminate dangling bonds.

By forming the buffer layer 54 on the surface of the LPSAS film 53b, it is possible to prevent natural oxidation of the surface of the crystal grains included in the LPSAS film 53b. That is, there is no problem even if the substrate is temporarily stored in the stocker after the process is advanced to this stage. In a production system in which a plurality of lots flow, it is necessary to adjust the process input timing of each lot. In this case, it is easy to adjust the schedule among a plurality of lots by forming the buffer layer 54 on the surface of the LPSAS film 53b.

In the case of forming an n-channel TFT, the impurity semiconductor film 55 may be formed by adding phosphorus as a typical impurity element and adding an impurity gas such as PH _{3 to} silicon hydride. When a p-channel TFT is formed, boron may be added as a typical impurity element, and an impurity gas such as B ₂ H ₆ may be added to silicon hydride. An amorphous semiconductor film to which an impurity imparting one conductivity type is added is formed on the buffer layer 54 side, and a microcrystalline semiconductor film to which an impurity imparting one conductivity type is added is formed thereon, whereby resistance Since it becomes stepwise, carriers can easily flow and mobility can be increased. The impurity semiconductor film 55 to which an impurity imparting one conductivity type is added is formed with a thickness of 2 nm to 50 nm.

The mask pattern 56 is formed using a resist coating / developing apparatus and an exposure apparatus. By using the second photomask, the resist applied on the impurity semiconductor film 55 to which an impurity imparting one conductivity type is added is exposed and developed to form a mask pattern 56.

Next, the microcrystalline semiconductor film 53a, the buffer layer 54, and the impurity semiconductor film 55 are etched and separated using the mask pattern 56, and the LPSAS film 61, the buffer layer 62, and the conductive layer are separated as shown in FIG. A semiconductor film 63 to which an impurity imparting a mold is added is formed. Thereafter, the mask pattern 56 is removed. Note that FIG. 13B (excluding the mask pattern 56) corresponds to a cross-sectional view taken along a line AB in FIG.

Since the side surfaces of the end portions of the LPSAS film 61 and the buffer layer 62 are inclined, it is possible to prevent a leakage current from being generated between the source and drain regions formed on the buffer layer 62 and the LPSAS film 61. It is. Further, it is possible to prevent a leak current from being generated between the wiring layer and the LPSAS film 61. The inclination angles of the end side surfaces of the LPSAS film 61 and the buffer layer 62 are 90 ° to 30 °, preferably 80 ° to 45 °. By setting such an angle, disconnection of the wiring layer due to the step shape can be prevented.

Next, as illustrated in FIG. 13B, conductive films 65a to 65c are formed over the semiconductor film 63 to which an impurity imparting a conductivity type is added and the gate insulating layer 52b, and masks are formed over the conductive films 65a to 65c. A pattern 66 is formed. The conductive films 65a to 65c are preferably formed using a single layer or a stacked layer of aluminum or an aluminum alloy to which a heat resistance improving element such as copper, silicon, titanium, neodymium, scandium, or molybdenum or a hillock preventing element is added. In addition, a film in contact with a semiconductor film to which an impurity imparting one conductivity type is added is formed using titanium, tantalum, molybdenum, tungsten, or a nitride of these elements, and aluminum or an aluminum alloy is formed thereover. It is good also as a laminated structure. Furthermore, a laminated structure in which the upper and lower surfaces of aluminum or an aluminum alloy are sandwiched between titanium, tantalum, molybdenum, tungsten, or nitrides of these elements may be employed. Here, a conductive film having a structure in which three layers of conductive films 65a to 65c are stacked is shown as the conductive film. The conductive films 65a and 65c are formed of a molybdenum film and the conductive film 65b is formed of an aluminum film. A laminated conductive film using a titanium film as the films 65a and 65c and an aluminum film as the conductive film 65b is shown. The conductive films 65a to 65c are formed by a sputtering apparatus.

The mask pattern 66 is formed in the same manner as the mask pattern 56. Then, as shown in FIG. 13C, part of the conductive films 65a to 65c is etched to form a pair of wiring layers 71a to 71c. Here, when the conductive films 65a to 65c are wet-etched using the mask pattern 66 formed by a photolithography process using a third photomask, the ends of the conductive films 65a to 65c are selectively etched. As a result, wiring layers 71 a to 71 c having an area smaller than that of the mask pattern 66 are formed.

Next, as shown in FIG. 14A, the semiconductor film 63 to which an impurity imparting one conductivity type is added is etched and separated using a mask pattern 66. As a result, a pair of source and drain regions 72 as shown in FIG. 14A can be formed. Note that part of the buffer layer 62 is also etched in the etching step. The buffer layer that is partially etched and has a groove is referred to as a buffer layer 73. The step of forming the source region and the drain region and the groove of the buffer layer can be formed in the same step. Since the depth of the groove of the buffer layer is 1/2 to 1/3 of the thickest region of the buffer layer, the distance between the source region and the drain region can be increased. Leakage current between the drain regions can be reduced. Thereafter, the mask pattern 66 is removed.

Note that FIG. 14A (excluding the mask pattern 66) corresponds to a cross-sectional view taken along a line AB in FIG. As shown in FIG. 15B, it can be seen that the end portions of the source region and the drain region 72 are located outside the end portion of the wiring layer 71c. Further, the end portion of the buffer layer 73 is located outside the end portions of the wiring layer 71 c and the source and drain regions 72. One of the wiring layers has a shape surrounding the other of the source region and the drain region (specifically, a U shape or a C shape). For this reason, since the area of the region in which carriers move can be increased, the amount of current can be increased and the area of the TFT can be reduced. In addition, since the microcrystalline semiconductor film and the wiring layer are overlapped over the gate electrode, the influence of the unevenness of the gate electrode is small, so that coverage can be reduced and leakage current can be suppressed.

As shown in FIG. 14B, the end portions of the wiring layers 71a to 71c and the end portions of the source region and the drain region 72 are not coincident with each other and are shifted from each other. Since the distance is increased, it is possible to prevent a leakage current or a short circuit between the wiring layers. Therefore, a highly reliable TFT can be manufactured. Through the above steps, a channel etch type TFT 74 can be formed.

In the TFT shown in this embodiment mode, a gate insulating layer, an LPSAS film, a buffer layer, a source region and a drain region, and a wiring layer are stacked over a gate electrode, and the buffer layer covers the surface of the LPSAS film functioning as a channel formation region. In addition, a groove is formed in a part of the buffer layer, and a region other than the groove is covered with the source region and the drain region. That is, since the distance between the source region and the drain region is separated by the groove formed in the buffer layer, the leakage current between the source region and the drain region can be reduced. In addition, since the groove is formed by etching a part of the buffer layer, etching residues generated in the formation process of the source region and the drain region can be removed, so that leakage occurs in the source region and the drain region through the residue. Generation of current (parasitic channel) can be reduced.

In addition, a buffer layer is formed between the LPSAS film functioning as a channel formation region and the source and drain regions. The surface of the LPSAS film is covered with a buffer layer. Since the buffer layer formed of a high resistance material extends between the LPSAS film and the source region and the drain region, it is possible to reduce the occurrence of leakage current in the TFT and to increase the voltage. Degradation due to application of can be reduced. Further, since an amorphous semiconductor film whose surface is terminated with hydrogen is formed as a buffer layer on the surface of the LPSAS film, it is possible to prevent the LPSAS film from being oxidized and to form a source region and a drain region. Etching residues generated in the process can be prevented from entering the LPSAS film. Therefore, a TFT having excellent electrical characteristics and excellent withstand voltage can be manufactured.

In addition, the end of the wiring layer and the end of the source region and the drain region are not coincident and shifted so that the distance between the ends of the wiring layer is increased, thereby preventing leakage current and short circuit between the wiring layers. be able to.

Next, as shown in FIG. 13C, a passivation film 76 is formed on the wiring layers 71a to 71c, the source and drain regions 72, the buffer layer 73, the LPSAS film 61, and the gate insulating layer 52b by a plasma CVD apparatus. To do. The passivation film 76 can be formed in the same manner as the gate insulating layers 52a and 52b. Note that the passivation film 76 is for preventing entry of contaminant impurities such as organic substances, metal substances, and water vapor floating in the atmosphere, and is preferably a dense film. In addition, by using a silicon nitride film for the passivation film 76, the oxygen concentration in the buffer layer 87 can be set to 5 × 10 ¹⁹ atoms / cm ³ or less, preferably 1 × 10 ¹⁹ atoms / cm ³ or less.

Next, a part of the passivation film 76 is etched using a mask pattern formed on the passivation film 76 using a fourth photomask to form a contact hole, and the pixel electrode 77 in contact with the wiring layer 75c in the contact hole. Form. Note that FIG. 14C corresponds to a cross-sectional view taken along a line AB in FIG.

The pixel electrode 77 includes indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, ITO, indium zinc oxide, and silicon oxide. A light-transmitting conductive material such as indium tin oxide can be used. The pixel electrode 77 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 70% or more at a wavelength of 550 nm. Moreover, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω · cm or less. As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more kinds thereof can be given.

In this embodiment, as the pixel electrode 77, an ITO film is formed by a sputtering method, and then a resist is applied on the ITO. Next, the resist is exposed and developed using a fifth photomask to form a mask pattern. Next, the pixel electrode 77 is formed by etching the ITO using the mask pattern.

Through the above steps, an element substrate that can be used for a display device can be formed.

Next, a method for manufacturing a TFT which is different from that described above will be described with reference to FIGS. Here, a process for manufacturing a TFT using a process capable of reducing the number of photomasks from the above mode is described.

As in FIGS. 12A and 12B, a mask pattern is formed by forming a conductive film over the substrate 50, applying a resist over the conductive film, and performing a photolithography process using the first photomask. The gate electrode 51 is formed by etching a part of the conductive film using Next, gate insulating layers 52 a and 52 b and a microcrystalline semiconductor film are sequentially formed over the gate electrode 51. Next, the microcrystalline semiconductor film 53a is irradiated with a laser beam 57 to form an LPSAS film 53b as shown in FIG. Next, a buffer layer 54, an impurity semiconductor film 55 to which an impurity imparting one conductivity type is added, and conductive films 65a to 65c are sequentially formed over the LPSAS film 53b. Next, a resist 80 is applied over the conductive film 65a. As the resist 80, a positive resist or a negative resist can be used. Here, a positive resist is used.

Next, the resist 80 is exposed to light by irradiating the resist 80 with light using the multi-tone mask 59 as a second photomask. As the multi-tone mask, a gray-tone mask, a half-tone mask, or the like can be applied.

By developing after exposure using a multi-tone mask, a mask pattern 81 having regions with different thicknesses can be formed as shown in FIG.

Next, the LPSAS film 53b, the buffer layer 54, the impurity semiconductor film 55 to which an impurity imparting one conductivity type is added, and the conductive films 65a to 65c are etched and separated by the mask pattern 81. As a result, as shown in FIG. 18A, the LPSAS film 61, the buffer layer 62, the semiconductor film 63 to which an impurity imparting one conductivity type is added, and the conductive films 85a to 85c can be formed. Note that FIG. 18A (excluding the mask pattern 81) corresponds to a cross-sectional view taken along a line AB in FIG.

Next, the mask pattern 81 is ashed. As a result, the resist area is reduced and the thickness is reduced. At this time, the resist in the thin region (the region overlapping with part of the gate electrode 51) is removed, and a separated mask pattern 86 can be formed as shown in FIG.

Next, using the mask pattern 86, the conductive films 85a to 85c are etched and separated. As a result, a pair of wiring layers 92a to 92c as shown in FIG. 18B can be formed. When the conductive films 89a to 89c are wet-etched using the mask pattern 86, the ends of the conductive films 89a to 89c are selectively etched. As a result, the wiring layers 92 a to 92 c having a smaller area than the mask pattern 86 can be formed.

Next, using the mask pattern 86, the semiconductor film 63 to which an impurity imparting one conductivity type is added is etched, so that a pair of source and drain regions 88 is formed. Note that part of the buffer layer 62 is also etched in the etching step. The partially etched buffer layer is referred to as a buffer layer 87. A concave portion is formed in the buffer layer 87. The step of forming the source region and the drain region and the groove of the buffer layer can be formed in the same step. Here, a part of the buffer layer 87 is partly etched by the mask pattern 86 whose area is reduced as compared with the mask pattern 81, so that the buffer layer 87 protrudes outside the source region and the drain region 88. . Thereafter, the mask pattern 86 is removed. In addition, the end portions of the wiring layers 92a to 92c and the end portions of the source region and the drain region 88 are not coincident with each other, and the end portions of the source region and the drain region 88 are located outside the end portions of the wiring layers 92a to 92c. Is formed.

Note that FIG. 18C (excluding the mask pattern 86) corresponds to a cross-sectional view taken along a line AB in FIG. As shown in FIG. 20B, it can be seen that the end portions of the source region and the drain region 88 are located outside the end portion of the wiring layer 92c. The end portion of the buffer layer 87 is located outside the end portions of the wiring layer 92 c and the source and drain regions 88. One of the wiring layers has a shape surrounding the other of the source region and the drain region (specifically, a U shape or a C shape). For this reason, since the area of the region in which carriers move can be increased, the amount of current can be increased and the area of the TFT can be reduced.

As shown in FIG. 18C, the end portions of the wiring layers 92a to 92c and the end portions of the source region and the drain region 88 are not aligned and shifted so that the end portions of the wiring layers 92a to 92c are formed. Since the distance is increased, it is possible to prevent a leakage current or a short circuit between the wiring layers. Therefore, a highly reliable TFT can be manufactured.

Through the above steps, a channel etch TFT 83 can be formed. In addition, a TFT can be formed using two photomasks.

Next, as shown in FIG. 19A, a passivation film 76 is formed over the wiring layers 92a to 92c, the source and drain regions 88, the buffer layer 87, the LPSAS film 90, and the gate insulating layer 52b. The passivation film 76 can be formed in the same manner as the gate insulating layers 52a and 52b.

Next, a part of the passivation film 76 is etched using a mask pattern formed using a third photomask to form a contact hole. Next, the pixel electrode 77 in contact with the wiring layer 75c in the contact hole is formed. Here, as the pixel electrode 77, an ITO film is formed by a sputtering method, and then a resist is applied on the ITO. Next, the resist is exposed and developed using a fourth photomask to form a mask pattern. Next, the pixel electrode 77 is formed by etching the ITO using the mask pattern. Note that FIG. 19B corresponds to a cross-sectional view taken along a line AB in FIG. Through the above steps, an element substrate that can be used for a display device can be formed.

13B or 18B, after forming the wiring layers 92a to 92c, the mask pattern 86 is removed, and an impurity imparting one conductivity type is added using the wiring layers 92a to 92c as a mask. The semiconductor film 63 may be etched. As a result, a TFT in which the wiring layers 71 a to 71 c and the end portions of the source region and the drain region 88 are matched can be formed. Here, after removing the mask pattern 86 in FIG. 13B, the semiconductor layer 63 to which an impurity imparting one conductivity type is added is etched using the wiring layers 92a to 92c as masks, so that a source region and a drain region are formed. FIG. 21 shows a TFT in which the end portion 89 and the end portions of the wiring layers 92a to 92c are aligned.

Through the above steps, a channel etch TFT can be formed. A channel-etch TFT has a small number of manufacturing steps and can reduce costs. Further, field effect mobility of 1 to ²⁰ cm ² / V · sec can be obtained by forming a channel formation region using a microcrystalline semiconductor film. Therefore, this TFT can be used as an element for switching a pixel in the pixel portion and an element for forming a driving circuit on the scanning line (gate line) side.

With this embodiment mode, a TFT with high electrical characteristics can be manufactured. In addition, a display substrate having a TFT with excellent electrical characteristics and high reliability can be manufactured. According to this embodiment, a display device equipped with a highly reliable TFT that exceeds the performance of the conventional amorphous silicon TFT can be produced by adding a minimum production facility without requiring a large modification. Can do. When the channel formation region is formed using a microcrystalline semiconductor, variation in threshold voltage is suppressed, field-effect mobility is improved, and an S value is reduced, so that high performance of the TFT can be achieved. As a result, the drive frequency of the display device can be increased, and it is possible to sufficiently cope with an increase in panel size and an increase in pixel density. Furthermore, since no significant production line change is required, it is possible to suppress the increase in capital investment and production cost while improving the performance of the TFT.

(Embodiment 8)
In this embodiment, a liquid crystal display device including the TFT described in Embodiment 7 is described below as one embodiment of the display device.

First, a VA (vertical alignment) liquid crystal display device is described. The VA liquid crystal display device is a type of a method for controlling the alignment of liquid crystal molecules in a liquid crystal panel. The VA liquid crystal display device is a method in which liquid crystal molecules face a vertical direction with respect to a panel surface when no voltage is applied. In the present embodiment, the pixel (pixel) is divided into several regions (sub-pixels), and each molecule is devised to tilt the molecules in different directions. This is called multi-domain or multi-domain design. In the following description, a liquid crystal display device considering multi-domain design will be described.

23 and 24 show a pixel electrode and a counter electrode, respectively. FIG. 23 is a plan view of the substrate side on which the pixel electrode is formed, and FIG. 22 shows a cross-sectional structure corresponding to the cutting line AB in the drawing. FIG. 24 is a plan view of the substrate side on which the counter electrode is formed. The following description will be given with reference to these drawings.

FIG. 22 illustrates a state in which a liquid crystal is injected by superimposing a substrate 600 on which a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor portion 630 are formed, and a counter substrate 601 on which the counter electrode 640 and the like are formed. Show.

A light shielding film 632, a first colored film 634, a second colored film 636, a third colored film 638, and a counter electrode 640 are formed at positions where the spacers 642 are formed on the counter substrate 601. With this structure, the heights of the protrusions 644 and the spacers 642 for controlling the alignment of the liquid crystal are made different. An alignment film 648 is formed over the pixel electrode 624, and similarly, an alignment film 646 is formed over the counter electrode 640. In the meantime, a liquid crystal layer 650 is formed.

The spacers 642 are shown here using columnar spacers, but bead spacers may be dispersed. Further, the spacer 642 may be formed over the pixel electrode 624 formed over the substrate 600.

A TFT 628, a pixel electrode 624 connected to the TFT 628, and a storage capacitor portion 630 are formed over the substrate 600. The pixel electrode 624 is connected to the wiring 618 through a contact hole 623 that passes through the insulating film 620 that covers the TFT 628, the wiring, and the storage capacitor portion 630, and the third insulating film 622 that covers the insulating film. As the TFT 628, the TFT described in Embodiment 7 can be used as appropriate. The storage capacitor portion 630 includes a first capacitor wiring 604 formed in the same manner as the gate wiring 602 of the TFT 628, a gate insulating layer 606, and a second capacitor wiring 617 formed in the same manner as the wirings 616 and 618. The

The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 overlap with each other to form a liquid crystal element.

FIG. 23 shows a structure on the substrate 600. The pixel electrode 624 is formed using the material described in Embodiment 7. The pixel electrode 624 is provided with a slit 625. The slit 625 is for controlling the alignment of the liquid crystal.

The TFT 629 and the pixel electrode 626 and the storage capacitor portion 631 connected to the TFT 629 shown in FIG. 23 can be formed in the same manner as the pixel electrode 624 and the storage capacitor portion 630, respectively. Both the TFT 628 and the TFT 629 are connected to the wiring 616. A pixel (pixel) of the liquid crystal panel includes a pixel electrode 624 and a pixel electrode 626. The pixel electrode 624 and the pixel electrode 626 are subpixels.

FIG. 24 shows a structure on the counter substrate side. A counter electrode 640 is formed on the light shielding film 632. The counter electrode 640 is preferably formed using a material similar to that of the pixel electrode 624. On the counter electrode 640, a protrusion 644 for controlling the alignment of the liquid crystal is formed. A spacer 642 is formed in accordance with the position of the light shielding film 632.

When a voltage is applied to the pixel electrode 624 provided with the slit 625, an electric field distortion (an oblique electric field) is generated in the vicinity of the slit 625. By arranging the slits 625 and the protrusions 644 on the counter substrate 601 to alternately engage with each other, an oblique electric field is effectively generated to control the alignment of the liquid crystal, so that the direction in which the liquid crystal is aligned is determined. It is different depending on. That is, the viewing angle of the liquid crystal panel is widened by multi-domain.

Next, a VA liquid crystal display device different from the above is described with reference to FIGS.

25 and 26 show a pixel structure of a VA liquid crystal panel. FIG. 26 is a plan view of the substrate 600, and FIG. 25 shows a cross-sectional structure corresponding to the cutting line AB shown in the drawing. The following description will be given with reference to both the drawings.

In this pixel structure, a single pixel has a plurality of pixel electrodes, and a TFT is connected to each pixel electrode. Each TFT is configured to be driven by a different gate signal. In other words, a multi-domain designed pixel has a configuration in which signals applied to individual pixel electrodes are controlled independently.

The pixel electrode 624 is connected to the TFT 628 through a wiring 618 in the contact hole 623. The pixel electrode 626 is connected to the TFT 629 through a wiring 619 in the contact hole 627. The gate wiring 602 of the TFT 628 and the gate wiring 603 of the TFT 629 are separated so that different gate signals can be given. On the other hand, the wiring 616 functioning as a data line is used in common by the TFT 628 and the TFT 629. As the TFT 628 and the TFT 629, the TFT described in Embodiment 7 can be used as appropriate.

The pixel electrode 624 and the pixel electrode 626 have different shapes and are separated by a slit 625. A pixel electrode 626 is formed so as to surround the outside of the V-shaped pixel electrode 624. The timing of the voltage applied to the pixel electrode 624 and the pixel electrode 626 is made different by the TFT 628 and the TFT 629, thereby controlling the alignment of the liquid crystal.

A counter substrate 601 is provided with a light shielding film 632, a second coloring film 636, and a counter electrode 640. In addition, a planarization film 637 is formed between the second coloring film 636 and the counter electrode 640 to prevent alignment disorder of the liquid crystal. FIG. 27 shows a structure of the counter substrate side. The counter electrode 640 is a common electrode between different pixels, but a slit 641 is formed. By disposing the slits 641 and the pixel electrodes 624 and the slits 625 on the pixel electrode 626 side so as to alternately engage with each other, an oblique electric field can be effectively generated to control the alignment of the liquid crystal. Thereby, the direction in which the liquid crystal is aligned can be varied depending on the location, and the viewing angle is widened.

The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 overlap with each other, so that a first liquid crystal element is formed. In addition, the pixel electrode 626, the liquid crystal layer 650, and the counter electrode 640 overlap with each other, so that a second liquid crystal element is formed. In addition, the multi-domain structure in which the first liquid crystal element and the second liquid crystal element are provided in one pixel.

Next, a horizontal electric field liquid crystal display device is described. The horizontal electric field method is a method of expressing gradation by driving a liquid crystal by applying an electric field in a horizontal direction to liquid crystal molecules in a cell. According to this method, the viewing angle can be expanded to about 180 degrees. In the following description, a liquid crystal display device adopting a horizontal electric field method will be described.

28 and 29 show a pixel structure of an FFS type liquid crystal display device. FIG. 28 shows a state in which the substrate 600 on which the TFT 628 and the pixel electrode 624 connected to the TFT 628 are overlapped with the counter substrate 601 and liquid crystal is injected. The counter substrate 601 is provided with a light-shielding film 632, a second coloring film 636, a planarization film 637, and the like. Since the pixel electrode is on the substrate 600 side, it is not provided on the counter substrate 601 side. A liquid crystal layer 650 is formed between the substrate 600 and the counter substrate 601.

Over the substrate 600, the first pixel electrode 607, the capacitor wiring 604 connected to the first pixel electrode 607, and the TFT 628 described in Embodiment 7 are formed. The first pixel electrode 607 can be formed using a material similar to that of the pixel electrode 77 described in Embodiment 7. In addition, the first pixel electrode 607 is formed in a shape partitioned into a substantially pixel shape. Note that a gate insulating layer 606 is formed over the first pixel electrode 607 and the capacitor wiring 604.

A wiring 616 and a wiring 618 of the TFT 628 are formed over the gate insulating layer 606. A wiring 616 is a data line for carrying a video signal in the liquid crystal panel and extends in one direction. At the same time, the wiring 616 is connected to the source region 610 and serves as one of a source electrode and a drain electrode. A wiring 618 serves as the other of the source and drain electrodes and is connected to the second pixel electrode 624.

A second insulating film 620 is formed over the wiring 616 and the wiring 618. A second pixel electrode 624 connected to the wiring 618 is formed over the insulating film 620 in a contact hole formed in the insulating film 620. The pixel electrode 624 is formed using a material similar to that of the pixel electrode 77 described in Embodiment 7.

In this manner, the TFT 628 and the first pixel electrode 624 connected to the TFT 628 are formed over the substrate 600. Note that the storage capacitor is formed between the first pixel electrode 607 and the second pixel electrode 624.

FIG. 29 is a plan view showing the configuration of the pixel electrode. The pixel electrode 624 is provided with a slit 625. The slit 625 is for controlling the alignment of the liquid crystal. In this case, an electric field is generated between the first pixel electrode 607 and the second pixel electrode 624. A gate insulating layer 606 is formed between the first pixel electrode 607 and the second pixel electrode 624. The thickness of the gate insulating layer 606 is 50 to 200 nm, and the liquid crystal layer is 2 to 10 μm. Since it is sufficiently thin compared to the thickness, an electric field is generated in a direction substantially parallel to the substrate 600 (horizontal direction). The orientation of the liquid crystal is controlled by this electric field. Liquid crystal molecules are rotated horizontally using an electric field in a direction substantially parallel to the substrate. In this case, since the liquid crystal molecules are horizontal in any state, there is little influence of contrast or the like depending on the viewing angle, and the viewing angle is widened. In addition, since the first pixel electrode 607 and the second pixel electrode 624 are both light-transmitting electrodes, the aperture ratio can be improved.

Next, another example of a horizontal electric field liquid crystal display device is described. 30 and 31 illustrate a pixel structure of an IPS liquid crystal display device. FIG. 31 is a plan view, and FIG. 30 shows a cross-sectional structure corresponding to the cutting line AB shown in the figure. The following description will be given with reference to both the drawings.

FIG. 30 shows a state in which the substrate 600 on which the TFT 628 and the pixel electrode 624 connected thereto are formed and the counter substrate 601 are overlapped and liquid crystal is injected. The counter substrate 601 is provided with a light-shielding film 632, a second coloring film 636, a planarization film 637, and the like. Since the pixel electrode is on the substrate 600 side, it is not provided on the counter substrate 601 side. A liquid crystal layer 650 is formed between the substrate 600 and the counter substrate 601.

Over the substrate 600, the common potential line 609 and the TFT 628 described in Embodiment 7 are formed. The common potential line 609 can be formed at the same time as the gate wiring 602 of the TFT 628. In addition, the first pixel electrode 607 is formed in a shape partitioned into a substantially pixel shape.

A wiring 616 and a wiring 618 of the TFT 628 are formed over the gate insulating layer 606. A wiring 616 is a data line for carrying a video signal in the liquid crystal panel and extends in one direction. At the same time, the wiring 616 is connected to the source region 610 and serves as one of a source electrode and a drain electrode. A wiring 618 serves as the other of the source and drain electrodes and is connected to the second pixel electrode 624.

A second insulating film 620 is formed over the wiring 616 and the wiring 618. A second pixel electrode 624 connected to the wiring 618 in the contact hole 623 formed in the insulating film 620 is formed over the insulating film 620. The pixel electrode 624 is formed using a material similar to that of the pixel electrode 77 described in Embodiment 7. As shown in FIG. 31, the pixel electrode 624 is formed so as to generate a lateral electric field with a comb-shaped electrode formed simultaneously with the common potential line 609. Further, the comb-tooth portion of the pixel electrode 624 is formed to alternately bite with the comb-shaped electrode formed simultaneously with the common potential line 609.

When an electric field is generated between the potential applied to the pixel electrode 624 and the potential of the common potential line 609, the alignment of the liquid crystal is controlled by this electric field. Liquid crystal molecules are rotated horizontally using an electric field in a direction substantially parallel to the substrate. In this case, since the liquid crystal molecules are horizontal in any state, there is little influence of contrast or the like depending on the viewing angle, and the viewing angle is widened.

In this manner, the TFT 628 and the pixel electrode 624 connected to the TFT 628 are formed on the substrate 600. The storage capacitor is formed by providing a gate insulating layer 606 between the common potential line 609 and the capacitor electrode 615. The capacitor electrode 615 and the pixel electrode 624 are connected through a contact hole 633.

Next, a form of a TN liquid crystal display device is described. 32 and 33 show a pixel structure of a TN liquid crystal display device. FIG. 33 is a plan view, and FIG. 32 shows a cross-sectional structure corresponding to the cutting line AB shown in the figure. The following description will be given with reference to both the drawings.

The pixel electrode 624 is connected to the TFT 628 by a wiring 618 through a contact hole 623. A wiring 616 functioning as a data line is connected to the TFT 628. Any of the TFTs described in Embodiment 7 can be used as the TFT 628.

The pixel electrode 624 is formed using the pixel electrode 77 described in Embodiment 7.

A counter substrate 601 is provided with a light shielding film 632, a second coloring film 636, and a counter electrode 640. In addition, a planarization film 637 is formed between the second coloring film 636 and the counter electrode 640 to prevent alignment disorder of the liquid crystal. The liquid crystal layer 650 is formed between the pixel electrode 624 and the counter electrode 640. A liquid crystal element is formed by overlapping the pixel electrode 624, the liquid crystal 161, and the counter electrode 640.

Further, a color filter, a shielding film (black matrix) for preventing disclination, or the like may be formed on the substrate 600 or the counter substrate 601. In addition, a polarizing plate is attached to the surface of the substrate 600 opposite to the surface on which the TFT is formed, and a polarizing plate is attached to the surface of the counter substrate 601 opposite to the surface on which the counter electrode 640 is formed. Keep it.

The counter electrode 141 can be formed using a material similar to that of the pixel electrode 77 as appropriate. A liquid crystal element 132 is formed by overlapping the pixel electrode 77, the liquid crystal 161, and the counter electrode 141.

The liquid crystal display device of this embodiment is a liquid crystal display device with high contrast and high visibility because it uses a TFT with low off-state current, excellent electrical characteristics, and high reliability. The production system described in Embodiments 1 to 6 can be applied to production of liquid crystal display devices of various forms.

(Embodiment 9)
Next, a light-emitting device that is one embodiment of the display device will be described with reference to FIGS. FIG. 34 shows a cross-sectional view of the TFT 93 used in the driver circuit 121 and a cross-sectional view of the TFT 83 used in the pixel portion 122. Here, the light-emitting device is described using a light-emitting element utilizing electroluminescence. A light-emitting element using electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element. Here, FIGS. 17 to 19 are used as a manufacturing process of a TFT, but FIGS. 12 to 14 can be used as appropriate.

In the organic EL element, by applying a voltage to the light emitting element, electrons and holes are respectively injected from the pair of electrodes into the layer containing a light emitting organic compound, and a current flows. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light emission mechanism is localized light emission utilizing inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element. In addition, a channel etch TFT shown in FIG. 18C is used as the TFT 83 for controlling driving of the light-emitting element, but a channel protection TFT can be used as appropriate.

Through the steps of FIGS. 17 to 19, TFTs 83 and 93 are formed on the substrate 50 as shown in FIG. 34, and a passivation film 76 that functions as a protective film is formed on the TFTs 83 and 93. Next, the planarization film 111 is formed on the passivation film 76, and the pixel electrode 112 connected to the wiring layer of the TFT 96 is formed on the planarization film 111. The planarization film 91 is preferably formed using an organic resin such as acrylic, polyimide, or polyamide, or siloxane.

In FIG. 34A, since the TFT 83 of the pixel is an n-type, it is desirable to use a cathode as the pixel electrode 112. Conversely, in the case of a p-type, it is desirable to use an anode. Specifically, a known material having a small work function, such as Ca, Al, CaF, MgAg, AlLi, or the like can be used as the cathode.

Next, as shown in FIG. 34B, a partition wall 113 is formed over the end portions of the planarization film 91 and the pixel electrode 112. The partition wall 113 has an opening, and the pixel electrode 112 is exposed in the opening. The partition 113 is formed using an organic resin film, an inorganic insulating film, or a siloxane polymer. In particular, it is preferable to use a photosensitive material and form an opening on the pixel electrode so that the side wall of the opening is an inclined surface formed with a continuous curvature.

Next, the light emitting layer 114 is formed so as to be in contact with the pixel electrode 112 in the opening of the partition wall 113. The light emitting layer 114 may be composed of a single layer or a plurality of layers stacked.

Then, a common electrode 115 using an anode is formed so as to cover the light emitting layer 114. The common electrode 115 can be formed using a light-transmitting conductive film using a light-transmitting conductive material listed as the pixel electrode 77 in Embodiment 7. In addition to the above light-transmitting conductive film, a titanium nitride film or a titanium film may be used as the common electrode 115. In FIG. 34B, ITO is used for the common electrode 115. In the opening of the partition wall 113, the pixel electrode 112, the light emitting layer 114, and the common electrode 115 are overlapped to form a light emitting element 117. After that, a protective film 116 is preferably formed over the common electrode 115 and the partition wall 113 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting element 117. As the protective film 116, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

Furthermore, in practice, when completed up to FIG. 34 (B), packaging with a protective film (laminate film, UV curable resin film, etc.) or cover material that is highly airtight and less degassed so as not to be exposed to the outside air ( (Encapsulation) is preferable.

Next, the structure of the light-emitting element is described with reference to FIG. Here, the cross-sectional structure of the pixel will be described with an example in which the driving TFT is an n-type.

In order to extract light emitted from the light-emitting element, at least one of the anode and the cathode may be transparent. Then, a TFT and a light emitting element are formed on the substrate, and a top emission that extracts light emission from a surface opposite to the substrate, a bottom emission that extracts light emission from the surface on the substrate side, and a surface opposite to the substrate side and the substrate. The pixel structure of this embodiment mode can be applied to a light-emitting element having any emission structure.

A light-emitting element having a top emission structure will be described with reference to FIG. FIG. 35A is a cross-sectional view of a pixel in the case where the driving TFT 701 is n-type and light emitted from the light-emitting element 702 is emitted to the anode 705 side. In FIG. 35A, the cathode 703 of the light-emitting element 702 and the driving TFT 701 are electrically connected, and the light-emitting layer 704 and the anode 705 are stacked over the cathode 703 in this order. A known material can be used for the cathode 703 as long as it has a low work function and reflects light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. The light emitting layer 704 may be formed of a single layer or may be formed of a plurality of layers stacked. In the case of a plurality of layers, the electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer are stacked in this order on the cathode 703. Note that it is not necessary to provide all of these layers. The anode 705 is formed using a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, or titanium oxide. A conductive conductive film having a light-transmitting property such as indium tin oxide, ITO, indium zinc oxide, or indium tin oxide to which silicon oxide is added may be used.

A region where the light emitting layer 704 is sandwiched between the cathode 703 and the anode 705 corresponds to the light emitting element 702. In the case of the pixel shown in FIG. 35A, light emitted from the light-emitting element 702 is emitted to the anode 705 side as indicated by a hollow arrow.

Next, a light-emitting element having a bottom emission structure will be described with reference to FIG. A cross-sectional view of a pixel in the case where the driving TFT 711 is n-type and light emitted from the light-emitting element 712 is emitted to the cathode 713 side is shown. In FIG. 35B, a cathode 713 of the light-emitting element 712 is formed over a light-transmitting conductive material 717 electrically connected to the driving TFT 711. The light-emitting layer 714 is formed over the cathode 713. An anode 715 is sequentially stacked. Note that in the case where the anode 715 has a light-transmitting property, a shielding film 716 for reflecting or shielding light may be formed so as to cover the anode. As in the case of FIG. 35A, a known material can be used for the cathode 713 as long as it is a conductive film having a low work function. However, the film thickness is set so as to transmit light (preferably, about 5 nm to 30 nm). For example, Al having a thickness of 20 nm can be used as the cathode 713. Similarly to FIG. 35A, the light-emitting layer 714 may be formed of a single layer or a stack of a plurality of layers. The anode 715 does not need to transmit light, but can be formed using a light-transmitting conductive material as in FIG. The shielding film 716 can be formed using, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin to which a black pigment is added can be used.

A region where the light emitting layer 714 is sandwiched between the cathode 713 and the anode 715 corresponds to the light emitting element 712. In the case of the pixel shown in FIG. 35B, light emitted from the light-emitting element 712 is emitted to the cathode 713 side as shown by a hollow arrow.

Next, a light-emitting element having a dual emission structure will be described with reference to FIG. In FIG. 35C, the cathode 723 of the light-emitting element 722 is formed over the light-transmitting conductive material 727 electrically connected to the driving TFT 721, and the light-emitting layer 724 is formed over the cathode 723. An anode 725 is sequentially stacked. As in the case of FIG. 35A, a known material can be used for the cathode 723 as long as it is a conductive film having a low work function. However, the film thickness is set so as to transmit light. For example, Al having a thickness of 20 nm can be used as the cathode 723. Similarly to FIG. 35A, the light-emitting layer 724 may be formed of a single layer or a stack of a plurality of layers. The anode 725 can be formed using a light-transmitting conductive material as in the case of FIG.

A portion where the cathode 723, the light emitting layer 724, and the anode 725 overlap corresponds to the light emitting element 722. In the case of the pixel shown in FIG. 35C, light emitted from the light-emitting element 722 is emitted to both the anode 725 side and the cathode 723 side as indicated by white arrows.

Note that although an organic EL element is described here as a light-emitting element, an inorganic EL element can also be provided as a light-emitting element.

Note that in this embodiment mode, an example in which a light emitting element (TFT for controlling driving of a light emitting element) and the light emitting element are electrically connected is shown. However, a current controlling TFT is provided between the driving TFT and the light emitting element. A configuration in which TFTs are connected may be used.

Note that the light-emitting device shown in this embodiment mode is not limited to the structure shown in FIG. 35, and various modifications based on the technical idea of this embodiment mode are possible.

Through the above steps, a light-emitting device can be manufactured. The light-emitting device of this embodiment is a light-emitting device with high contrast and high visibility because it uses a TFT with low off-state current, excellent electrical characteristics, and high reliability. The production system described in Embodiments 1 to 6 can be applied to production of liquid crystal display devices of various forms.

1 is a diagram illustrating a configuration of a production system according to Embodiment 1. FIG. FIG. 2 shows a structure of a plasma CVD apparatus according to Embodiment 1; FIG. 2 shows a structure of a plasma CVD apparatus according to Embodiment 1; The figure which shows the structure of the production system which concerns on Embodiment 2. FIG. FIG. 5 shows a structure of a plasma CVD apparatus and a laser apparatus according to Embodiment 2. FIG. 5 is a diagram showing a configuration of a production system according to a third embodiment. FIG. 5 shows a structure of a plasma CVD apparatus and a laser apparatus according to Embodiment 3. The figure which shows the structure of the production system which concerns on Embodiment 4. FIG. FIG. 6 is a diagram showing a configuration of a production system according to a fifth embodiment. FIG. 6 shows a structure of a plasma CVD apparatus according to a fifth embodiment. 6 is a flowchart for explaining an example of a manufacturing process of a display device applied in the production system shown in Embodiments 1 to 5. 8A and 8B are cross-sectional views illustrating a method for manufacturing a display device of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a display device of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a display device of the present invention. 8A to 8D are top views illustrating a method for manufacturing a display device of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a display device of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a display device of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a display device of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a display device of the present invention. The top view explaining the semiconductor manufacturing apparatus applicable to this invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a display device of the present invention. 4A and 4B illustrate a liquid crystal display device of the present invention. 4A and 4B illustrate a liquid crystal display device of the present invention. 4A and 4B illustrate a liquid crystal display device of the present invention. 4A and 4B illustrate a liquid crystal display device of the present invention. 4A and 4B illustrate a liquid crystal display device of the present invention. 4A and 4B illustrate a liquid crystal display device of the present invention. 4A and 4B illustrate a liquid crystal display device of the present invention. 4A and 4B illustrate a liquid crystal display device of the present invention. 4A and 4B illustrate a liquid crystal display device of the present invention. 4A and 4B illustrate a liquid crystal display device of the present invention. 4A and 4B illustrate a liquid crystal display device of the present invention. 4A and 4B illustrate a liquid crystal display device of the present invention. 9A to 9D are cross-sectional views illustrating a method for manufacturing a light-emitting device of the present invention. FIG. 14 is a cross-sectional view illustrating a pixel that can be used in the light-emitting device of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Interprocess conveyance mechanism 11 In-process conveyance mechanism 12 Stocker 13 Plasma CVD apparatus 14 Sputtering apparatus 15 Dry etching apparatus 16 Wet etching apparatus 17 Resist coating / developing apparatus 18 Exposure apparatus 19 Peeling apparatus 20 Cleaning apparatus 21 Inspection apparatus 22 Cassette 23 Laser processing Apparatus 24 Transport cart 25 Substrate transport robot 26 Substrate carry-in / out chamber 27 First processing chamber 28 Second processing chamber 29 Third processing chamber 30 Fourth processing chamber 31 Fifth processing chamber 32 Transport chamber 33 Laser processing chamber 34 Laser light source 35 Light introduction Window 36 Exhaust means 37 Gas supply unit 38 High frequency power supply 50 Substrate 51 Gate electrode 52a Gate insulating layer 52b Gate insulating layer 52c Gate insulating layer 53a Microcrystalline semiconductor film 53b LPSAS film 54 Buffer layer 55 Impurity semiconductor film 56 Mask pattern 57 Laser beam 59 Multi-tone mask 59a Gray tone mask 59b Half tone mask 61 LPSAS film 62 Buffer layer 63 Semiconductor film 65a Conductive film 65b Conductive film 66 Mask pattern 71a Wiring layer 71c Wiring layer 72 Drain region 73 Buffer layer 74 TFT
75c Wiring layer 76 Passivation film 77 Pixel electrode 80 Resist 81 Mask pattern 83 TFT
85a conductive film 86 mask pattern 87 buffer layer 88 drain region 89 drain region 89a conductive film 90 LPSAS film 91 planarizing film 92a wiring layer 92b wiring layer 92c wiring layer 93 TFT
96 TFT
111 planarization film 112 pixel electrode 113 partition 114 light emitting layer 115 common electrode 116 protective film 117 light emitting element 132 liquid crystal element 141 counter electrode 161 liquid crystal 163 substrate 164 light shielding part 165 diffraction grating 166 light transmission amount 167 semitransmission part 168 light shielding part 169 light Transmission amount 600 Substrate 601 Counter substrate 602 Gate wiring 603 Gate wiring 604 Capacitance wiring 605 Capacitance wiring 606 Gate insulating layer 607 Pixel electrode 609 Common potential line 610 Source region 615 Capacitance electrode 616 Wiring 617 Capacitance wiring 618 Wiring 619 Wiring 620 Insulating film 622 Insulating Film 623 Contact hole 624 Pixel electrode 624 Pixel electrode 625 Slit 626 Pixel electrode 627 Contact hole 628 TFT
629 TFT
630 Holding capacitor portion 631 Holding capacitor portion 632 Light shielding film 633 Contact hole 634 Colored film 636 Colored film 637 Flattened film 638 Colored film 640 Counter electrode 641 Slit 642 Spacer 644 Protrusion 646 Alignment film 648 Alignment film 650 Liquid crystal layer 651 Liquid layer element 652 Liquid crystal element 701 Driving TFT
702 Light-emitting element 703 Cathode 704 Light-emitting layer 705 Anode 711 Driving TFT
712 Light-emitting element 713 Cathode 714 Light-emitting layer 715 Anode 716 Shielding film 717 Conductive material 721 Driving TFT
722 Light-emitting element 723 Cathode 724 Light-emitting layer 725 Anode 727 Conductive material

Claims (2)

A CVD apparatus;
A sputtering apparatus;
An etching apparatus;
A resist coating / developing device;
An exposure device;
An inter-process transport mechanism and an in-process transport mechanism for transporting process work products to each of the plasma CVD apparatus, the sputtering apparatus, the etching apparatus, the resist coating / developing apparatus, and the exposure apparatus;
In a display device production method for producing a display device having a thin film transistor including a microcrystalline semiconductor film on a substrate to be processed,
The thin film transistor has a bottom gate structure,
A laser processing apparatus is added to the plasma CVD apparatus,
Forming the microcrystalline semiconductor film on the substrate to be processed by the plasma CVD apparatus;
By the laser processing apparatus, the laser light is irradiated to the microcrystalline semiconductor film, to improve the crystallinity of the surface remain the microcrystalline semiconductor layer of the microcrystalline semiconductor film as the gate insulating film direction,
The laser beam is energy that does not melt the microcrystalline semiconductor film,
A method for producing a display device, characterized in that the substrate to be processed moves without being exposed to the atmosphere between the plasma CVD device and the laser processing device by an in-device transport mechanism. In claim 1,
A method for producing a display device, wherein a laser processing chamber of the laser processing apparatus is connected to a processing chamber of the plasma CVD apparatus.

Images