JP5303449B2 - 集積回路の設計を最適化するための方法とシステム - Google Patents

集積回路の設計を最適化するための方法とシステム Download PDF

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JP5303449B2
JP5303449B2 JP2009502900A JP2009502900A JP5303449B2 JP 5303449 B2 JP5303449 B2 JP 5303449B2 JP 2009502900 A JP2009502900 A JP 2009502900A JP 2009502900 A JP2009502900 A JP 2009502900A JP 5303449 B2 JP5303449 B2 JP 5303449B2
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routing
resources
wiring
wiring resources
placement
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JP2009536376A5 (https=
JP2009536376A (ja
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ヨヴァンカ シリック ヴュイコヴィック
ケニス エス マケルヴェイン
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Synopsys Inc
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Synopsys Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2009502900A 2006-03-24 2007-03-23 集積回路の設計を最適化するための方法とシステム Active JP5303449B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US78544306P 2006-03-24 2006-03-24
US60/785,443 2006-03-24
US11/726,777 US7873930B2 (en) 2006-03-24 2007-03-22 Methods and systems for optimizing designs of integrated circuits
US11/726,777 2007-03-22
PCT/US2007/007311 WO2007112032A2 (en) 2006-03-24 2007-03-23 Fpga routing with reservation for long lines and sharing long lines

Publications (3)

Publication Number Publication Date
JP2009536376A JP2009536376A (ja) 2009-10-08
JP2009536376A5 JP2009536376A5 (https=) 2010-05-06
JP5303449B2 true JP5303449B2 (ja) 2013-10-02

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JP2009502900A Active JP5303449B2 (ja) 2006-03-24 2007-03-23 集積回路の設計を最適化するための方法とシステム

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US (4) US7873930B2 (https=)
EP (1) EP2005341A2 (https=)
JP (1) JP5303449B2 (https=)
CN (1) CN101421733B (https=)
WO (1) WO2007112032A2 (https=)

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US7873930B2 (en) * 2006-03-24 2011-01-18 Synopsys, Inc. Methods and systems for optimizing designs of integrated circuits
US20090249276A1 (en) * 2008-02-25 2009-10-01 The Chinese University Of Hong Kong Methods and systems for fpga rewiring and routing in eda designs
US8296695B1 (en) 2010-06-11 2012-10-23 Altera Corporation Method and apparatus for performing fast incremental resynthesis
WO2012047735A2 (en) * 2010-09-29 2012-04-12 The Regents Of The University Of California In-place resynthesis and remapping techniques for soft error mitigation in fpga
US8850377B1 (en) 2011-01-20 2014-09-30 Xilinx, Inc. Back annotation of output time delays
WO2012154616A2 (en) * 2011-05-06 2012-11-15 Xcelemor, Inc. Computing system with hardware reconfiguration mechanism and method of operation thereof
US8930872B2 (en) * 2012-02-17 2015-01-06 Netronome Systems, Incorporated Staggered island structure in an island-based network flow processor
US8902902B2 (en) 2012-07-18 2014-12-02 Netronome Systems, Incorporated Recursive lookup with a hardware trie structure that has no sequential logic elements
CN104750885A (zh) * 2013-12-29 2015-07-01 北京华大九天软件有限公司 集成电路版图布线中引脚布线资源预分配方法
US9208273B1 (en) * 2014-10-01 2015-12-08 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing clone design components in an electronic design
US20160232006A1 (en) * 2015-02-09 2016-08-11 Qualcomm Incorporated Fan out of result of explicit data graph execution instruction
US10331840B2 (en) 2016-01-15 2019-06-25 International Business Machines Corporation Resource aware method for optimizing wires for slew, slack, or noise
US10120970B2 (en) 2016-06-14 2018-11-06 International Business Machines Corporation Global routing framework of integrated circuit based on localized routing optimization
US11361133B2 (en) * 2017-09-26 2022-06-14 Intel Corporation Method of reporting circuit performance for high-level synthesis
US10699053B1 (en) * 2018-01-17 2020-06-30 Xilinx, Inc. Timing optimization of memory blocks in a programmable IC
US11481535B2 (en) * 2018-05-15 2022-10-25 Nanobridge Semiconductor, Inc. Numerical information generation apparatus, numerical information generation method, and program

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JPH01286438A (ja) * 1988-05-13 1989-11-17 Hitachi Ltd セルの配置配線方式
JPH02218148A (ja) * 1989-02-17 1990-08-30 Sharp Corp 大規模ｌｓｉ中のブロックの端子位置決定方法
US6286128B1 (en) * 1998-02-11 2001-09-04 Monterey Design Systems, Inc. Method for design optimization using logical and physical information
US6438735B1 (en) 1999-05-17 2002-08-20 Synplicity, Inc. Methods and apparatuses for designing integrated circuits
US6449762B1 (en) 1999-10-07 2002-09-10 Synplicity, Inc. Maintaining correspondence between text and schematic representations of circuit elements in circuit synthesis
US6536028B1 (en) * 2000-03-14 2003-03-18 Ammocore Technologies, Inc. Standard block architecture for integrated circuit design
JP4349742B2 (ja) * 2000-12-27 2009-10-21 富士通マイクロエレクトロニクス株式会社 回路設計装置、および回路設計方法
CN1150481C (zh) * 2002-01-15 2004-05-19 清华大学 基于关键网络技术优化时延的标准单元总体布线方法
US6973632B1 (en) 2002-06-11 2005-12-06 Synplicity, Inc. Method and apparatus to estimate delay for logic circuit optimization
JP2004252762A (ja) * 2003-02-20 2004-09-09 Fujitsu Ltd 遅延調整方法及び遅延調整システム
US7251800B2 (en) * 2003-05-30 2007-07-31 Synplicity, Inc. Method and apparatus for automated circuit design
CN1271786C (zh) * 2003-12-16 2006-08-23 复旦大学 可编程逻辑器件结构建模方法
US7051295B2 (en) * 2003-12-23 2006-05-23 Intel Corporation IC design process including automated removal of body contacts from MOSFET devices
US7131096B1 (en) * 2004-06-01 2006-10-31 Pulsic Limited Method of automatically routing nets according to current density rules
US7620917B2 (en) * 2004-10-04 2009-11-17 Synopsys, Inc. Methods and apparatuses for automated circuit design
US7149997B1 (en) 2004-10-15 2006-12-12 Xilinx, Inc. Routing with frame awareness to minimize device programming time and test cost
US7363607B2 (en) * 2005-11-08 2008-04-22 Pulsic Limited Method of automatically routing nets according to parasitic constraint rules
US7873930B2 (en) * 2006-03-24 2011-01-18 Synopsys, Inc. Methods and systems for optimizing designs of integrated circuits
US7519927B1 (en) * 2008-07-02 2009-04-14 International Business Machines Corporation Wiring methods to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle-time overlap violations

Also Published As

Publication number Publication date
US20140215427A1 (en) 2014-07-31
US7873930B2 (en) 2011-01-18
US20070240091A1 (en) 2007-10-11
US8689165B2 (en) 2014-04-01
US9208281B2 (en) 2015-12-08
US20110113399A1 (en) 2011-05-12
CN101421733A (zh) 2009-04-29
WO2007112032A3 (en) 2008-03-06
JP2009536376A (ja) 2009-10-08
WO2007112032A2 (en) 2007-10-04
US10296690B2 (en) 2019-05-21
CN101421733B (zh) 2012-08-08
HK1132057A1 (en) 2010-02-12
EP2005341A2 (en) 2008-12-24
US20160092609A1 (en) 2016-03-31

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