JP5297491B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin semiconductor having chips stacked in multi-stages. <P>SOLUTION: A reformed region PL is formed by irradiating a semiconductor substrate 1S of a semiconductor wafer 1W with laser light having its condensing point inside the semiconductor substrate 1S. After a reverse surface of the semiconductor wafer 1W is subsequently coated with a liquid adhesive by a rotary coating method, the adhesive is dried to form a solid adhesive layer 8a. Then the semiconductor wafer 1W is divided into individual semiconductor chips based upon the reformed region PL as a division starting point. A semiconductor chip is bonded onto a principal surface of another semiconductor chip with an adhesive layer 8a on the reverse surface thereof to manufacture a semiconductor device having the semiconductor chips stacked in multi-stages. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device technology, and more particularly, to a multistage stacking technology for chips.

  In recent years, with the reduction in size and weight of mobile devices such as mobile phones and digital cameras, and information storage media such as memory cards, the density of semiconductor devices incorporated therein has been increased. In order to increase the density of a semiconductor device, it is indispensable to reduce the thickness of a semiconductor chip constituting the semiconductor device. In addition, a multistage stacked structure in which thinned semiconductor chips are stacked in multiple stages, such as two stages and three stages, has been developed, and the density of semiconductor devices has been further increased.

  In the method of bonding semiconductor chips stacked in multiple stages, for example, the second stage is formed on a region inside a plurality of electrodes formed on the main surface of the first stage semiconductor chip via a paste-like adhesive. There is a method of stacking semiconductor chips. However, in this method, due to the pressing load when the second-stage semiconductor chip is mounted, the paste-like adhesive material moves horizontally between the upper and lower semiconductor chips (towards the plurality of electrodes of the first-stage semiconductor chip). In some cases, it protrudes and covers the electrode on the main surface of the lower semiconductor chip. Further, since the semiconductor chip is thin, the paste-like adhesive material may roll up from the back surface of the upper semiconductor chip to the main surface through the side surface. Further, since the adhesive is in a paste form, the thickness accuracy is low, and the semiconductor chip placed on the adhesive may be inclined.

  As a method for solving these problems, for example, a film-like adhesive member such as a die attach film (hereinafter referred to as DAF) has been developed to reduce the size and thickness of a semiconductor device and to stack multiple layers of semiconductor chips. Contributing to Semiconductor chip bonding methods using DAF include, for example, a cut-and-reel method and a wafer back surface bonding method. The cut-and-reel method is a method in which a DAF cut to a chip size is transported and pasted to a chip mounting surface of a lower semiconductor chip, and another semiconductor chip is pasted thereon. On the other hand, in the above wafer backside pasting method, after the DAF is pasted so as to cover the entire backside of the semiconductor wafer, the DAF is cut simultaneously with the semiconductor chip at the time of dicing, and the semiconductor chip is cut into the lower semiconductor by the DAF on the backside. This is a method of pasting on the chip mounting surface of the chip.

  The die bonding technique is described, for example, in JP-A-8-236554 (Patent Document 1). After forming a thermoplastic conductive polyimide resin layer on the back surface of the wafer by spin coating, the wafer is chipped. A technique for obtaining a semiconductor device separated into units and having a thermoplastic conductive polyimide resin layer on the back surface is disclosed.

JP-A-8-236554

  However, the present inventor has found that the multi-layered structure of semiconductor chips using the film-like adhesive member has the following problems.

  The first problem is related to the thickness of the film-like adhesive member. That is, the thickness of the film-like adhesive member is limited to about 10 μm for the reasons of conveyance and production of the film-like adhesive member. More specifically, since the film-like adhesive member has an adhesive layer formed on the film substrate, the thickness of the film substrate cannot be ignored. Therefore, it is difficult to reduce the thickness to 10 μm or less. For this reason, there is a problem that the overall thinning of the multi-layered structure of the semiconductor chips is hindered.

  The second is a problem due to the change of the dicing method. In the dicing method, since the dicing blade is cut so as to press the surface of the wafer while rotating at high speed, the stress applied to the wafer is very high. That is, although the semiconductor wafer is being thinned as described above, there is a problem that when the thin semiconductor wafer is cut by the blade dicing method, the semiconductor wafer is chipped, and the bending strength of the thin semiconductor chip is remarkably lowered. From the viewpoint of improving the operation speed of a semiconductor device, there is a product that uses a low dielectric constant film (so-called Low-k film) whose dielectric constant is lower than that of silicon oxide as a wiring interlayer insulating film of a semiconductor chip. Since the K film is fragile, it may be easily peeled off or may have fine bubbles inside, and may not be cut well by the blade dicing method. Therefore, stealth dicing has attracted attention as a new dicing method that avoids these problems. This stealth dicing method is a dicing method in which a laser beam is irradiated inside a semiconductor wafer to selectively form a modified layer, and the semiconductor wafer is cut using the modified layer as a division starting point. According to this method, even an extremely thin semiconductor wafer having a thickness of about 30 μm can be directly cut without physically stressing, so that chipping can be reduced and the bending strength of the semiconductor chip is not lowered. In addition, regardless of the thickness of the semiconductor wafer, high-speed dicing at 300 mm or more per second is possible, so that throughput can be improved. Therefore, the stealth dicing method is an essential technique for thinning the semiconductor chip. However, when adopting the wafer back surface sticking method as described above, if the stealth dicing method is performed, the resin layer cannot be cut because the resin layer does not pass the laser, and the DAF can be cut well. There are cases where it is not possible. For this reason, it is necessary to select a resin material with adjusted hardness and brittleness excellent as a material for DAF. In this case, however, the material cost is high, and the cutting surface of the resin is not uniformed and dicing is performed. It is difficult to cut cleanly along the line. For this reason, the yield and reliability of the semiconductor device are reduced. In order to make the cutting surface uniform, it is effective to make the resin layer as thin as about 5 μm or less, but as described above, the thickness of the DAF is limited to about 10 μm. Therefore, there is a problem that the adoption of the stealth dicing method is hindered and the thinning of the semiconductor chip is hindered.

  Therefore, an object of the present invention is to provide a technique capable of reducing the thickness of a semiconductor device having a configuration in which chips are stacked in multiple stages.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, the present invention includes a step of applying a liquid adhesive on the back surface of a wafer by a spin coating method or a printing method to form a solid adhesive layer, and a step of performing a laser dicing process on the wafer. It is.

  In addition, the present invention has a configuration in which a plurality of chips are stacked in multiple stages, and the thickness of an adhesive layer between the plurality of chips is between a lowermost chip of the plurality of chips and a wiring board on which the chip is mounted. It is thinner than the thickness of the adhesive layer.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, a multi-stage process includes a step of applying a liquid adhesive to the back surface of the wafer by a spin coating method or a printing method to form a solid adhesive layer, and a step of performing a laser dicing process on the wafer. Since the thickness of the adhesive layer between the stacked chips can be reduced, a semiconductor device having a structure in which chips are stacked in multiple stages can be reduced in thickness.

It is a flowchart of the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 2 is an overall plan view of the main surface of the semiconductor wafer after the pre-process of FIG. 1. FIG. 3 is an enlarged plan view of a main part of an example of the semiconductor wafer of FIG. 2. FIG. 4 is an enlarged plan view of a region R1 in FIG. It is sectional drawing of the X1-X1 line | wire of FIG. It is sectional drawing of the semiconductor wafer in the back surface process of FIG. FIG. 7 is a cross-sectional view of a semiconductor wafer in a back surface processing step subsequent to FIG. 6. FIG. 8 is a cross-sectional view of the semiconductor wafer in a back surface processing step subsequent to FIG. 7. It is sectional drawing of the semiconductor wafer at the time of the laser irradiation process of the chip | tip division | segmentation process of FIG. FIG. 2 is an enlarged plan view of a main part of a semiconductor wafer during a laser irradiation process of the chip dividing process of FIG. 1. It is sectional drawing of the semiconductor wafer at the time of the contact bonding layer formation process of the chip | tip division | segmentation process of FIG. The left side is a cross-sectional view of the semiconductor wafer in the adhesive layer forming step following FIG. 11, and the right side is an overall plan view of the back surface of the semiconductor wafer in the adhesive layer forming step subsequent to FIG. The left side is a cross-sectional view of the semiconductor wafer during the adhesive layer forming step following FIG. 12, and the right side is an overall plan view of the back surface of the semiconductor wafer during the adhesive layer forming step following FIG. FIG. 2 is a cross-sectional view of a semiconductor wafer during a wafer mounting process of the chip dividing process of FIG. 1. It is sectional drawing of the semiconductor wafer at the time of the WSS peeling process of the chip | tip division | segmentation process of FIG. FIG. 16 is a cross-sectional view of the semiconductor wafer during the WSS peeling process of FIG. 1 following FIG. 15. FIG. 2 is an overall plan view of a main surface of a semiconductor wafer after the wafer mounting step of FIG. 1 and a jig to which the semiconductor wafer is attached. It is sectional drawing of the X2-X2 line | wire of FIG. It is sectional drawing of the semiconductor wafer at the time of the division | segmentation process of the chip | tip division | segmentation process of FIG. FIG. 2 is an overall plan view of the back surface of the semiconductor wafer during the dividing step of FIG. 1. It is sectional drawing of the semiconductor wafer at the time of the pick-up process of the assembly process of FIG. FIG. 2 is a perspective view of a semiconductor chip during a die bonding process of the assembly process of FIG. 1. FIG. 2 is a cross-sectional view of a semiconductor chip during a die bonding process in the assembly process of FIG. 1. FIG. 2 is a cross-sectional view of the semiconductor device after a wire bonding process in the assembly process of FIG. 1. It is sectional drawing of the semiconductor device after the sealing process of the assembly process of FIG. It is sectional drawing of the semiconductor wafer at the time of the contact bonding layer formation process of FIG. 1 in the manufacturing process of the semiconductor device which is other embodiment of this invention. It is a top view of the mask used at the time of the contact bonding layer formation process of FIG. FIG. 27 is a cross-sectional view of the semiconductor wafer during an adhesive layer formation step subsequent to FIG. 26. FIG. 29 is a plan view of the back surface side of the semiconductor wafer of FIG. 28. FIG. 29 is a cross-sectional view of the semiconductor wafer during an adhesive layer formation step subsequent to FIG. 28. FIG. 31 is a plan view of the back surface of the semiconductor wafer of FIG. 30. FIG. 31 is a cross-sectional view of a semiconductor wafer during a wafer mounting process of a chip dividing process following FIG. 30. FIG. 33 is a cross-sectional view of the semiconductor wafer after the WSS peeling step following FIG. 32. FIG. 34 is a cross-sectional view of the semiconductor wafer during the dividing step following FIG. 33. FIG. 35 is an overall plan view of the back surface of the semiconductor wafer of FIG. 34. It is a flowchart of the manufacturing process of the semiconductor device which is further another embodiment of this invention. FIG. 37 is a cross-sectional view of the semiconductor wafer during an adhesive layer forming step of the chip dividing step of FIG. 36. The left side is a cross-sectional view of the semiconductor wafer in the adhesive layer forming step of the chip dividing step following FIG. 37, and the right side is an overall plan view of the semiconductor wafer at this time. The left side is a cross-sectional view of the semiconductor wafer in the adhesive layer forming step of the chip dividing step following FIG. 38, and the right side is an overall plan view of the semiconductor wafer at this time. FIG. 40 is a cross-sectional view of the semiconductor wafer during the wafer mounting step of FIG. 36 following FIG. 39; FIG. 41 is a cross-sectional view of the semiconductor wafer during the laser irradiation step of FIG. 36 following FIG. 40. FIG. 43 is a cross-sectional view of the semiconductor wafer during the WSS peeling process of FIG. 36 following FIG. 41. FIG. 37 is a cross-sectional view of the semiconductor wafer during the adhesive layer formation step of FIG. 36 in the manufacturing process of the semiconductor device according to another embodiment of the present invention; FIG. 44 is a cross-sectional view of the semiconductor wafer during an adhesive layer forming step subsequent to FIG. 43. FIG. 45 is a cross-sectional view of the semiconductor wafer during an adhesive layer formation step subsequent to FIG. 44. FIG. 46 is a cross-sectional view of the semiconductor wafer during the wafer mounting process following FIG. 45. FIG. 47 is a cross-sectional view of the semiconductor wafer during the laser irradiation step following FIG. 46. It is a top view of the mask used at the time of the contact bonding layer formation process of the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 49 is a cross-sectional view of the semiconductor wafer during the adhesive layer formation step using the mask of FIG. 48. FIG. 50 is a cross-sectional view of the semiconductor wafer during an adhesive layer formation step subsequent to FIG. 49. FIG. 52 is an enlarged plan view of the main part of the back surface of the semiconductor wafer of FIG. 50. FIG. 51 is a cross-sectional view of the semiconductor wafer during a wafer mounting process following FIG. 50. FIG. 53 is a cross-sectional view of the semiconductor wafer after the WSS peeling step following FIG. 52. FIG. 54 is a cross-sectional view of the semiconductor wafer during the dividing step following FIG. 53. It is sectional drawing of the semiconductor device which is other embodiment of this invention. It is sectional drawing of the semiconductor device which is other embodiment of this invention. It is sectional drawing of the semiconductor device which is other embodiment of this invention. It is sectional drawing of the semiconductor device which is other embodiment of this invention.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
A method of manufacturing the semiconductor device according to the first embodiment will be described with reference to the flowchart of FIG.

  First, in the pre-process 100, a semiconductor wafer (hereinafter referred to as a wafer) having a main surface and a back surface that are opposite to each other along the thickness direction is prepared, and a plurality of wafers are formed on the main surface (device forming surface) of the wafer. A semiconductor chip (hereinafter referred to as a chip) is formed. This pre-process 100 is also called a wafer process or wafer fabrication, and is a process until a chip (element or circuit) is formed on the main surface of the wafer and an electrical test can be performed with a probe or the like. The pre-process includes a film formation process, an impurity introduction (diffusion or ion implantation) process, a photolithography process, an etching process, a metallization process, a cleaning process, and an inspection process between the processes.

  2 is an overall plan view of the main surface of the wafer 1W after this pre-process 100, FIG. 3 is an enlarged plan view of the main part of an example of the wafer 1W in FIG. 2, and FIG. 4 is an enlarged plan view of a region R1 in FIG. 5 shows a cross-sectional view taken along line X1-X1 of FIG.

  The wafer 1W is made of, for example, a substantially planar semiconductor thin plate having a diameter of about 300 mm, and a plurality of planar rectangular chips 1C, for example, are disposed on the main surface thereof through a cutting region (separation region) CR around each of them. Are arranged. A semiconductor substrate (hereinafter referred to as a substrate) 1S of the wafer 1W is made of, for example, silicon (Si) single crystal, and an element and a wiring layer 1L are formed on its main surface. The thickness of the wafer 1W at this stage (the sum of the thickness of the substrate 1S and the thickness of the wiring layer 1L) is, for example, about 775 μm. In addition, the code | symbol N of FIG. 2 has shown the notch. Moreover, the code | symbol CL of FIG. 4 has shown the cutting line. Further, the cutting line CL is arranged so as to pass through substantially the center in the width direction (short direction) of the cutting region CR.

The wiring layer 1L includes an interlayer insulating film 1Li, a wiring, a bonding pad (external terminal; hereinafter referred to as a pad) 1LB, a test (TEG) pad 1LBt, an alignment target Am, and a surface protective film (hereinafter referred to as a “protecting layer”). 1 Lp (referred to as a protective film) is formed. The interlayer insulating film 1Li has a plurality of interlayer insulating films 1Li1, 1Li2, 1Li3. For the interlayer insulating films 1Li1, 1Li3, for example, an inorganic insulating film such as silicon oxide (SiO ₂ or the like) is used. For the interlayer insulating film 1Li2, a low dielectric constant film (Low-k film) having a dielectric constant lower than that of silicon oxide, such as organic polymer or organic silica glass, is used from the viewpoint of improving the operation speed of the semiconductor device. ing.

  As this organic polymer (fully organic low dielectric interlayer insulating film), for example, SiLK (manufactured by The Dow Chemical Co., USA, relative dielectric constant = 2.7, heat-resistant temperature = 490 ° C. or higher, dielectric breakdown voltage = 4.0 to 4.0) 5.0 MV / Vm) or FLARE of polyallyl ether (PAE) material (manufactured by Honeywell Electronic Materials, relative permittivity = 2.8, heat-resistant temperature = 400 ° C. or higher). This PAE material is characterized by high basic performance and excellent mechanical strength, thermal stability and low cost.

  Examples of the organic silica glass (SiOC-based material) include HSG-R7 (manufactured by Hitachi Chemical Co., Ltd., relative dielectric constant = 2.8, heat-resistant temperature = 650 ° C.), Black Diamond (manufactured by Applied Materials, Inc., relative dielectric constant). = 3.0-2.4, heat-resistant temperature = 450 ° C.) or p-MTES (manufactured by Hitachi Development Co., Ltd., relative dielectric constant = 3.2). Examples of other SiOC-based materials include CORAL (manufactured by Novellus Systems, Inc., relative dielectric constant = 2.7 to 2.4, heat-resistant temperature = 500 ° C.), Aurora 2.7 (manufactured by Japan ASM Co., Ltd.). , Relative dielectric constant = 2.7, heat-resistant temperature = 450 ° C.).

  Other low dielectric constant film materials include, for example, fully organic SiOF materials such as FSG, HSQ (hydrogen silsesquioxane) materials, MSQ (methyl silsesquioxane) materials, porous HSQ materials, and porous MSQ materials. Alternatively, a porous organic material can be used.

  Examples of the HSQ-based material include OCD T-12 (manufactured by Tokyo Ohka Kogyo Co., Ltd., dielectric constant = 3.4 to 2.9, heat-resistant temperature = 450 ° C.), FOx (manufactured by Dow Corning Corp., USA), dielectric constant = 2.9) or OCL T-32 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative permittivity = 2.5, heat-resistant temperature = 450 ° C.).

  Examples of the MSQ material include OCD T-9 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.7, heat-resistant temperature = 600 ° C.), LKD-T200 (manufactured by JSR, relative dielectric constant = 2.7-2. 5, heat-resistant temperature = 450 ° C., HOSP (manufactured by Honeywell Electronic Materials, relative dielectric constant = 2.5, heat-resistant temperature = 550 ° C.), HSG-RZ25 (manufactured by Hitachi Chemical, relative dielectric constant = 2.5, heat-resistant Temperature = 650 ° C.), OCL T-31 (manufactured by Tokyo Ohka Kogyo Co., Ltd., dielectric constant = 2.3, heat-resistant temperature = 500 ° C.) or LKD-T400 (manufactured by JSR, dielectric constant = 2.2-2, heat-resistant temperature) = 450 ° C.).

  Examples of the porous HSQ material include XLK (manufactured by Dow Corning Corp., relative dielectric constant = 2.5-2), OCL T-72 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.2-1.9). , Heat resistant temperature = 450 ° C), Nanoglass (manufactured by Honeywell Electronic Materials, relative dielectric constant = 2.2 to 1.8, heat resistant temperature = 500 ° C or higher) or MesoELK (US Air Products and Chemicals, Inc, relative dielectric constant = 2) Etc.)

  Examples of the porous MSQ material include HSG-6221X (manufactured by Hitachi Chemical Co., Ltd., relative dielectric constant = 2.4, heat-resistant temperature = 650 ° C.), ALCAP-S (manufactured by Asahi Kasei Kogyo Co., Ltd., relative dielectric constant = 2.3-1). .8, heat resistant temperature = 450 ° C.), OCL T-77 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.2 to 1.9, heat resistant temperature = 600 ° C.), HSG-6210X (manufactured by Hitachi Chemical Co., Ltd., dielectric constant) Rate = 2.1, heat-resistant temperature = 650 ° C.) or silica aerogel (manufactured by Kobe Steel, relative dielectric constant: 1.4 to 1.1).

  Examples of the porous organic material include PolyELK (US Air Products and Chemicals, Inc., dielectric constant = 2 or less, heat-resistant temperature = 490 ° C.), and the like.

The SiOC material and the SiOF material are formed by, for example, a CVD method (Chemical Vapor Deposition). For example, the Black Diamond is formed by a CVD method using a mixed gas of trimethylsilane and oxygen. The p-MTES is formed by, for example, a CVD method using a mixed gas of methyltriethoxysilane and N ₂ O. The other low dielectric constant insulating materials are formed by, for example, a coating method.

In FIG. 5, the interlayer insulating film 1Li2 is shown as a single layer for the sake of simplicity, but actually, a plurality of low dielectric constant films are stacked. An insulating film such as silicon carbide (SiC) or silicon carbonitride (SiCN) is interposed between the plurality of low dielectric constant films. In addition, a cap insulating film made of silicon oxide (SiO _x ) typified by silicon dioxide (SiO ₂ ) is interposed between the insulating film such as silicon carbide or silicon carbonitride and the low dielectric constant film. Sometimes it is done. The cap insulating film has functions such as ensuring the mechanical strength, surface protection, and moisture resistance of the low dielectric constant film during, for example, chemical mechanical polishing (CMP). The cap insulating film is formed to be relatively thinner than the low dielectric constant film. However, the cap insulating film is not limited to the silicon oxide film and can be variously changed. For example, a silicon nitride (Si _x N _y ) film, a silicon carbide film, or a silicon carbonitride film may be used. These silicon nitride film, silicon carbide film, or silicon carbonitride film can be formed by, for example, a plasma CVD method. As a silicon carbide film formed by the plasma CVD method, for example, there is BLOk (manufactured by AMAT, relative permittivity = 4.3). In the formation, for example, a mixed gas of trimethylsilane and helium (or N ₂ , NH ₃ ) is used.

  Further, in FIG. 5, wiring is not shown in the interlayer insulating film 1Li2 for the sake of simplicity, but actually, the wiring is formed in a multilayer in the interlayer insulating film 1Li2. This wiring is, for example, a buried wiring. That is, this wiring is formed by embedding a conductor film in a wiring groove formed in each layer of the interlayer insulating film 1Li2. The conductor film forming the wiring has a main conductor film and a barrier metal film formed so as to cover the outer peripheral surface (bottom surface and side surface) thereof. The main conductor film is made of, for example, copper (Cu). The barrier metal film is made of, for example, titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), tungsten (W), titanium tungsten (TiW), or a laminated film thereof. Is formed.

  The wiring on the interlayer insulating film 1Li3, the pads 1LB, 1LBt, and the alignment target Am are formed of a metal film such as aluminum. Such uppermost wiring and pads 1LB, 1LBt, etc. are covered with a protective film 1Lp formed on the uppermost layer of the wiring layer 1L. The protective film 1Lp includes an inorganic insulating film such as silicon oxide, an inorganic insulating film such as silicon nitride deposited thereon, and a polyimide resin such as polyimide resin deposited thereon. It is formed of a laminated film with such an organic insulating film. An opening 2 is formed in a part of the protective film 1Lp, and parts of the pads 1LB and 1LBt are exposed therefrom. The pads 1LB are arranged side by side along the outer periphery of the chip 1C, and are electrically connected to the integrated circuit elements of the chip 1C through the wiring in the interlayer insulating film 1Li.

  The test pad 1LBt and the alignment target Am are arranged in the cutting region CR of the chip 1C. The test pad 1LBt is formed in, for example, a rectangular shape, and is electrically connected to the TEG element through the wiring. The alignment target Am is a pattern used for alignment between a manufacturing apparatus such as an exposure apparatus and the chip 1C of the wafer 1W, and is formed in a planar cross shape, for example. In addition to the cross shape, the alignment target Am may be formed in an L shape or a dot shape.

  In the subsequent test process 101 of FIG. 1, various electrical characteristic inspections are performed by applying probes to the pads 1LB of each chip 1C of the wafer 1W and the test pads 1LBt of the cutting region CR. This test process is also referred to as a G / W (Good chip / Wafer) check process, and is a test process that mainly electrically determines the quality of each chip 1C formed on the wafer 1W.

  A subsequent process 102 in FIG. 1 is a process until the chip 1C is housed in a sealing body (package) and completed, and includes a back surface processing process 102A, a chip dividing process 102B, and an assembling process 102C. Hereinafter, the back surface processing step 102A, the chip dividing step 102B, and the assembly step 102C will be described in order.

  6 to 8 are sectional views of the wafer 1W in the back surface processing step 102A.

  First, as shown in FIG. 6, the adhesive layer 3 is uniformly applied to the entire main surface of the wafer 1W by a spin coating method or the like. Subsequently, as shown in FIG. 7, the support substrate 4 is bonded to the main surface of the wafer 1W via the adhesive layer 3 (step 102A1 in FIG. 1). The support substrate 4 is a wafer support system (WSS) that functions as a reinforcing member for the wafer 1W in the subsequent process. As a result, when the wafer 1W is transported, the ultra-thin and large-diameter wafer 1W can be handled in a stable state, and the wafer 1W can be protected from external impacts. Can be suppressed or prevented. In each subsequent process, warping and bending of the wafer 1W can be suppressed or prevented, and the flatness of the ultra-thin and large-diameter wafer 1W can be improved, so that the processing stability in each process is improved. And controllability can be improved. As a material of the support substrate 4, for example, a hard support substrate (Hard-WSS or Glass-WSS) such as transparent glass is used. However, as another material of the support substrate 4, for example, another hard support substrate (Hard-WSS) such as stainless steel may be used. Further, as another material of the support substrate 4, a tape WSS in which an insulating support substrate such as PET (Polyethylene Terephthalate) or PEN (Polyethylene Naphthalate) is attached to a tape base material may be used. When the support substrate 4 is attached to the main surface of the wafer 1W, the support substrate 4 is fixed to the main surface of the wafer 1W by pressing the formation surface of the release layer 4a of the support substrate 4 against the adhesive layer 3. The peeling layer 4a is a functional layer for facilitating peeling when the support substrate 4 is peeled from the wafer 1W.

  Thereafter, as shown in FIG. 8, after measuring the thickness of the wafer 1W, the wafer 1W is thinned based on the measurement result. Here, grinding processing and polishing processing (flat processing) are sequentially performed on the back surface of the wafer 1W (steps 102A2 and 102A3 in FIG. 1). The thickness of the wafer 1W after such thinning processing (the sum of the thickness of the substrate 1S and the thickness of the wiring layer 1L) is, for example, 100 μm or less (for example, about 90 μm, about 70 μm, or about 50 μm). Here, when the thickness of the wafer 1W is reduced to 100 μm or less, the bending strength of the chip decreases due to damage or stress generated on the back surface of the wafer 1W by the back surface grinding process, and the chip is mounted. The problem that the chip breaks due to pressure is likely to occur. For this reason, the back surface polishing process after the back surface grinding process is an important process for eliminating damage and stress on the back surface of the wafer 1W so as not to cause such a problem. As the back surface polishing treatment, for example, an etching method using nitric acid and hydrofluoric acid may be used in addition to a polishing method using a polishing pad and silica or a chemical mechanical polishing (CMP) method. However, if the back surface of the wafer 1W is flattened by polishing, impurities may easily diffuse from the back surface of the wafer 1W toward the inside of the wafer 1W (device formation surface). Therefore, in the case of a product that requires the unevenness (damage, stress, etc.) on the back surface of the wafer 1W to function as a gettering layer for trapping impurities, the back surface polishing process is not performed and the unevenness ( In some cases, damage or stress is intentionally left. 8 indicates the substrate 1S before the thinning process.

  Next, FIG. 9 is a cross-sectional view of the wafer 1W during the laser irradiation step 102B1 in the chip dividing step 102B, and FIG. 10 is an enlarged plan view of the main part of the wafer 1W in FIG.

  First, the ultra-thin wafer 1W is transferred to the laser dicing apparatus with the support substrate 4 attached to the main surface thereof, and placed on the suction stage with the back surface of the wafer 1W facing up. Subsequently, by using an infrared camera (hereinafter referred to as an IR camera) from the back surface of the wafer 1W, a pattern on the main surface of the wafer 1W (a pattern of the chip 1C and the cutting region CR, a pad 1LBt disposed in the cutting region CR, Alignment target Am, pad 1LB arranged in chip 1C, etc.) are recognized. Then, after alignment (position correction) of the cutting line CL is performed based on the pattern information obtained by the IR camera, the laser beam (energy beam) LB1 emitted from the laser generator 5 is applied from the back side of the wafer 1W. Irradiation is performed in a state where the condensing point is aligned with the inside of the substrate 1S of the wafer 1W, and the wafer 1W is moved along the cutting line CL aligned based on the pattern information. As a result, a modified region (optically damaged portion or fractured layer) PL by multiphoton absorption is formed inside the substrate 1S in the cutting region CR of the wafer 1W. The modified region PL is formed by heating and melting the inside of the wafer 1W by multiphoton absorption, and becomes a cutting start region of the wafer 1W in the subsequent chip dividing step. This melting treatment region is a region that has been once melted and then re-solidified, a region that is in a molten state, a region that is re-solidified from a molten state, and can also be referred to as a phase-changed region or a region in which the crystal structure has changed. . The melt treatment region can also be said to be a region in which one structure is changed to another structure in a single crystal structure, an amorphous structure, or a polycrystalline structure. For example, in the substrate 1S portion, a region changed from a single crystal structure to an amorphous structure, a region changed from a single crystal structure to a polycrystalline structure, and a region changed from a single crystal structure to a structure including an amorphous structure and a polycrystalline structure Means.

  The laser beam LB1 may be irradiated continuously along the cutting region CR, or may be irradiated intermittently. When the laser beam LB1 is continuously irradiated, the modified region PL is formed linearly along the cutting line CL. When the laser beam LB1 is intermittently irradiated, the modified region PL is formed in a broken line shape (dot shape). Since the low dielectric constant film has a low thermal conductivity and heat is likely to be trapped, it may be discolored by the heat at the time of irradiation with the laser beam LB1, but when the laser beam LB1 is intermittently irradiated, the irradiation area of the laser beam LB1 is reduced. Since the generation of heat due to irradiation with the laser beam LB1 can be suppressed as much as possible, discoloration of the low dielectric constant film due to heat can be suppressed or prevented.

  Since the back surface of the wafer 1W is an incident surface for the laser beam LB1, it is preferably flat and smooth to reduce or prevent scattering of the laser beam LB1. Further, in the formation of the modified region PL, since the laser beam LB1 is hardly absorbed on the back surface of the wafer 1W, the back surface of the wafer 1W is not melted. Moreover, although it does not specifically limit, the irradiation conditions of the laser beam LB1 are as follows, for example. That is, the type of the laser beam LB1 is, for example, an LD-excited solid pulse laser, the light source is, for example, a YAG laser having a wavelength of 1064 nm, the frequency is, for example, 400 kHz, the laser power is, for example, 1 W or less, and the laser spot diameter is, for example, 1-2 μm The moving speed of the laser beam LB1 is, for example, about 300 mm / s.

  Next, FIGS. 11 to 13 show the state of the wafer 1W during the adhesive layer forming step 102B2 of the chip dividing step 102B. 11 is a cross-sectional view of the wafer 1W, the left side of FIGS. 12 and 13 is a cross-sectional view of the wafer 1W, and the right side is an overall plan view of the back surface of the wafer 1W.

  First, the wafer 1W taken out from the laser dicing apparatus is transported to a spin coater (spin coater) with the support substrate 4 still attached to the main surface thereof, and the back surface of the wafer 1W is directed upward. It is fixed by placing it on a rotating support and sucking it with vacuum. Subsequently, as shown in FIG. 11, a liquid (paste-like) adhesive material 8 is dropped from the nozzle 7 of the spin coater onto the center of the back surface of the wafer 1W. The base material of the adhesive material 8 is formed of, for example, a thermoplastic resin. As a specific example of the thermoplastic resin, for example, there is a polyimide resin. Further, for example, a thermosetting resin may be used as the base material of the adhesive material 8. Specific examples of the thermosetting resin include, for example, an epoxy resin, a polyimide resin, or a silicone resin. Thereafter, as shown in FIG. 12, the wafer 1W is rotated at a high speed to form a thin film of the adhesive 8 on the entire back surface of the wafer 1W (rotary coating method). Thereafter, the wafer 1W is transported onto a heat stage with the support substrate 4 attached to the main surface thereof, and dried, for example, at 100 to 200 ° C. for about 30 minutes to solidify the adhesive 8. . When the base material of the adhesive 8 is a thermosetting resin, the thermosetting resin is cured to some extent by performing a heat treatment, but is not completely cured but remains in an adhesive state. In this way, as shown in FIG. 13, a solid thin adhesive layer 8a is formed on the entire back surface of the wafer 1W. The adhesive layer 8a obtained by solidifying the adhesive 8 is for fixing the chip 1C obtained from the wafer 1W in the subsequent process on another chip, and the thickness thereof is uniform. It is formed on the entire back surface of the wafer 1W. The thickness of the adhesive layer 8a is, for example, thinner than 10 μm, for example, about 5 μm or less. Further, since the adhesive layer 8a is formed by spin-coating only the adhesive 8 as described above and then solidifying, the thickness of the adhesive layer 8a is thinner than that of the DAF because the film substrate is not required unlike the DAF. It is possible to form.

  In the first embodiment, after a liquid (paste-like) adhesive material 8 is dropped from the nozzle 7 of the spin coater onto the center of the back surface of the wafer 1W, the wafer 1W is rotated at a high speed so that the entire surface of the back surface of the wafer 1W is rotated. Although the method of forming the thin adhesive film 8 has been described, in the case where the adhesive 8 having a high viscosity is used, the liquid (paste-like) adhesive 8 is preliminarily rotated with the wafer 1W rotated at a high speed. It is preferable to drop the film onto the center of the back surface of 1 W, and then change the number of revolutions to form a thin film of adhesive 8 on the entire back surface of wafer 1 W.

  In the first embodiment, by forming the adhesive layer 8a using the spin coating method as described above, the thickness of the adhesive layer 8a can be reduced as described above. Further, since the adhesive layer 8a is formed by the resin coating method, the uniformity of the thickness of the adhesive layer 8a in the back surface of the wafer 1W can be improved. Further, since the adhesive 8 can be spin-coated while the flatness of the wafer 1W is high by attaching the support substrate 4 to the main surface of the wafer 1W, the thickness of the adhesive layer 8a within the back surface of the wafer 1W is uniform. Can be improved. When the WSS is not used, when only the tape material is attached to the main surface of the wafer 1W, or when the tape WSS is used, the adhesive material 8 is vacuum-sucked on the entire main surface of the wafer 1W toward the rotary support base. Is preferably applied by spin coating. Thus, by vacuum-sucking the entire main surface of the wafer 1W, warping and bending of the ultra-thin and large-diameter wafer 1W can be reduced or prevented, and the flatness of the wafer 1W can be improved. The uniformity of the thickness of the adhesive layer 8a in the back surface of the wafer 1W can be improved.

  When DAF is used, the specifications vary depending on the size and thickness of the wafer 1W. However, in the case of the resin coating method as in the first embodiment, only one type of resin material may be used, and particularly the size of the wafer 1W. It does not depend on the thickness. Further, since the molding technique and processing technique required for DAF are unnecessary, the cost can be reduced. In addition, when DAF is bonded to the wafer 1W, it is necessary to apply pressure to the wafer 1W in order to eliminate wrinkles and voids between the wafer 1W and the DAF and improve adhesion, but in the case of a thin wafer 1W having a thickness of 50 μm or less. There is an increasing concern about damage to the wafer 1W due to pressurization. On the other hand, in the first embodiment, it is not necessary to apply pressure to the wafer 1W in forming the adhesive layer 8a, and damage deterioration of the wafer 1W can be reduced or prevented. Therefore, the yield and reliability of the semiconductor device can be improved.

  Next, FIG. 14 shows a cross-sectional view of the wafer 1W after the wafer mounting process 102B3 of the chip dividing process 102B.

  In this step, as shown in FIG. 14, the back surface (formation surface of the adhesive layer 8 a) of the wafer 1 </ b> W is attached to the tape 10 of the jig 10 with the support substrate 4 being attached to the main surface of the wafer 1 </ b> W. . The tape base of the tape 10a of the jig 10 is made of, for example, a flexible plastic material, and an adhesive layer is formed on the main surface thereof. The wafer 1W is firmly fixed by the adhesive layer of the tape 10a. For example, a UV tape is also preferably used as the tape 10a. UV tape is a pressure-sensitive adhesive tape that uses ultraviolet (UV) curable resin as the material for the adhesive layer, and has the property that the adhesive strength of the adhesive layer suddenly weakens when irradiated with ultraviolet light while having strong adhesive strength. doing. A ring 10b is attached to the outer periphery of the main surface of the tape 10a with an adhesive layer of the tape 10a. The ring 10b is a reinforcing member for the tape 10a. From the viewpoint of reinforcement, the ring 10b is preferably formed of a metal such as stainless steel, but may be formed of a plastic material whose thickness is set to have the same degree of hardness as the metal.

  Next, FIGS. 15 to 18 show the state of the wafer 1W during the WSS peeling process 102B4 of the chip dividing process 102B. 15 and 16 are sectional views of the wafer 1W, FIG. 17 is an overall plan view of the main surface of the wafer 1W, and FIG. 18 is a sectional view taken along line X2-X2 of FIG.

  In this step, first, as shown in FIG. 15, the laser beam LB2 emitted from the laser generator 11 is focused on the adhesive layer 3 on the main surface of the wafer 1W via the transparent support substrate 4. Then, scanning is performed from end to end of the main surface of the wafer 1W. The conditions of the laser beam LB2 are, for example, an infrared laser with a wavelength of 1064 nm, output: 20 W, irradiation speed: 2000 mm / s, and spot diameter: f200 μm. Thereby, as shown in FIG. 16, the support substrate 4 is peeled from the main surface of the wafer 1W.

  The adhesive layer 3 may be formed of, for example, an ultraviolet curable resin (UV resin). The UV resin has a strong adhesive force, and has a property that curing is accelerated and the adhesive force is rapidly weakened when irradiated with ultraviolet rays. When a UV resin is used, the laser beam LB2 uses an ultraviolet laser instead of the infrared laser. Thereby, since the adhesive force of the contact bonding layer 3 can be weakened, the support substrate 4 can be peeled easily. Subsequently, as shown in FIGS. 17 and 18, the adhesive layer 3 on the main surface of the wafer 1W is removed.

  Next, FIG. 19 and FIG. 20 show a sectional view of the wafer 1W and an overall plan view of the back surface of the wafer 1W at the time of the dividing step 102B5. Although FIG. 20 is a plan view, hatching is given to the formation region of the adhesive layer 8a for easy viewing of the drawing.

  In this step, as shown in FIG. 19, after placing the jig 10 on which the wafer 1W is placed on the mounting table 12, the mounting table 12 is perpendicular to the main surface of the wafer 1W while the ring 10b of the jig 10 is fixed. Push up in the direction indicated by arrow A. Then, as a result of the tape 10a being stretched in the diameter direction of the wafer 1W (direction indicated by the arrow B), the extending force of the tape 10a causes the modified region PL of the wafer 1W to be divided starting points along the thickness direction of the wafer 1W. Cracks. Thus, the wafer 1W is divided into individual chips (second chips) 1C (stealth dicing). At the same time, the adhesive layer 8a is also broken between the individual chips 1C by dividing the chips 1C. When the DAF material is used as the adhesive layer on the back surface of the chip 1C, the outer periphery of the DAF material on the back surface of the chip 1C extends without being cut when the chip 1C is cut by stealth dicing. The material may not be cut well. On the other hand, in the first embodiment, as described above, the thickness of the adhesive layer 8a is extremely thin compared to the DAF material. Therefore, the adhesive layer 8a is cut well and clean when the chip 1C is divided by stealth dicing. Can do. Therefore, since stealth dicing can be employed, the chip 1C can be made thinner and the semiconductor device can be made thinner. Moreover, since the appearance defect of the chip 1C can be reduced, the yield of the semiconductor device can be improved.

  Further, in the case of the blade dicing method in which the wafer 1W is cut by a dicing blade, chipping tends to occur at the time of cutting when the wafer 1W becomes thin, and the bending strength of the chip is lowered. From the viewpoint of ensuring the quality of the chip 1C. Processing must be performed at low speed (for example, about 60 mm per second or less depending on the thickness of the wafer 1W). On the other hand, in the case of the first embodiment, since only the inside is cleaved without damaging the surface of the wafer 1W, chipping existing on the surface of the chip 1C can be minimized. For this reason, the bending strength of the chip 1 </ b> C can be improved. Further, for example, a high-speed cutting process of 300 mm per second can be performed, so that the throughput can be improved.

  Further, as described above, when the laser beam is irradiated from the main surface side of the wafer 1W to the cutting region CR of the main surface of the wafer 1W, the test pad 1LBt becomes an obstacle and the portion is processed (formation of a modified layer). May not be successful. On the other hand, in the first embodiment, the laser beam LB is irradiated from the back surface side of the wafer 1W where there is no metal such as the test pad 1LBt. The modified region PL can be formed, and the wafer 1W can be cut well.

  Next, FIG. 21 shows a cross-sectional view of the wafer 1W during the pickup process 102C1 of the assembly process 102C. In this step, the jig 10 holding the plurality of chips 1C is transported to the pickup device and placed on the mounting table 15. Subsequently, in a state where the back surface of the tape 10a of the jig 10 is vacuum-sucked, the chip 1C is pushed up from the back surface of the tape 10a by a push-up pin. At this time, when the UV tape is used as the tape 10a, the adhesive layer is cured by irradiating the adhesive layer of the tape 10a with ultraviolet rays to weaken the adhesive force. In this state, the chip 1C is pulled up by vacuum suction with a collet of the pickup device.

  Next, FIG. 22 is a perspective view of the chip 1C and the wiring board 17 at the time of the die bonding process 102C2 of the assembly process 102C, and FIG. 23 is a sectional view of the chip 1C and the wiring board 17 at the time of the process of FIG. In this step, the chip 1C picked up as described above is placed on the main surface of another chip (first chip) 18C mounted on the main surface of the wiring board 17, as shown in FIGS. Transport to. Subsequently, the chip 1C is lowered and placed on the main surface of the chip 18C with the adhesive layer 8a on the back surface of the chip 1C facing the main surface of the chip 18C. Thereafter, when the base material of the adhesive layer 8a is a thermoplastic resin, the adhesive layer 8a on the back surface of the chip 1C is lightly applied to the main surface of the chip 18C in a state where the adhesive layer 8a is heated and softened to have adhesiveness. By pressing, the chip 1C is fixed on the main surface of the chip 18C. The heating temperature at this time is not particularly limited, but is about 400 ° C. On the other hand, when the base material of the adhesive layer 8a is a thermosetting resin, the adhesive layer 8a is heated to be completely cured, and the chip 1C is fixed on the main surface of the chip 18C. In this way, the chips 1C are stacked on the chips 18C.

  As described above, in the first embodiment, not only the thickness of the chip 1C but also the thickness of the adhesive layer 8a on the back surface of the chip 1C can be reduced, so that the stacking height of the chips 1C and 18C is reduced. Can do. Therefore, a semiconductor device having a configuration in which the chips 1C and 18C are stacked can be reduced in thickness. Further, since the adhesive layer 8a is thin, the amount of moisture absorbed can be reduced and the generation of voids can be reduced, so that the reliability of the semiconductor device can be improved. Further, since the adhesive layer 8a is solid, it does not protrude to the outer periphery of the chip 1C when the chip 1C is mounted, and there is a problem that the adhesive layer 8a covers the pad of the lower chip 18C. Does not occur. Even if the chip 1C is thin, the adhesive layer 8a on the back surface of the chip 1C does not roll up to the main surface through the side surface of the chip 1C. Furthermore, the thickness accuracy of the adhesive layer 8a is high, and the upper chip 1C does not tilt. Note that the picked-up chip 1C may be accommodated in a transport tray, transported and shipped to another manufacturing factory (for example, an assembly fab), and assembly after this process may be requested (process 103A in FIG. 1).

  Here, an example of the configuration and mounting method of the wiring board 17 and the chip 18C will be described. The wiring board 17 is made of, for example, a printed wiring board having a multilayer wiring configuration, and has a main surface and a back surface that are opposite to each other in the thickness direction. A chip 18 </ b> C is mounted on the main surface of the wiring board 17. A plurality of electrodes 17a are arranged on the main surface of the wiring board 17 so as to surround the outer periphery of the chip 18C. A plurality of electrodes 17 b are disposed on the back surface of the wiring board 17. The electrode 17 a on the main surface of the wiring board 17 and the electrode 17 b on the back surface are electrically connected through wiring on the inner layer of the wiring board 17. The electrodes 17a and 17b and the wiring of the wiring board 17 are made of, for example, copper. The exposed surfaces of the electrodes 17a and 17b are plated with gold (Au) on a nickel (Ni) base.

  The configuration of the chip 18C is substantially the same as that of the chip 1C. The substrate 18S of the chip 18C is made of, for example, silicon (Si) single crystal, and elements and a wiring layer 18L are formed on the main surface. The configuration of the wiring layer 18L is the same as that of the wiring layer 1L of the chip 1C, and the pad 18LB is disposed on the uppermost layer. The chip 18C is mounted on the main surface of the wiring board 17 with its main surface facing upward and its back surface fixed to the main surface of the wiring substrate 17 by the adhesive layer 20a. The adhesive layer 20a is formed of a thermoplastic resin such as a polyimide resin. The thickness of the adhesive layer 20a is thicker than the adhesive layer 8a on the back surface of the chip 1C, for example, 10 μm or more. The reason is that the adhesive layer 20a absorbs large irregularities due to the wiring and electrodes formed on the main surface of the wiring board 17. If the first-stage semiconductor chip 18C is mounted via the adhesive layer 8a formed by the resin coating method, the thickness of the adhesive layer 8a is as thin as about 5 μm, so that it is formed on the main surface of the wiring board 17. Unevenness cannot be absorbed by the adhesive layer 8a. That is, a gap is generated between the main surface of the wiring board 17 and the adhesive layer 8a, and there may be a problem of a void defect in which the sealing resin is not filled in the subsequent sealing body forming step. On the other hand, the unevenness of the back surface of the chip 1C is, for example, about 1-2 μm (MAX), and the unevenness of the main surface of the chip 18C on which the chip 1C is stacked is, for example, about 1-2 μm (MAX). Since there is no unevenness as much as the main surface of the wiring board 17, there is no problem even if the adhesive layer 8a on the back surface of the chip 1C is thin.

  The mounting method of such a chip 18C is, for example, as follows. First, the wiring substrate 17 is prepared, and a paste-like adhesive is applied to the chip mounting region on the main surface. This paste-like adhesive is formed of a thermoplastic resin such as a polyimide resin. Subsequently, the back surface of the chip 18C is pressed against the paste-like adhesive material to place the chip 18C on the main surface of the wiring substrate 17, and then the paste-like adhesive material is dried to form the solid adhesive layer 20a. . Thereby, the chip 18 </ b> C is fixed to the wiring board 17.

  As shown in FIG. 58, DAF (Die Attach Film) may be used as the material of the adhesive layer 20a. That is, the first-stage semiconductor chip 18C is mounted on the main surface of the wiring substrate 17 via the DAF (adhesive layer 20a), and the second-stage and subsequent semiconductor chips mounted on the main surface of the one-section semiconductor chip are Alternatively, it may be mounted via an adhesive layer 8a formed by a resin coating method. Thereby, since the DAF (adhesive layer 20a) used for the first-stage semiconductor chip 18C is solid, the DAF (adhesion layer 20a) does not protrude from the outer periphery of the semiconductor chip 18C when the semiconductor chip 18C is mounted. That is, since the adhesive (adhesive layer 20a) does not protrude toward the electrode 17a disposed on the main surface of the wiring board, the distance between the semiconductor chip 18C and the electrode 17a can be shortened, and thus the paste-like adhesive The semiconductor device can be downsized as compared with the case of using a material.

  Next, FIG. 24 is a cross-sectional view of the semiconductor device after the wire bonding step 102C3 in the assembly step 102C, and FIG. 25 is a cross-sectional view of the semiconductor device after the sealing step 102C4 in the assembly step 102C.

  First, in the wire bonding step 102C3, as shown in FIG. 24, the pad 1LB of the upper chip 1C and the pad 18LB of the lower chip 18C are connected by a bonding wire (hereinafter referred to as a wire) 21 and the lower chip 18C. The pad 18LB and the electrode 17a of the wiring board 17 are connected by a wire 21. The pad 1LB of the upper chip 1C and the electrode 17a of the wiring board 17 may be connected by a wire 21. The wire 21 is made of, for example, gold (Au). Subsequently, in the sealing step 102C4, as shown in FIG. 25, the chips 1C and 18C, the wires 21 and the like are sealed with a sealing body 22 made of an epoxy resin or the like using, for example, a transfer mold method. Further, solder balls 23 are formed as external terminals on the electrodes 17b. The solder ball 23 is made of, for example, a lead solder material of lead (Pb) -tin (Sn) or a lead-free solder material of, for example, tin (Sn) -silver (Ag) -copper (Cu). A semiconductor device is manufactured as described above.

(Embodiment 2)
In the second embodiment, as in the first embodiment, after the laser irradiation step 102B1 from the previous step 100 in FIG. 1, in the adhesive layer forming step 102B2 of the chip dividing step 102B, the back surface of the wafer is printed by a printing method. An adhesive layer is formed.

  FIG. 26 is a cross-sectional view of the wafer 1W during the adhesive layer forming step 102B2, and FIG. 27 is a plan view of the mask 25A used during the adhesive layer forming step 102B2. Although FIG. 27 is a plan view, the mask 25A is hatched to make the drawing easy to see.

  First, as shown in FIG. 26, a mask 25A is placed on the back surface of the wafer 1W in an aligned state, and then a liquid (paste-like) adhesive material 8 is applied to the wafer 1W from above the mask 25A by the squeegee 26. Stretch along the back side. In the mask 25A, as shown in FIGS. 26 and 27, openings 25A1 having substantially the same planar dimensions as the individual chips 1C are formed at the corresponding positions of the individual chips 1C on the wafer 1W. The back surface of each chip 1C is exposed from the portion 25A1. Further, in the mask 25A, a mask pattern 25A2 is formed at the corresponding position of the cutting region CR (formation region of the modified region PL) between the adjacent chips 1C of the wafer 1W, thereby adjacent to the chip 1C. A portion corresponding to the cutting region CR is covered.

  Next, FIG. 28 is a cross-sectional view of the wafer 1W showing that the liquid adhesive 8 is stretched by the squeegee 26 and selectively applied to the back surface of the wafer 1W through the mask 25A. FIG. 29 is a cross-sectional view of the wafer 1W of FIG. The top view of the back surface side of is shown. Although FIG. 29 is a plan view, hatching is applied to the application region of the adhesive 8 in order to make the drawing easy to see. Further, in FIG. 29, the wafer 1W is shown through in order to make the drawing easy to see.

  As shown in FIGS. 28 and 29, when the squeegee 26 is moved while the adhesive 8 is stretched along the back surface of the wafer 1W, the liquid adhesive 8 enters the opening 25A1 of the mask 25A. Thereby, the adhesive 8 adheres to the back surface of the chip 1C, but does not adhere to the cutting region CR. In this way, the squeegee 26 is moved from end to end of the wafer 1W.

  Next, FIG. 30 is a cross-sectional view of the wafer 1W with the mask 25A removed, and FIG. 31 is a plan view of the back surface of the wafer 1W in FIG. In addition, although FIG. 31 is a top view, in order to make drawing easy to see, the application | coating area | region of the adhesive material 8 (adhesion layer 8b) was hatched.

  After applying the adhesive material 8 to the back surface of the wafer 1W, the mask 25A is removed, and the adhesive material 8 is dried in the same manner as in the first embodiment, so that the region of each chip 1C on the back surface of the wafer 1W is selectively used. A solid adhesive layer 8b is formed. The adhesive layer 8b is not formed in the cutting region CR.

  Next, FIG. 32 is a sectional view of the wafer 1W during the wafer mounting step 102B3 of the chip dividing step 102B, and FIG. 33 is a sectional view of the wafer 1W after the WSS peeling step 102B4.

  In this step, as shown in FIG. 32, the back surface (formation surface of the adhesive layer 8b) of the wafer 1W is attached to the tape 10 of the jig 10 as shown in FIG. In the same manner as in the first embodiment, the support substrate 4 is peeled off, and then the adhesive layer 3 is removed.

  Next, FIGS. 34 and 35 show a sectional view of the wafer 1W and an overall plan view of the back surface of the wafer 1W at the time of the dividing step 102B5. FIG. 35 is a plan view, but hatching is applied to the formation region of the adhesive layer 8b to make the drawing easy to see.

  In this step, as shown in FIGS. 34 and 35, the wafer 1W is divided into individual chips (second chips) 1C using the modified region PL of the wafer 1W as a starting point, as in the first embodiment. Yes (stealth dicing). At this time, in the second embodiment, the adhesive layer 8b is already divided for each chip 1C before the dividing step 102B5, and the adhesive layer 8b is not formed in the cutting region CR. The adhesive layer 8b can be separated cleanly. That is, the chip 1C can be neatly divided by stealth dicing without causing a defect in the outer peripheral portion of the adhesive layer 8b on the back surface of the chip 1C. Accordingly, since stealth dicing can be employed, the semiconductor device can be thinned. Moreover, since the appearance defect of the chip 1C can be reduced, the yield of the semiconductor device can be improved. Other than this, the same effects as those of the first embodiment can be obtained.

  Since the subsequent assembly process 102C is the same as that of the first embodiment, the description thereof is omitted.

(Embodiment 3)
In the first and second embodiments, the case where the adhesive layer is formed on the back surface of the wafer 1W after the laser irradiation process for forming the modified region LB in the chip dividing process has been described. In the third embodiment, a case will be described in which a laser irradiation step for forming the modified region LB is performed after an adhesive layer is formed on the back surface of the wafer 1W in the chip dividing step.

  FIG. 36 shows a flowchart of the semiconductor device of the third embodiment. In the third embodiment, similarly to the first embodiment, after the pre-process 200 and the test process 201 in FIG. 36, the WSS mounting process 202A1, the back-grinding process 202A2 in the back-surface machining process 202A in the post-process 202, and The back surface polishing step 202A3 is sequentially performed.

  Subsequently, in the third embodiment, in the chip dividing process 202B, the adhesive layer forming process 202B1 is performed before performing the laser irradiation process for forming the modified region PL. 37 to 39 show the state of the wafer 1W during the adhesive layer forming step 202B1 of the chip dividing step 202B. FIG. 37 is a sectional view of the wafer 1W, the left side of FIGS. 38 and 39 is a sectional view of the wafer 1W, and the right side is an overall plan view of the back surface of the wafer 1W. Moreover, although the right side of FIG. 38 and FIG. 39 is a top view, in order to make drawing easy to see, the adhesive material 8 (adhesive layer 8a) was hatched.

  Here, as shown in FIG. 37, in the same manner as in the first embodiment, after the liquid (paste-like) adhesive 8 is dropped from the nozzle 7 of the spin coater onto the center on the back surface of the wafer 1W, FIG. As shown in FIG. 2, a thin film of the adhesive 8 is formed on the entire back surface of the wafer 1W by rotating the wafer 1W at a high speed (rotary coating method). Thereafter, as in the first embodiment, the adhesive 8 on the back surface of the wafer 1W is dried to solidify the adhesive 8, and the entire back surface of the wafer 1W is solid as shown in FIG. A thin adhesive layer 8a is formed. Thereby, similarly to the first embodiment, the thin adhesive layer 8a can be formed on the back surface of the wafer 1W so as to have a uniform thickness.

  Next, FIG. 40 is a cross-sectional view of the wafer 1W during the wafer mounting step 202B2 of FIG. 36, FIG. 41 is a cross-sectional view of the wafer 1W during the laser irradiation step 202B3 of FIG. Sectional views of the wafer 1W are shown.

  First, as shown in FIG. 40, as in the first embodiment, the back surface of the wafer 1W (the surface on which the adhesive layer 8a is formed) is attached to the tape 10a of the jig 10, and the wafer 1W is placed on the jig 10. Subsequently, the wafer 1W is transferred to the laser dicing apparatus while being placed on the jig 10, and placed on the suction stage with the main surface of the wafer 1W (ie, the upper surface of the support substrate 4) facing upward. To do. Subsequently, using the IR camera, the pattern on the main surface of the wafer 1W from above the main surface of the wafer 1W (in addition to the pattern of the chip 1C and the cutting region CR, the pad 1LBt, the alignment target Am, and the chip arranged in the cutting region CR) After recognizing the pad 1LB and the like arranged in 1C), alignment (position correction) of the cutting line CL is performed based on the pattern information obtained thereby.

  Thereafter, as shown in FIG. 41, the laser beam LB1 emitted from the laser generating unit 5 installed above the main surface of the wafer 1W is passed through the transparent support substrate 4 from the main surface side of the wafer 1W. Irradiation is performed with the condensing point aligned inside the substrate 1S, and the substrate 1S is moved along the cutting line CL aligned based on the pattern information. Thus, the modified region PL is formed in the substrate 1S in the cutting region CR of the wafer 1W. The scanning method and irradiation conditions of the laser beam LB1 are the same as those described in the first embodiment.

  Thereafter, as shown in FIG. 42, the laser beam LB2 radiated from the laser generator 11 is scanned from end to end of the main surface of the wafer 1W through the transparent support substrate 4, and the main surface of the wafer 1W is scanned. Irradiate the adhesive layer 3. Thereby, the adhesive force of the adhesive layer 3 is reduced, and the support substrate 4 is peeled from the wafer 1W in the same manner as in the first embodiment. Thereafter, as in the first embodiment, the adhesive layer 3 on the main surface of the wafer 1W is removed.

  Subsequent division process 202B5, assembly process 202C (pickup process 202C1, die bonding process 202C2, wire bonding process 202C3, sealing process 202C4) and transfer / shipping process 203A are the same as the processes described in the first embodiment, and thus will be described. Is omitted.

(Embodiment 4)
In the fourth embodiment, as in the third embodiment, after the back surface polishing step 202A3 from the previous step 200 in FIG. To form an adhesive layer.

  FIG. 43 is a cross-sectional view of the wafer 1W during the adhesive layer forming step 202B1, and FIG. 44 shows a state in which the liquid adhesive 8 is stretched by the squeegee 26 and selectively applied to the back surface of the wafer 1W through the mask 25A. 45 is a cross-sectional view of the wafer 1W, and FIG. 45 is a cross-sectional view of the wafer 1W showing a state where the mask 25A is removed.

  First, as shown in FIG. 43, as in the second embodiment, after the mask 25A is placed on the back surface of the wafer 1W in an aligned state, liquid (paste-like) adhesion is performed on the mask 25A. The material 8 is stretched along the back surface of the wafer 1W by the squeegee 26. Then, as shown in FIG. 44, as in the second embodiment, the liquid adhesive 8 enters the opening 25A2 of the mask 25A and adheres to the back surface of the wafer 1W. After the adhesive material 8 is selectively applied to the back surface of the wafer 1W in this way, the mask 25A is removed as in the second embodiment, as shown in FIG. Thereafter, as in the first and second embodiments, the adhesive 8 is dried to selectively form a solid adhesive layer 8b in the region of the chip 1C on the back surface of the wafer 1W. The adhesive layer 8b is not formed in the cutting region CR.

  46 is a sectional view of the wafer 1W during the wafer mounting step 202B2 of the chip dividing step 202B, and FIG. 47 is a sectional view of the wafer 1W during the laser irradiation step 202B3 of FIG.

  First, as shown in FIG. 46, as in the first to third embodiments, the back surface of the wafer 1W (formation surface of the adhesive layer 8b) is attached to the tape 10 of the jig 10, and then the third embodiment. Similarly to the above, the above pattern on the main surface of the wafer 1W is recognized from above the main surface of the wafer 1W using an IR camera. Then, alignment (position correction) of the cutting line CL is performed based on the pattern information obtained thereby. Subsequently, as shown in FIG. 47, similarly to the third embodiment, the laser beam LB1 emitted from the laser generating unit 5 installed above the main surface of the wafer 1W is passed through the transparent support substrate 4. Irradiation from the main surface side of the wafer 1W to the inside of the substrate 1S of the wafer 1W in a state where the condensing points are aligned, is performed along the cutting line CL aligned based on the pattern information. Thus, the modified region PL is formed in the substrate 1S in the cutting region CR of the wafer 1W.

  Thereafter, as in the third embodiment, after the support substrate 4 is peeled from the main surface of the wafer 1W, the adhesive layer 3 on the main surface of the wafer 1W is removed, and the same as in the first to third embodiments. The wafer 1W is divided into individual chips 1C. Since the subsequent steps are the same as those in the third embodiment, description thereof is omitted.

(Embodiment 5)
In the fifth embodiment, a modification example in which an adhesive layer is formed on the back surface of a wafer by a printing method will be described.

  FIG. 48 is a plan view of the mask 25B used in the adhesive layer forming step of the fifth embodiment. In addition, although FIG. 48 is a top view, it hatched in order to make drawing easy to see.

  In the fifth embodiment, the mask pattern of the transfer region D of the mask 25B is a fine mesh pattern. That is, in the transfer area D of the mask 25B, a plurality of openings smaller than the planar dimension of the chip 1C are arranged in the transfer area D in a state adjacent to each other in the vertical and horizontal directions.

  Next, FIG. 49 is a cross-sectional view of the wafer 1W during the adhesive layer forming step 102B2, FIG. 50 is a cross-sectional view of the wafer 1W with the mask 25B removed, and FIG. 51 is a main part of the back surface of the wafer 1W in FIG. Each enlarged plan view is shown. Note that FIG. 51 is a plan view, but the adhesive layer 8b is hatched for easy viewing of the drawing.

  First, as shown in FIG. 49, after covering the mask 25B shown in FIG. 48 on the back surface of the wafer 1W in the same manner as in the second embodiment, a liquid (paste) is applied from above the mask 25B. The adhesive material 8 is stretched along the back surface of the wafer 1W by the squeegee 26 and selectively applied to the back surface of the wafer 1W through the opening 25B1 of the mask 25B. At this time, the adhesive 8 is not applied to the position corresponding to the mask pattern 25B2 of the mask 25B on the back surface of the wafer 1W.

  After the adhesive 8 is selectively applied to the back surface of the wafer 1W in this way, the mask 25B is removed as in the second embodiment, as shown in FIG. After that, as in the first and second embodiments, the adhesive 8 is dried to selectively form a plurality of solid fine adhesive layers 8c on the back surface of the wafer 1W. Here, as shown in FIG. 51, the plane area of the adhesive layer 8c is extremely smaller than the plane area of the chip 1C. For this reason, even if the position of the adhesive layer 8c is slightly shifted in the vertical and horizontal directions from the planned position, the total area of the adhesive layer 8c arranged in the region of the chip 1C is not greatly different. The total adhesive force of the adhesive layer 8c on the back surface of 1C does not drop greatly. Even if the position of the adhesive layer 8c is slightly shifted vertically and horizontally from the planned position and the adhesive layer 8c is disposed in the cutting region CR of the wafer 1W, the individual adhesive layers 8c are fine and isolated. Since they are separated from each other, they do not hinder the cutting of the wafer 1W. Therefore, the planar alignment accuracy between the mask 25B for forming the adhesive layer 8c and the wafer 1W can be relaxed.

  Next, FIG. 52 is a sectional view of the wafer 1W during the wafer mounting step 102B3 of the chip dividing step 102B, FIG. 53 is a sectional view of the wafer 1W after the WSS peeling step 102B4, and FIG. 54 is a sectional view of the wafer 1W during the dividing step 102B5. The figure is shown.

  In this step, as shown in FIG. 52, the back surface (formation surface of the adhesive layer 8c) of the wafer 1W is affixed to the tape 10a of the jig 10 as shown in FIGS. As shown, like the first to fourth embodiments, the support substrate 4 is peeled, and then the adhesive layer 3 is removed. Thereafter, as shown in FIG. 54, similarly to the first to fourth embodiments, the wafer 1W is divided into individual chips 1C using the modified region PL of the wafer 1W as a division starting point (stealth dicing). At this time, in the fifth embodiment, since the adhesive layer 8c is smaller than the chip 1C and separated from each other, the adhesive layer 8c can also be separated cleanly when the chip 1C is cut. Accordingly, since stealth dicing can be employed, the semiconductor device can be thinned. Moreover, since the appearance defect of the chip 1C can be reduced, the yield of the semiconductor device can be improved. Other than this, the same effects as those of the first and second embodiments can be obtained.

  Since the subsequent assembly process 102C is the same as that of the first and second embodiments, description thereof will be omitted. In the fifth embodiment, the flow shown in FIG. 1 is described. However, the method described in the fifth embodiment can be applied to the flow shown in FIG.

(Embodiment 6)
FIG. 55 shows a sectional view of the semiconductor device of the sixth embodiment. In the sixth embodiment, the lower chip 18C is mounted on the main surface of the wiring board 17 via the bump electrodes 30 with the main surface (device forming surface) facing the main surface of the wiring board 17. ing. The integrated circuit of the chip 18 </ b> C is electrically connected to the electrode on the main surface of the wiring substrate 17 through the bump electrode 30 and further electrically connected to the wiring of the wiring substrate 17. The bump electrode 30 is formed of, for example, lead (Pb) -tin (Sn) solder. An underfill 31 is filled between the facing surfaces of the chip 18 </ b> C and the wiring board 17.

  A chip 1C is mounted on the back surface of the chip 18C. The back surface of the chip 1C is bonded to the back surface of the chip 18C through the adhesive layer 8a. The integrated circuit on the main surface of the chip 1C is electrically connected to the electrode 17a of the wiring board 17 through the wire 21 as in the first embodiment. The thickness of the adhesive layer 8a is smaller than the distance between the facing surfaces of the chip 18C and the wiring board 17.

  The mounting method of the lower layer chip 18C is, for example, as follows. First, the chip 18C is transferred to the chip mounting region of the wiring board 17 with its main surface facing downward, and the bump electrode 30 on the main surface of the chip 18C and the electrode on the main surface of the wiring board 17 are used with a paste material. And temporarily fix. Subsequently, the bump electrode 30 of the chip 18C and the electrode of the wiring board 17 are fixed by reflow treatment (heat treatment) (flip chip bonding). Thereafter, an underfill 31 is filled between the facing surfaces of the chip 18C and the wiring board 17. Since the mounting method of the upper layer chip 1C is the same as that of the first embodiment, the description thereof is omitted. The adhesive layer 8a may be the adhesive layers 8b and 8c described in the second, fourth, and fifth embodiments.

(Embodiment 7)
FIG. 56 is a sectional view of the semiconductor device according to the seventh embodiment. In the seventh embodiment, another chip 1C2 (1C) is mounted on the main surface of the chip 1C1 (1C) with the main surface facing upward. The back surface of the uppermost chip 1C2 is bonded to the main surface of the chip 1C1 through the adhesive layer 8a. The integrated circuit on the main surface of the chip 1C2 is electrically connected to the electrode 17a of the wiring board 17 through the wire 21. Since the adhesive layer 8a on the back surface of the chips 1C1 and 1C2 is formed thin, the semiconductor device having the multi-stage configuration of the chips 18C, 1C1 and 1C2 can be thinned. The thickness of the adhesive layer 8a on the back surface of the uppermost chip 1C2 is equal to the thickness of the adhesive layer 8a on the back surface of the chip 1C1 as the intermediate layer. By making the thickness of the adhesive layer 8a on the back surface of each chip 1C1, 1C2 equal, the thickness design of the adhesive layer 8a on the back surface of each chip 1C1, 1C2 can be facilitated.

  Note that the lowermost chip 18C may be bonded onto the main surface of the wiring board 17 by the adhesive layer 20a as in the first embodiment. In this case, the adhesive layer 20a is thicker than the adhesive layer 8a on the back surface of the chips 1C1 and 1C2. The adhesive layer 8a may be the adhesive layers 8b and 8c described in the second, fourth, and fifth embodiments.

(Embodiment 8)
FIG. 57 is a sectional view of the semiconductor device according to the eighth embodiment. The semiconductor device according to the eighth embodiment is a SIP (System In Package) in which a system having a desired function is built in one package. On the main surface of the wiring substrate 17, a plurality of thin chips 18, 1C, 37C are stacked. The lowermost chip 18C is mounted on the main surface of the wiring board 17 via the bump electrodes 30 on the main surface. On the main surface of the chip 18C, a logic circuit such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor) is formed. On the back surface of the chip 18C, the chip 1C is mounted via an adhesive layer 8a. A memory circuit such as an SRAM (Static Random Access Memory) or a flash memory is formed on the main surface of the chip 1C. The pads 1LB on the main surface of the chip 1C are electrically connected to the electrodes 17a on the main surface of the wiring board 17 through the wires 21. A chip 37C is mounted on the main surface of the chip 1C via a spacer 35 and a DAF 36. A memory circuit such as an SRAM or a flash memory is formed on the chip 37C. The pads on the main surface of the chip 37C are electrically connected to the electrodes 17a on the main surface of the wiring board 17 through the wires 21. It is connected. Such chips 18C, 1C, 37C and wires 21 are sealed by a sealing body 22.

  Note that the chip 18C may be bonded onto the main surface of the wiring board 17 by the adhesive layer 20a as in the first embodiment. The adhesive layer 8a may be the adhesive layers 8b and 8c described in the second, fourth, and fifth embodiments.

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above description, the case where the invention made mainly by the present inventor is applied to the method of manufacturing a semiconductor device which is a field of use as the background has been described. However, the present invention is not limited to this and can be applied in various ways. It can also be applied to a micromachine manufacturing method.

  The present invention can be applied to the semiconductor device manufacturing industry.

1W semiconductor wafer 1C semiconductor chip (second chip)
1S Semiconductor substrate 1L Wiring layer 1Li, 1Li1, 1Li2, 1Li3 Interlayer insulating film 1LB Bonding pad 1LBt Bonding pad 1Lp for test Surface protective film 2 Opening 3 Adhesive layer 4 Support substrate 4a Peeling layer 5 Laser generating part 7 Nozzle 8 Adhesive 8a, 8b, 8c Adhesive layer 10 Jig 10a Tape 10b Ring 11 Laser generator 12 Mounting table 15 Mounting table 17 Wiring boards 17a, 17b Electrode 18C Semiconductor chip (first chip)
18S Semiconductor substrate 18L Wiring layer 18LB Bonding pad 20a Adhesive layer 21 Bonding wire 22 Sealing body 23 Solder balls 25A, 25B Masks 25A1, 25B1 Openings 25A2, 25B2 Mask pattern 26 Squeegee 30 Bump electrode 31 Underfill 35 Spacer 36 DAF
37C Semiconductor chip CR Cutting region CL Cutting line Am Alignment target LB1 Laser beam LB2 Laser beam PL Modified region

Claims (5)

A wiring board having an upper surface, a plurality of wirings formed on the upper surface, a plurality of first electrodes formed on the upper surface, a lower surface opposite to the upper surface, and a plurality of second electrodes formed on the lower surface; ,
First surface, the first located between the plurality of first bonding pads formed on the first surface, before Symbol first back surface opposite to the first surface, and the first back surface and said first surface The plurality of wirings of the wiring board having one side surface, the first back surface facing the top surface of the wiring board , and the plurality of first electrodes of the wiring board not being covered. A first semiconductor chip mounted on the upper surface of the wiring board via a first adhesive layer so as to be covered ,
A second surface, the first located between the plurality of second bonding pads formed on the second surface, before Symbol second back surface opposite to the second surface, and the second back surface and the second surface has two sides, so that the second rear surface so as to face the first surface of the first semiconductor chip, and is not covered said plurality of first bonding pads of the first semiconductor chip, and wherein A second semiconductor chip mounted on the first surface of the first semiconductor chip via a second adhesive layer so as to be positioned between the plurality of first bonding pads of the first semiconductor chip;
A plurality of first wires that respectively electrically connect the plurality of first bonding pads of the first semiconductor chip and the plurality of first electrodes of the wiring board;
A sealing member for sealing the first semiconductor chip, before Symbol second semiconductor chip and the plurality of first wires,
A plurality of external terminals formed on the plurality of second electrodes;
Including
A portion of the first side surface of the first semiconductor chip is covered with the first adhesive layer;
The second side surface of the second semiconductor chip is not covered with the second adhesive layer,
The thickness of the portion of the second adhesive layer that overlaps with the second semiconductor chip in a plane is thinner than the thickness of the portion of the first adhesive layer that overlaps with the first semiconductor chip in a plane. A featured semiconductor device. In claim 1,
The roughness of the upper surface of the wiring board is larger than the roughness of the first surface of the first semiconductor chip,
The semiconductor device according to claim 1 , wherein a roughness of the first surface of the first semiconductor chip is smaller than a thickness of a portion of the second adhesive layer that overlaps the second semiconductor chip in a planar manner. In claim 2,
The first adhesive layer has a film substrate,
The semiconductor device, wherein the second adhesive layer does not have the film substrate. In claim 3,
The semiconductor device according to claim 1, wherein the second adhesive layer is formed by a spin coating method. In claim 1,
The plurality of second bonding pads of the second semiconductor chip are electrically connected to the plurality of first bonding pads of the first semiconductor chip through a plurality of second wires, respectively. Semiconductor device.

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