JP5274857B2 - Capacitor structure - Google Patents

Abstract

The capacitor structure includes a first electrode having a plurality of teeth protruding in a comb shape from an electrode base of a first electrode line and a second electrode having a plurality of teeth protruding in a comb shape from an electrode base of a second electrode line, both formed in a first wiring layer. The first and second electrodes face each other with their teeth interdigitated with each other via a dielectric. At least one of the teeth of the first electrode is electrically connected with a third electrode line formed in a second wiring layer.

Description

  The present invention relates to a capacitor structure formed in an integrated circuit on a semiconductor substrate.

As a conventional example of a capacitor structure formed in an integrated circuit on a semiconductor substrate, a pair of counter electrodes formed in a comb shape is arranged in a so-called interdigitation in which comb-shaped teeth portions are meshed with each other. There is a configuration one. According to this capacitor structure, a capacitance is formed between the tooth portions. That is, the surface area of the counter electrode can be increased, and a capacitor having the same area and a large capacity can be obtained as compared with a simple parallel plate capacitor (see, for example, Patent Document 1).
JP-A-4-268756 (page 3, FIG. 1)

  However, in the conventional capacitor structure described above, a capacitance is formed not at the main wiring of the electrode but at the tooth portion of the comb-shaped electrode. It will end up. For this reason, when using for the purpose of noise removal between two electrodes like a bypass capacitor, a noise attenuation characteristic may not be enough with respect to a high frequency area | region, for example. Therefore, with the miniaturization and speeding up of integrated circuits, it is necessary to improve capacitor characteristics.

  In view of the above problems, an object of the present invention is to provide a capacitor structure having an area comparable to that of the prior art, a smaller parasitic inductance component and parasitic resistance component than those of the prior art, and having good high frequency characteristics.

According to the present invention, as a capacitor structure formed on a semiconductor substrate, a plurality of first and second electrode wirings formed in a first wiring layer and a plurality of comb-shaped protrusions projecting from an electrode base of the first electrode wiring A first electrode having a plurality of teeth, and a second electrode having a plurality of teeth protruding in a comb shape from the electrode base of the second electrode wiring, the first electrode and the second electrode The electrodes are opposed to each other in a state where the tooth portions are engaged with each other via a dielectric, and at least one of the tooth portions is different from the first wiring layer. The third electrode wiring is electrically connected to a third electrode wiring formed in the second wiring layer, and the third electrode wiring is at least one of a plurality of tooth portions of the second electrode in plan view. It extends across the, butt comb shape from the electrode base of the third electrode wire Having a plurality of teeth that includes a third electrode, the second electrode, wherein at least one of the teeth, and the teeth of the third electrode are opposed.

According to the capacitor structure of the present invention, the comb-shaped first electrode provided in the first electrode wiring in the first wiring layer has at least one of the tooth portions different from the first wiring layer. The second electrode layer is electrically connected to the third electrode wiring. Therefore, in the first electrode, a capacitor is formed on a path through which a current flows from the first electrode wiring to the third electrode wiring. Thus, compared with the conventional capacitor structure, Ru can be reduced parasitic inductance and parasitic resistance component.

  According to the present invention, since the capacitor is formed on the path through which the current flows in the electrode, the parasitic inductance component and the parasitic resistance component can be made smaller than those of the conventional capacitor structure. Therefore, compared to the conventional configuration, the deterioration of characteristics due to parasitic inductance components and parasitic resistance components can be suppressed and the high-frequency characteristics can be greatly improved with the same area. Thereby, for example, a capacitor having a high noise bypass effect in a high frequency region can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Each embodiment shown below shows one mode of the present invention, does not limit the present invention, and can be arbitrarily combined and changed within the scope of the present invention.

(Embodiment 1)
FIG. 1 is a top view showing a capacitor structure formed in an integrated circuit on a semiconductor substrate according to Embodiment 1 of the present invention. In FIG. 1, 11 and 21 are the 1st and 2nd electrode wiring formed in the upper wiring layer as a 1st wiring layer. A first electrode 16 is formed on the first electrode wiring 11. The first electrode 16 has a plurality (five in FIG. 1) of tooth portions 15 protruding in a comb shape from the electrode base portion 14 of the first electrode wiring 11. A second electrode 26 is formed on the second electrode wiring 21. The second electrode 26 has a plurality of (five in FIG. 1) tooth portions 25 protruding in a comb shape from the electrode base portion 24 of the second electrode wiring 21. The first electrode 16 and the second electrode 26 are opposed to each other with the tooth portions 15 and 25 meshing with each other via a dielectric. That is, the first electrode 16 and the second electrode 26 are in a so-called interdigitation arrangement.

  In addition, the tip of each tooth portion 15 of the first electrode 16 is connected to the third electrode wiring 12 formed in the lower wiring layer as the second wiring layer different from the first wiring layer, and the via 13. Are electrically connected. The tip of each tooth portion 25 of the second electrode 26 is electrically connected to the fourth electrode wiring 22 formed in the lower wiring layer via the via 23.

  According to the capacitor structure according to the present embodiment configured as shown in FIG. 1, since the opposing first and second electrodes 16 and 26 are arranged in an interdigitation, the surface area of the opposing electrode is increased, Compared to a simple parallel plate capacitor, a capacitor having the same area and a large capacity can be obtained. Furthermore, since the tips of the tooth portions 15 and 25 of the first and second electrodes 16 and 26 are electrically connected to the third and fourth electrode wirings 12 and 22 of the lower wiring layer, On the path through which current flows in the first and second electrodes 16 and 26 (from the first electrode wiring 11 to the third electrode wiring 12 and from the second electrode wiring 21 to the fourth electrode wiring 22), a capacitor Will be formed. Thereby, the parasitic inductance component and the parasitic resistance component of the capacitor can be reduced.

  Therefore, according to the present embodiment, it is possible to realize a capacitor having a large capacity and less characteristic deterioration due to a parasitic inductance component and a parasitic resistance component in a space equivalent to that of a conventional capacitor.

  In the configuration of FIG. 1, the tip portion of each of the tooth portions of the opposing electrode is electrically connected to the electrode wiring of the lower wiring layer, but the present invention is not limited to this, and at least It is sufficient that one tooth portion is electrically connected to the electrode wiring of the lower wiring layer. Even with this configuration, it is possible to make the parasitic inductance component and parasitic resistance component of the capacitor smaller than in the past. In addition, a portion other than the tip portion of the tooth portion of the opposing electrode may be electrically connected to the electrode wiring of the lower wiring layer. However, in order to obtain better capacitor characteristics, a configuration in which the tip of each tooth portion of the electrode is electrically connected to the electrode wiring as shown in FIG. 1 is preferable.

  Moreover, it is good also as a structure which electrically connects a tooth | gear part with the electrode wiring of a lower wiring layer about any one of the electrodes which oppose, for example, only the 1st electrode 16. For example, this configuration may be adopted when the second electrode 26 is grounded.

  In the configuration of FIG. 1, the first and second electrodes 16 and 26 are formed in the upper wiring layer, and the third and fourth electrode wirings 12 and 22 are formed in the lower wiring layer. However, the hierarchical relationship of the formed wiring layers is not limited to this. For example, the third and fourth electrode wirings 12 and 22 may be formed in the wiring layer above the wiring layer on which the first and second electrodes 16 and 26 are formed. One or more wiring layers are sandwiched between the wiring layer in which the first and second electrodes 16 and 26 are formed and the wiring layer in which the third and fourth electrode wirings 12 and 22 are formed. It does not matter.

(Embodiment 2)
FIG. 2 is a top view showing a capacitor structure formed in an integrated circuit on a semiconductor substrate according to the second embodiment of the present invention. The capacitor structure shown in FIG. 2 has a configuration in which the comb-shaped electrode in the capacitor structure according to the first embodiment shown in FIG. 1 is replaced with a spiral electrode.

  In FIG. 2, 31 and 41 are the 1st and 2nd electrode wiring formed in the upper wiring layer as a 1st wiring layer. A first electrode 36 is formed on the first electrode wiring 31. The first electrode 36 has a spiral portion 35 extending from the first electrode wiring 31. A second electrode 46 is formed on the second electrode wiring 41. The second electrode 46 has a spiral portion 45 extending from the second electrode wiring 41. The first electrode 36 and the second electrode 46 face each other in a state where the spiral portions 35 and 45 are intertwined with each other via a dielectric.

  In addition, the tip of the spiral portion 35 of the first electrode 36, that is, the central portion of the spiral is a third electrode wiring 32 formed in a lower wiring layer as a second wiring layer different from the first wiring layer. Are electrically connected through vias 33. The tip of the spiral portion 45 of the second electrode 46, that is, the central portion of the spiral is electrically connected to the fourth electrode wiring 42 formed in the lower wiring layer via the via 43.

  According to the capacitor structure according to the present embodiment configured as shown in FIG. 2, the opposing first and second electrodes 36 and 46 have a configuration in which the spiral portions 35 and 45 are entangled with each other. The surface area of the electrode is increased, and a capacitor having the same area and a large capacity can be obtained as compared with a simple parallel plate capacitor. Furthermore, since the tips of the spiral portions 35 and 45 of the first and second electrodes 36 and 46 are electrically connected to the third and fourth electrode wirings 32 and 42 of the lower wiring layer, the first In addition, a capacitor is formed on a path through which current flows in the second electrodes 36 and 46 (from the first electrode wiring 31 to the third electrode wiring 32 and from the second electrode wiring 41 to the fourth electrode wiring 42). Will be. Thereby, the parasitic inductance component and the parasitic resistance component of the capacitor can be reduced.

  Therefore, according to the present embodiment, as in the first embodiment, a capacitor having a large capacity and less characteristic deterioration due to a parasitic inductance component and a parasitic resistance component can be realized in the same space as the conventional capacitor. Can do.

  In the configuration of FIG. 2, the tip of the spiral portion of the opposing electrode is electrically connected to the electrode wiring of the lower wiring layer, but the present invention is not limited to this, and the opposing electrode A portion other than the tip of the spiral portion may be electrically connected to the electrode wiring of the lower wiring layer. However, in order to obtain better capacitor characteristics, a configuration in which the tip of the spiral portion of the electrode is electrically connected to the electrode wiring as shown in FIG.

  Moreover, it is good also as a structure which electrically connects a spiral part with the electrode wiring of a lower wiring layer about any one of the electrodes which oppose, for example, only the 1st electrode 36. FIG. For example, this configuration may be employed when the second electrode 46 is grounded.

  In the configuration of FIG. 2, the first and second electrodes 36 and 46 are formed in the upper wiring layer, and the third and fourth electrode wirings 32 and 42 are formed in the lower wiring layer. However, the hierarchical relationship of the formed wiring layers is not limited to this. For example, the third and fourth electrode wirings 32 and 42 may be formed in the wiring layer above the wiring layer on which the first and second electrodes 36 and 46 are formed. Further, one or more wiring layers are sandwiched between the wiring layer in which the first and second electrodes 36 and 46 are formed and the wiring layer in which the third and fourth electrode wirings 32 and 42 are formed. It does not matter.

(Embodiment 3)
FIG. 3 is a top view showing a capacitor structure formed in an integrated circuit on a semiconductor substrate according to the third embodiment of the present invention, in which (a) is a planar structure in an upper wiring layer, (b ) Shows a planar structure in the lower wiring layer. 4 is a cross-sectional view taken along line AA ′ of FIG.

  The capacitor structure shown in FIGS. 3 and 4 is based on the capacitor structure shown in FIG. 1 and is configured such that a capacitor is formed with electrodes facing each other in the lower wiring layer and between the upper and lower wiring layers. is there.

  As shown in FIG. 3, in the upper wiring layer, the first electrode 16 having a plurality of teeth 15 protruding in a comb shape from the electrode base 14 of the first electrode wiring 11, and the electrode of the second electrode wiring 21 A second electrode 26 having a plurality of tooth portions 25 protruding in a comb shape from the base portion 24 is formed. The tip of each tooth portion 15 of the first electrode 16 is electrically connected to the third electrode wiring 12 formed in the lower wiring layer via the via 13, and the second electrode 26. The tip of each tooth portion 25 is electrically connected to the fourth electrode wiring 22 formed in the lower wiring layer via the via 23. The above configuration is the same as the capacitor structure of FIG.

  In the lower wiring layer, the third electrode wiring 12 is formed with a third electrode 19 having a plurality of teeth 18 protruding from the electrode base 17 in a comb shape. A fourth electrode 29 having a plurality of teeth 28 protruding in a comb shape from the electrode base 27 is formed on the fourth electrode wiring 22. The third electrode 19 and the fourth electrode 29 are opposed to each other with the tooth portions 18 and 28 meshing with each other via a dielectric. That is, the third electrode 19 and the fourth electrode 29 are in a so-called interdigitation arrangement.

  The first electrode 16 in the upper wiring layer and the third electrode 19 in the lower wiring layer are electrically connected via the via 13, and the second electrode 26 in the upper wiring layer and the lower wiring layer are connected. The fourth electrode 29 is electrically connected via the via 23.

  4, 51 is a semiconductor substrate, 52 is an interlayer insulating film, 53 is a lower wiring layer, and 54 is an upper wiring layer. As shown in FIG. 4, the tooth portion 25 of the second electrode 26 formed in the upper wiring layer 54 is opposed to the tooth portion 18 of the third electrode 19 formed in the lower wiring layer 53. The teeth 15 of the first electrode 16 formed in the upper wiring layer 54 are opposed to the teeth 28 of the fourth electrode 29 formed in the lower wiring layer 53.

  According to the capacitor structure according to the present embodiment configured as shown in FIGS. 3 and 4, the capacitor structure of FIG. 1 is the basic configuration, and therefore the same operational effects as those of the first embodiment can be obtained. Further, since the electrodes are opposed not only in the upper wiring layer but also in the lower wiring layer and the upper and lower wiring layers, in addition to the capacitance C1 of the counter electrode in the upper wiring layer, the counter electrode in the lower wiring layer Capacitor C2 and counter electrode capacitor C3 between the upper and lower wiring layers. Therefore, the capacitor structure according to the present embodiment can hold a capacitance of (C1 + C2 + C3), and a capacitor with a larger capacity can be formed on the current path in the electrode than in the first embodiment. Become.

  Note that a configuration in which any one of the opposing electrodes in the lower wiring layer is omitted, for example, a configuration in which the fourth electrode 29 is omitted and only the third electrode 19 is formed may be employed. In this case, no capacitance is formed in the lower wiring layer, but the second electrode 26 and the third electrode 19 face each other between the upper and lower wiring layers, and a capacitance is formed. In this case, the fourth electrode wiring 22 may be omitted.

  3 and 4, the teeth of the lower wiring layer are opposed to the teeth of the electrodes of the upper wiring layer. However, the present invention is not limited to this, and the upper wiring The teeth of the lower wiring layer only need to face each other with respect to at least one tooth of the electrode of the layer.

(Embodiment 4)
FIG. 5 is a top view showing a capacitor structure formed in an integrated circuit on a semiconductor substrate according to Embodiment 4 of the present invention, in which (a) is a planar structure in an upper wiring layer, (b) ) Shows a planar structure in the lower wiring layer. FIG. 6 is a cross-sectional view taken along line BB ′ of FIG.

  The capacitor structure shown in FIGS. 5 and 6 is based on the capacitor structure shown in FIG. 2 and is configured such that a capacitor is formed with electrodes facing each other in the lower wiring layer and between the upper and lower wiring layers. is there.

  As shown in FIG. 5, in the upper wiring layer, a second electrode having a first electrode 36 having a spiral portion 35 extending from the first electrode wiring 31 and a spiral portion 45 extending from the second electrode wiring 41. An electrode 46 is formed. The tip of the spiral portion 35 of the first electrode 36 is electrically connected to the third electrode wiring 32 formed in the lower wiring layer via the via 33, and the second electrode 46 The tip of the spiral portion 45 is electrically connected to the fourth electrode wiring 42 formed in the lower wiring layer through the via 43. The above configuration is the same as the capacitor structure of FIG.

  In the lower wiring layer, the third electrode 39 having a plurality of protruding portions 38 protruding from the electrode base portion 37 is formed on the third electrode wiring 32. A fourth electrode 49 having a plurality of protrusions 48 protruding from the electrode base 47 is formed on the fourth electrode wiring 42. The third electrode 39 and the fourth electrode 49 are opposed to each other in a state where the protrusions 38 and 48 are engaged with each other via a dielectric.

  The first electrode 36 in the upper wiring layer and the third electrode 39 in the lower wiring layer are electrically connected via the via 33, and the second electrode 46 in the upper wiring layer and the lower wiring layer are connected. The fourth electrode 49 is electrically connected via the via 43.

  In the cross-sectional view of FIG. 6, 61 is a semiconductor substrate, 62 is an interlayer insulating film, 63 is a lower wiring layer, and 64 is an upper wiring layer. As shown in FIG. 6, the spiral portion 35 of the first electrode 36 formed in the upper wiring layer 64 faces the protruding portion 48 of the fourth electrode 49 formed in the lower wiring layer 63, The spiral portion 45 of the second electrode 46 formed in the upper wiring layer 64 faces the protruding portion 38 of the third electrode 39 formed in the lower wiring layer 63.

  The capacitor structure according to the present embodiment configured as shown in FIGS. 5 and 6 is based on the capacitor structure of FIG. 2, so that the same operational effects as those of the second embodiment can be obtained. Furthermore, since the electrodes are opposed not only in the upper wiring layer but also in the lower wiring layer and the upper and lower wiring layers, in addition to the capacitance C1a of the counter electrode in the upper wiring layer, the counter electrode in the lower wiring layer Capacitor C2a and a counter electrode capacitor C3a between the upper and lower wiring layers. Therefore, the capacitor structure according to the present embodiment can hold a capacitance of (C1a + C2a + C3a), and a capacitor with a larger capacity can be formed on the current path in the electrode than in the second embodiment. Become.

  Note that a configuration in which one of the opposing electrodes in the lower wiring layer is omitted, for example, a configuration in which the fourth electrode 49 is omitted and only the third electrode 39 is formed may be employed. In this case, no capacitance is formed in the lower wiring layer, but the second electrode 46 and the third electrode 39 face each other between the upper and lower wiring layers, and a capacitance is formed. Further, in this case, the fourth electrode wiring 42 may be omitted.

  5 and FIG. 6, the protruding portion of the lower wiring layer is opposed to almost the entire spiral portion of the electrode of the upper wiring layer, but the present invention is not limited to this, The protrusion part of the lower wiring layer should just oppose about at least one part of a spiral part.

(Embodiment 5)
In the fifth embodiment of the present invention, vias are formed above or below the tooth portions 15 and 25 of the first and second electrodes 16 and 26 in the capacitor structure of the first embodiment. Alternatively, in the capacitor structure of the second embodiment, vias are formed above or below the spiral portions 35 and 45 of the first and second electrodes 36 and 46.

  FIG. 7 is a cross-sectional view of the capacitor structure according to the present embodiment, and the top view is the same as FIG. As shown in FIG. 7, vias 77 are formed under the teeth 15 of the first electrode 16, and vias 78 are formed under the teeth 25 of the second electrode 26.

  According to the capacitor structure according to this embodiment shown in FIG. 7, not only the counter electrode in the upper wiring layer, but also the capacitance is formed between the vias arranged therebelow. Therefore, a capacitor with a larger capacity can be formed on the current path in the electrode than in the first or second embodiment.

(Embodiment 6)
FIG. 8 is a top view showing a capacitor structure formed in an integrated circuit on a semiconductor substrate according to Embodiment 6 of the present invention, in which (a) is a planar structure in an upper wiring layer, (b) ) Shows a planar structure in the lower wiring layer. FIG. 9 is a cross-sectional view taken along line CC ′ of FIG.

  The capacitor structures of FIGS. 8 and 9 are based on the capacitor structure of FIG. 1 and are configured such that a capacitor is formed with electrodes and vias facing each other even in the lower wiring layer.

  As shown in FIG. 8, in the upper wiring layer, the first electrode 16 having a plurality of teeth 15 protruding in a comb shape from the electrode base 14 of the first electrode wiring 11, and the electrode of the second electrode wiring 21 A second electrode 26 having a plurality of tooth portions 25 protruding in a comb shape from the base portion 24 is formed. The tip of each tooth portion 15 of the first electrode 16 is electrically connected to the third electrode wiring 12 formed in the lower wiring layer via the via 13, and the second electrode 26. The tip of each tooth portion 25 is electrically connected to the fourth electrode wiring 22 formed in the lower wiring layer via the via 23. The above configuration is the same as the capacitor structure of FIG.

  In the lower wiring layer, the third electrode 83 having a plurality of teeth 82 protruding in a comb shape from the electrode base 81 is formed on the third electrode wiring 12. In addition, a fourth electrode 86 having a plurality of teeth 85 protruding in a comb shape from the electrode base 84 is formed on the fourth electrode wiring 22. The third electrode 83 and the fourth electrode 86 are opposed to each other with the tooth portions 82 and 85 meshing with each other via a dielectric. That is, the third electrode 83 and the fourth electrode 86 are in a so-called interdigitation arrangement.

  A via 87 is formed to electrically connect each tooth portion 15 of the first electrode 16 of the upper wiring layer and each tooth portion 82 of the third electrode 83 of the lower wiring layer. In addition, a via 88 is formed to electrically connect each tooth portion 25 of the second electrode 26 in the upper wiring layer and each tooth portion 85 of the fourth electrode 86 in the lower wiring layer.

  9, 51 is a semiconductor substrate, 52 is an interlayer insulating film, 53 is a lower wiring layer, and 54 is an upper wiring layer. As shown in FIG. 9, the teeth 25 of the second electrode 26 formed in the upper wiring layer 54 are connected to the teeth 85 of the fourth electrode 86 formed in the lower wiring layer 53 and vias 88. The tooth portion 15 of the first electrode 16 formed in the upper wiring layer 54 is connected to the tooth portion 82 of the third electrode 83 formed in the lower wiring layer 53 and the via 87. Is electrically connected.

  According to the capacitor structure according to the present embodiment configured as shown in FIGS. 8 and 9, the capacitor structure of FIG. 1 is used as a basic configuration, so that the same operational effects as those of the first embodiment can be obtained. Furthermore, since the electrodes and vias face each other not only in the upper wiring layer but also in the lower wiring layer, the capacitance C4 of the counter electrode in the lower wiring layer in addition to the capacitance C1 of the counter electrode in the upper wiring layer. And the capacitor C5 of the opposing via is formed. Therefore, the capacitor structure according to the present embodiment can hold a capacitance of (C1 + C4 + C5), and a capacitor having a larger capacity than that of the first embodiment can be formed on the current path in the electrode. Become.

  8 and 9, the vias for connecting the teeth of the upper wiring layer to the teeth of the lower wiring layer are provided, but the present invention is limited to this. Instead, it is sufficient that at least one tooth portion is connected to the tooth portion of the lower wiring layer via a via.

(Embodiment 7)
FIG. 10 is a top view showing a capacitor structure formed in an integrated circuit on a semiconductor substrate according to the seventh embodiment of the present invention, in which (a) is a planar structure in an upper wiring layer, (b) ) Shows a planar structure in the lower wiring layer. FIG. 11 is a cross-sectional view taken along line DD ′ of FIG.

  The capacitor structure shown in FIGS. 10 and 11 is based on the capacitor structure shown in FIG. 2 and is configured such that a capacitor is formed with electrodes and vias facing each other even in the lower wiring layer.

  As shown in FIG. 10, in the upper wiring layer, a second electrode having a first electrode 36 having a spiral portion 35 extending from the first electrode wiring 31 and a spiral portion 45 extending from a second electrode wiring 41 is provided. An electrode 46 is formed. The tip of the spiral portion 35 of the first electrode 36 is electrically connected to the third electrode wiring 32 formed in the lower wiring layer via the via 33, and the second electrode 46 The tip of the spiral portion 45 is electrically connected to the fourth electrode wiring 42 formed in the lower wiring layer through the via 43. The above configuration is the same as the capacitor structure of FIG.

  In the lower wiring layer, a third electrode 93 having a plurality of protruding portions 92 protruding from the electrode base 91 is formed on the third electrode wiring 32. A fourth electrode 96 having a plurality of protruding portions 95 protruding from the electrode base portion 94 is formed on the fourth electrode wiring 42. The third electrode 93 and the fourth electrode 96 are opposed to each other in a state where the protruding portions 92 and 95 are engaged with each other via a dielectric.

  A via 97 is formed to electrically connect the spiral portion 35 of the first electrode 36 in the upper wiring layer and the protruding portion 92 of the third electrode 93 in the lower wiring layer. A via 98 is formed to electrically connect the spiral portion 45 of the second electrode 46 in the upper wiring layer and the protruding portion 95 of the fourth electrode 96 in the lower wiring layer.

  In the cross-sectional view of FIG. 11, 61 is a semiconductor substrate, 62 is an interlayer insulating film, 63 is a lower wiring layer, and 64 is an upper wiring layer. As shown in FIG. 11, the spiral portion 35 of the first electrode 36 formed in the upper wiring layer 64 passes through the protruding portion 92 of the third electrode 93 formed in the lower wiring layer 63 and the via 97. The spiral portion 45 of the second electrode 46 formed in the upper wiring layer 64 is connected to the protruding portion 95 of the fourth electrode 96 formed in the lower wiring layer 63 and the via 98. Is electrically connected.

  According to the capacitor structure according to the present embodiment configured as shown in FIGS. 10 and 11, the capacitor structure of FIG. 2 is a basic configuration, and therefore the same operational effects as those of the second embodiment can be obtained. Furthermore, since the electrodes and vias face each other not only in the upper wiring layer but also in the lower wiring layer, in addition to the capacitance C1a of the counter electrode in the upper wiring layer, the capacitance C4a of the counter electrode in the lower wiring layer. In addition, a capacitance C5a of the opposing via is formed. Therefore, the capacitor structure according to the present embodiment can maintain a capacitance of (C1a + C4a + C5a), and a capacitor with a larger capacity can be formed on the current path in the electrode than in the second embodiment. Become.

(Embodiment 8)
FIG. 12 is a top view showing a capacitor structure formed in an integrated circuit on a semiconductor substrate according to the eighth embodiment of the present invention. In FIG. 12, reference numerals 101 and 201 denote first and second electrode wirings formed in the upper wiring layer as the first wiring layer. A first electrode 110 is formed on the first electrode wiring 101. The first electrode 110 has a plurality of tooth portions 105, 106, 107, 108, and 109 protruding in a comb shape from the electrode base portion 104 of the first electrode wiring 101. A second electrode 210 is formed on the second electrode wiring 201. The second electrode 210 has a plurality of teeth 205, 206, 207, 208, and 209 protruding in a comb shape from the electrode base 204 of the second electrode wiring 201. The first electrode 110 and the second electrode 210 are opposed to each other with the tooth portions 105 to 109 and 205 to 209 meshing with each other via a dielectric. That is, the first electrode 110 and the second electrode 210 are in a so-called interdigitation arrangement.

  Further, the tip portions of the tooth portions 105 to 109 of the first electrode 110 are provided with a third electrode wiring 102 formed in a lower wiring layer as a second wiring layer different from the first wiring layer, and a via 103. Is electrically connected. The tip portions of the tooth portions 205 to 209 of the second electrode 210 are electrically connected to the fourth electrode wiring 202 formed in the lower wiring layer through vias.

  When the capacitor structure of FIG. 12 is compared with FIG. 1, the position of the base end where the electrode wiring extends from the comb-shaped electrode is different. That is, when the comb-shaped electrode is regarded as a rectangle, in the capacitor structure of FIG. 1, the electrode wiring extends from the diagonal position of this rectangle, whereas in the capacitor structure of FIG. An electrode wiring extends from the center of the electrode.

  In the capacitor structure of FIG. 12, the wiring widths of the tooth portions 105 to 109 of the first electrode 110 are not constant but are different. Specifically, the wiring width of each tooth portion 105 to 109 becomes thicker as the distance between the proximal end of the tooth portion and the proximal end of the electrode base portion 104 of the first electrode wiring 101 is longer. That is, the wiring width of the tooth portion 107 closest to the base end of the first electrode wiring 101 is the narrowest, and the wiring width of the tooth portions 105 and 109 farthest from the base end of the first electrode wiring 101 is the widest. It has become. Similarly, the wiring widths of the tooth portions 205 to 209 of the second electrode 210 are also different.

  Thus, by adjusting the wiring width of each tooth portion, the resistance values of all the paths from the entrance to the exit of the comb-shaped electrode can be made substantially constant. As a result, the current flowing through each path of the comb-shaped electrode can be made substantially equal, which is effective as a countermeasure against migration.

  FIG. 12 shows a structure in which the electrode wiring extends from the center part of the opposing sides of the rectangle formed by the comb-shaped electrode. However, the position of the base end from which the electrode wiring extends is limited to that shown in FIG. Instead, it may be set at an arbitrary position. In that case, according to the position of the base end from which the electrode wiring extends, the wiring width of each tooth portion may be adjusted so that the resistance value of all the paths from the entrance to the exit of the comb-shaped electrode becomes substantially constant. . That is, if the resistance value is desired to be increased, the wiring width may be narrowed, and if the resistance value is desired to be decreased, the wiring width may be increased.

  As described above, according to the present embodiment, even when the position of the base end where the electrode wiring extends in the comb-shaped electrode is arbitrarily arranged in accordance with the layout of the integrated circuit, the countermeasure against electromigration can be easily performed, and As with the capacitor structure of the first embodiment, a capacitor having a large capacity and little characteristic deterioration can be realized.

  In the present invention, a capacitor having good high-frequency characteristics can be provided, so that, for example, a noise bypass effect in a high-frequency region can be improved. For this reason, it is useful as a noise removal application of a wide frequency such as a bypass capacitor.

It is a top view which shows the capacitor structure which concerns on Embodiment 1 of this invention. It is a top view which shows the capacitor structure which concerns on Embodiment 2 of this invention. It is a top view which shows the capacitor structure which concerns on Embodiment 3 of this invention, (a) is a planar structure in an upper wiring layer, (b) is a planar structure in a lower wiring layer. It is sectional drawing which shows the capacitor structure which concerns on Embodiment 3 of this invention. It is a top view which shows the capacitor structure which concerns on Embodiment 4 of this invention, (a) shows the planar structure in an upper wiring layer, (b) shows the planar structure in a lower wiring layer. It is sectional drawing which shows the capacitor structure which concerns on Embodiment 4 of this invention. It is sectional drawing which shows the capacitor structure which concerns on Embodiment 5 of this invention. It is a top view which shows the capacitor structure which concerns on Embodiment 6 of this invention, (a) is a planar structure in an upper wiring layer, (b) is a planar structure in a lower wiring layer. It is sectional drawing which shows the capacitor structure which concerns on Embodiment 6 of this invention. It is a top view which shows the capacitor structure which concerns on Embodiment 7 of this invention, (a) is a planar structure in an upper wiring layer, (b) is a planar structure in a lower wiring layer. It is sectional drawing which shows the capacitor structure which concerns on Embodiment 7 of this invention. It is a top view which shows the capacitor structure based on Embodiment 8 of this invention.

11 First electrode wiring 12 Third electrode wiring 13 Via 14 Electrode base 15 Tooth 16 First electrode 17 Electrode base 18 Tooth 19 Third electrode 21 Second electrode wiring 22 Fourth electrode wiring 23 Via 24 Electrode base 25 Tooth part 26 Second electrode 27 Electrode base 28 Tooth part 29 Fourth electrode 31 First electrode wiring 32 Third electrode wiring 33 Via 35 Spiral part 36 First electrode 37 Electrode base 38 Projection part 39 3rd electrode 41 2nd electrode wiring 42 4th electrode wiring 43 Via 45 Spiral part 46 2nd electrode 47 Electrode base 48 Projection part 49 4th electrode 53 Lower wiring layer (2nd wiring layer)
54 Upper wiring layer (first wiring layer)
63 Lower wiring layer (second wiring layer)
64 Upper wiring layer (first wiring layer)
77, 78 Via 81 Electrode base 82 Tooth 83 Third electrode 84 Electrode base 85 Tooth 86 Fourth electrode 87, 88 Via 91 Electrode base 92 Projection 93 Third electrode 94 Electrode base 95 Projection 96 Fourth Electrodes 97, 98 Via 101 First electrode wiring 102 Third electrode wiring 103 Via 104 Electrode base 105, 106, 107, 108, 109 Tooth 110 First electrode 201 Second electrode wiring 202 Fourth electrode Wiring 203 Via 204 Electrode base 205, 206, 207, 208, 209 Teeth 210 Second electrode

Claims (5)

A capacitor structure formed on a semiconductor substrate,
First and second electrode wirings formed in the first wiring layer;
A first electrode having a plurality of teeth protruding in a comb shape from an electrode base of the first electrode wiring;
A second electrode having a plurality of teeth protruding in a comb shape from the electrode base of the second electrode wiring,
The first electrode and the second electrode are opposed to each other with the tooth portions meshing with each other via a dielectric,
In the first electrode, at least one of the tooth portions is electrically connected to a third electrode wiring formed in a second wiring layer different from the first wiring layer,
The third electrode wiring extends in a plan view so as to cross at least one of the plurality of tooth portions of the second electrode ,
A third electrode having a plurality of teeth protruding in a comb shape from the electrode base of the third electrode wiring;
The capacitor structure according to claim 2, wherein at least one of the tooth portions of the second electrode is opposed to the tooth portion of the third electrode . The capacitor structure of claim 1.
The capacitor structure according to claim 1, wherein the first and second electrodes have vias formed above or below each tooth portion. The capacitor structure of claim 1.
In the second electrode, at least one of the tooth portions is electrically connected to a fourth electrode wiring formed in the second wiring layer,
Before SL having a plurality of teeth projecting in comb-shape from the electrode base of the fourth electrode wire, comprising a fourth electrodes,
The third electrode and the fourth electrode are opposed to each other in a state where the tooth portions mesh with each other via a dielectric,
At least one of the tooth portions of the first electrode is connected to the tooth portion of the third electrode via a via;
At least one of the tooth portions of the second electrode is connected to the tooth portion of the fourth electrode via a via. The capacitor structure of claim 1.
The capacitor structure according to claim 1, wherein the first electrode has a width of at least one of the tooth portions different from that of the other tooth portions. The capacitor structure according to claim 4 , wherein
The first electrode is such that the wiring width of each tooth portion becomes thicker as the distance between the proximal end of the tooth portion and the proximal end of the electrode base portion of the first electrode wiring is longer. Characteristic capacitor structure.

Images