JP5272892B2 - Test condition adjusting apparatus and test condition adjusting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test condition adjustment device and a test condition adjustment method, for preventing the increase of the scale of a chip. <P>SOLUTION: A comparison part 2 compares voltage drop under first operation conditions with voltage drop under second operation conditions in a semiconductor circuit to be designed, for example by performing simulation. In this case, the first operation conditions are, for example, operation conditions in actual operation after a semiconductor circuit is completed, and the second operation conditions are, for example, operation conditions when performing a shipping test (in a test) after the semiconductor circuit is completed. An adjustment part 3 adjusts the second operation conditions based on the delay characteristics of the semiconductor circuit when the voltage drop under the second operation conditions is larger than voltage drop under the first operation conditions. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a test condition adjusting device and a test condition adjusting method.

  As one of the characteristics of the semiconductor chip, it is known that the voltage supplied to the memory cell is reduced (hereinafter referred to as IR drop) in combination with the current drawn from the power supply line due to the influence of the parasitic resistance of the power supply rail. Yes. When the IR drop occurs, a timing delay occurs, which causes a malfunction of the semiconductor chip.

  By the way, in recent years, there are cases where a plurality of semiconductor chip circuits that are not operated simultaneously during actual operation are simultaneously operated during testing, for example, due to shortening of a test (Primary Test) performed at the time of shipment. It has increased.

  In particular, a flip chip has a pad (PAD) for supplying power from the periphery for primary testing to reduce test costs, and power is supplied from the periphery in the same way as a peripheral semiconductor chip. There may be cases where the primary test is performed.

JP 2004-102725 A

  When such a primary test is performed, a load higher than that in actual operation is applied to the semiconductor chip. Accordingly, the IR drop during the primary test is larger than the IR drop during actual operation. For this reason, it is necessary to create a power supply that assumes an IR drop during the primary test, or to perform a timing design that takes into account the IR drop during the primary test.

  However, when such a design is performed, an excessive amount of power supply or an excessive timing is guaranteed for the actual operation of the product. Therefore, there is a problem that the size of the semiconductor chip is increased.

  The present invention has been made in view of these points, and an object of the present invention is to provide a test condition adjusting device and a test condition adjusting method for preventing an increase in chip size.

In order to achieve the above object, a disclosed test condition adjusting apparatus is provided. This test condition adjustment apparatus has a comparison part and an adjustment part.
The comparison unit compares the voltage drop under the first operating condition of the semiconductor circuit to be designed with the voltage drop under the second operating condition.

When the voltage drop under the second operating condition is larger than the voltage drop under the first operating condition, the adjusting unit adjusts the second operating condition based on the delay characteristics of the semiconductor circuit.
According to this test condition adjusting apparatus, the comparison unit compares the voltage drop under the first operating condition of the semiconductor circuit to be designed with the voltage drop under the second operating condition. When the voltage drop under the second operating condition is larger than the voltage drop under the first operating condition, the adjusting unit adjusts the second operating condition based on the delay characteristics of the semiconductor circuit.

  According to the disclosed test condition adjusting apparatus, an increase in the circuit scale of the semiconductor circuit can be prevented.

It is a figure which shows the outline | summary of the test condition adjustment apparatus of embodiment. It is a figure which shows the hardware structural example of a test condition adjustment apparatus. It is a block diagram which shows the function of a test condition adjustment apparatus. It is a figure which shows a hardware constraint condition. It is a figure which shows the specific example of a coefficient management table. It is a figure which shows the table for test condition production | generation. It is a flowchart which shows the process of a test condition adjustment apparatus. It is a flowchart which shows the process of a test condition adjustment apparatus. It is a figure which shows a calculation result. It is a figure which shows the test condition production | generation table of a specific example.

Hereinafter, embodiments will be described in detail with reference to the drawings.
First, the test condition adjusting apparatus according to the embodiment will be described, and then the embodiment will be described more specifically.

FIG. 1 is a diagram illustrating an outline of a test condition adjusting apparatus according to an embodiment.
The test condition adjustment apparatus 1 according to the embodiment includes a comparison unit 2 and an adjustment unit 3.
The comparison unit 2 compares the voltage drop under the first operation condition of the semiconductor circuit to be designed with the voltage drop under the second operation condition, for example, by performing a simulation.

In FIG. 1, the first operating condition and the second operating condition are conditions for operating in an environment of an ambient temperature of 100 [° C.] and a power supply voltage of 1.1 [V], respectively.
Here, the first operation condition is, for example, an operation condition during actual operation after the completion of the semiconductor circuit, and the second operation condition is, for example, when a shipping test is performed after the completion of the semiconductor circuit (during testing). This is an operating condition.

  As described above, due to reasons such as shortening the test time, a plurality of circuits that are not operated at the time of actual operation may be operated at the same time during the test. In such a case, a higher load is applied to the semiconductor circuit than during actual operation. Therefore, the voltage effect at the time of the test is larger than the voltage drop at the actual operation.

FIG. 1 shows that the voltage drop (4%) under the second operating condition is larger than the voltage drop (2%) under the first operating condition.
In FIG. 1, the voltage drop under the first operating condition and the voltage drop under the second operating condition are input from the outside of the test condition adjusting device 1, and the comparison unit 2 compares the input voltage drops with each other. doing. However, the present invention is not limited to this, and the comparison unit 2 may calculate and compare the voltage drop from the input first operating condition and second input operating condition.

When the voltage drop under the second operating condition is larger than the voltage drop under the first operating condition, the adjusting unit 3 adjusts the second operating condition based on the delay characteristics of the semiconductor circuit.
As a method for adjusting the second operating condition, for example, the temperature may be adjusted or the operating voltage may be adjusted. FIG. 1 shows a case where the temperature is adjusted.

  FIG. 1 shows a graph 4 in which delay characteristics that change depending on temperature and voltage during actual operation of a semiconductor circuit to be designed are quantified (coefficientized). Parts having the same numerical value indicate that the delay characteristics of the semiconductor circuits are the same.

  The adjustment unit 3 uses the graph 4 to adjust the second operating condition. Specifically, when the semiconductor circuit is operated under the second operating condition in the simulation and a voltage drop of 4% occurs, a voltage drop of 0.05 [V] occurs and becomes 1.05 [V]. To do.

Here, referring to the part of graph 4 where 100 [° C.] and 1.05 [V] overlap, the delay coefficient is 1.1. This means that the delay becomes larger than that in actual operation.
Accordingly, even when operating at a voltage of 1.05 [V], when searching for a temperature at which the delay is to be eliminated, that is, a temperature at which the delay coefficient becomes 1.0 at a voltage of 1.05 [V], 85 [° C.]. It becomes.

Therefore, the test under the second operating condition is performed at 85 [° C.] and 1.1 [V].
According to such a test condition adjusting apparatus 1, even if a larger voltage drop occurs during the test than during the actual operation, no delay occurs because the test is performed at a lower temperature than during the actual operation. Accordingly, it is not necessary to mount a power supply with a large capacity in preparation for a voltage drop during a test, and it is not necessary to provide a delay compensation circuit, so that an increase in chip size can be prevented.

Hereinafter, the embodiment will be described more specifically.
FIG. 2 is a diagram illustrating a hardware configuration example of the test condition adjusting device.
The entire test condition adjusting apparatus 10 is controlled by a CPU (Central Processing Unit) 101. A random access memory (RAM) 102, a hard disk drive (HDD) 103, a graphic processing device 104, an input interface 105, an external auxiliary storage device 106, and a communication interface 107 are connected to the CPU 101 via a bus 108. Yes.

  The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 stores various data necessary for processing by the CPU 101. The HDD 103 stores an OS and application programs. A program file is stored in the HDD 103.

  A monitor 104 a is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 104a in accordance with a command from the CPU 101. A keyboard 105 a and a mouse 105 b are connected to the input interface 105. The input interface 105 transmits a signal transmitted from the keyboard 105 a and the mouse 105 b to the CPU 101 via the bus 108.

  The external auxiliary storage device 106 reads information written on the recording medium and writes information on the recording medium. Examples of the recording medium that can be read and written by the external auxiliary storage device 106 include a magnetic recording device, an optical disc, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic recording device include an HDD, a flexible disk (FD), and a magnetic tape. Examples of the optical disc include a DVD (Digital Versatile Disc), a DVD-RAM (Random Access Memory), a CD-ROM (Compact Disc Read Only Memory), and a CD-R (Recordable) / RW (ReWritable). Examples of the magneto-optical recording medium include MO (Magneto-Optical disk).

  The communication interface 107 is connected to the network 30. The communication interface 107 transmits and receives data to and from other computers via the network 30.

  With the hardware configuration as described above, the processing functions of the present embodiment can be realized. The following functions are provided in the test condition adjusting apparatus 10 having such a hardware configuration.

FIG. 3 is a block diagram illustrating functions of the test condition adjusting device.
The test condition adjustment apparatus 10 includes a physical design unit 11, an IR drop simulation unit 12, a hardware constraint condition management DB 13, a condition generation unit 14, and an output unit 15.

  The physical design unit 11 performs power design, P & R (Place and Route), and timing verification of the target LSI based on the target IR drop value set by the designer for the target LSI.

  The target IR drop value is, for example, when the power supply voltage is 1.2V and the guaranteed range is 1.2V ± 0.1V, the amount dropped from the lower limit voltage 1.1V in advance in units of V or%. Decide it. This value is determined in consideration of the chip size, power supply quantity, power consumption, and the like.

  In the test condition adjusting apparatus 10, since the condition generation unit 14 generates the test condition, the designer only needs to set the IR drop value during the actual operation instead of the IR drop value during the primary test.

The physical design unit 11 also receives an input of a target operating temperature set by the designer for the LSI to be designed.
The IR drop simulation unit 12 calculates the power consumption during the actual operation and the power consumption during the primary test of the LSI to be designed.

  Based on the calculation result of power consumption during actual operation, an IR drop during actual operation of the LSI to be designed is calculated. Further, the IR drop during the primary test is calculated based on the calculation result of the power consumption during the primary test of the LSI to be designed.

  Then, it is determined whether the IR drop during the primary test is larger than the IR drop during actual operation. If the IR drop during the primary test is greater than the IR drop during actual operation, the process is taken over by the condition generation unit 14.

  The hardware constraint management DB 13 stores the hardware constraint of a tester that performs a primary test of the LSI to be designed. The hardware constraint condition is not particularly limited, and examples thereof include a temperature condition and an applied voltage condition.

The condition generation unit 14 generates a test condition when the power consumption during the primary test is greater than the power consumption during the actual operation.
Specifically, the condition generation unit 14 first acquires the voltage dependency and temperature dependency of the delay of some circuits (representative circuits) of the LSI to be designed.

  The circuit part to be acquired is not particularly limited. For example, the circuit part of the path where the timing is strict and the delay error is likely to occur, such as the chain structure of the inverter, in particular, the voltage dependency and the temperature of the delay of the part having the strictest timing. It is preferable to acquire the dependency. Thereby, the delay can be reliably compensated according to the generated test conditions.

Further, the circuit part to be acquired may be one place or a plurality of places.
The obtained delay dependency is converted into a coefficient (index) with a delay time due to a predetermined voltage and temperature during actual operation of the LSI to be designed as 1.00. The converted coefficient (hereinafter referred to as delay coefficient) is stored in association with the voltage, temperature, and delay time. In addition, when a plurality of locations are acquired, each location may be stored in association with the voltage, temperature, and delay time.

  And the condition production | generation part 14 produces | generates the test conditions at the time of a primary test by adjusting temperature conditions and voltage conditions. At this time, considering the hardware constraint conditions of the tester stored in the hardware constraint management DB 13, the temperature condition and the applied voltage condition that cannot be tested are excluded. A method for generating test conditions during the primary test will be described in detail later.

The output unit 15 outputs the test conditions generated by the condition generation unit 14 to the monitor 104a.
In addition, when the output unit 15 receives other information to be notified from the IR drop simulation unit 12 to the designer, the output unit 15 outputs the information to the monitor 104a.

Next, a specific example of information stored in the hardware constraint management DB 13 and information stored in the condition generation unit 14 will be described.
FIG. 4 is a diagram illustrating hardware constraint conditions.

The hardware constraint conditions are managed as a table.
The hardware constraint condition table 13a is provided with columns for conditions and allowable values, and pieces of information arranged in the horizontal direction are associated with each other.

In the condition column, the hardware constraint condition described above is set.
A range of values that can be tested by the tester and a range of values determined by the standard are set in the allowable value column.

FIG. 5 is a diagram illustrating a specific example of the coefficient management table.
The coefficient management table 14a includes columns for voltage, temperature, delay, and delay coefficient, and values arranged in the horizontal direction are associated with each other.

  In general, the lower the voltage and the higher the temperature, the longer the delay time. Therefore, for example, the delay time La2 [ps] of the temperature A + a1 [° C] of the voltage X [V] is longer than the delay time La1 [ps] of the temperature A [° C] of the voltage X [V]. For this reason, the delay coefficient Ma2 of the delay time La2 [ps] is larger than the delay coefficient 1.00 of the delay time La1 [ps].

  Further, the delay time Lb1 [ps] of the temperature A [° C.] of the voltage X + x1 [V] is larger than the delay time La1 [ps] of the temperature A [° C.] of the voltage X [V]. For this reason, the delay coefficient 1.00 of the delay time La1 [ps] is larger than the delay coefficient Mb1 of the delay time Lb1 [ps].

FIG. 6 is a diagram showing a test condition generation table.
In the test condition generation table 14b, the delay coefficient at the upper limit value and the lower limit value of the allowable value of each condition is set.

  Specifically, values of voltage X + x1 [V], which is a lower limit value of the voltage acquired from the hardware constraint table 13a, and voltage X + x2 [V], which is an upper limit value, are set in the voltage column.

  In the temperature column, a temperature A + a1 [° C.] which is a lower limit value of the temperature acquired from the hardware constraint table 13a and a temperature A + a2 [° C.] which is an upper limit value are set.

  Furthermore, the delay coefficient acquired from the coefficient management table 14a is set in the part where the conditions overlap. In FIG. 6, the delay coefficient Mb2 is set at a portion where the voltage X + x1 [V] and the temperature A + a1 [° C.] overlap. Similarly, a delay coefficient Mc2 is set at a portion where the voltage X + x2 [V] and the temperature A + a1 [° C.] overlap. A delay coefficient Mb3 is set at a portion where the voltage X + x1 [V] and the temperature A + a2 [° C.] overlap. A delay coefficient Mc3 is set at a portion where the voltage X + x2 [V] and the temperature A + a2 [° C.] overlap.

Next, the process of the test condition adjusting apparatus 10 will be described.
7 and 8 are flowcharts showing the processing of the test condition adjusting device.
First, the physical design unit 11 receives an IR drop input during actual operation targeted by the LSI to be designed (step S1). Here, the IR drop rate (N%) is accepted.

Next, the physical design unit 11 receives an input of an estimate of the power supply capacity (initial power supply) that can satisfy the IR drop received in step S1 (step S2).
Next, the physical design unit 11 creates a power supply path for the LSI to be designed (power supply design) (step S3).

  Next, the physical design unit 11 places (Places) each gate registered in the library (not shown) based on the logically synthesized circuit, and performs wiring (Route) between the terminals of the gate ( Step S4). The library may be provided inside the test condition adjusting apparatus 10 or may exist outside the test condition adjusting apparatus 10.

Next, the physical design unit 11 performs timing verification as to whether each signal of the LSI to be designed operates correctly within a predetermined time (step S5).
Next, the IR drop simulation unit 12 calculates power consumption during actual operation (step S6). For example, a value obtained by adding power consumption due to transistor leakage, power consumption due to transistor switching, and power consumption due to through current of the transistor is calculated as power consumption during actual operation.

Next, the IR drop simulation unit 12 calculates an IR drop rate during actual operation (step S7).
Next, the IR drop simulation unit 12 determines whether or not the IR drop rate during the actual operation calculated in step S7 is equal to or less than the target IR drop rate (N%) set in step S10. (Step S8).

  If the IR drop during actual operation is larger than the target IR drop rate (N%) (No in step S8), the process proceeds to step S1, and for example, an error is displayed on the monitor 104a to notify the designer. Is notified. Then, when a new input of the target IR drop by the designer is received, the processing after step S2 is performed again.

  If the IR drop during actual operation is larger than the target IR drop rate (N%), the process proceeds to step S3, and the physical design unit 11 re-calculates the power supply, thereby calculating the IR drop rate again. You may do it.

  On the other hand, when the IR drop during actual operation is equal to or less than the target IR drop rate (N%) (Yes in step S8), the IR drop simulation unit 12 generates layout data considering the IR drop during actual operation. (Step S9 in FIG. 8).

Next, the IR drop simulation unit 12 calculates the power consumption during the primary test using the layout data considering the IR drop during actual operation (step S10).
Next, the IR drop simulation unit 12 calculates the IR drop rate (S%) during the primary test using the layout data generated in step S9 (step S11).

  Next, the IR drop simulation unit 12 determines whether or not the IR drop rate (S%) calculated in step S11 is larger than the IR drop rate (N%) (step S12).

  When the IR drop rate (S%) is equal to or less than the IR drop rate (N%) (No in step S12), that is, the IR drop value during the primary test is equal to or less than the IR drop value during actual operation. In this case, no adjustment is necessary, and the process is terminated. In this case, the IR drop simulation unit 12 sends to the output unit 15 that the design with the IR drop rate (N%) received in step S1 is successful. The output unit 15 outputs that fact to the monitor 104a.

  On the other hand, when the IR drop rate (S%) is greater than the IR drop rate (N%) (Yes in step S12), that is, the IR drop value during the primary test is greater than the IR drop value during actual operation. In this case, since the adjustment is necessary, the condition generation unit 14 performs the following processing.

  The condition generation unit 14 acquires the voltage dependency and temperature dependency of the delay of the representative circuit described above (step S13). The acquired delay value is converted into a coefficient with the delay value under the reference condition as 1.00.

Next, the condition generation unit 14 refers to the hardware constraint condition table 13a and acquires the hardware constraint condition of the tester (step S14).
The condition generation unit 14 generates the test condition generation table 14b based on the temperature dependency acquired in step S13 and the hardware constraint conditions acquired in step S14 (step S15). Specifically, the voltage X + x1 [V] which is the lower limit value of the voltage and the voltage X + x2 [V] which is the upper limit value are acquired from the hardware constraint condition table 13a. Each value is set in the voltage column.

  Next, the temperature A + a1 [° C.] which is the lower limit value of the temperature and the temperature A + a2 [° C.] which is the upper limit value are acquired from the hardware constraint condition table 13a. Each value is set in the temperature column.

  Next, the coefficient management table 14a is referred to, and a delay coefficient is set in a portion where conditions overlap. In FIG. 6, the delay coefficient Mb2 is set at a portion where the voltage X + x1 [V] and the temperature A + a1 [° C.] overlap. Similarly, the delay coefficient Mc2 is set at a portion where the voltage X + x2 [V] and the temperature A + a1 [° C.] overlap. The delay coefficient Mb3 is set at a portion where the voltage X + x1 [V] and the temperature A + a2 [° C.] overlap. The delay coefficient Mc3 is set at a portion where the voltage X + x2 [V] and the temperature A + a2 [° C.] overlap. Thereby, the test condition generation table 14b is completed.

  Next, the test condition in the IR drop rate (S%) at the time of the primary test obtained by the condition generation unit 14 in step S11 is extracted from the test condition generation table 14b generated in step S15 (step S16).

For example, the voltage value after IR drop of the IR drop rate (N%) during the actual operation and the IR drop rate (S%) during the primary test is calculated.
FIG. 9 is a diagram illustrating a calculation result.

A table 14d illustrated in FIG. 9 illustrates the calculation result calculated by the condition generation unit 14.
The table 14d shows that the voltage and temperature before the IR drop during the actual operation and the primary test are both X + x1 [V] and A + a1 [° C.]. The IR drop rate during actual operation is N%, indicating that the voltage after IR drop is Xn [V]. Further, the IR drop rate during the primary test is S%, indicating that the voltage after IR drop is Xs [V].

Returning again to FIG.
Then, the condition generation unit 14 refers to the test condition generation table 14b and extracts a temperature ratio corresponding to the voltage ratio after the IR drop. The temperature at the primary test is calculated as the temperature conversion value. It is also possible to calculate a voltage value. Which is converted is determined in advance in consideration of the calculation cost and the like.

Next, it is determined whether or not the IR drop (S%) obtained in step S11 is outside the range of the test condition generation table 14b generated in step S15 (step S17).
If the IR drop value obtained in step S11 is outside the range of the test condition generation table 14b generated in step S15 (Yes in step S17), the process proceeds to step S1, for example, an error is displayed on the monitor 104a. Notify the designer to that effect. Then, when a new input of the target IR drop by the designer is received, the processing after step S2 is performed again.

  On the other hand, if it is within the range of the test condition generation table 14b (No in step S17), the process is terminated. In this case, the condition generation unit 14 sends the test conditions extracted in step S16 to the output unit 15. The output unit 15 outputs this test condition to the monitor 104a.

<Specific example>
Next, a method for generating test conditions will be described using a specific example.
FIG. 10 is a diagram showing a test condition generation table of a specific example.

Hereinafter, a method for generating test conditions by adjusting the temperature will be described.
The LSI to be designed is premised on operation at 100 [° C.] and 1.1 [V] in actual operation. In this case, the coefficient management table 14a sets the delay coefficient at 100 [° C.] and 1.1 [V] to 1.0.

It is assumed that IR drop occurs at 0.1 [V] and becomes 1.0 [V] during the primary test.
Here, referring to a portion where 100 [° C.] and 1.0 [V] overlap in the test condition generation table 14c, the delay coefficient is 1.1. This means that the delay becomes larger than that in actual operation.

Accordingly, when the temperature at which the delay is to be eliminated at the voltage of 1.0 [V], that is, the temperature at which the delay coefficient becomes 1.0 at the voltage of 1.0 [V], 85 [° C.] corresponds.
Therefore, the primary test is performed at 85 [° C.] and 1.1 [V].

  Thus, even when an IR drop occurs during the primary test and the voltage drops to 1.0 [V], the test is performed at 85 [° C.], that is, the primary test is performed under the condition that the coefficient is 1.0. Therefore, the load is equivalent to 100 [° C.] and 1.1 [V] during actual operation. Therefore, the primary test can be performed under the same conditions as in the actual operation without designing an excessive power supply for the primary test.

  When the test conditions are generated by adjusting the voltage, the same effect as described above can be obtained by changing the voltage while keeping the temperature constant. That is, at 100 [° C.], the voltage at which the delay coefficient is 1.0 is 1.1 [V], so the IR drop voltage difference of 0.1 [V] is added to 1.1 [V]. Then, it becomes 1.2 [V].

Therefore, the primary test is performed at 100 [° C.] and 1.2 [V].
<Modification>
The primary test temperature and voltage can also be determined based on the worst case delay.

An LSI in which 2% IR drop occurs during actual operation and 4% IR drop occurs during the primary test will be described as an example.
The worst condition for delay during actual operation is when the test is performed at 125 [° C.] and 1.1 [V], and the voltage when the IR drop occurs is 1.1 × 0.98 = 1. 078 [V]. The best conditions are when the test is performed at −40 [° C.] and 1.3 [V].

  On the other hand, the worst condition for the delay in the primary test is when the test is performed at 125 [° C.] and 1.1 [V], and the voltage when the IR drop occurs is 1.1 × 0.96 = 1.056 [V]. The best conditions are when the test is performed at −40 [° C.] and 1.3 [V].

  When adjusting the temperature, the difference between the delay times of 125 [° C.] and x [° C.] equal to the difference between the delay times of 1.078 [V] and 1.056 [V] is obtained. Here, x = 100 [° C.]. Therefore, the primary test is performed at 100 [° C.] and 1.1 [V].

  When adjusting the voltage, a primary test is performed by adding a voltage difference of 0.024 V between 1.078 [V] and 1.056 [V] to 1.1 V. That is, the primary test is performed at 125 [° C.] and 1.124 V [V].

  As described above, according to the test condition adjusting apparatus 10, when the IR drop during the primary test is larger than the IR drop during the actual operation, the condition generation unit 14 stores the test condition generation tables 14b and 14c. Based on the determined delay coefficient, the test conditions for the primary test were generated.

  As a result, even if a larger voltage drop occurs during the primary test than during the actual operation, no delay occurs because the test is performed at a lower temperature than during the actual operation or a higher power supply voltage than during the actual operation.

  Therefore, it is not necessary to mount a power supply having a large capacity in the LSI in preparation for a voltage drop at the time of the primary test, or to provide a delay compensation circuit, so that an increase in the circuit scale of the LSI can be prevented.

  In addition, the condition generation unit 14 generates a test condition generation table 14b, and generates a test condition for the primary test based on this table. Thereby, a test condition can be easily generated.

  In addition, the condition generation unit 14 generates the test condition generation table 14b in consideration of the tester voltage and temperature constraints. Thereby, it can test reliably with a tester using the produced | generated test conditions.

  Further, the condition generation unit 14 acquires a circuit portion of a path where a delay error is likely to occur when acquiring the voltage dependency and temperature dependency of the delay of the representative circuit. Thereby, the delay can be reliably compensated according to the generated test conditions.

The type of LSI to be designed to which the test condition adjusting apparatus 10 can be applied is not particularly limited, and examples thereof include a flip chip and a peripheral LSI.
When the LSI to be designed is a flip chip, when power is supplied from the primary test pad, the IR drop during the primary test may be larger than the IR drop during actual operation.

  In addition, when the LSI to be designed is a peripheral LSI, the operation circuit is operated at the same frequency as in the actual operation during the primary test, and the operation circuit is more active during the primary test than during the actual operation in order to shorten the test time. Many.

Therefore, in this LSI, the IR drop during the primary test may be larger than the IR drop during actual operation.
The test condition adjusting apparatus 10 is not limited to the type of LSI to be designed, and can prevent an increase in the circuit scale of the LSI.

  Note that the processing performed by the test condition adjustment device 10 may be distributed by a plurality of devices. For example, one apparatus may perform physical design and perform timing verification, and another apparatus may perform simulation using the result and generate test conditions.

  The test condition adjusting apparatus and the test condition adjusting method of the present invention have been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each part has the same function. Any configuration can be substituted. Moreover, other arbitrary structures and processes may be added to the present invention.

In addition, the present invention may be a combination of any two or more configurations (features) of the above-described embodiments.
The above processing functions can be realized by a computer. In that case, a program describing the processing contents of the functions of the test condition adjusting apparatus 10 is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic recording device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic recording device include a hard disk device (HDD), a flexible disk (FD), and a magnetic tape. Examples of the optical disc include a DVD (Digital Versatile Disc), a DVD-RAM (Random Access Memory), a CD-ROM (Compact Disc Read Only Memory), and a CD-R (Recordable) / RW (ReWritable). Examples of the magneto-optical recording medium include MO (Magneto-Optical disk).

  When distributing the program, for example, a portable recording medium such as a DVD or a CD-ROM in which the program is recorded is sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  A computer that executes the test condition adjustment program stores, for example, a program recorded on a portable recording medium or a program transferred from a server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time the program is transferred from the server computer, the computer can sequentially execute processing according to the received program.

Regarding the above embodiment, the following additional notes are disclosed.
(Additional remark 1) The comparison part which compares the voltage drop in the 1st operation condition of the semiconductor circuit to be designed with the voltage drop in the 2nd operation condition,
An adjustment unit that adjusts the second operating condition based on a delay characteristic of the semiconductor circuit when a voltage drop under the second operating condition is larger than a voltage drop under the first operating condition;
A test condition adjusting apparatus comprising:

(Additional remark 2) The said adjustment part adjusts the operating temperature of the said 2nd operating condition lower than the operating temperature of the said 1st operating condition, The test condition adjustment apparatus of Additional remark 1 characterized by the above-mentioned.
(Additional remark 3) The said adjustment part adjusts the operating voltage of the said 2nd operating condition lower than the operating voltage of the said 1st operating condition, The test condition adjusting apparatus of Additional remark 1 characterized by the above-mentioned.

  (Additional remark 4) The said adjustment part produces | generates the information showing the relationship of the delay characteristic with respect to the voltage change of the predetermined part of the said semiconductor circuit, and a temperature change, and adjusts the said 2nd operating condition based on the said information. The test condition adjusting device as set forth in Appendix 1, characterized by:

  (Additional remark 5) The said adjustment part produces | generates the said information in consideration of the predetermined restrictions of the voltage and temperature in a said 2nd operating condition, The test condition adjustment apparatus of Additional remark 4 characterized by the above-mentioned.

(Additional remark 6) The said predetermined site | part is a circuit part which has a path | route with the strictest timing of the said semiconductor circuit, The test condition adjustment apparatus of Additional remark 4 characterized by the above-mentioned.
(Supplementary note 7)
Compare the voltage drop under the first operating condition of the semiconductor circuit to be designed with the voltage drop under the second operating condition,
When the voltage drop under the second operating condition is larger than the voltage drop under the first operating condition, the second operating condition is adjusted based on the delay characteristics of the semiconductor circuit;
The test condition adjustment method characterized by this.

(Appendix 8)
Comparison means for comparing the voltage drop under the first operating condition of the semiconductor circuit to be designed with the voltage drop under the second operating condition;
Adjusting means for adjusting the second operating condition based on a delay characteristic of the semiconductor circuit when a voltage drop under the second operating condition is larger than a voltage drop under the first operating condition;
Test condition adjustment program characterized by functioning as

DESCRIPTION OF SYMBOLS 1, 10 Test condition adjustment apparatus 2 Comparison part 3 Adjustment part 4 Graph 11 Physical design part 12 IR drop simulation part 13 Hardware constraint condition management DB
13a Hardware constraint condition table 14 Condition generation unit 14a Coefficient management table 14b, 14c Test condition generation table 15 Output unit

Claims (5)

A comparison unit for comparing a voltage drop under a first operation condition that is an operation condition during actual operation of a semiconductor circuit to be designed with a voltage drop under a second operation condition that is an operation condition during testing ;
An adjustment unit that adjusts the second operating condition based on a delay characteristic of the semiconductor circuit when a voltage drop under the second operating condition is larger than a voltage drop under the first operating condition;
A test condition adjusting apparatus characterized by comprising: The test condition adjusting apparatus according to claim 1, wherein the adjustment unit adjusts the operating temperature of the second operating condition to be lower than the operating temperature of the first operating condition. The test condition adjusting apparatus according to claim 1, wherein the adjustment unit adjusts the operating voltage of the second operating condition to be higher than the operating voltage of the first operating condition. The adjusting unit generates information representing a relationship of delay characteristics with respect to voltage change and temperature change of a predetermined portion of the semiconductor circuit, and adjusts the second operating condition based on the information. The test condition adjusting device according to claim 1. Computer
Compare the voltage drop under the first operating condition, which is the operating condition during the actual operation of the semiconductor circuit to be designed, with the voltage drop under the second operating condition, which is the operating condition during the test ,
When the voltage drop under the second operating condition is larger than the voltage drop under the first operating condition, the second operating condition is adjusted based on the delay characteristics of the semiconductor circuit;
The test condition adjustment method characterized by this.

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