JP2011028644A - Method and program for analyzing power supply noise - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and an apparatus for SSO (Simultaneous Switching Output) noise analysis which can reduce a circuit scale of a package model without reducing the analysis accuracy of SSO noise. <P>SOLUTION: The method for power supply noise analysis uses a model including: a plurality of signal drive circuits; first wiring for supplying a first power supply voltage to the plurality of signal drive circuits; second wiring for supplying a second power supply voltage to the plurality of signal drive circuits; and a plurality of third wiring for propagating signals driven by the plurality of signal drive circuits. The method for power supply noise analysis includes the steps of: extracting self-inductances and mutual inductances of the first to third wiring from layout information; specifying a current route of a current flowing during the drive of a signal; obtaining respective effective inductances of the first to third wiring by combining the self-inductances and the mutual inductances based on the information of the specified current route; and executing a circuit simulator by using the model including the effective inductances. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present disclosure generally relates to computer-based design, and more particularly to a power supply noise analysis method in computer-based design.

  In an LSI (Large Scale Integration) circuit, a power supply voltage variation called SSO (Simultaneous Switching Output) noise occurs due to simultaneous operation of an IO circuit (input / output circuit). SSO noise generated inside the LSI propagates not only inside the LSI but also to a PCB (Printed Circuit Board). SSO noise not only causes circuit malfunctions in the LSI and on the PCB, but also causes MIS noise to be mixed into the inter-LSI transmission signal waveform, resulting in erroneous logic recognition due to signal waveform quality degradation and timing margin failure due to delay variation. .

  In the future, SSO noise is expected to increase as LSIs are further increased in speed and increased in pin count. Furthermore, it is considered that the SSO noise resistance of the transmission signal waveform and timing decreases with the increase in the speed and the voltage of the bus clock. Therefore, it is expected that the influence of SSO noise on the transmission signal between LSIs will increase more and more.

  Under such circumstances, it is indispensable to accurately estimate the SSO noise and take appropriate measures. Since the SSO noise is generated by a rapid current change caused by the simultaneous operation of the IO circuit and the inductor component of the package, it is necessary to accurately model the inductor component of the package in the SSO noise analysis. Therefore, in the past, SSO noise analysis was performed by modeling all of the mutual inductance between the signal wiring and signal wiring of the package and between the signal wiring and power wiring as well as the self-inductance of the signal wiring and power wiring of the package. Yes.

  However, since modeling is performed including not only the self-inductance of signal wiring and power supply wiring but also mutual inductance, if the number of signals to be modeled increases, the circuit scale of the package model increases exponentially. As a result, the simulation time and convergence of the SSO noise analysis are deteriorated. On the contrary, if the mutual inductance between the wirings of the package is ignored in order to improve the simulation time and convergence, the analysis accuracy of the SSO noise is deteriorated.

JP 2002-197136 A JP 2004-54522 A

  In view of the above, an SSO noise analysis method and apparatus that can reduce the circuit scale of a package model without degrading the SSO noise analysis accuracy is desired.

  A plurality of signal drive circuits; a first wiring for supplying a first power supply voltage to the plurality of signal drive circuits; a second wiring for supplying a second power supply voltage to the plurality of signal drive circuits; A method of performing a power supply noise analysis by executing a circuit simulator by a computer using a model including a plurality of third wirings for propagating signals driven by a plurality of signal driving circuits is based on the first to the second from layout information. 3 extracts the self-inductance and the mutual inductance of the wiring 3, specifies the current path that flows when the signal is driven, and combines the self-inductance and the mutual inductance based on the information on the specified current path. The effective inductance of each of the first to third wirings is obtained, and circuit simulation is performed using the model including the effective inductance. Wherein each step of performing the data, wherein the performing by each stage computer.

  A plurality of signal driving circuits; a first wiring for supplying a first power supply voltage to the plurality of signal driving circuits; a second wiring for supplying a second power supply voltage to the plurality of signal driving circuits; A program for performing power supply noise analysis by executing a circuit simulator by a computer using a model including a plurality of third wirings for propagating signals driven by the plurality of signal driving circuits is obtained from layout information based on the first information Extracting the self-inductance and the mutual inductance of the third wiring, specifying the current path that flows when the signal is driven, and synthesizing the self-inductance and the mutual inductance based on the information on the specified current path The effective inductance of each of the first to third wirings is obtained by using the model including the effective inductance. Wherein each step of performing a road simulator, characterized in that to execute the respective steps in a computer.

  According to at least one embodiment of the present disclosure, since the mutual inductance between the wirings is not modeled as an explicit circuit element, the circuit scale of the package model can be reduced, and the simulation time of the SSO noise analysis can be reduced. Convergence can be improved. In addition, since the effective inductance obtained by incorporating the influence of the mutual inductance between the wirings into the self-inductance is used, it is possible to reduce the circuit scale of the package model without degrading the SSO noise analysis accuracy.

It is a figure which shows an example of the model of the circuit system used as the object of SSO noise analysis. It is a figure which shows an example of the model of the circuit system used as the object of SSO noise analysis. It is a flowchart which shows the flow of the process which calculates effective inductance. It is a figure which shows typically the circuit of the object of noise analysis. It is a figure which shows 4x4 inductance matrix. It is a figure which shows extraction of an inductance matrix. It is a figure which shows extraction of an inductance matrix. It is a figure which shows an example of the synthetic | combination process of the effective inductance at the time of a signal rise, and the effective inductance at the time of a signal fall. It is a figure which shows the circuit of the object of the noise analysis modeled by the effective inductance. It is a figure which shows the circuit of the object of the noise analysis modeled with the effective inductance in case the number of signal wiring is n. It is a figure which shows the inductance matrix L in case the number of signal wiring is n pieces. It is a figure which shows the value of each diagonal element of the inductance matrix L of FIG. It is a figure for demonstrating the method of dividing a signal wiring into several groups and modeling. It is a flowchart which shows the whole flow of SSO noise analysis processing. It is a figure which shows the flowchart of the circuit operation | movement analysis by a circuit simulator. It is a figure which shows the precision comparison of SSO noise analysis. It is a figure which shows another precision comparison of SSO noise analysis. It is a figure which shows the structure of the apparatus which performs a SSO noise analysis process.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a diagram illustrating an example of a model of a circuit system that is an object of SSO noise analysis. The circuit system shown in FIG. 1 includes an LSI circuit 10, a package 11, a PCB 12, and a counterpart device 13. The LSI circuit 10 includes an input signal source 20 and a signal drive circuit 21.

  The input signal source 20 is an internal circuit of the LSI circuit 10 and executes an intended desired operation to generate an input signal to the signal drive circuit 21 (that is, an output signal from the LSI circuit 10). The signal drive circuit 21 is an output circuit of the LSI circuit 10 and operates based on the input signal generated by the input signal source 20 to drive the output signal. Although not shown in the drawing, the signal drive circuit 21 includes not only an output circuit for outputting a signal but also an input circuit for inputting an external signal and supplying the signal to the inside of the LSI circuit 10, and an input / output circuit. May work as. For the sake of illustration, only one signal driving circuit 21 is shown, but actually, a plurality of signal driving circuits 21 are provided corresponding to a plurality of output signals. As the signal driving circuit 21, a model such as IBIS (IO Buffer Information Specification) normally used in PCB design is insufficient in accuracy, and a net list including a transistor may be used.

  A signal output from the signal driving circuit 21 is sent to the transmission line 25 on the PCB 12 via the package 11. For the sake of illustration, one transmission path 25 is shown, but in practice, a plurality of transmission paths 25 are provided corresponding to a plurality of output signals. The model of the transmission line 25 may be an LCR ladder circuit, a W-Element model, or an S parameter. The output signal of the LSI circuit 10 that has propagated through the transmission path 25 is input to the input circuit of the counterpart device 13. In the example of FIG. 1, the counterpart device 13 is modeled by the input capacitance 26 of the input circuit. The input circuit of the counterpart device 13 may be a model such as IBIS, or may be a transistor level netlist.

  A power supply wiring 22 for supplying a positive power supply voltage VDE and a power supply wiring 23 for supplying a negative power supply voltage VSS (ground voltage) are provided for the plurality of signal drive circuits 21. Further, a signal wiring 24 that propagates a signal driven by the signal driving circuit 21 is provided. For convenience of illustration, only one signal line 24 is shown, but actually, a plurality of signal lines 24 are provided corresponding to a plurality of output signals. The power supply wiring 22 and the power supply wiring 23 are for supplying power from the PCB 12 to the LSI circuit 10 and are provided in the package 11. The signal wiring 24 is for transmitting the output signal of the LSI circuit 10 to the PCB 12 and is provided in the package 11.

  In the circuit model to be subjected to the SSO noise analysis shown in FIG. 1, the power supply wiring 22, the power supply wiring 23, and the signal wiring 24 of the package 11 may be modeled by an LCR ladder circuit. This model may be modeled including the bonding wire portion and the interposer portion. In FIG. 1, the number of stages of the LCR ladder circuit is two, but in actuality, modeling may be performed with a larger number of stages.

  The LCR ladder circuit representing the power supply wiring 22, the power supply wiring 23, and the signal wiring 24 of the package 11 includes a self-inductance L, a resistance R, a mutual inductance LM, and an inter-wiring capacitance C. Note that the mutual inductance LM and the inter-wiring capacitance C also exist between the plurality of signal wirings 24. As described above, since the SSO noise is generated by a rapid current change caused by the simultaneous operation of the IO circuit and the inductor component of the package, it is necessary to accurately model the inductor component of the package in the SSO noise analysis. . However, when modeling including not only the self-inductance L but also the mutual inductance LM as shown in FIG. 1, the circuit scale of the package model increases exponentially in proportion to the number of signal wirings 24 to be modeled. End up. As a result, the simulation time and convergence of the SSO noise analysis are deteriorated. Therefore, in the embodiment described below, the effective inductance of each of the plurality of signal wirings 24 is obtained by synthesizing the self-inductance and the mutual inductance, and the circuit analysis simulator is executed using the model based on the effective inductance to perform SSO noise. Perform analysis.

  FIG. 2 is a diagram illustrating an example of a model of a circuit system that is an object of SSO noise analysis according to the present embodiment. 2, the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted. In the model of the package 11 shown in FIG. 2, the mutual inductance LM shown in FIG. 1 is not provided. Instead, the effective inductance Lr of each of the plurality of signal wirings 24 is obtained by combining the self-inductance L and the mutual inductance LM shown in FIG. 1, and a model is constructed from the effective inductance Lr.

  Specifically, the power supply wiring 22 is referred to as a first wiring, the power supply wiring 23 is referred to as a second wiring, and the signal wiring 24 is referred to as a third wiring. Extract the mutual inductance. These self-inductance and mutual inductance are given as an n × n inductance matrix as described later. n is the total number of first to third wirings. There are usually a plurality of first wirings and third wirings, but the same power supply can be obtained by imposing the constraint that the LSI ends and PCB ends of the plurality of power supply wirings of the same power supply type have the same potential. It is possible to combine a plurality of types of power supply wirings into one. Next, a current path that flows when the signal is driven is specified. For example, when the signal rises, a current flows through a path indicated by an arrow as the current I1 in FIG. 2, and the current flows from the power supply voltage VDE into the input capacitor 26 to accumulate charges. At this time, the amount of current flowing through the first wiring 22 is equal to the amount of current flowing through the third wiring 24, and it can be considered that no current flows through the second wiring 23. Further, when there are a plurality of third wirings 24, it can be considered that the amounts of currents flowing through the respective wirings 24 are equal to each other in the worst condition in which all signals to be subjected to power supply noise analysis rise simultaneously. Further, when the signal falls, a current flows as a current I2 in FIG. 2 through a path indicated by an arrow, the charge of the input capacitor 26 is discharged, and a discharge current flows to the ground voltage VSS. At this time, the amount of current flowing through the second wiring 23 and the amount of current flowing through the third wiring 24 are equal, and it can be considered that no current flows through the first wiring 22. Further, when there are a plurality of third wirings 24, it can be considered that the amounts of currents flowing through the respective wirings 24 are equal to each other in the worst condition in which all signals to be analyzed for power supply noise fall at the same time. In order to assume that the amount of current flowing through the plurality of third wirings 24 is uniform, it is necessary that the plurality of signal driving circuits 21 have the same characteristics, in particular, have the same driving force. .

  Next, the effective inductance of each of the first to third wirings is obtained by combining the self-inductance and the mutual inductance based on the specified current path information. Specifically, if the current path is specified as described above and the amount of current flowing through each of the plurality of third wirings 24 is assumed to be equal, the currents flowing through one target wiring are coupled by mutual inductance. The current flowing through the other wiring can be expressed. Thereby, the value of the effective inductance, which is an effective self-inductance, can be obtained by linearly coupling the value of the mutual inductance and the value of the self-inductance. For example, if the amount of current flowing in one of the plurality of m third wirings 24 is I, the current flowing in the other third wiring 24 is the same amount of current I in the same direction. The direction of the current that flows through either the first wiring 22 or the second wiring 23 is opposite, and the amount of current is mI. Therefore, the mutual inductance LM for each of the other third wirings 24 is included in the effective inductance Lr as + LM, and the mutual inductance LM for one of the first wiring 22 or the second wiring 23 is effective inductance as -mLM. It will be included in Lr. That is, the effective inductance Lr is obtained as the sum of the self-inductance L, m−1 + LM, and 1 −mLM. In the above description, the mutual inductance LM is described as if it is a single value for convenience. However, the mutual inductance LM with respect to the other wiring is usually a different value for each wiring.

  The SSO noise is analyzed by executing a circuit simulator on a computer using the model including the effective inductance obtained as described above. That is, by executing the circuit simulator, the time change of the voltage and current at each terminal including the terminals 27, 28, and 29 shown in FIG. 2 is calculated. The time change of voltage and current is calculated by a circuit simulator solving a differential equation based on the model. By outputting the time change of the voltage and current at each terminal as, for example, waveform data, it is possible to know how much the voltage and current at each terminal are affected by the SSO noise.

  FIG. 3 is a flowchart showing a flow of processing for calculating the effective inductance. FIG. 4 is a diagram schematically showing a circuit to be subjected to noise analysis. Below, the process which calculates effective inductance is demonstrated using FIG.3 and FIG.4.

  In step S1, an instruction for designating a target range for SSO noise analysis is input to the power supply noise analysis device (computer). Specifically, for example, wirings 31 to 34 shown in FIG. 4 are designated as regions to be analyzed for the package. Here, the wiring 31 is a power supply wiring of the package PKG that supplies the power supply voltage VDE, and the wiring 34 is a power supply wiring of the package PKG that supplies the ground voltage VSS. The wirings 32 and 33 are signal wirings of the package PKG through which a signal driven by the signal driving circuit 21 similar to that described in FIG. 1 propagates. For convenience of explanation, FIG. 4 shows an example in which two wirings are provided as signal wirings. However, the number of signal wirings may be one, or three or more.

  In step S2, an inductance matrix of the VDE power supply wiring and the two signal wirings is extracted. The inductance matrix is a 3 × 3 matrix. First, a 4 × 4 inductance matrix L of the signal wirings 32 and 33, the VDE power supply wiring 31, and the VSS power supply wiring 34 as shown in FIG. 4 will be described. The value of each element of the inductance matrix (each inductance value) is extracted from the package layout data.

FIG. 5 is a diagram showing a 4 × 4 inductance matrix. In this 4 × 4 inductance matrix L, diagonal elements are self-inductances L _{11 to} L ₄₄ , and other elements are mutual inductances L _xy (x ≠ y). These self-inductance and mutual inductance are schematically shown in FIG. This 4 × 4 inductance matrix L is a column vector composed of four voltage values corresponding to the four wirings 31 to 34 and a time vector differentiation of four current values corresponding to the four wirings 31 to 34. Represents an inductance component. That is, when the time differentiation of the current flowing through the VDE power supply wiring 31 is I1, the time differentiation of the current flowing through the signal wirings 32 and 33 is I2 and I3, respectively, and the time differentiation of the current flowing through the VSS power supply wiring 34 is I4. The voltage drop V1 due to the inductance component in the power supply wiring 31 is expressed as follows.

_{V1 = L 11 I1 + L 12} I2 + L 13 I3 + L 14 I4
The voltage drops V2 and V3 due to the inductance components in the signal wirings 32 and 33 are expressed as follows.

V2 = L ₂₁ I1 + L ₂₂ I2 + L ₂₃ I3 + L ₂₄ I4
V3 = L ₃₁ I1 + L ₃₂ I2 + L ₃₃ I3 + L ₃₄ I4
The voltage drop V4 due to the inductance component in the VSS power supply wiring 34 is expressed as follows.

V4 = L ₄₁ I1 + L ₄₂ I2 + L ₄₃ I3 + L ₄₄ I4
In step S2, a 3 × 3 inductance matrix for the VDE power supply wiring 31 and the signal wirings 32 and 33 is extracted from the inductance matrix L. That is, as shown in FIG. 6, a 3 × 3 inductance matrix 41 corresponding to a portion 40 surrounded by a dotted line is extracted from the 4 × 4 inductance matrix L.

  In step S3, the effective inductance of the VDE power supply wiring and the two signal wirings is calculated. At this time, the path through which the current flows is specified, and the relative magnitude of the current flowing through each path can also be specified. Therefore, as described above, the mutual inductance value and the self-inductance value are linearly combined to be effective. The inductance value can be determined. That is, when the output signal of the signal drive circuit 21 shown in FIG. 4 rises from LOW to HIGH, assuming that the current flowing through the VDE power supply wiring 31 is I1, the voltage drop V1 due to the inductance component in the VDE power supply wiring 31 is expressed as follows. It is.

_{V1 = L 11 I1 + L 12} (-I1 / 2) + L 13 (-I1 / 2)
_{= (L 11 -L 12/2} -L 13/2) I1
That is, the effective inductance Lr ₁₁ of the VDE power supply wiring 31 is
Lr ₁₁ = L ₁₁ − (1/2) (L ₁₂ + L ₁₃ )
It becomes. Further, assuming that the currents flowing through the signal wirings 32 and 33 are I2 and I3, voltage drops V2 and V3 due to inductance components in the signal wirings 32 and 33 are expressed as follows.

_{V2 = L 21 (-2I2) +} L 22 I2 + L 23 I2
= (L ₂₂ + L ₂₃ -2L ₂₁ ) I2
_{V3 = L 31 (-2I3) +} L 32 I3 + L 33 I3
= (L ₃₂ + L ₃₃ -2L ₃₁ ) I3
That is, the effective inductances Lr ₂₂ and Lr ₃₃ of the signal wirings 32 and ₃₃ are
Lr ₂₂ = L ₂₂ + L ₂₃ -2L ₂₁
Lr ₃₃ = L ₃₂ + L ₃₃ -2L ₃₁
It becomes. The matrix L is a symmetric matrix, and L ₂₁ = L ₁₂ and L ₃₁ = L ₁₃ . In this way, an effective inductance matrix 42 as shown in FIG. 6 is obtained.

  In step S4 in FIG. 3, an inductance matrix between the VSS power supply wiring and the two signal wirings is extracted. That is, as shown in FIG. 7, a 3 × 3 inductance matrix 51 corresponding to a portion 50 surrounded by a dotted line is extracted from the 4 × 4 inductance matrix L. In step S5, the effective inductance of the VSS power supply wiring and the two signal wirings is calculated. That is, the following effective inductance is obtained in the same manner as in step S3.

Lf ₂₂ = L ₂₂ + L ₂₃ -2L ₂₄
Lf ₃₃ = L ₃₃ + L ₂₃ -2L _{34
Lf 44 = L 44 - (1/2} ) (L 24 + L 34)
That is, an effective inductance matrix 52 as shown in FIG. 7 is obtained.

In step S6 of FIG. 3, the average value of the effective inductances of the two signal wires calculated in the processing of step S3 and step S5 is calculated. The effective inductance obtained in step S3 is the effective inductance in the case of signal rise. The effective inductance obtained in step S5 is the effective inductance in the case of signal fall. Since the effective inductance for the VDE power supply wiring 31 is only required for the calculation of the SSO noise analysis at the time of signal rise, the effective inductance Lr ₁₁ at the time of signal rise obtained in step S3 may be used as it is. Further, since the effective inductance for the VSS power supply wiring 34 is necessary for calculation of the SSO noise analysis only when the signal falls, the effective inductance Lf ₄₄ obtained when the signal falls in step S5 may be used as it is.

On the other hand, the effective inductance with respect to the signal wirings 32 and 33 is used for the calculation of the SSO noise analysis in both the case where the signal rises and the case where the signal falls. In this case, the effective inductance calculated in step S3 may be used at the time of calculation when the signal rises, and the effective inductance calculated at step S5 may be used at the time of calculation when the signal falls. That is, for the effective inductance of the signal wires 32 and 33, the value of the effective inductance may be switched between when the signal rises and when it falls. However, in the circuit analysis simulator, a single value is designated as a self-inductance value as a circuit parameter, and voltage and current changes are calculated using that value. Therefore, the circuit parameter value is switched according to the circuit operation. That is generally difficult. In such a case, as described below, the effective inductance when the signal obtained for the signal wirings 32 and 33 rises and the effective inductance when the signal falls are combined, and the signal wirings 32 and 33 are combined. Find the effective inductance of. For example, an average value of the effective inductances Lr ₂₂ and Lr ₃₃ at the time of signal rise obtained at step S3 and the effective inductances Lf ₂₂ and Lf ₃₃ at the time of signal fall obtained at step S5 is obtained, and the average value is obtained as the signal wiring 32. And 33 effective inductance.

  Finally, in step S7 in FIG. 3, the effective inductances of the VDE power supply wiring, the VSS power supply wiring, and the two signal wirings are output. That is, a 4 × 4 inductance matrix composed of effective inductances for the VDE power supply wiring 31, the signal wirings 32 and 33, and the VSS power supply wiring 34 is output.

FIG. 8 is a diagram illustrating an example of a synthesis process of the effective inductance at the time of signal rise and the effective inductance at the time of signal fall. In the example of FIG. 8, the effective inductance matrix 42 obtained as shown in FIG. 6 and the effective inductance matrix 52 obtained as shown in FIG. 7 are combined to output a 4 × 4 inductance matrix 55. This matrix 55 is a diagonal matrix including effective inductance values Lrf ₁₁ , Lrf ₂₂ , Lrf ₃₃ , and Lrf ₄₄ as diagonal elements. Lrf ₁₁ is equal to the effective inductance Lr ₁₁ when the signal rises in step S3. Lrf ₂₂ is an average value of the effective inductance Lr _{22 in} the case of the signal rise obtained in step S3 and the effective inductance Lf _{22 in} the case of the signal fall obtained in step S5. Lrf ₃₃ is an average value of the effective inductance Lr _{33 in} the case of the signal rise obtained in step S3 and the effective inductance Lf _{33 in} the case of the signal fall obtained in step S5. Lrf ₄₄ is equal to the effective inductance Lf ₄₄ in the case of the signal falling edge obtained in step S5.

FIG. 9 is a diagram illustrating a circuit to be subjected to noise analysis modeled by effective inductance. 9, the same components as those of FIG. 4 are referred to by the same numerals, and a description thereof will be omitted. As shown in FIG. 9, the VDE power supply wiring 31, the signal wiring 32, the signal wiring 33, and the VSS power supply wiring 34 have effective inductances Lrf ₁₁ , Lrf ₂₂ , Lrf ₃₃ , and Lrf ₄₄ , respectively. These effective inductances reflect the values of self-inductance and mutual inductance shown in FIG.

FIG. 10 is a diagram showing a circuit to be subjected to noise analysis modeled by effective inductance when the number of signal wirings is n. The signal drive circuit 21 is the same signal drive circuit as described in FIG. In FIG. 10, a VDE power supply wiring 61-1, n signal wirings 61-2 to 61-n + 1, and a VSS power supply wiring 61-n + 2 are provided. The wirings 61-1 to 61-n + 2 have effective inductances Lrf _{11 to} Lrf _{n + 2 and n + 2} , respectively.

  FIG. 11 is a diagram showing an inductance matrix L when the number of signal wirings is n. As shown in FIG. 11, the inductance matrix L in this case is a diagonal matrix of (n + 2) × (n + 2), the diagonal elements are effective inductance values, and the values of the other elements are zero.

  FIG. 12 is a diagram illustrating the values of the diagonal elements of the inductance matrix L in FIG. As shown in FIG. 12, each effective inductance value is a linear combination of a self-inductance value and a mutual inductance value. These effective inductance values can be obtained in the same manner as the flowchart shown in FIG. That is, first, it is assumed that current paths are specified separately at the time of rising and at the time of falling, and further, the amount of current flowing through each of the plurality of signal wirings is equal. If this assumption is used, the current flowing through the other wiring coupled by the mutual inductance can be expressed using the current flowing through the single wiring of interest. Accordingly, the effective inductance value can be obtained by linearly coupling the mutual inductance value and the self-inductance value.

  FIG. 13 is a diagram for explaining a method of modeling signal wirings divided into a plurality of groups. The circuit system shown in FIG. 13 includes an LSI circuit 70, a package 71, a PCB 72, and a counterpart device 73. A plurality of signal wires 82-1 of the package 71 are connected to the plurality of pads 81-1 of the LSI circuit 70. The plurality of signal wirings 82-1 are coupled to the counterpart device 73 via the transmission path 75-1 of the PCB 72. A plurality of signal wirings 82-2 of the package 71 are connected to the plurality of pads 81-2 of the LSI circuit. The plurality of signal wirings 82-2 are coupled to the counterpart device 73 via the transmission path 75-2 of the PCB 72. The signal wiring 82-1 is a wiring for inputting / outputting a data signal, for example, and the signal wiring 82-2 is a wiring for inputting / outputting a control signal, an address signal, etc., for example. In this way, when the types of signals propagated in the first group of signal wirings 82-1 and the second group of signal wirings 82-2 are different, the first group of signal wirings 82-1 and the second group. The signal wiring 82-2 is unlikely to change signals simultaneously. In such a case, the model using the effective inductance is applied to each of the first group of signal wirings 82-1 and the second group of signal wirings 82-2 by applying the modeling method described above. It may be generated separately. That is, the signal wiring is divided into the first group wiring and the second group wiring, the effective inductance of each of the power supply wiring and the signal wiring is obtained for the first group, What is necessary is just to obtain | require the effective inductance of each of a power supply wiring and a signal wiring.

  FIG. 14 is a flowchart showing the overall flow of the SSO noise analysis process. In step S1, an SSO noise analysis LSI model 102 is created based on the LSI layout information stored in the LSI layout information storage unit 101. In step S <b> 2, an SSO noise analysis PKG model 104 is created based on the PKG layout information stored in the PKG (package) layout information storage unit 103. In step S3, the SSO noise analysis PCB model 106 is created based on the PCB layout information stored in the PCB layout information storage unit 105.

  In step S4, a circuit analysis simulator is executed based on the SSO noise analysis LSI model 102, the SSO noise analysis PKG model 104, and the SSO noise analysis PCB model 106. As a result, power supply noise information inside the LSI, power supply noise information on the printed circuit board, power supply pin current waveform information, and the like are output as SSO noise analysis results.

  FIG. 15 is a diagram illustrating a flowchart of the circuit operation analysis by the circuit simulator. The process according to the flowchart of FIG. 15 corresponds to the process of step S4 of FIG.

  In step S1 of FIG. 15, a circuit definition file is input. That is, a file defining a circuit of each SSO noise analysis model is input to formulate a circuit network. In step S2, a library is input. That is, the library used in the SSO noise analysis model is input. For example, in the SSO noise analysis LSI model, if the information defined in the library is used for the output circuit (signal drive circuit), the information is input.

  In step S3, DC operating point analysis is performed, and the voltage and current of each terminal at time 0 are calculated.

  In step S4, a transient analysis is executed. That is, the voltage and current of each terminal at each time after time 0 are calculated by solving the matrix differential equation including the above-described inductance matrix. The size of this inductance matrix depends on the number of terminals. Since the non-diagonal component of the inductance matrix corresponds to the mutual inductance, for example, the analysis time and convergence are improved by making the non-diagonal component zero by including the mutual inductance in the effective inductance as shown in FIG. To do.

  In step S5, the analysis result is output. That is, the time change of the voltage and current at each terminal is output as, for example, waveform data. This makes it possible to know how much the voltage and current at each terminal are affected by SSO noise. By using the analysis result data obtained in this manner and checking a part where there is a problem with the power supply noise and correcting the design, it becomes possible to appropriately cope with the SSO noise at the design stage.

  FIG. 16 is a diagram showing accuracy comparison of SSO noise analysis. The upper part of FIG. 16 shows the waveform of the voltage change at the VDE power supply terminal (for example, terminal 27 in FIG. 2). The horizontal axis indicates time, and the vertical axis indicates voltage. The voltage waveform 111 is an SSO noise analysis result using a model using the above-described effective inductance, and the voltage waveform 112 is an SSO noise analysis result using a model using the self-inductance and the mutual inductance as they are. The voltage waveform 113 is an SSO noise analysis result using a model using only the self-inductance while ignoring the mutual inductance. As can be seen from these waveforms, the voltage waveform 113 when the mutual inductance is simply ignored is quite different from the precisely calculated voltage waveform 112. On the other hand, the voltage waveform 111 when the mutual inductance is incorporated into the effective inductance is quite close to the precisely calculated voltage waveform 112. The effect is particularly noticeable in the waveform portion 114. The lower part of FIG. 16 shows the voltage change waveform at the VSS power supply terminal (for example, terminal 28 in FIG. 2). The voltage waveform 121 is an SSO noise analysis result using a model using effective inductance, and the voltage waveform 122 is an SSO noise analysis result using a model using self-inductance and mutual inductance as they are. Further, the voltage waveform 123 is an SSO noise analysis result using a model using only the self-inductance while ignoring the mutual inductance. In the waveform portion 124 and the like, it can be seen that the voltage waveform 121 when the mutual inductance is incorporated into the effective inductance is quite close to the precisely calculated voltage waveform 122.

  FIG. 17 is a diagram showing another accuracy comparison of the SSO noise analysis. FIG. 17 shows a voltage change waveform at the receiving end of the counterpart device (for example, the terminal 29 in FIG. 2). The horizontal axis indicates time, and the vertical axis indicates voltage. The voltage waveform 131 is an SSO noise analysis result using the above-described model using the effective inductance, and the voltage waveform 132 is an SSO noise analysis result using the model using the self-inductance and the mutual inductance as they are. The voltage waveform 133 is an SSO noise analysis result using a model using only the self-inductance while ignoring the mutual inductance. As can be seen from these waveforms, the voltage waveform 133 when the mutual inductance is simply ignored is quite different from the precisely calculated voltage waveform 132. On the other hand, the voltage waveform 131 when the mutual inductance is incorporated into the effective inductance is quite close to the precisely calculated voltage waveform 132. The effect is particularly noticeable in the waveform portions 134 and 135.

  FIG. 18 is a diagram illustrating a configuration of an apparatus that executes SSO noise analysis processing including package modeling. As shown in FIG. 18, the apparatus that executes the SSO noise analysis process is realized by a computer such as a personal computer or an engineering workstation. The apparatus of FIG. 18 includes a computer 510, a display device 520 connected to the computer 510, and an input device. The input device includes a keyboard 521 and a mouse 522, for example. The computer 510 includes a CPU 511, a RAM 512, a graphic processing device 513, a secondary storage device 514 such as a hard disk HDD, a communication interface 515, and an input interface 516.

  The keyboard 521 and the mouse 522 provide an interface with the user, and various commands for operating the computer 510, user responses to requested data, and the like are input. The display device 520 displays the results processed by the computer 510 and displays various data to enable interaction with the user when operating the computer 510. The graphic processing device 513 executes drawing processing for an image to be displayed on the display device 520. The communication interface 515 is for performing communication with a remote place via the network 530, and includes, for example, a modem or a network interface.

  The SSO noise analysis method is provided as a computer program executable by the computer 510. This computer program is loaded into the RAM 512 or the secondary storage device 514 via the communication interface 515, for example.

  When there is a program execution instruction from the user via the keyboard 521 and / or the mouse 522, the CPU 511 loads the program from the secondary storage device 514 to the RAM 512, for example. The CPU 511 uses the free storage space of the RAM 512 as a work area, executes the program loaded in the RAM 512, and advances the process while appropriately interacting with the user. By executing this computer program, the computer 510 executes the SSO noise analysis method as described in the above embodiment.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

The present invention includes the following contents.
(Appendix 1)
A plurality of signal drive circuits; a first wiring for supplying a first power supply voltage to the plurality of signal drive circuits; a second wiring for supplying a second power supply voltage to the plurality of signal drive circuits; Using a model including a plurality of third wirings that propagate signals driven by a plurality of signal driving circuits, a circuit simulator is executed by a computer to perform power supply noise analysis,
Extracting the self-inductance and mutual inductance of the first to third wirings from the layout information,
Identify the current path that flows when driving the signal,
By determining the effective inductance of each of the first to third wirings by combining the self-inductance and the mutual inductance based on the information on the specified current path,
A power supply noise analysis method comprising: each step of executing a circuit simulator using the model including the effective inductance, wherein each step is executed by a computer.
(Appendix 2)
Determining the effective inductance comprises:
Determining an effective inductance when the signal rises with respect to the first and third wirings;
Determining an effective inductance when the signal falls with respect to the second and third wirings;
And combining the effective inductance when the signal obtained for the third wiring rises and the effective inductance when the signal falls to obtain the effective inductance of the third wiring, The step of executing the simulator includes effective inductance when the signal obtained for the first wiring rises, effective inductance when the signal obtained for the second wiring falls, and the first wiring The power supply noise analysis method according to appendix 1, wherein the model including the effective inductance obtained by combining the three wirings is used.
(Appendix 3)
Further comprising dividing the third wiring into a first group of wirings and a second group of wirings, and determining the effective inductance comprises:
Obtaining an effective inductance of each of the first to third wirings for the first group;
The power supply noise analysis method according to claim 1 or 2, further comprising: calculating each effective inductance of each of the first to third wirings with respect to the second group.
(Appendix 4)
A plurality of signal drive circuits; a first wiring for supplying a first power supply voltage to the plurality of signal drive circuits; a second wiring for supplying a second power supply voltage to the plurality of signal drive circuits; Using a model including a plurality of third wirings for propagating signals driven by a plurality of signal driving circuits, a program for executing a circuit simulator by a computer and performing power supply noise analysis,
Extracting the self-inductance and mutual inductance of the first to third wirings from the layout information,
Identify the current path that flows when driving the signal,
By determining the effective inductance of each of the first to third wirings by combining the self-inductance and the mutual inductance based on the information on the specified current path,
A power supply noise analysis program, comprising: each step of executing a circuit simulator using the model including the effective inductance, and causing a computer to execute the steps.
(Appendix 5)
Determining the effective inductance comprises:
Determining an effective inductance when the signal rises with respect to the first and third wirings;
Determining an effective inductance when the signal falls with respect to the second and third wirings;
And combining the effective inductance when the signal obtained for the third wiring rises and the effective inductance when the signal falls to obtain the effective inductance of the third wiring, The step of executing the simulator includes effective inductance when the signal obtained for the first wiring rises, effective inductance when the signal obtained for the second wiring falls, and the first wiring The voltage noise analysis program according to appendix 4, wherein the model including the effective inductance obtained by combining the three wirings is used.
(Appendix 6)
Further comprising dividing the third wiring into a first group of wirings and a second group of wirings, and determining the effective inductance comprises:
Obtaining an effective inductance of each of the first to third wirings for the first group;
6. The power supply noise analysis program according to appendix 4 or 5, further comprising each step of obtaining an effective inductance of each of the first to third wirings with respect to the second group.
(Appendix 7)
A plurality of signal drive circuits; a first wiring for supplying a first power supply voltage to the plurality of signal drive circuits; a second wiring for supplying a second power supply voltage to the plurality of signal drive circuits; An information processing apparatus that performs power supply noise analysis by executing a circuit simulator using a model including a plurality of third wirings that propagate signals driven by a plurality of signal driving circuits,
A memory for storing layout information and programs;
A processing unit, and the processing unit executes the program,
Extracting the self-inductance and mutual inductance of the first to third wirings from the layout information,
Identify the current path that flows when driving the signal,
By determining the effective inductance of each of the first to third wirings by combining the self-inductance and the mutual inductance based on the information on the specified current path,
An information processing apparatus that executes each stage of executing a circuit simulator using the model including the effective inductance.
(Appendix 8)
Determining the effective inductance comprises:
Determining an effective inductance when the signal rises with respect to the first and third wirings;
Determining an effective inductance when the signal falls with respect to the second and third wirings;
And combining the effective inductance when the signal obtained for the third wiring rises and the effective inductance when the signal falls to obtain the effective inductance of the third wiring, The step of executing the simulator includes effective inductance when the signal obtained for the first wiring rises, effective inductance when the signal obtained for the second wiring falls, and the first wiring The information processing apparatus according to appendix 7, wherein the model including the effective inductance obtained by combining the three wirings is used.
(Appendix 9)
The processing unit further performs a step of dividing the third wiring into a first group wiring and a second group wiring, and obtaining the effective inductance comprises:
Obtaining an effective inductance of each of the first to third wirings for the first group;
The information processing apparatus according to claim 7 or 8, further comprising: each step of obtaining an effective inductance of each of the first to third wirings for the second group.

10 LSI circuit 11 Package 12 PCB
13 partner device 20 input signal source 21 signal drive circuit 22 power supply wiring 23 power supply wiring 24 signal wiring 25 transmission line 26 input capacitance

Claims (5)

A plurality of signal drive circuits; a first wiring for supplying a first power supply voltage to the plurality of signal drive circuits; a second wiring for supplying a second power supply voltage to the plurality of signal drive circuits; Using a model including a plurality of third wirings that propagate signals driven by a plurality of signal driving circuits, a circuit simulator is executed by a computer to perform power supply noise analysis,
Extracting the self-inductance and mutual inductance of the first to third wirings from the layout information,
Identify the current path that flows when driving the signal,
By determining the effective inductance of each of the first to third wirings by combining the self-inductance and the mutual inductance based on the information on the specified current path,
A power supply noise analysis method comprising: each step of executing a circuit simulator using the model including the effective inductance, wherein each step is executed by a computer. Determining the effective inductance comprises:
Determining an effective inductance when the signal rises with respect to the first and third wirings;
Determining an effective inductance when the signal falls with respect to the second and third wirings;
And combining the effective inductance when the signal obtained for the third wiring rises and the effective inductance when the signal falls to obtain the effective inductance of the third wiring, The step of executing the simulator includes effective inductance when the signal obtained for the first wiring rises, effective inductance when the signal obtained for the second wiring falls, and the first wiring 3. The power supply noise analysis method according to claim 1, wherein the model including the effective inductance obtained by combining the three wirings is used. Further comprising dividing the third wiring into a first group of wirings and a second group of wirings, and determining the effective inductance comprises:
Obtaining an effective inductance of each of the first to third wirings for the first group;
3. The power supply noise analysis method according to claim 1, further comprising: calculating each effective inductance of each of the first to third wirings with respect to the second group. A plurality of signal drive circuits; a first wiring for supplying a first power supply voltage to the plurality of signal drive circuits; a second wiring for supplying a second power supply voltage to the plurality of signal drive circuits; Using a model including a plurality of third wirings for propagating signals driven by a plurality of signal driving circuits, a program for executing a circuit simulator by a computer and performing power supply noise analysis,
Extracting the self-inductance and mutual inductance of the first to third wirings from the layout information,
Identify the current path that flows when driving the signal,
By determining the effective inductance of each of the first to third wirings by combining the self-inductance and the mutual inductance based on the information on the specified current path,
A power supply noise analysis program, comprising: each step of executing a circuit simulator using the model including the effective inductance, and causing a computer to execute the steps. Determining the effective inductance comprises:
Determining an effective inductance when the signal rises with respect to the first and third wirings;
Determining an effective inductance when the signal falls with respect to the second and third wirings;
And combining the effective inductance when the signal obtained for the third wiring rises and the effective inductance when the signal falls to obtain the effective inductance of the third wiring, The step of executing the simulator includes effective inductance when the signal obtained for the first wiring rises, effective inductance when the signal obtained for the second wiring falls, and the first wiring The voltage noise analysis program according to claim 4, wherein the model including the effective inductance obtained by combining the three wirings is used.

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