JP5271505B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with high reliability capable of preventing a short circuit and current leakage between a gate electrode layer and a semiconductor layer due to covering failure of an insulating layer, and to provide a method for fabricating such a semiconductor device. <P>SOLUTION: In order to form a plurality of semiconductor elements on an insulation surface, a first element isolation region having a high resistance and a second element isolation region in contact with an element region and having an opposite conductivity type to a source region and a drain region of the element region are formed, as element isolation regions that electrically insulates and isolates a plurality of element regions functioning as semiconductor elements in a continuous semiconductor layer, without dividing the semiconductor layer into a plurality of island-like semiconductor layers. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

The present invention relates to a semiconductor device having a plurality of semiconductor elements and a manufacturing method thereof.

In the case where a plurality of semiconductor elements are provided over an insulating surface, a method of processing a semiconductor film formed over the insulating surface into a plurality of island-shaped semiconductor layers by an etching process is used. A semiconductor element has a stacked structure of a plurality of thin films. In the case of a planar thin film transistor, a gate insulating layer is stacked so as to cover a semiconductor layer separated in an island shape.

Since the semiconductor layer processed into an island shape has a step at the end, defects such as thinning of the gate insulating layer and destruction of the film occur at the end of the semiconductor layer.

When the gate insulating layer is thinned, a leak current flows between the gate electrode and the semiconductor layer, and when the gate insulating layer is destroyed, the gate electrode and the semiconductor layer come into contact with each other and short-circuit (short). The characteristic defect occurs.

In order to solve the above problem, a method of laminating two gate insulating layers having different shapes to alleviate a step due to an end portion of a semiconductor layer and improving coverage is performed. (For example, refer to Patent Document 1).
JP-A-10-242471

However, the above-described method for reducing the level difference cannot sufficiently prevent a short circuit due to contact between the semiconductor film and the gate electrode and a defect such as a leakage current depending on the film thickness of the semiconductor layer and the gate insulating layer. It was. In particular, when the semiconductor element is miniaturized (for example, the gate length is 1 μm or less), there is a problem that the leakage current appears remarkably.

The present invention provides a highly reliable semiconductor device in which a short circuit between a gate electrode and a semiconductor layer due to a poor coating of a gate insulating layer and a defect such as a leakage current are prevented, and a method for manufacturing such a semiconductor device. Objective.

In order to form a plurality of semiconductor elements on an insulating surface, the present invention does not separate a semiconductor layer into a plurality of island-shaped semiconductor layers, and a plurality of element regions functioning as semiconductor elements in one continuous semiconductor layer As the element isolation region for electrically insulating and isolating the first and second element isolation regions having high resistance, the second element isolation region having a conductivity type opposite to the source and drain regions of the element region is formed. To do.

The plurality of element regions are provided around the element region so as to surround the second element isolation region which is an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region. A first element isolation region, which is a high resistance region, is provided adjacent to the outer side of the two element isolation regions. Therefore, the adjacent first element region and second element region are the second element isolation region in contact with the first element region, the first element isolation region, and the second element isolation in contact with the second element region. Adjacent through a region.

In the case where the source region and the drain region of the first element region and the second element region have the same electric type, for example, in the case of an n-type impurity region, the second element isolation region also has the opposite conductivity type to the element region. It becomes a p-type impurity region. On the other hand, the first element region and the second element are such that the source region and the drain region of the first element region are n-type impurity regions, and the source region and the drain region of the second element region are p-type impurity regions. When the regions are of the opposite conductivity type, the second element isolation region included in each region is also combined with the element regions, and the first element region side is a p-type impurity region, and the second element region side is an n-type impurity region. It becomes.

The first element isolation region that is adjacent to the element region via the second element isolation region is the first element isolation region that does not selectively contribute to conductivity in order to electrically isolate the elements in one continuous semiconductor layer. It is formed by adding one impurity element. In the present specification, “does not contribute to conductivity” means that the conductivity is not improved by adding the element.

As the first impurity element that does not contribute to conductivity (does not improve conductivity), at least one impurity element of oxygen, nitrogen, and carbon can be used. In the element isolation region to which the first impurity element is added, the conductivity decreases due to the mixing of the first impurity element that does not contribute to the conductivity, and also due to physical impact on the semiconductor layer at the time of addition (so-called sputtering effect). Increased resistance due to lower crystallinity. In the element isolation region with a high resistance, the field effect mobility is also reduced, so that the elements can be electrically isolated, while the region to which no impurity element is added maintains the field effect mobility that can function as an element. Therefore, it can be used as an element region.

The resistance of the first element isolation region is preferably 1 × 10 ¹⁰ Ω · cm or more, and the concentration of the first impurity element such as oxygen, nitrogen, or carbon is 1 × 10 ²⁰ cm ⁻³ or more and 4 × 10 ²² cm. Less than ^-3 is preferable.

The first element isolation region can be said to be amorphous because the crystallinity is lowered by the addition of the impurity element. On the other hand, since the element region is a crystalline semiconductor layer, when a semiconductor element is formed in the element region, the crystallinity of the channel formation region is higher than that of the first element isolation region, and high field effect mobility can be obtained as a semiconductor element. it can.

As the first impurity element added to the first element isolation region, a rare gas element such as argon (Ar), neon (Ne), krypton (Kr), or xenon (Xe) may be used. In addition to oxygen, nitrogen, and carbon, the addition of these rare gas elements, which are relatively large elements, can increase the physical impact on the semiconductor layer. The crystallinity of the element isolation region can be reduced.

The second element isolation region provided between the element region and the first element isolation region in contact with the element region is added with a second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region. Form.

The element region has a source region, a drain region, and a channel formation region. The source region and the drain region are impurity regions having one conductivity type (for example, an n-type impurity region or a p-type impurity region). A second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region is added to the second element isolation region, and the second element isolation region is used as a source region and a drain in the adjacent element region. The impurity region has a conductivity type opposite to that of the region. That is, when the source region and the drain region in the element region are n-type impurity regions, the adjacent second element isolation region is a p-type impurity region, and similarly, the source region and the drain region in the element region are p-type impurity regions. In some cases, the adjacent second element isolation region may be an n-type impurity region. The adjacent element region and the second element isolation region form a PN junction. Therefore, the element regions can be further insulated and separated by the second element isolation region provided between the element regions.

The present invention provides a first element isolation region which is a high resistance region by addition of a first impurity element that does not contribute to conductivity as an element isolation region for insulating and isolating element regions, and further, a source region and a drain region in the element region By providing a second element isolation region which is an impurity region by adding a second impurity element imparting a conductivity type opposite to that of the semiconductor element, one continuous semiconductor layer is separated into a plurality of element regions. According to the present invention, since the element regions can be separated from each other by the effects of the first element isolation region and the second element isolation region, a higher element isolation effect can be obtained.

Note that in this specification, the element region includes an element formation region before an element is formed. Therefore, in the middle of the element manufacturing process, even if it is not completed as an element (before the formation of another electrode layer or insulating layer), it is insulated and separated into the element isolation region which is a high resistance region in the semiconductor layer. The element formation region is called an element region.

For the addition (introduction) of the impurity element in forming the first element isolation region and the second element isolation region, an ion implantation method, an (ion) doping method, or the like can be used.

Further, the element isolation region may have a concentration gradient of the first impurity element and the second impurity element. Of course, the first impurity element and the second impurity element may be added to the first and second element isolation regions at a substantially uniform concentration. That is, the concentration peak of the first impurity element and the second impurity element can be set as appropriate in the first and second element isolation regions. The second element isolation region may be an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region in contact with the second element isolation region. An impurity element imparting a mold may be contained. The second element isolation region may contain the first impurity element described above, and the second element isolation region may be added by adding the second impurity element to a part of the first element isolation region. It can also be formed.

Therefore, when the present invention is used, the semiconductor layer can be separated into a plurality of element regions without being divided into islands. Since the step due to the end portion of the semiconductor layer does not occur and the gate insulating layer is formed on the flat semiconductor layer, the coverage of the gate insulating layer is improved. Accordingly, it is possible to provide a highly reliable semiconductor device in which a short circuit between the gate electrode and the semiconductor layer due to a poor coating of the gate insulating layer and a defect such as a leakage current are prevented, and a method for manufacturing such a semiconductor device.

Note that in the present invention, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. By using the present invention, a device having a circuit including a semiconductor element (a transistor, a memory element, a diode, or the like) or a semiconductor device such as a chip having a processor circuit can be manufactured.

One embodiment of a semiconductor device of the present invention includes a semiconductor layer including a first element isolation region, a second element isolation region, and an element region over an insulating surface, and the element region includes a source region, a drain region, and a channel formation. The second element isolation region is in contact with the element region, the first element isolation region is in contact with the second element isolation region, and the first element isolation region is formed of oxygen, nitrogen, and carbon. Of these, at least one or more types of first impurity elements are included, and the second element isolation region includes a second impurity element that imparts a conductivity type opposite to that of the source region and the drain region to the second element isolation region. The element isolation region has lower crystallinity than the channel formation region.

In the above structure, in one embodiment of the semiconductor device of the present invention, the second element isolation region is provided so as to surround the element region, and the first element isolation region is provided so as to surround the second element isolation region.

According to one embodiment of the semiconductor device of the present invention, a first element adjacent to the insulating surface via a first element isolation region, a second element isolation region, a first element isolation region, and a second element isolation region is provided. The first element region includes a first source region, a first drain region, and a first channel formation region; and the second element region includes a second element region. The first source region, the first drain region, the second source region, and the second drain region are of the same conductivity type. The first element isolation region contains at least one or more kinds of first impurity elements of oxygen, nitrogen, and carbon; the second element isolation region is in contact with the first element region and the second element region; The first element isolation region is in contact with the second element isolation region. The second element isolation region provides the second element isolation region with a conductivity type opposite to that of the first source region, the first drain region, the second source region, and the second drain region. The first element isolation region has lower crystallinity than the first channel formation region and the second channel formation region.

One embodiment of a semiconductor device of the present invention includes a first element isolation region, a second element isolation region, a third element isolation region, a first element isolation region, a second element isolation region, and a first element isolation region on an insulating surface. A semiconductor layer including a first element region and a second element region that are adjacent to each other with the three element isolation regions interposed therebetween. The first element region includes a first source region, a first drain region, and a first element region. Including a channel formation region, the second element region includes a second source region, a second drain region, and a second channel formation region, and the first source region and the first drain region are n-type impurity regions. The second source region and the second drain region are p-type impurity regions, and the first element isolation region contains at least one kind of first impurity element of oxygen, nitrogen, and carbon, The element isolation region is in contact with the first element region, The element isolation region is in contact with the second element isolation region, the third element isolation region is in contact with the second element region, and the first element isolation region is the second element isolation region and the third element isolation region. The second element isolation region includes an impurity element that imparts p-type to the second element isolation region, and the third element isolation region imparts n-type to the third element isolation region. The first element isolation region has lower crystallinity than the first channel formation region and the second channel formation region.

In one embodiment of a method for manufacturing a semiconductor device of the present invention, a semiconductor layer is formed over an insulating surface, and at least one or more first impurity elements of oxygen, nitrogen, and carbon are selectively added to the semiconductor layer, A first element isolation region including an element region and a first impurity element is formed in the semiconductor layer, a second impurity element imparting one conductivity type is selectively added to the semiconductor layer, and the first element isolation region is added A second element isolation region is formed between the element region and the element region, an insulating layer is formed on the element region, the first element isolation region, and the second element isolation region, and a conductive layer is formed on the element region and the insulating layer. Then, a channel formation region, a source region and a drain region having a conductivity type opposite to that of the second impurity element are formed in the element region.

In one embodiment of a method for manufacturing a semiconductor device of the present invention, a semiconductor layer is formed over an insulating surface, and at least one or more first impurity elements of oxygen, nitrogen, and carbon are selectively added to the semiconductor layer, A first element isolation region including an element region and a first impurity element is formed in the semiconductor layer, a second impurity element imparting one conductivity type is selectively added to the semiconductor layer, and the first element isolation region is added A second element isolation region is formed between the element region and the element region, an insulating layer is formed on the element region, the first element isolation region, and the second element isolation region, and a conductive layer is formed on the element region and the insulating layer. And an impurity element imparting a conductivity type opposite to that of the second impurity element is added to the element region to form a channel formation region and a source region and drain region having a conductivity type opposite to that of the second element isolation region. .

In one embodiment of a method for manufacturing a semiconductor device of the present invention, a semiconductor layer is formed over an insulating surface, an insulating layer is formed over the semiconductor layer, and at least one of oxygen, nitrogen, and carbon is selectively formed over the semiconductor layer. The first impurity element is added through the insulating layer, the element region and the first element isolation region containing the first impurity element are formed in the semiconductor layer, and one conductivity type is selectively given to the semiconductor layer. A second impurity element is added through an insulating layer, a second element isolation region is formed between the first element isolation region and the element region, and a conductive layer is formed on the element region and the insulating layer; A channel formation region, a source region and a drain region having a conductivity type opposite to that of the second impurity element are formed in the element region.

In one embodiment of a method for manufacturing a semiconductor device of the present invention, a semiconductor layer is formed over an insulating surface, an insulating layer is formed over the semiconductor layer, and at least one of oxygen, nitrogen, and carbon is selectively formed over the semiconductor layer. The first impurity element is added through the insulating layer, the element region and the first element isolation region containing the first impurity element are formed in the semiconductor layer, and one conductivity type is selectively given to the semiconductor layer. A second impurity element is added through an insulating layer, a second element isolation region is formed between the first element isolation region and the element region, and a conductive layer is formed on the element region and the insulating layer; An impurity element imparting a conductivity type opposite to that of the second impurity element is added to the element region, so that a channel formation region and a source region and drain region having a conductivity type opposite to that of the second element isolation region are formed.

By using the present invention, a semiconductor layer can be separated into a plurality of element regions without being divided into islands, and a plurality of semiconductor elements can be manufactured. Accordingly, a step due to the end portion of the semiconductor layer does not occur, and the gate insulating layer is formed on the flat semiconductor layer, so that the coverage of the gate insulating layer is improved.

Accordingly, it is possible to provide a highly reliable semiconductor device in which a short circuit between the gate electrode and the semiconductor layer due to a poor coating of the gate insulating layer and a defect such as a leakage current are prevented, and a method for manufacturing such a semiconductor device. Therefore, further miniaturization and high integration can be performed in the semiconductor device, and high performance of the semiconductor device can be achieved.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
In this embodiment, an NMOS as an example of a semiconductor device for preventing a short circuit between a gate electrode layer and a semiconductor layer and a leakage current due to a poor coating of a gate insulating layer and providing higher reliability. , CMOS (Complementary Metal Oxide Semiconductor) will be described with reference to drawings.

1A and 1B illustrate an example of a semiconductor device having an NMOS structure in this embodiment. FIG. 1A is a top view, FIG. 1B is a cross-sectional view taken along line QR in FIG. C) is a sectional view taken along line ST.

Over the substrate 600 over which the insulating layer 601 that functions as a base film of the semiconductor layer is formed, an NMOS structure including the transistor 610a which is an n-channel thin film transistor and the transistor 610b which is an n-channel transistor, and the insulating layer 606 are formed. . The transistor 610a includes an element region including n-type impurity regions 607a and 607b and a channel formation region 609a, and a gate electrode layer 605a. The transistor 610b includes an element region including n-type impurity regions 608a and 608b and a channel formation region 609b. The gate insulating layer 604 and the insulating layer 606 are formed in succession to the transistors 610a and 610b. In addition, a wiring layer 611a which is a source or drain electrode layer connected to the n-type impurity region 607a, a wiring layer 611b which is a source or drain electrode layer connected to the n-type impurity region 607b and the n-type impurity region 608a, A wiring layer 611c which is a source electrode layer or a drain electrode layer connected to the n-type impurity region 608b is provided, and the transistor 610a and the transistor 610b are electrically connected by the wiring layer 611b (FIG. 1A to FIG. 1A). (See (C).)

In the semiconductor layer, an element region including n-type impurity regions 607a and 607b and a channel formation region 609a included in the transistor 610a, and an element region including n-type impurity regions 608a and 608b and a channel formation region 609b included in the transistor 610b. Are electrically isolated by the first element isolation region 602 (602a, 602b, 602c, 602d, 602e) and the second element isolation region 613 (613a, 613b), 614 (614a, 614b).

FIG. 1 shows a case where a plurality of n-channel thin film transistors are formed. Since the source region or drain region of the transistor 610a is n-type impurity regions 607a and 607b, the second element isolation in contact with the n-type impurity regions 607a and 607b is used. The regions 613a and 613b are p-type impurity regions. Similarly, since the source region or the drain region of the transistor 610b is also the n-type impurity regions 608a and 608b, the second element isolation regions 614a and 614b in contact with the n-type impurity regions 608a and 608b are p-type impurity regions. . By adding an impurity element imparting p-type (for example, boron (B), aluminum (Al), gallium (Ga), or the like), second element isolation regions 613 (613a and 613b) which are p-type impurity regions are added. ), 614 (614a, 614b).

First element isolation regions 602a, 602b, and 602c are provided in contact with the second element isolation regions 613a, 613b, 614a, and 614b. As shown in FIG. 1B, the element region of the transistor 610a and the element region of the transistor 610b are in contact with the n-type impurity region 607b and in contact with the second element isolation region 613b and the n-type impurity region 608a. Two element isolation regions 614a are provided, and a first element isolation region 602b is provided between the second element isolation region 613b and the second element isolation region 614a. In the top view of FIG. 1A, the element regions of the transistors 610a and 610b are surrounded by second element isolation regions 613 and 614, respectively, and further between the second element isolation regions 613 and 614. A first element isolation region 602 is formed. By providing the first element isolation region 602 and the second element isolation regions 613 and 614 in this manner, the transistor 610a and the transistor 610b are isolated and formed as individual elements.

When the element regions of the transistors having the same conductivity type are insulated and separated as shown in FIG. 1, the second element isolation region may be provided continuously over the two element regions. 27A to 27C show examples in which the formation regions of the first element isolation region and the second element isolation region are different in the NMOS configuration of FIGS. 1A to 1C. In FIG. 27, the element region of the transistor 610a and the element region of the transistor 610b are a first element isolation region 622 (622a, 622b, 622c, 622d), and a second element isolation region 615 (615a, 615b, 615c, 615d, 615e).

In FIG. 27, a second element isolation region 615b which is a p-type impurity region is continuously formed between an n-type impurity region 607b of the transistor 610a and an n-type impurity region 608a of the transistor 610b. Since the n-type impurity region 607b, the second element isolation region 615b which is a p-type impurity region, and the n-type impurity region 608a are formed adjacent to each other, PNP and PN junction are repeated. As a result, the n-type impurity regions and the p-type impurity regions are alternately provided adjacent to each other, so that the impurity regions of the same conductivity type can be insulated and separated. As described above, the second element isolation region is not necessarily provided for each single element, and may be continuously provided so as to surround a plurality of elements of the same conductivity type.

4A and 4B illustrate an example of a semiconductor device having a CMOS structure in this embodiment. FIG. 4A is a top view, FIG. 4B is a cross-sectional view taken along line AB in FIG. C) is a sectional view taken along line CD.

On the substrate 200 on which the insulating layer 201 functioning as a base film of the semiconductor layer is formed, a CMOS structure including the transistor 210a which is an n-channel thin film transistor and the transistor 210b which is a p-channel thin film transistor, and the insulating layer 206 are formed. . The transistor 210a includes an element region including n-type impurity regions 207a and 207b and a channel formation region 209a, and a gate electrode layer 205a. The transistor 210b includes an element region including p-type impurity regions 208a and 208b and a channel formation region 209b. The gate insulating layer 204 and the insulating layer 206 are formed in succession to the transistors 210a and 210b. In addition, a wiring layer 211a which is a source or drain electrode layer connected to the n-type impurity region 207a, a wiring layer 211b which is a source or drain electrode layer connected to the n-type impurity region 207b and the p-type impurity region 208a, A wiring layer 211c which is a source electrode layer or a drain electrode layer connected to the p-type impurity region 208b is provided, and the transistor 210a and the transistor 210b are electrically connected to each other by the wiring layer 211b (FIG. 4A to FIG. 4). (See (C).)

In the semiconductor layer, an element region including n-type impurity regions 207a and 207b and a channel formation region 209a constituting the transistor 210a, and an element region including p-type impurity regions 208a and 208b and a channel formation region 209b constituting the transistor 210b. Is electrically isolated by the first element isolation region 202 (202a, 202b, 202c, 202d, 202e) and the second element isolation region 213 (213a, 213b), 214 (214a, 214b).

FIG. 4 shows a case where an n-channel thin film transistor and a p-channel thin film transistor are formed. Since the source region or the drain region of the transistor 210a is the n-type impurity regions 207a and 207b, the second region in contact with the n-type impurity regions 207a and 207b. The element isolation regions 213a and 213b are p-type impurity regions. On the other hand, since the source region or the drain region of the transistor 210b is the p-type impurity regions 208a and 208b, the second element isolation regions 214a and 214b in contact with the p-type impurity regions 208a and 208b are n-type impurity regions. . Impurity elements imparting n-type (for example, phosphorus (P), arsenic (As), etc.) or impurity elements imparting p-type (for example, boron (B), aluminum (Al), gallium (Ga), etc.) ) Is added to the second element isolation region 213 (213a, 213b) which is an impurity region having a p-type and the second element isolation region 214 (214a, 214b) which is an impurity region having an n-type. Can be formed.

First element isolation regions 202a, 202b, and 202c are provided in contact with the second element isolation regions 213a, 213b, 214a, and 214b. As shown in FIG. 4B, the element region of the transistor 210a and the element region of the transistor 210b are in contact with the n-type impurity region 207b and in contact with the second element isolation region 213b and the p-type impurity region 208a. The second element isolation region 214a is provided, and the first element isolation region 202b is provided between the second element isolation region 213b and the second element isolation region 214a. 4A, the element regions of the transistor 210a and the transistor 210b are surrounded by the second element isolation regions 213 and 214, respectively, and further between the second element isolation regions 213 and 214. A first element isolation region 202 is formed. Thus, by providing the first element isolation region 202 and the second element isolation regions 213 and 214, the transistor 210a and the transistor 210b are formed as isolated elements.

In this embodiment, in order to form a plurality of semiconductor elements over an insulating surface, a semiconductor layer is not separated into a plurality of island-shaped semiconductor layers, and a plurality of element regions functioning as semiconductor elements in one semiconductor layer As the element isolation region for electrically insulating and isolating the first and second element isolation regions having high resistance, the second element isolation region having a conductivity type opposite to the source and drain regions of the element region is formed. To do.

The plurality of element regions are provided around the element region so as to surround the second element isolation region which is an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region. A first element isolation region, which is a high resistance region, is provided adjacent to the outer side of the two element isolation regions. Therefore, the adjacent first element region and second element region are the second element isolation region in contact with the first element region, the first element isolation region, and the second element isolation in contact with the second element region. Adjacent through a region.

In the case where the source region and the drain region of the first element region and the second element region have the same electric type, for example, in the case of an n-type impurity region, the second element isolation region also has the opposite conductivity type to the element region. It becomes a p-type impurity region. On the other hand, the first element region and the second element are such that the source region and the drain region of the first element region are n-type impurity regions, and the source region and the drain region of the second element region are p-type impurity regions. When the regions are of the opposite conductivity type, the second element isolation region included in each region is also combined with the element regions, and the first element region side is a p-type impurity region, and the second element region side is an n-type impurity region. It becomes.

The first element isolation region adjacent to the element region via the second element isolation region is the first element that does not selectively contribute to conductivity in order to electrically isolate the elements in one semiconductor layer. It is formed by adding an impurity element. In the present specification, “does not contribute to conductivity” means that the conductivity is not improved by adding the element.

As the first impurity element that does not contribute to conductivity (does not improve conductivity), at least one impurity element of oxygen, nitrogen, and carbon can be used. In the element isolation region to which the first impurity element is added, the conductivity decreases due to the mixing of the first impurity element that does not contribute to the conductivity, and also due to physical impact on the semiconductor layer at the time of addition (so-called sputtering effect). Increased resistance due to lower crystallinity. In the element isolation region with a high resistance, the field effect mobility is also reduced, so that the elements can be electrically isolated, while the region to which no impurity element is added maintains the field effect mobility that can function as an element. Therefore, it can be used as an element region.

The resistance of the first element isolation region is preferably 1 × 10 ¹⁰ Ω · cm or more, and the concentration of the first impurity element such as oxygen, nitrogen, or carbon is 1 × 10 ²⁰ cm ⁻³ or more and 4 × 10 ²² cm. Less than ^-3 is preferable.

The first element isolation region can be said to be amorphous because the crystallinity is lowered by the addition of the impurity element. On the other hand, since the element region is a crystalline semiconductor layer, when a semiconductor element is formed in the element region, the crystallinity of the channel formation region is higher than that of the first element isolation region, and high field effect mobility can be obtained as a semiconductor element. it can.

As the first impurity element added to the first element isolation region, a rare gas element such as argon (Ar), neon (Ne), krypton (Kr), or xenon (Xe) may be used. In addition to oxygen, nitrogen, and carbon, the addition of these rare gas elements, which are relatively large elements, can increase the physical impact on the semiconductor layer. The crystallinity of the element isolation region can be reduced.

The second element isolation region provided between the element region and the first element isolation region in contact with the element region is added with a second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region. Form.

The element region has a source region, a drain region, and a channel formation region. The source region and the drain region are impurity regions having one conductivity type (for example, an n-type impurity region or a p-type impurity region). A second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region is added to the second element isolation region, and the second element isolation region is used as a source region and a drain in the adjacent element region. The impurity region has a conductivity type opposite to that of the region. That is, when the source region and the drain region in the element region are n-type impurity regions, the adjacent second element isolation region is a p-type impurity region, and similarly, the source region and the drain region in the element region are p-type impurity regions. In some cases, the adjacent second element isolation region may be an n-type impurity region. The adjacent element region and the second element isolation region form a PN junction. Therefore, the element regions can be further insulated and separated by the second element isolation region provided between the element regions.

The present invention provides a first element isolation region which is a high resistance region by addition of a first impurity element that does not contribute to conductivity as an element isolation region for insulating and isolating element regions, and further, a source region and a drain region in the element region A semiconductor layer is separated into a plurality of element regions by providing a second element isolation region which is an impurity region by addition of a second impurity element imparting a reverse conductivity type. According to the present invention, since the element regions can be separated from each other by the effects of the first element isolation region and the second element isolation region, a higher element isolation effect can be obtained.

Note that in this specification, the element region includes an element formation region before an element is formed. Therefore, in the middle of the element manufacturing process, even if it is not completed as an element (before the formation of another electrode layer or insulating layer), it is insulated and separated into the element isolation region which is a high resistance region in the semiconductor layer. The element formation region is called an element region.

For the addition (introduction) of the impurity element in forming the first element isolation region and the second element isolation region, an ion implantation method, an (ion) doping method, or the like can be used.

Further, the element isolation region may have a concentration gradient of the first impurity element and the second impurity element. Of course, the first impurity element and the second impurity element may be added to the first and second element isolation regions at a substantially uniform concentration. That is, the concentration peak of the first impurity element and the second impurity element can be set as appropriate in the first and second element isolation regions. The second element isolation region may be an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region in contact with the second element isolation region. An impurity element imparting a mold may be contained. The second element isolation region may contain the first impurity element described above, and the second element isolation region may be added by adding the second impurity element to a part of the first element isolation region. It can also be formed.

In this embodiment, the NMOS structure and the CMOS structure are shown as examples. However, the same applies to the PMOS structure. The source region and the drain region of the element region are p-type impurity regions. A second impurity element imparting n-type conductivity may be added so as to be an impurity region. Therefore, the present invention can be used with any of an NMOS structure, a PMOS structure, and a CMOS structure.

In FIG. 1C, the gate electrode layer 605 is formed over the channel formation region 609a, the first element isolation regions 602d and 602e, and the second element isolation regions 613c and 613d in the semiconductor layer with the gate insulating layer 604 interposed therebetween. ing. In the present invention, since the element isolation region and the element region are provided in the continuous semiconductor layer, the first element isolation regions 602d and 602e, the second element isolation regions 613c and 613d, and the channel formation region 609a The area is continuous. Therefore, the surface has high flatness and does not have a steep step.

Similarly, in FIG. 4C, the gate electrode layer 205 is formed over the channel formation region 209a, the first element isolation regions 202d and 202e, the second element isolation regions 213c and 213d in the semiconductor layer via the gate insulating layer 204. Is formed. In the present invention, since the element isolation region and the element region are provided in the continuous semiconductor layer, the element which is the first element isolation regions 202d and 202e, the second element isolation regions 213c and 213d, and the channel formation region 209a The area is continuous. Therefore, the surface has high flatness and does not have a steep step.

Since the gate insulating layers 604 and 204 are formed over a highly flat semiconductor layer, the gate insulating layers 604 and 204 have good coverage and are unlikely to have a shape defect. Therefore, defects such as a leakage current and a short circuit can be prevented in the gate electrode layers 605 and 205 formed over the gate insulating layers 604 and 204 and the element region. Therefore, the semiconductor device having the NMOS structure or the CMOS structure of this embodiment is a highly reliable semiconductor device in which a short circuit between the gate electrode and the semiconductor layer due to a poor coating of the gate insulating layer and a defect such as a leakage current are prevented. Can do.

Further, in FIG. 1B, the impurity region is indicated by hatching and white background, but this does not indicate that the impurity element is not added to the white background portion, but the concentration of the impurity element in this region. This is because it is possible to intuitively understand that the distribution reflects the mask and doping conditions. This also applies to other drawings in this specification. For example, when an impurity element is added from an oblique direction rather than perpendicular to the surface of the semiconductor layer, the added region in the semiconductor layer changes.

As the substrate 200 which is a substrate having an insulating surface, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate having an insulating layer formed on the surface, or the like can be used.

As the insulating layer 201, the gate insulating layer 204, and the insulating layer 206, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be used, and a single layer or a stacked structure of two layers or three layers may be used. Note that in this specification, silicon oxynitride is a substance in which the oxygen content is higher than the nitrogen content, and can also be referred to as silicon oxide containing nitrogen. Similarly, silicon nitride oxide is a substance in which the nitrogen content is higher than the oxygen content, and can be said to be silicon nitride containing oxygen.

As other materials for the insulating layer 201, the gate insulating layer 204, and the insulating layer 206, aluminum nitride, aluminum oxynitride with an oxygen content higher than the nitrogen content, and aluminum oxynitride with a nitrogen content higher than the oxygen content Alternatively, it can be formed of a material selected from substances including aluminum oxide, diamond-like carbon (DLC), nitrogen-containing carbon, polysilazane, and other inorganic insulating materials. A material containing siloxane may be used. Note that siloxane corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aryl group) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Moreover, an oxazole resin can also be used, for example, photocurable polybenzoxazole or the like can be used.

The insulating layer 201, the gate insulating layer 204, and the insulating layer 206 are formed by a sputtering method, a PVD method (Physical Vapor Deposition), a low pressure CVD method (LPCVD method), or a CVD method (Chemical Vapor Deposition) such as a plasma CVD method, or a selection method. Droplet discharge method that can form a pattern automatically, printing method that can transfer or draw a pattern (method that forms a pattern such as screen printing or offset printing), other coating methods such as spin coating, dipping method, dispenser method, etc. Can also be used.

As the etching process for processing into a desired shape, either plasma etching (dry etching) or wet etching may be employed. Plasma etching is suitable for processing large area substrates. As an etching gas, a fluorine-based gas such as CF ₄ or NF ₃ or a chlorine-based gas such as Cl ₂ or BCl ₃ may be used, and an inert gas such as He or Ar may be appropriately added. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

Alternatively, the gate insulating layer may be formed by performing plasma treatment on the semiconductor layer. By performing the plasma treatment in a nitrogen atmosphere or an oxygen atmosphere, for example, the surface of the semiconductor layer using silicon and the vicinity thereof can be nitrided or oxidized to form a nitrogen plasma treatment layer or an oxygen plasma treatment layer. . In addition, when the gate insulating layer is subjected to oxidation treatment or nitridation treatment (or both oxidation treatment and nitridation treatment may be performed) using plasma treatment, the surface of the gate insulating layer is modified to form a denser gate insulating layer. it can. Therefore, defects such as pinholes can be suppressed and the characteristics of the semiconductor device can be improved.

As solid-phase oxidation treatment or solid-phase nitridation treatment by plasma treatment, the electron density is 1 × 10 ¹¹ cm ⁻³ or more and 1 × 10 ¹³ cm ⁻³ or less when excited by microwaves (typically 2.45 GHz), and It is preferable to use plasma having an electron temperature of 0.5 eV to 1.5 eV. This is because in the solid phase oxidation treatment or solid phase nitridation treatment, a dense insulating layer is formed at a temperature of 500 ° C. or lower and a practical reaction rate is obtained.

In the case of oxidizing the surface of the semiconductor layer by this plasma treatment, oxygen (O ₂ ) or dinitrogen monoxide (N ₂ O) and a rare gas (He, Ne, Ar, Kr, Xe) In an atmosphere containing at least one) or in an atmosphere of oxygen or dinitrogen monoxide and hydrogen (H ₂ ) and a rare gas. In the case of performing nitridation by plasma treatment, nitrogen and hydrogen are used in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe)). Plasma treatment is performed in a rare gas atmosphere or in a rare gas atmosphere with NH ₃ . As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. Note that the plasma treatment includes oxidation treatment, nitridation treatment, oxynitridation treatment, hydrogenation treatment, and surface modification treatment for a semiconductor layer, an insulating layer, and a conductive layer. When plasma excitation is performed by introduction of microwaves, plasma with a low electron temperature (3 eV or less, preferably 1.5 eV or less) and a high electron density (1 × 10 ¹¹ cm ⁻³ or more) can be generated. The surface of the semiconductor layer can be oxidized or nitrided by oxygen radicals (which may include OH radicals) and / or nitrogen radicals (which may include NH radicals) generated by this high-density plasma. When a rare gas such as argon is mixed with the plasma processing gas, oxygen radicals or nitrogen radicals can be efficiently generated by the excited species of the rare gas.

As a typical example of the semiconductor layer, the surface of the silicon layer is oxidized by plasma treatment, whereby a dense oxide layer without distortion at the interface can be formed. Further, the oxide layer can be further densified by nitriding the plasma layer by plasma treatment to form a nitride layer by replacing oxygen in the surface layer with nitrogen. Thereby, an insulating layer having a high withstand voltage can be formed.

However, in the present invention, plasma treatment is performed under conditions that do not adversely affect the electrical characteristics of the transistor.

In addition, after forming a substrate, an insulating layer, an interlayer insulating layer, and other insulating layers and conductive layers forming a semiconductor device, the substrate, the insulating layer, and the interlayer are formed by performing oxidation treatment or nitriding treatment using plasma treatment. The surface of the insulating layer may be oxidized or nitrided. When the insulating layer is oxidized or nitrided using plasma treatment, the surface of the insulating layer is modified, so that a denser insulating layer can be obtained as compared with an insulating layer formed by a CVD method or a sputtering method. Therefore, defects such as pinholes can be suppressed and the characteristics of the semiconductor device can be improved. The plasma treatment as described above can also be performed on a conductive layer such as a gate electrode layer, a source wiring layer, and a drain wiring layer, and the surface and the vicinity of the surface can be nitrided or oxidized.

The semiconductor layer is preferably formed using a single crystal semiconductor or a polycrystalline semiconductor. For example, a semiconductor layer formed over the entire surface of the substrate can be crystallized and formed on the substrate by a sputtering method, a plasma CVD method, or a low pressure CVD method. As the semiconductor material, silicon is preferable, and a silicon germanium semiconductor can also be used. As a method for crystallizing a semiconductor layer, a laser crystallization method, a crystallization method using rapid thermal annealing (RTA) or a heat treatment using a furnace annealing furnace, a crystallization method using a metal element that promotes crystallization, or a combination of these methods. Can be used.

A p-type impurity may be implanted into the semiconductor layer. For example, boron is used as the p-type impurity, and may be added at a concentration of about 5 × 10 ¹⁵ atoms / cm ³ to 1 × 10 ¹⁶ atoms / cm ³ . This is for controlling the threshold voltage of the transistor, and effectively acts when added to the channel formation regions 209a and 209b.

Note that a wiring layer and a gate electrode layer included in the transistor are indium tin oxide (ITO), indium oxide mixed with zinc oxide (ZnO), indium zinc oxide (IZO), and indium oxide mixed with silicon oxide (SiO ₂ ). Conductive material, organic indium, organic tin, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, tungsten (W), molybdenum ( Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum ( Pt), aluminum (Al), copper (Cu), silver (Ag), etc. It can be selected from a metal or an alloy thereof, or a metal nitride thereof.

Without being limited to this embodiment mode, the thin film transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed. The thin film transistor in the peripheral driver circuit region may have a single gate structure, a double gate structure, or a triple gate structure.

Therefore, when the present invention is used, the semiconductor layer can be separated into a plurality of element regions without being divided into islands. Since the step due to the end portion of the semiconductor layer does not occur and the gate insulating layer is formed on the flat semiconductor layer, the coverage of the gate insulating layer is improved. Therefore, it is possible to provide a highly reliable semiconductor device in which a short circuit between the gate electrode layer and the semiconductor layer due to a poor coating of the gate insulating layer and a defect such as a leakage current are prevented, and a method for manufacturing such a semiconductor device. . Therefore, further miniaturization and high integration can be performed in the semiconductor device, and high performance of the semiconductor device can be achieved. In addition, since defects due to such a film shape defect are reduced, production can be performed with high yield even in the manufacturing process.

(Embodiment 2)
In this embodiment mode, a nonvolatile semiconductor memory device is provided as a semiconductor device for preventing defects such as a short circuit between an electrode layer and a semiconductor layer due to a coating failure of an insulating layer and a leakage current and imparting higher reliability. An example will be described with reference to the drawings.

The nonvolatile memory element has a structure similar to that of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and is characterized in that a region capable of accumulating electric charge for a long period is provided on the channel formation region. This charge accumulation region is formed on the insulating layer and is also isolated from the surroundings, so that it is also called a floating gate electrode layer. The floating gate electrode layer is also called a charge storage layer because it has a function of storing charges. In this specification, this charge accumulation region mainly including the floating gate electrode layer is referred to as a charge accumulation layer. A control gate electrode layer is further provided on the floating gate electrode layer through an insulating layer.

The so-called floating gate type nonvolatile semiconductor memory device having such a structure is operated to store and release charges in the charge storage layer by a voltage applied to the control gate electrode layer. In other words, the data is stored by taking in and out the charges held in the charge storage layer. Specifically, injection and extraction of charges from the charge storage layer are performed by applying a high voltage between the semiconductor layer in which the channel formation region is formed and the control gate electrode layer. At this time, it is said that Fowler-Nordheim type (FN type) tunnel current (NAND type) and thermal electrons (NOR type) flow through the insulating layer on the channel formation region. Thus, the insulating layer is also called a tunnel insulating layer.

2A and 2B illustrate an example of a semiconductor device which is a nonvolatile semiconductor memory device in this embodiment. FIG. 2A is a top view and FIG. 2B is a cross-sectional view taken along line EF in FIG. FIG. 2C is a cross-sectional view taken along line GH.

A memory element 270 that is a nonvolatile memory element and an interlayer insulating layer 258 are formed over a substrate 250 over which an insulating layer 251 that functions as a base film of a semiconductor layer is formed. The memory element 270 includes an element region including high-concentration impurity regions 261a and 261b, low-concentration impurity regions 262a and 262b, and a channel formation region 253, a first insulating layer 254, a charge storage layer 271, a second insulating layer 256, a control It includes a gate electrode layer 272 and wiring layers 259a and 259b. Second element isolation regions 273a and 273b are formed in contact with the element region, and first element isolation regions 252a and 252b are formed adjacent to the outer side. Has been. (See FIGS. 2A to 2C.)

The high-concentration impurity regions 261a and 261b and the low-concentration impurity regions 262a and 262b contain an impurity element imparting n-type (such as phosphorus (P) or arsenic (As)) as an impurity element imparting one conductivity type. The high concentration impurity regions 261a and 261b are regions functioning as a source and a drain in the memory element.

In the semiconductor layer, an element region including the high-concentration impurity regions 261a and 261b, the low-concentration impurity regions 262a and 262b, and the channel formation region 253 is a second element isolation region 273 (273a, 273b, 273c, and 273d) surrounding the periphery. In addition, the first element isolation region 252 (252a, 252b, 252c, 252d) is electrically isolated from other semiconductor elements.

In this embodiment, in order to form a plurality of semiconductor elements over an insulating surface, a semiconductor layer is not separated into a plurality of island-shaped semiconductor layers, and a plurality of element regions functioning as semiconductor elements in one semiconductor layer As the element isolation region for electrically insulating and isolating the first and second element isolation regions having high resistance, the second element isolation region having a conductivity type opposite to the source and drain regions of the element region is formed. To do.

The plurality of element regions are provided around the element region so as to surround the second element isolation region which is an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region. A first element isolation region, which is a high resistance region, is provided adjacent to the outer side of the two element isolation regions. Therefore, the adjacent first element region and second element region are the second element isolation region in contact with the first element region, the first element isolation region, and the second element isolation in contact with the second element region. Adjacent through a region.

In the case where the source region and the drain region of the first element region and the second element region have the same electric type, for example, in the case of an n-type impurity region, the second element isolation region also has the opposite conductivity type to the element region. It becomes a p-type impurity region. On the other hand, the first element region and the second element are such that the source region and the drain region of the first element region are n-type impurity regions, and the source region and the drain region of the second element region are p-type impurity regions. When the regions are of the opposite conductivity type, the second element isolation region included in each region is also combined with the element regions, and the first element region side is a p-type impurity region, and the second element region side is an n-type impurity region. It becomes.

The first element isolation region adjacent to the element region via the second element isolation region is the first element that does not selectively contribute to conductivity in order to electrically isolate the elements in one semiconductor layer. It is formed by adding an impurity element.

As the first impurity element that does not contribute to conductivity (does not improve conductivity), at least one impurity element of oxygen, nitrogen, and carbon can be used. In the element isolation region to which the first impurity element is added, the conductivity decreases due to the mixing of the first impurity element that does not contribute to the conductivity, and also due to physical impact on the semiconductor layer at the time of addition (so-called sputtering effect). Increased resistance due to lower crystallinity. In the element isolation region with a high resistance, the field effect mobility is also reduced, so that the elements can be electrically isolated, while the region to which no impurity element is added maintains the field effect mobility that can function as an element. Therefore, it can be used as an element region.

The resistance of the first element isolation region is preferably 1 × 10 ¹⁰ Ω · cm or more, and the concentration of the first impurity element such as oxygen, nitrogen, or carbon is 1 × 10 ²⁰ cm ⁻³ or more and 4 × 10 ²² cm. Less than ^-3 is preferable.

The first element isolation region can be said to be amorphous because the crystallinity is lowered by the addition of the impurity element. On the other hand, since the element region is a crystalline semiconductor layer, when a semiconductor element is formed in the element region, the crystallinity of the channel formation region is higher than that of the first element isolation region, and high field effect mobility can be obtained as a semiconductor element. it can.

As the first impurity element added to the first element isolation region, a rare gas element such as argon (Ar), neon (Ne), krypton (Kr), or xenon (Xe) may be used. In addition to oxygen, nitrogen, and carbon, the addition of these rare gas elements, which are relatively large elements, can increase the physical impact on the semiconductor layer. The crystallinity of the element isolation region can be reduced.

The second element isolation region provided between the element region and the first element isolation region in contact with the element region is added with a second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region. Form.

The element region has a source region, a drain region, and a channel formation region. The source region and the drain region are impurity regions having one conductivity type (for example, an n-type impurity region or a p-type impurity region). A second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region is added to the second element isolation region, and the second element isolation region is used as a source region and a drain in the adjacent element region. The impurity region has a conductivity type opposite to that of the region. That is, when the source region and the drain region in the element region are n-type impurity regions, the adjacent second element isolation region is a p-type impurity region, and similarly, the source region and the drain region in the element region are p-type impurity regions. In some cases, the adjacent second element isolation region may be an n-type impurity region. The adjacent element region and the second element isolation region form a PN junction. Therefore, the element regions can be further insulated and separated by the second element isolation region provided between the element regions.

The present invention provides a first element isolation region which is a high resistance region by addition of a first impurity element that does not contribute to conductivity as an element isolation region for insulating and isolating element regions, and further, a source region and a drain region in the element region A semiconductor layer is separated into a plurality of element regions by providing a second element isolation region which is an impurity region by addition of a second impurity element imparting a reverse conductivity type. According to the present invention, since the element regions can be separated from each other by the effects of the first element isolation region and the second element isolation region, a higher element isolation effect can be obtained.

For the addition (introduction) of the impurity element in forming the first element isolation region and the second element isolation region, an ion implantation method, an (ion) doping method, or the like can be used.

Further, the element isolation region may have a concentration gradient of the first impurity element and the second impurity element. Of course, the first impurity element and the second impurity element may be added to the first and second element isolation regions at a substantially uniform concentration. That is, the concentration peak of the first impurity element and the second impurity element can be set as appropriate in the first and second element isolation regions. The second element isolation region may be an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region in contact with the second element isolation region. An impurity element imparting a mold may be contained. The second element isolation region may contain the first impurity element described above, and the second element isolation region may be added by adding the second impurity element to a part of the first element isolation region. It can also be formed.

FIG. 2 shows a case where a plurality of memory elements are formed, and the second element isolation region 273 (273a, 273b, 273c, 273d) is provided in contact with the n-type high concentration impurity regions 261a, 261b. An impurity element imparting p-type conductivity (e.g., boron (B), aluminum (Al), gallium (Ga), or the like) may be added as the second impurity element imparting hydrogen to form a p-type impurity region.

FIG. 2C illustrates the first insulating layer 254, the charge storage layer 271, and the channel formation region 253, the first element isolation regions 252c and 252d, and the second element isolation regions 273c and 273d in the semiconductor layer. A control gate electrode layer 272 is formed with the second insulating layer 256 interposed therebetween. In the present invention, since the element isolation region and the element region are provided in the continuous semiconductor layer, the first element isolation regions 252c and 252d, the second element isolation regions 273c and 273d, and the channel formation region 253 The area is continuous. Therefore, the surface has high flatness and does not have a steep step.

Since the first insulating layer 254 is formed over a highly flat semiconductor layer, the first insulating layer 254 has good coverage and is unlikely to have a shape defect. Accordingly, defects such as a leakage current and a short circuit in the charge storage layer 271 and the channel formation region 253 formed over the first insulating layer 254 can be prevented. Therefore, the semiconductor device which is the nonvolatile semiconductor memory device of this embodiment is a highly reliable semiconductor in which defects such as a short circuit and a leakage current between the charge storage layer and the semiconductor layer due to a coating failure of the first insulating layer 254 are prevented. It can be a device.

FIG. 2 shows an example in which the element region in the semiconductor layer is smaller in the line GH direction than the charge storage layer 271 and larger in the line EF direction than the control gate electrode layer 272. However, the present invention is not limited to this. Not. 26 and 3 show other combinations of the element region, the charge storage layer, and the control gate electrode layer. 3 and FIG. 26 are the same as those in FIG. 2 except for the charge storage layer and the control gate electrode layer, so that the description thereof is omitted.

In the memory element 290 of FIG. 26, the element region in the semiconductor layer is substantially the same as the charge storage layer 291 in the line GH direction, and the charge storage layer 291 is substantially the same as the control gate electrode layer 292 in the line EF direction. is there. Accordingly, in FIG. 26B, the end portion of the charge accumulation layer 291 and the end portion of the control gate electrode layer 292 are substantially aligned with each other through the second insulating layer 256. In FIG. The end portion of the channel formation region 253 in the element region and the end portion of the charge storage layer 291 substantially coincide with each other through the one insulating layer 254.

In the memory element 280 of FIG. 3, the element region in the semiconductor layer is larger in the line GH direction than the charge storage layer 281, and the charge storage layer 281 is smaller in the line EF direction than the control gate electrode layer 282. Therefore, in FIG. 3B, the end portion of the charge accumulation layer 281 is located inside the end portion of the control gate electrode layer 282 with the second insulating layer 256 interposed therebetween. In FIG. The end of the channel formation region 253 in the element region is located outside the end of the charge storage layer 281 with the insulating layer 254 interposed therebetween.

As described above, the capacitance formed in the second insulating layer 256 between the charge storage layer and the control gate electrode layer, the charge storage layer, and the charge storage layer, depending on the combination of the sizes of the element region, the charge storage layer, and the control gate electrode layer. Since the capacitance formed in the first insulating layer 254 between the semiconductor layers can be controlled, the voltage value to be applied can also be controlled.

As the interlayer insulating layer 258, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be used, and a single layer or a stacked structure of two layers or three layers may be used. Note that in this specification, silicon oxynitride is a substance in which the oxygen content is higher than the nitrogen content, and can also be referred to as silicon oxide containing nitrogen. Similarly, silicon nitride oxide is a substance in which the nitrogen content is higher than the oxygen content, and can be said to be silicon nitride containing oxygen.

As another material for the interlayer insulating layer 258, aluminum nitride, aluminum oxynitride having an oxygen content higher than the nitrogen content, aluminum nitride oxide or aluminum oxide having a nitrogen content higher than the oxygen content, diamond-like carbon ( DLC), nitrogen-containing carbon, polysilazane, and other materials including inorganic insulating materials. A material containing siloxane may be used. Note that siloxane corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aryl group) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Moreover, an oxazole resin can also be used, for example, photocurable polybenzoxazole or the like can be used.

The interlayer insulating layer 258 is formed by a sputtering method, a PVD method (Physical Vapor Deposition), a low pressure CVD method (LPCVD method), a CVD method such as a plasma CVD method (Chemical Vapor Deposition), or a droplet capable of selectively forming a pattern. An ejection method, a printing method that can transfer or draw a pattern (a method for forming a pattern such as screen printing or offset printing), a coating method such as a spin coating method, a dipping method, a dispenser method, or the like can also be used.

As the etching process for processing into a desired shape, either plasma etching (dry etching) or wet etching may be employed. Plasma etching is suitable for processing large area substrates. As an etching gas, a fluorine-based gas such as CF ₄ or NF ₃ or a chlorine-based gas such as Cl ₂ or BCl ₃ may be used, and an inert gas such as He or Ar may be appropriately added. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

The semiconductor layer is preferably formed using a single crystal semiconductor or a polycrystalline semiconductor. For example, a semiconductor layer formed over the entire surface of the substrate can be crystallized and formed on the substrate by a sputtering method, a plasma CVD method, or a low pressure CVD method. As the semiconductor material, silicon is preferable, and a silicon germanium semiconductor can also be used. As a method for crystallizing a semiconductor layer, a laser crystallization method, a crystallization method using rapid thermal annealing (RTA) or a heat treatment using a furnace annealing furnace, a crystallization method using a metal element that promotes crystallization, or a combination of these methods. Can be used.

A p-type impurity may be implanted into the semiconductor layer. For example, boron is used as the p-type impurity, and may be added at a concentration of about 5 × 10 ¹⁵ atoms / cm ³ to 1 × 10 ¹⁶ atoms / cm ³ . This is for controlling the threshold voltage of the semiconductor element, and acts effectively when added to the channel formation region 253.

The first insulating layer 254 may be formed using silicon oxide or a stacked structure of silicon oxide and silicon nitride. The first insulating layer 254 may be formed by depositing an insulating layer by a plasma CVD method or a low pressure CVD method, but is preferably formed by solid phase oxidation or solid phase nitridation by plasma treatment. This is because an insulating layer formed by oxidizing or nitriding a semiconductor layer (typically a silicon layer) by plasma treatment is dense, has high withstand voltage, and is excellent in reliability. Since the first insulating layer 254 is used as a tunnel insulating layer for injecting charges into the charge storage layers 271, 281 and 291, such a strong one is preferable. The first insulating layer 254 is preferably formed to a thickness of 1 nm to 20 nm, preferably 3 nm to 6 nm. For example, when the gate length is 600 nm, the first insulating layer 254 can be formed to a thickness of 3 nm to 6 nm.

As solid-phase oxidation treatment or solid-phase nitridation treatment by plasma treatment, the electron density is 1 × 10 ¹¹ cm ⁻³ or more and 1 × 10 ¹³ cm ⁻³ or less when excited by microwaves (typically 2.45 GHz), and It is preferable to use plasma having an electron temperature of 0.5 eV to 1.5 eV. This is because in the solid phase oxidation treatment or solid phase nitridation treatment, a dense insulating layer is formed at a temperature of 500 ° C. or lower and a practical reaction rate is obtained.

In the case of oxidizing the surface of the semiconductor layer by this plasma treatment, oxygen (O ₂ ) or dinitrogen monoxide (N ₂ O) and a rare gas (He, Ne, Ar, Kr, Xe) In an atmosphere containing at least one) or in an atmosphere of oxygen or dinitrogen monoxide and hydrogen (H ₂ ) and a rare gas. In the case of performing nitridation by plasma treatment, nitrogen and hydrogen are used in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe)). Plasma treatment is performed in a rare gas atmosphere or in a rare gas atmosphere with NH ₃ . As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. Note that the plasma treatment includes oxidation treatment, nitridation treatment, oxynitridation treatment, hydrogenation treatment, and surface modification treatment for a semiconductor layer, an insulating layer, and a conductive layer. When plasma excitation is performed by introduction of microwaves, plasma with a low electron temperature (3 eV or less, preferably 1.5 eV or less) and a high electron density (1 × 10 ¹¹ cm ⁻³ or more) can be generated. The surface of the semiconductor layer can be oxidized or nitrided by oxygen radicals (which may include OH radicals) and / or nitrogen radicals (which may include NH radicals) generated by this high-density plasma. When a rare gas such as argon is mixed with the plasma processing gas, oxygen radicals or nitrogen radicals can be efficiently generated by the excited species of the rare gas.

In FIG. 2, an example of a suitable first insulating layer 254 formed by plasma treatment is that a silicon oxide layer is formed with a thickness of 3 nm to 6 nm on a semiconductor layer by plasma treatment under an oxygen atmosphere, and then a nitrogen atmosphere. Below, a nitrogen plasma treatment layer is formed by treating the surface of the silicon oxide layer with nitriding plasma. Specifically, first, a silicon oxide layer is formed with a thickness of 3 nm to 6 nm on the semiconductor layer by plasma treatment in an oxygen atmosphere. Then, a nitrogen plasma processing layer having a high nitrogen concentration is provided on or near the surface of the silicon oxide layer by subsequently performing plasma processing in a nitrogen atmosphere. Note that the vicinity of the surface means a depth of approximately 0.5 nm to 1.5 nm from the surface of the silicon oxide layer. For example, by performing plasma treatment in a nitrogen atmosphere, a structure containing nitrogen at a ratio of 20 to 50 atomic% at a depth of approximately 1 nm from the surface of the silicon oxide layer is obtained.

By oxidizing the surface of a silicon layer as a typical example of the semiconductor layer by plasma treatment, a dense oxide layer without distortion at the interface can be formed. Further, the oxide layer can be further densified by nitriding the plasma layer by plasma treatment to form a nitride layer by replacing oxygen in the surface layer with nitrogen. Thereby, an insulating layer having a high withstand voltage can be formed.

In any case, the heat formed at 950 ° C. to 1050 ° C. even when a glass substrate having a heat resistant temperature of 700 ° C. or less is used by using the solid phase oxidation treatment or solid phase nitridation treatment by the plasma treatment as described above. An insulating layer equivalent to the oxide film can be obtained. That is, a highly reliable tunnel insulating layer can be formed as the tunnel insulating layer of the nonvolatile memory element.

The charge storage layers 271, 281, and 291 are formed over the first insulating layer 254. The charge storage layers 271, 281, and 291 may be a single layer or a stack of a plurality of layers.

As the semiconductor material for forming the charge storage layers 271, 281, and 291, the charge storage layers 271, 281, and 291 can be typically formed using silicon, a silicon compound, germanium, or a germanium compound. As the silicon compound, silicon germanium, metal nitride, metal oxide, or the like containing silicon nitride, silicon nitride oxide, silicon carbide, germanium at a concentration of 10 atomic% or more can be used. A typical example of the germanium compound is silicon germanium. In this case, it is preferable that germanium is contained at 10 atomic% or more with respect to silicon.

The charge storage layer functioning as a floating gate is applied to the nonvolatile semiconductor memory device according to the present invention for the purpose of storing charges, but other materials can be applied as long as they have the same function. For example, a ternary semiconductor containing germanium may be used. Further, the semiconductor material may be hydrogenated. Further, it can be replaced with an oxide or nitride layer of germanium or a germanium compound as a function as a charge storage layer of the nonvolatile memory element.

In addition, a metal nitride or a metal oxide can be used for forming the charge storage layers 271, 281, and 291. As the metal nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium nitride, or the like can be used. As the metal oxide, tantalum oxide, titanium oxide, tin oxide, or the like can be used.

Further, the charge storage layers 271, 281, and 291 may be formed by a stacked structure of the above materials. When the above-described silicon or silicon compound, metal nitride or metal oxide layer is provided on the upper layer side of the layer formed of germanium or germanium compound, a barrier for water resistance and chemical resistance is provided in the manufacturing process. Can be used as a layer. Thereby, the handling of the substrate in the photolithography process, the etching process, and the cleaning process becomes easy, and the productivity can be improved. That is, the charge storage layer can be easily processed.

The second insulating layer 256 includes one layer or a plurality of layers such as silicon oxide, silicon oxynitride (SiOxNy) (x> y> 0), silicon nitride (SiNx), or silicon nitride oxide (SiNxOy) (x> y> 0). Are formed by a low pressure CVD method or a plasma CVD method. The second insulating layer 256 may be formed using aluminum oxide (AlOx), hafnium oxide (HfOx), or tantalum oxide (TaOx). The thickness of the second insulating layer 256 is 1 nm to 20 nm, preferably 5 to 10 nm. For example, a silicon nitride layer deposited to a thickness of 3 nm and a silicon oxide layer deposited to a thickness of 5 nm can be used. Further, plasma treatment is performed on the surfaces of the charge storage layers 271, 281, and 291 to form a nitride film (for example, silicon nitride when silicon is used as the charge storage layers 271, 281, and 291). May be. In any case, the first insulating layer 254 and the second insulating layer 256 have one or both of the sides in contact with the charge storage layers 271, 281, and 291 as a nitride film or a layer subjected to nitriding treatment. Oxidation of the accumulation layers 271 281 291 can be prevented.

The control gate electrode layers 272, 282, and 292 are metals selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr), niobium (Nb), or the like, or these metals It is preferable to form with an alloy material or a compound material whose main component is. Alternatively, polycrystalline silicon to which an impurity element such as phosphorus is added can be used. In addition, the control gate electrode layers 272, 282, and 292 may be formed using a stacked structure of one or more metal nitride layers and the above metal layer. As the metal nitride, tungsten nitride, molybdenum nitride, or titanium nitride can be used. By providing the metal nitride layer, the adhesion of the metal layer can be improved and peeling can be prevented. In addition, since the metal nitride such as tantalum nitride has a high work function, the thickness of the first insulating layer 254 can be increased by a synergistic effect with the second insulating layer 256.

The wiring layers 259a and 259b are made of indium tin oxide (ITO), IZO (indium zinc oxide) in which indium oxide is mixed with zinc oxide (ZnO), conductive material in which indium oxide is mixed with silicon oxide (SiO ₂ ), organic indium , Organic tin, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, tungsten (W), molybdenum (Mo), zirconium ( Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum ( Al), copper (Cu), silver (Ag) and other metals or alloys thereof, Alternatively, the metal nitride can be selected.

In order to inject electrons into the charge storage layer, there are a method using thermal electrons and a method using FN type tunnel current. When thermoelectrons are used, a positive voltage is applied to the control gate electrode layer, and a high voltage is applied to the drain to generate thermoelectrons. Thereby, thermoelectrons can be injected into the charge storage layer. When the FN type tunnel current is used, a positive voltage is applied to the control gate electrode layer and injected from the semiconductor layer into the charge storage layer by the FN type tunnel current.

As an example of a semiconductor device using the present invention, nonvolatile semiconductor memory devices having various modes having a nonvolatile memory element can be obtained. FIG. 12 shows an example of an equivalent circuit of a nonvolatile memory cell array. The memory cell MS01 that stores 1-bit information includes a selection transistor S01 and a nonvolatile memory element M01. The selection transistor S01 is inserted in series between the bit line BL0 and the nonvolatile memory element M01, and the gate is connected to the word line WL1. The gate of the nonvolatile memory element M01 is connected to the word line WL11. When writing data to the nonvolatile memory element M01, if the word line WL1 and the bit line BL0 are set to the H level, the bit line BL1 is set to the L level, and a high voltage is applied to the word line WL11, the charge storage layer is charged as described above. Is accumulated. When erasing data, the word line WL1 and the bit line BL0 are set to H level, and a negative high voltage is applied to the word line WL11.

In the memory cell MS01, an element region 30 formed by separating the select transistor S01 and the nonvolatile memory element M01 by an element isolation region to which an impurity element is added in a semiconductor layer continuously formed on an insulating surface. , 32 can prevent interference with other selection transistors or nonvolatile memory elements. Further, since both the select transistor S01 and the nonvolatile memory element M01 in the memory cell MS01 are n-channel type, the wiring connecting the two elements can be omitted by forming both in one element region. .

FIG. 13 shows an equivalent circuit of a NOR type memory cell array in which a nonvolatile memory element is connected to a bit line. In this memory cell array, word lines WL and bit lines BL are arranged so as to intersect with each other, and nonvolatile memory elements are arranged at each intersection. In the NOR type memory cell array, the drains of the individual nonvolatile memory elements are connected to the bit lines BL. The sources of the nonvolatile memory elements are commonly connected to the source line SL.

Also in this case, in the memory cell MS01, the nonvolatile memory element M01 is formed by the element region 32 formed by being separated by the element isolation region to which the impurity element is added in the semiconductor layer continuously formed on the insulating surface. Accordingly, interference with other nonvolatile memory elements can be prevented without separating the semiconductor layer into a plurality of island-shaped semiconductor layers. Further, a plurality of nonvolatile memory elements (for example, M01 to M23 shown in FIG. 13) are treated as one block, and an impurity element is added in a semiconductor layer in which these nonvolatile memory elements are continuously formed on an insulating surface. By forming in the element region formed by being separated by the formed element isolation region, an erasing operation can be performed in block units.

The operation of the NOR type memory cell array is as follows, for example. In data writing, the source line SL is set to 0 V, a high voltage is applied to the word line WL selected for writing data, and a potential corresponding to data “0” and “1” is applied to the bit line BL. For example, H level and L level potentials are applied to the bit line BL for “0” and “1”, respectively. In order to write “0” data, in the nonvolatile memory element to which the H level is given, hot electrons are generated near the drain and injected into the charge storage layer. In the case of “1” data, such electron injection does not occur.

  In a memory cell to which “0” data is given, hot electrons are generated in the vicinity of the drain due to a strong lateral electric field between the drain and the source, and this is injected into the charge storage layer. As a result, the state in which the threshold voltage is increased by the injection of electrons into the charge storage layer is “0”. In the case of “1” data, hot electrons are not generated, electrons are not injected into the charge storage layer, and a low threshold voltage state, that is, an erased state is maintained.

When erasing data, a positive voltage of about 10 V is applied to the source line SL, and the bit line BL is left floating. Then, a negative high voltage is applied to the word line WL (a negative high voltage is applied to the control gate), and electrons are extracted from the charge storage layer. As a result, the data “1” is erased.

For data reading, the source line SL is set to 0V and the bit line BL is set to about 0.8V, and the selected word line WL is set to an intermediate value between the threshold values of data “0” and “1”. A voltage is applied, and the presence / absence of current draw in the nonvolatile memory element is determined by a sense amplifier connected to the bit line BL.

FIG. 14 shows an equivalent circuit of a NAND memory cell array. A NAND cell NS1 in which a plurality of nonvolatile memory elements are connected in series is connected to the bit line BL. A plurality of NAND-type cells gather to constitute a block BLK. The block BLK1 shown in FIG. 14 has 32 word lines (word lines WL0 to WL31). The nonvolatile memory elements located in the same row of the block BLK1 are commonly connected to word lines corresponding to this row.

In this case, since the select transistors S1 and S2 and the nonvolatile memory elements M0 to M31 are connected in series, these may be formed as a single semiconductor layer 34. Accordingly, wiring for connecting the nonvolatile memory elements can be omitted, so that integration can be achieved. Further, it is possible to easily separate adjacent NAND cells. Further, the semiconductor layer 36 of the select transistors S1 and S2 and the semiconductor layer 38 of the NAND cell may be formed separately. When performing an erasing operation for extracting charges from the charge storage layers of the nonvolatile memory elements M0 to M31, the erasing operation can be performed in units of the NAND type cells. Further, the nonvolatile memory elements (for example, the row of M30) commonly connected to one word line may be formed by one semiconductor layer 40.

The write operation is executed after the NAND cell NS1 is in the erased state, that is, the threshold value of each nonvolatile memory element of the NAND cell NS1 is set to a negative voltage state. Writing is performed in order from the memory element M0 on the source line SL side. An example of writing to the memory element M0 is as follows.

In FIG. 24A, when "0" is written, for example, Vcc (power supply voltage) is applied to the selection gate line SG2 to turn on the selection transistor S2 and to set the bit line BL to 0 V (ground voltage). The selection gate line SG1 is set to 0V, and the selection transistor S1 is turned off. Next, the word line WL0 connected to the nonvolatile memory element M0 is set to the high voltage Vpgm (about 20V), and the other word lines are set to the intermediate voltage Vpass (about 10V). Since the voltage of the bit line BL is 0V, the potential of the channel formation region of the selected nonvolatile memory element M0 is 0V. Since the potential difference between the word line WL0 and the channel formation region of the nonvolatile memory element M0 is large, electrons are injected into the charge storage layer of the memory cell M0 by the FN tunnel current as described above. As a result, the threshold voltage of the nonvolatile memory element M0 becomes positive (a state in which “0” is written).

On the other hand, when “1” is written, the bit line BL is set to Vcc (power supply voltage), for example, as shown in FIG. Since the voltage of the selection gate line SG2 is Vcc, the selection transistor S2 is cut off when the gate voltage of the selection transistor S2 becomes Vth> Vcc. Accordingly, the channel formation region of the nonvolatile memory element M0 is in a floating state. Next, when a high voltage Vpgm (20 V) is applied to the word line WL0 and an intermediate voltage Vpass (10 V) is applied to the other word lines, a nonvolatile memory element is formed by capacitive coupling between each word line and the channel formation region. The voltage of the channel formation region of M0 rises from Vcc-Vth to about 8V, for example. The voltage of the channel formation region is boosted, but unlike the case of writing “0”, the potential difference between the word line WL0 and the channel formation region of the nonvolatile memory element M0 is small. Therefore, electron injection due to the FN tunnel current does not occur in the charge storage layer of the nonvolatile memory element M0. Therefore, the threshold value of the nonvolatile memory element M0 is kept in a negative state (a state where “1” is written).

When performing the erase operation, as shown in FIG. 25A, a negative high voltage (Vers) is applied to the selected word line (WL0), and the word line WL of the non-selected nonvolatile memory element is selected. A voltage Von (eg, 3V) is applied to the gate line SG1 and the selection gate line SG2, and a conduction voltage Vopen (0V) is applied to the bit line BL and the source line SL. As described in the above embodiment, electrons in the charge storage layer of the selected nonvolatile memory element can be emitted. As a result, the threshold voltage of the selected nonvolatile memory element is shifted in the negative direction.

In the reading operation shown in FIG. 25B, the word line WL0 connected to the nonvolatile memory element M0 selected for reading is set to the voltage Vr (for example, 0 V), and the word lines WL1 to WL31 and the selection gates of the non-selected memory cells are selected. The lines SG1 and SG2 are set to the read intermediate voltage Vread that is slightly higher than the power supply voltage. That is, as shown in FIG. 13, the memory elements other than the selected memory element function as transfer transistors. Thus, it is detected whether or not a current flows through the nonvolatile memory element M0 selected for reading. That is, when the data stored in the nonvolatile memory element M0 is “0”, the nonvolatile memory element M0 is off, and the bit line BL is not discharged. On the other hand, in the case of “1”, since the nonvolatile memory element M0 is turned on, the bit line BL is discharged.

FIG. 19 shows an example of a circuit block diagram of a nonvolatile semiconductor memory device. In the nonvolatile semiconductor memory device, the memory cell array 52 and the peripheral circuit 54 are formed on the same substrate. The memory cell array 52 has a configuration as shown in FIG. 12, FIG. 13, and FIG. The configuration of the peripheral circuit 54 is as follows.

A row decoder 62 for selecting a word line and a column decoder 64 for selecting a bit line are provided around the memory cell array 52. The address is sent to the control circuit 58 via the address buffer 56, and the internal row address signal and the internal column address signal are transferred to the row decoder 62 and the column decoder 64, respectively.

For writing and erasing data, a potential obtained by boosting the power supply potential is used. Therefore, a booster circuit 60 controlled by the control circuit 58 according to the operation mode is provided. The output of the booster circuit 60 is supplied to the word line W and the bit line BL via the row decoder 62 and the column decoder 64. The sense amplifier 66 receives the data output from the column decoder 64. Data read by the sense amplifier 66 is held in the data buffer 68, and the data is randomly accessed under the control of the control circuit 58 and output via the data input / output buffer 70. The write data is temporarily held in the data buffer 68 via the data input / output buffer 70 and transferred to the column decoder 64 under the control of the control circuit 58.

Thus, in the nonvolatile semiconductor memory device, it is necessary to use a potential different from the power supply potential in the memory cell array 52. Therefore, it is desirable that at least the memory cell array 52 and the peripheral circuit 54 are electrically isolated from each other.

Therefore, when the present invention is used, the semiconductor layer can be separated into a plurality of element regions without being divided into islands. Since the step due to the end portion of the semiconductor layer does not occur and the insulating layer is formed on the flat semiconductor layer, the coverage of the insulating layer is improved. Therefore, a semiconductor device which is a highly reliable nonvolatile semiconductor memory device in which defects such as a short circuit between the charge storage layer, the control gate electrode layer and the semiconductor layer and a leakage current due to a poor coating of the insulating layer are prevented, and such A method for manufacturing a semiconductor device can be provided. Therefore, further miniaturization and high integration can be performed in the semiconductor device, and high performance of the semiconductor device can be achieved. In addition, since defects due to such a film shape defect are reduced, production can be performed with high yield even in the manufacturing process.

(Embodiment 3)
In this embodiment mode, a memory element (memory) that aims to prevent defects such as a short circuit between a gate electrode layer and a semiconductor layer and a leakage current due to a coating failure of an insulating layer in a semiconductor element and to provide higher reliability. An example of a semiconductor device having an element) is described with reference to drawings. FIG. 15 is a top view of the semiconductor device of this embodiment, FIG. 16A is a cross-sectional view taken along line I-J in FIG. 15, and FIG.

FIG. 15 shows an equivalent circuit of a NOR type memory cell array in which the nonvolatile memory elements M (M01, M02, M03) are connected to the bit lines BL (BL0, BL1, BL2). In this memory cell array, word lines WL (WL1, WL2, WL3) and bit lines BL (BL0, BL1, BL2) are arranged so as to intersect with each other, and nonvolatile memory elements (M01, M02, M03) are arranged at each intersection. Is arranged. In the NOR type memory cell array, the drains of the individual nonvolatile memory elements (M01, M02, M03) are connected to the bit lines BL (BL0, BL1, BL2). Sources of nonvolatile memory elements are commonly connected to source lines SL (SL0, SL1, SL2).

In FIG. 15, the memory elements M01, M02, and M03 have drains connected to the bit line BL305 (305a and 305b) and sources connected to the source line SL306, respectively. The memory element M01 includes an element region 302a, a charge storage layer 303a, and a control gate electrode layer 304a. The memory element M02 includes an element region 302b, a charge storage layer 303b, and a control gate electrode layer 304b, and includes a first insulating layer 312, A second insulating layer 313 and an interlayer insulating layer 314 are formed continuously with the memory elements M01 and M02. Note that the element region 302a and the element region 302b each have a channel formation region, a high-concentration n-type impurity region that functions as a source and a drain, and a low-concentration impurity region.

In the semiconductor layer, an element region 302a constituting the memory element M01 and an element region 302b constituting the memory element M02 are divided into a first element isolation region 301 (301a, 301b, 301c, 301d, 301e) and a second element isolation. The regions 315 (315a, 315b) and 316 (316a, 316b, 316c, 316d) are electrically separated.

In this embodiment, in order to form a plurality of semiconductor elements over an insulating surface, a semiconductor layer is not separated into a plurality of island-shaped semiconductor layers, and a plurality of element regions functioning as semiconductor elements in one semiconductor layer As the element isolation region for electrically insulating and isolating the first and second element isolation regions having high resistance, the second element isolation region having a conductivity type opposite to the source and drain regions of the element region is formed. To do.

The plurality of element regions are provided around the element region so as to surround the second element isolation region which is an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region. A first element isolation region, which is a high resistance region, is provided adjacent to the outer side of the two element isolation regions. Therefore, the adjacent first element region and second element region are the second element isolation region in contact with the first element region, the first element isolation region, and the second element isolation in contact with the second element region. Adjacent through a region.

In the case where the source region and the drain region of the first element region and the second element region have the same electric type, for example, in the case of an n-type impurity region, the second element isolation region also has the opposite conductivity type to the element region. It becomes a p-type impurity region. On the other hand, the first element region and the second element are such that the source region and the drain region of the first element region are n-type impurity regions, and the source region and the drain region of the second element region are p-type impurity regions. When the regions are of the opposite conductivity type, the second element isolation region included in each region is also combined with the element regions, and the first element region side is a p-type impurity region, and the second element region side is an n-type impurity region. It becomes.

The first element isolation region adjacent to the element region via the second element isolation region is the first element that does not selectively contribute to conductivity in order to electrically isolate the elements in one semiconductor layer. It is formed by adding an impurity element.

As the first impurity element that does not contribute to conductivity (does not improve conductivity), at least one impurity element of oxygen, nitrogen, and carbon can be used. In the element isolation region to which the first impurity element is added, the conductivity decreases due to the mixing of the first impurity element that does not contribute to the conductivity, and also due to physical impact on the semiconductor layer at the time of addition (so-called sputtering effect). Increased resistance due to lower crystallinity. In the element isolation region with a high resistance, the field effect mobility is also reduced, so that the elements can be electrically isolated, while the region to which no impurity element is added maintains the field effect mobility that can function as an element. Therefore, it can be used as an element region.

The resistance of the first element isolation region is preferably 1 × 10 ¹⁰ Ω · cm or more, and the concentration of the first impurity element such as oxygen, nitrogen, or carbon is 1 × 10 ²⁰ cm ⁻³ or more and 4 × 10 ²² cm. Less than ^-3 is preferable.

The first element isolation region can be said to be amorphous because the crystallinity is lowered by the addition of the impurity element. On the other hand, since the element region is a crystalline semiconductor layer, when a semiconductor element is formed in the element region, the crystallinity of the channel formation region is higher than that of the first element isolation region, and high field effect mobility can be obtained as a semiconductor element. it can.

As the first impurity element added to the first element isolation region, a rare gas element such as argon (Ar), neon (Ne), krypton (Kr), or xenon (Xe) may be used. In addition to oxygen, nitrogen, and carbon, the addition of these rare gas elements, which are relatively large elements, can increase the physical impact on the semiconductor layer. The crystallinity of the element isolation region can be reduced.

The second element isolation region provided between the element region and the first element isolation region in contact with the element region is added with a second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region. Form.

The element region has a source region, a drain region, and a channel formation region. The source region and the drain region are impurity regions having one conductivity type (for example, an n-type impurity region or a p-type impurity region). A second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region is added to the second element isolation region, and the second element isolation region is used as a source region and a drain in the adjacent element region. The impurity region has a conductivity type opposite to that of the region. That is, when the source region and the drain region in the element region are n-type impurity regions, the adjacent second element isolation region is a p-type impurity region, and similarly, the source region and the drain region in the element region are p-type impurity regions. In some cases, the adjacent second element isolation region may be an n-type impurity region. The adjacent element region and the second element isolation region form a PN junction. Therefore, the element regions can be further insulated and separated by the second element isolation region provided between the element regions.

The present invention provides a first element isolation region which is a high resistance region by addition of a first impurity element that does not contribute to conductivity as an element isolation region for insulating and isolating element regions, and further, a source region and a drain region in the element region A semiconductor layer is separated into a plurality of element regions by providing a second element isolation region which is an impurity region by addition of a second impurity element imparting a reverse conductivity type. According to the present invention, since the element regions can be separated from each other by the effects of the first element isolation region and the second element isolation region, a higher element isolation effect can be obtained.

For the addition (introduction) of the impurity element in forming the first element isolation region and the second element isolation region, an ion implantation method, an (ion) doping method, or the like can be used.

Further, the element isolation region may have a concentration gradient of the first impurity element and the second impurity element. Of course, the first impurity element and the second impurity element may be added to the first and second element isolation regions at a substantially uniform concentration. That is, the concentration peak of the first impurity element and the second impurity element can be set as appropriate in the first and second element isolation regions. The second element isolation region may be an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region in contact with the second element isolation region. An impurity element imparting a mold may be contained. The second element isolation region may contain the first impurity element described above, and the second element isolation region may be added by adding the second impurity element to a part of the first element isolation region. It can also be formed.

15 and 16 show a case where a plurality of memory elements are formed. The second element isolation regions 315 (315a, 315b) and 316 (316a, 316b, 316c, 316d) are element regions 302a having n-type impurity regions. , 302b, an impurity element imparting p-type conductivity (for example, boron (B), aluminum (Al), gallium (Ga), or the like) is added as a second impurity element imparting reverse conductivity, and p A type impurity region may be used. As a result, the n-type impurity regions and the p-type impurity regions are provided alternately adjacent to each other, so that the same conductivity type impurity regions can be insulated and separated.

In FIG. 16B, the charge storage layer 303b is formed over the element region 302b and the second element isolation regions 316c and 316d in the semiconductor layer with the first insulating layer 312 interposed therebetween. In the present invention, since the element isolation region and the element region are provided in the continuous semiconductor layer, the first element isolation regions 301d and 301e, the second element isolation regions 316c and 316d, and the element region 302b are continuously formed. Yes. Therefore, the surface has high flatness and does not have a steep step.

Since the first insulating layer 312 is formed over a semiconductor layer with high flatness, the first insulating layer 312 has good coverage and is less likely to have a shape defect. Accordingly, defects such as a leakage current and a short circuit can be prevented in the charge storage layers 303a and 303b and the element regions 302a and 302b formed over the first insulating layer 312. Therefore, the semiconductor device which is the nonvolatile semiconductor memory device of this embodiment is a highly reliable semiconductor device in which a short circuit between the charge storage layer and the semiconductor layer due to a coating failure of the first insulating layer and a defect such as a leakage current are prevented. It can be.

  This embodiment can be implemented in combination with any of the other embodiments described in this specification.

Therefore, when the present invention is used, the semiconductor layer can be separated into a plurality of element regions without being divided into islands. Since the step due to the end portion of the semiconductor layer does not occur and the insulating layer is formed on the flat semiconductor layer, the coverage of the insulating layer is improved. Accordingly, a semiconductor device which is a highly reliable nonvolatile semiconductor memory device in which defects such as a charge storage layer, a control gate electrode layer, a short circuit between the gate electrode layer and the semiconductor layer and a leakage current due to a poor coating of the insulating layer are prevented, In addition, a method for manufacturing such a semiconductor device can be provided. Therefore, further miniaturization and high integration can be performed in the semiconductor device, and high performance of the semiconductor device can be achieved. In addition, since defects due to such a film shape defect are reduced, production can be performed with high yield even in the manufacturing process.

(Embodiment 4)
In this embodiment mode, a memory element (in order to prevent defects such as a short circuit between a gate electrode layer and a semiconductor layer and a leakage current due to a poor coating of an insulating layer in a semiconductor element and to provide higher reliability) An example of a semiconductor device including a memory element) is described with reference to drawings. FIG. 17 is a top view of the semiconductor device of this embodiment, FIG. 18A is a cross-sectional view taken along line MN in FIG. 17, and FIG. 18B is a cross-sectional view taken along OP.

In this embodiment, the case where a plurality of nonvolatile memory elements are provided in one element region in the structure described in Embodiment 2 will be described with reference to drawings. In addition, description is abbreviate | omitted when referring to the same thing as the said embodiment.

  In the semiconductor device described in this embodiment, element regions 322a and 322b in the semiconductor layer electrically connected to the bit lines BL0 and BL1 are provided, and a plurality of nonvolatile elements are provided in each of the element regions 322a and 322b. A memory element is provided (see FIGS. 17 and 18). Specifically, in the element region 322a, a NAND cell 350a having a plurality of nonvolatile memory elements M0 to M30 and M31 is provided between the select transistors S1 and S2. In the element region 322b, a NAND cell 350b having a plurality of nonvolatile memory elements is provided between the select transistors. Further, by providing a first element isolation region 321 (321a, 321b, 321c, 321d) and a second element isolation region 335 (335a, 335b, 335c, 335d) between the element regions 322a, 322b, adjacent NANDs The type cell 350a and the NAND type cell 350b can be insulated and separated.

  In addition, by providing a plurality of nonvolatile memory elements in one element region, the nonvolatile memory elements can be more integrated, and a large-capacity nonvolatile semiconductor memory device can be formed.

17 and 18, select transistors S1, S2, memory elements M0, M30, M31 are provided over a substrate 330 provided with an insulating layer 331, and gate electrode layers (SG2, SG1) 327a, 327b, Charge storage layers 323a, 323b, 323c, control gate electrode layers (WL31, WL30, WL0) 324a, 324b, 324c, a first insulating layer 332, a second insulating layer 333, and an interlayer insulating layer 334 are provided. The selection transistor S1 is connected to the bit line BL0, and the selection transistor S2 is connected to the source line (SL0) 326.

In the semiconductor layer, the element region 322a constituting the NAND cell 350a and the element region 322b constituting the NAND cell 350b are a first element isolation region 321 (321a, 321b, 321c, 321d) and a second element isolation. The regions 335 (335a, 335b, 335c, 335d) are electrically separated.

In this embodiment, in order to form a plurality of semiconductor elements over an insulating surface, a semiconductor layer is not separated into a plurality of island-shaped semiconductor layers, and a plurality of element regions functioning as semiconductor elements in one semiconductor layer As the element isolation region for electrically insulating and isolating the first and second element isolation regions having high resistance, the second element isolation region having a conductivity type opposite to the source and drain regions of the element region is formed. To do.

The plurality of element regions are provided around the element region so as to surround the second element isolation region which is an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region. A first element isolation region, which is a high resistance region, is provided adjacent to the outer side of the two element isolation regions. Therefore, the adjacent first element region and second element region are the second element isolation region in contact with the first element region, the first element isolation region, and the second element isolation in contact with the second element region. Adjacent through a region.

In the case where the source region and the drain region of the first element region and the second element region have the same electric type, for example, in the case of an n-type impurity region, the second element isolation region also has the opposite conductivity type to the element region. It becomes a p-type impurity region. On the other hand, the first element region and the second element are such that the source region and the drain region of the first element region are n-type impurity regions, and the source region and the drain region of the second element region are p-type impurity regions. When the regions are of the opposite conductivity type, the second element isolation region included in each region is also combined with the element regions, and the first element region side is a p-type impurity region, and the second element region side is an n-type impurity region. It becomes.

The first element isolation region adjacent to the element region via the second element isolation region is the first element that does not selectively contribute to conductivity in order to electrically isolate the elements in one semiconductor layer. It is formed by adding an impurity element.

As the first impurity element that does not contribute to conductivity (does not improve conductivity), at least one impurity element of oxygen, nitrogen, and carbon can be used. In the element isolation region to which the first impurity element is added, the conductivity decreases due to the mixing of the first impurity element that does not contribute to the conductivity, and also due to physical impact on the semiconductor layer at the time of addition (so-called sputtering effect). Increased resistance due to lower crystallinity. In the element isolation region with a high resistance, the field effect mobility is also reduced, so that the elements can be electrically isolated, while the region to which no impurity element is added maintains the field effect mobility that can function as an element. Therefore, it can be used as an element region.

The resistance of the first element isolation region is preferably 1 × 10 ¹⁰ Ω · cm or more, and the concentration of the first impurity element such as oxygen, nitrogen, or carbon is 1 × 10 ²⁰ cm ⁻³ or more and 4 × 10 ²² cm. Less than ^-3 is preferable.

The first element isolation region can be said to be amorphous because the crystallinity is lowered by the addition of the impurity element. On the other hand, since the element region is a crystalline semiconductor layer, when a semiconductor element is formed in the element region, the crystallinity of the channel formation region is higher than that of the first element isolation region, and high field effect mobility can be obtained as a semiconductor element. it can.

As the first impurity element added to the first element isolation region, a rare gas element such as argon (Ar), neon (Ne), krypton (Kr), or xenon (Xe) may be used. In addition to oxygen, nitrogen, and carbon, the addition of these rare gas elements, which are relatively large elements, can increase the physical impact on the semiconductor layer. The crystallinity of the element isolation region can be reduced.

The second element isolation region provided between the element region and the first element isolation region in contact with the element region is added with a second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region. Form.

The element region has a source region, a drain region, and a channel formation region. The source region and the drain region are impurity regions having one conductivity type (for example, an n-type impurity region or a p-type impurity region). A second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region is added to the second element isolation region, and the second element isolation region is used as a source region and a drain in the adjacent element region. The impurity region has a conductivity type opposite to that of the region. That is, when the source region and the drain region in the element region are n-type impurity regions, the adjacent second element isolation region is a p-type impurity region, and similarly, the source region and the drain region in the element region are p-type impurity regions. In some cases, the adjacent second element isolation region may be an n-type impurity region. The adjacent element region and the second element isolation region form a PN junction. Therefore, the element regions can be further insulated and separated by the second element isolation region provided between the element regions.

The present invention provides a first element isolation region which is a high resistance region by addition of a first impurity element that does not contribute to conductivity as an element isolation region for insulating and isolating element regions, and further, a source region and a drain region in the element region A semiconductor layer is separated into a plurality of element regions by providing a second element isolation region which is an impurity region by addition of a second impurity element imparting a reverse conductivity type. According to the present invention, since the element regions can be separated from each other by the effects of the first element isolation region and the second element isolation region, a higher element isolation effect can be obtained.

For the addition (introduction) of the impurity element in forming the first element isolation region and the second element isolation region, an ion implantation method, an (ion) doping method, or the like can be used.

Further, the element isolation region may have a concentration gradient of the first impurity element and the second impurity element. Of course, the first impurity element and the second impurity element may be added to the first and second element isolation regions at a substantially uniform concentration. That is, the concentration peak of the first impurity element and the second impurity element can be set as appropriate in the first and second element isolation regions. The second element isolation region may be an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region in contact with the second element isolation region. An impurity element imparting a mold may be contained. The second element isolation region may contain the first impurity element described above, and the second element isolation region may be added by adding the second impurity element to a part of the first element isolation region. It can also be formed.

17 and 18 show a case where a plurality of memory elements are formed, and the second element isolation region 335 (335a, 335b, 335c, 335d) is provided in contact with the element regions 322a, 322b having n-type impurity regions. If an impurity element imparting p-type (for example, boron (B), aluminum (Al), gallium (Ga), or the like) is added as a second impurity element imparting reverse conductivity type, a p-type impurity region is obtained. Good. As a result, the n-type impurity regions and the p-type impurity regions are provided alternately adjacent to each other, so that the same conductivity type impurity regions can be insulated and separated.

In FIG. 18B, a charge storage layer 323c is formed over the element region 322a and the second element isolation regions 335c and 335d in the semiconductor layer with the first insulating layer 332 interposed therebetween. In the present invention, since the element isolation region and the element region are provided in the continuous semiconductor layer, the first element isolation regions 321c and 321d, the second element isolation regions 335c and 335d, and the element region 322a are continuously provided. Yes. Therefore, the surface has high flatness and does not have a steep step.

Since the first insulating layer 332 is formed over a semiconductor layer with high flatness, the first insulating layer 332 has good coverage and does not easily cause a shape defect. Accordingly, defects such as a leakage current and a short circuit can be prevented in the charge storage layers 323a, 323b, and 323c and the element region 322a formed over the first insulating layer 332. Therefore, the semiconductor device which is the nonvolatile semiconductor memory device of this embodiment is a highly reliable semiconductor device in which a short circuit between the charge storage layer and the semiconductor layer due to a coating failure of the first insulating layer and a defect such as a leakage current are prevented. It can be.

This embodiment can be implemented in combination with any of the other embodiments described in this specification.

Therefore, when the present invention is used, the semiconductor layer can be separated into a plurality of element regions without being divided into islands. Since the step due to the end portion of the semiconductor layer does not occur and the insulating layer is formed on the flat semiconductor layer, the coverage of the insulating layer is improved. Accordingly, a semiconductor device which is a highly reliable nonvolatile semiconductor memory device in which defects such as a charge storage layer, a control gate electrode layer, a short circuit between the gate electrode layer and the semiconductor layer and a leakage current due to a poor coating of the insulating layer are prevented, In addition, a method for manufacturing such a semiconductor device can be provided. Therefore, further miniaturization and high integration can be performed in the semiconductor device, and high performance of the semiconductor device can be achieved. In addition, since defects due to such a film shape defect are reduced, production can be performed with high yield even in the manufacturing process.

(Embodiment 5)
In this embodiment, an example of a nonvolatile semiconductor memory device is described as a semiconductor device to which the present invention is applied. In the present invention, a plurality of semiconductor elements are manufactured in one semiconductor layer without dividing the semiconductor layer into islands. The present invention may be applied to all semiconductor elements provided in a semiconductor device or may be partially applied. The present invention may be applied as appropriate depending on the function required for the semiconductor element. An example of a semiconductor device to which the present invention is applied will be described with reference to FIG.

20A to 20D are top views of the semiconductor device of the present invention, and are simply expressed by a substrate, a peripheral circuit portion provided on the substrate, and a memory element portion. In the semiconductor device of this embodiment mode shown in FIG. 20, the memory element portion and the peripheral circuit portion are formed on the same substrate. 20A illustrates an example in which a peripheral circuit portion 472 and a memory element portion 471 are provided over a substrate 470, and a semiconductor layer is formed over the entire surface of the substrate 470. On the substrate 470, the semiconductor layers of the peripheral circuit portion 472 and the memory element portion 471 are element isolation regions (first resistance regions to which an impurity element is added, which are element isolation regions formed by adding an impurity element to which the present invention is applied. An element isolation region and a second element isolation region which is an impurity region having a conductivity type opposite to that of the element region) and the element region are separated to form a plurality of semiconductor elements. A semiconductor layer in a region other than the peripheral circuit portion 472 and the memory element portion 471 provided over the substrate 470 is a high resistance region to which an impurity element is added in the same manner as the element isolation region in the peripheral circuit portion 472 and the memory element portion 471. The first element isolation region or the second element isolation region which is an impurity region having a conductivity type opposite to that of the element region may be used.

FIG. 20B illustrates an example in which the semiconductor layer is not provided over the entire surface of the substrate 475 and the semiconductor layer in a region other than the peripheral circuit portion 477 and the memory element portion 476 provided over the substrate 475 is removed by etching or the like. is there. The peripheral circuit portion 477 and the memory element portion 476 in FIG. 20B are also a first element isolation which is a high resistance region to which an impurity element is added, similarly to the peripheral circuit portion 472 and the memory element portion 471 in FIG. A plurality of semiconductor elements are formed in one semiconductor layer by the region and the second element isolation region which is an impurity region having a conductivity type opposite to that of the element region. A semiconductor layer in a region over a substrate where a semiconductor element is not formed as illustrated in FIG. 20B may be a high resistance region or may be removed. A structure in which a plurality of semiconductor elements are adjacent to each other and a separation process of a fine semiconductor layer is necessary, and the element separation method of the present invention is applied. May be.

FIG. 20C illustrates an example in which different element isolation methods are applied to a semiconductor element provided over a substrate 480 depending on a required function and size. In FIG. 20C, a peripheral circuit portion 482 provided over a substrate 480 is formed using a semiconductor element processed into an island shape, and each semiconductor element is separated by etching to remove a semiconductor layer. . On the other hand, the memory element portion 481 forms a first element isolation region which is a high resistance region in which an impurity element is added to one semiconductor layer, and a second element isolation region which is an impurity region having a conductivity type opposite to that of the element region. The semiconductor elements are separated by the first and second element isolation regions. When the required characteristics of the semiconductor element are different between the peripheral circuit portion and the memory element portion, for example, the voltage applied to the semiconductor element in the memory element portion (for example, the (write) voltage is about 10 to 20 V) is the peripheral circuit. When the voltage applied to the semiconductor element in the portion (for example, the voltage is about 3 to 5 V) is high, the adverse effect of the defective coating of the gate insulating layer is more likely to occur. Therefore, a semiconductor element using an element region in one semiconductor layer for the memory element portion 481 in FIG. 20C and a device element using an element region separated into island-shaped semiconductor layers may be used for the peripheral circuit portion 482. Formed on the same substrate are a memory element section that needs to be written and erased at a voltage of about 10V to 20V and a peripheral circuit section that operates at a voltage of about 3V to 7V and mainly controls data input / output and commands. Even in this case, mutual interference due to a difference in voltage applied to each element can be prevented.

20D is an example in which different element isolation methods are applied to a semiconductor element provided over a substrate 485 depending on a required function and size, similarly to FIG. 20C. In FIG. 20D, a peripheral circuit portion 487b provided over a substrate 485 is formed using island-shaped semiconductor elements, and the semiconductor elements are separated by etching to remove a semiconductor layer. . On the other hand, the peripheral circuit portion 487a and the memory element portion 486 are a first element isolation region which is a high resistance region in which an impurity element is added to one semiconductor layer, and a second element which is an impurity region having a conductivity type opposite to that of the element region. An isolation region is formed, and each semiconductor element is isolated by the first and second element isolation regions. As described above, the element isolation is selectively performed by the island-shaped semiconductor layer in the peripheral circuit portion 487b, and the element isolation region is provided in one semiconductor layer in the peripheral circuit portion 487a and the memory element portion 486 to isolate the elements. May be combined as appropriate according to the circuit configuration provided on the substrate.

The semiconductor elements provided on the substrate have different required characteristics depending on their functions, and the shape changes according to the required characteristics (for example, the thickness of the gate insulating layer). In a finely structured region where semiconductor elements are close to each other, an element isolation region is provided in one semiconductor layer to form a plurality of semiconductor elements. On the other hand, the element spacing is relatively wide or structurally relative to the gate insulating layer. In regions where thinning is not so required, the semiconductor layer can be removed, and a plurality of semiconductor elements can be manufactured as island-shaped semiconductor layers. In this manner, by selecting an element isolation method appropriately in accordance with characteristics required on a substrate, a semiconductor device having high performance capable of high-speed response and high reliability can be manufactured.

In this embodiment, in order to form a plurality of semiconductor elements over an insulating surface, a semiconductor layer is not separated into a plurality of island-shaped semiconductor layers, and a plurality of element regions functioning as semiconductor elements in one semiconductor layer As the element isolation region for electrically insulating and isolating the first and second element isolation regions having high resistance, the second element isolation region having a conductivity type opposite to the source and drain regions of the element region is formed. To do.

The plurality of element regions are provided around the element region so as to surround the second element isolation region which is an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region. A first element isolation region, which is a high resistance region, is provided adjacent to the outer side of the two element isolation regions. Therefore, the adjacent first element region and second element region are the second element isolation region in contact with the first element region, the first element isolation region, and the second element isolation in contact with the second element region. Adjacent through a region.

In the case where the source region and the drain region of the first element region and the second element region have the same electric type, for example, in the case of an n-type impurity region, the second element isolation region also has the opposite conductivity type to the element region. It becomes a p-type impurity region. On the other hand, the first element region and the second element are such that the source region and the drain region of the first element region are n-type impurity regions, and the source region and the drain region of the second element region are p-type impurity regions. When the regions are of the opposite conductivity type, the second element isolation region included in each region is also combined with the element regions, and the first element region side is a p-type impurity region, and the second element region side is an n-type impurity region. It becomes.

The first element isolation region adjacent to the element region via the second element isolation region is the first element that does not selectively contribute to conductivity in order to electrically isolate the elements in one semiconductor layer. It is formed by adding an impurity element.

As the first impurity element that does not contribute to conductivity (does not improve conductivity), at least one impurity element of oxygen, nitrogen, and carbon can be used. In the element isolation region to which the first impurity element is added, the conductivity decreases due to the mixing of the first impurity element that does not contribute to the conductivity, and also due to physical impact on the semiconductor layer at the time of addition (so-called sputtering effect). Increased resistance due to lower crystallinity. In the element isolation region with a high resistance, the field effect mobility is also reduced, so that the elements can be electrically isolated, while the region to which no impurity element is added maintains the field effect mobility that can function as an element. Therefore, it can be used as an element region.

The resistance of the first element isolation region is preferably 1 × 10 ¹⁰ Ω · cm or more, and the concentration of the first impurity element such as oxygen, nitrogen, or carbon is 1 × 10 ²⁰ cm ⁻³ or more and 4 × 10 ²² cm. Less than ^-3 is preferable.

The first element isolation region can be said to be amorphous because the crystallinity is lowered by the addition of the impurity element. On the other hand, since the element region is a crystalline semiconductor layer, when a semiconductor element is formed in the element region, the crystallinity of the channel formation region is higher than that of the first element isolation region, and high field effect mobility can be obtained as a semiconductor element. it can.

As the first impurity element added to the first element isolation region, a rare gas element such as argon (Ar), neon (Ne), krypton (Kr), or xenon (Xe) may be used. In addition to oxygen, nitrogen, and carbon, the addition of these rare gas elements, which are relatively large elements, can increase the physical impact on the semiconductor layer. The crystallinity of the element isolation region can be reduced.

The second element isolation region provided between the element region and the first element isolation region in contact with the element region is added with a second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region. Form.

The element region has a source region, a drain region, and a channel formation region. The source region and the drain region are impurity regions having one conductivity type (for example, an n-type impurity region or a p-type impurity region). A second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region is added to the second element isolation region, and the second element isolation region is used as a source region and a drain in the adjacent element region. The impurity region has a conductivity type opposite to that of the region. That is, when the source region and the drain region in the element region are n-type impurity regions, the adjacent second element isolation region is a p-type impurity region, and similarly, the source region and the drain region in the element region are p-type impurity regions. In some cases, the adjacent second element isolation region may be an n-type impurity region. The adjacent element region and the second element isolation region form a PN junction. Therefore, the element regions can be further insulated and separated by the second element isolation region provided between the element regions.

The present invention provides a first element isolation region which is a high resistance region by addition of a first impurity element that does not contribute to conductivity as an element isolation region for insulating and isolating element regions, and further, a source region and a drain region in the element region A semiconductor layer is separated into a plurality of element regions by providing a second element isolation region which is an impurity region by addition of a second impurity element imparting a reverse conductivity type. According to the present invention, since the element regions can be separated from each other by the effects of the first element isolation region and the second element isolation region, a higher element isolation effect can be obtained.

For the addition (introduction) of the impurity element in forming the first element isolation region and the second element isolation region, an ion implantation method, an (ion) doping method, or the like can be used.

Further, the element isolation region may have a concentration gradient of the first impurity element and the second impurity element. Of course, the first impurity element and the second impurity element may be added to the first and second element isolation regions at a substantially uniform concentration. That is, the concentration peak of the first impurity element and the second impurity element can be set as appropriate in the first and second element isolation regions. The second element isolation region may be an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region in contact with the second element isolation region. An impurity element imparting a mold may be contained. The second element isolation region may contain the first impurity element described above, and the second element isolation region may be added by adding the second impurity element to a part of the first element isolation region. It can also be formed.

Therefore, according to the present embodiment, a highly reliable memory element in which defects such as a short circuit between the charge storage layer, the control gate electrode layer, the gate electrode layer and the semiconductor layer, and a leakage current due to a poor coating of the insulating layer are prevented. And a method for manufacturing such a semiconductor device can be provided. Therefore, further miniaturization and high integration can be performed in a semiconductor device having a memory element, and high performance of the semiconductor device can be achieved. In addition, since defects due to such a film shape defect are reduced, production can be performed with high yield even in the manufacturing process.

(Embodiment 6)
In this embodiment mode, a memory element (memory) that aims to prevent defects such as a short circuit between a gate electrode layer and a semiconductor layer and a leakage current due to a coating failure of an insulating layer in a semiconductor element and to provide higher reliability. An example of a semiconductor device having an element) is described with reference to drawings. A top view of the semiconductor device of this embodiment is shown in FIG. 11A, and a cross-sectional view taken along line XY in FIG. 11A is shown in FIG.

  As shown in FIG. 11A, a memory element portion 404 which is a semiconductor device having a memory element, a circuit portion 421, and an antenna 431 are formed over a substrate 400. 11A and 11B show a state where a memory element portion, a circuit portion, and an antenna are formed over a substrate 400 that can withstand the manufacturing conditions in the middle of the manufacturing process. Materials and manufacturing steps may be selected and manufactured in the same manner as in Embodiment Mode 3.

  A memory element 441 is provided in the memory element portion 404 and a transistor 442 is provided in the circuit portion 421 with a separation layer 452 and an insulating layer 453 provided over the substrate 400. An insulating layer 455 is formed over the memory element 441 and the transistor 442.

  In the semiconductor device in FIG. 11B, an antenna 431a, an antenna 431b, an antenna 431c, and an antenna 431d are formed over the insulating layer 455. The antenna 431c is formed in contact with the wiring layer 456b in an opening reaching the wiring layer 456b formed in the insulating layer 455, and electrically connects the antenna to the memory element portion 404 and the circuit portion 421.

Note that this embodiment can be freely combined with the above embodiment. In addition, the semiconductor device manufactured in this embodiment can be provided over a flexible substrate by being separated from the substrate by a separation process and bonded to a flexible substrate, so that the semiconductor device has flexibility. Can do.

A case where a semiconductor device is attached to a flexible substrate to form a flexible semiconductor device is also referred to as an IC film. An IC film is a flexible semiconductor device having a thickness of 100 μm or less, preferably 50 μm or less, more preferably 20 μm or less, and the included semiconductor layer has a film thickness of 100 μm or less, preferably 70 μm or less.

Flexible substrates include PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PES (polyethersulfone), polypropylene, polypropylene sulfide, polycarbonate, polyetherimide, polyphenylene sulfide, polyphenylene oxide, polysulfone, polyphthalamide, etc. Substrate made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, paper made of fibrous material, base film (polyester, polyamide, inorganic vapor deposition film, paper, etc.) and adhesive synthetic resin It corresponds to a laminated film with a film (acrylic synthetic resin, epoxy synthetic resin, etc.). The film is subjected to heat treatment and pressure treatment, and when the heat treatment and pressure treatment are performed, the film is provided on the adhesive layer provided on the outermost surface of the film or on the outermost layer. The layer (not the adhesive layer) is melted by heat treatment and bonded by pressure. Further, an adhesive layer may be provided on the substrate, or an adhesive layer may not be provided. The adhesive layer corresponds to a layer containing an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, or a resin additive.

In the semiconductor device of the present invention, after a memory element is formed over a first substrate that can withstand process conditions (such as temperature), the semiconductor device may be transferred to a second substrate to have a memory element. In this specification, transposition means that a memory element formed over a first substrate is peeled off from the first substrate and transferred to the second substrate. That is, it can be said that the place where the memory element is provided is moved to another substrate.

Note that in the transfer step to another substrate, a peeling layer and an insulating layer are formed between the substrate and the element formation layer, a metal oxide film is provided between the peeling layer and the insulating layer, and the metal oxide film is crystallized. A method of peeling the element formation layer after weakening, an amorphous silicon film containing hydrogen is provided between the substrate and the element formation layer with high heat resistance, and the amorphous silicon film is formed by laser irradiation or etching. By removing the element formation layer, a separation layer and an insulating layer are formed between the substrate and the element formation layer, and a metal oxide film is provided between the separation layer and the insulation layer. A method of forming an element forming layer by embrittlement by crystallization and removing a part of the peeling layer by etching with a solution or halogen fluoride gas such as NF ₃ , BrF ₃ , or ClF ₃ , and then peeling in the weakened metal oxide film The substrate on which the It can be used a solution or _{NF 3,} BrF 3, ClF appropriate method for removing by etching with halogen fluoride gas such as _3. In addition, a film containing nitrogen, oxygen, hydrogen, or the like (for example, an amorphous silicon film containing hydrogen, a hydrogen-containing alloy film, an oxygen-containing alloy film, or the like) is used as the separation layer, and the separation layer is irradiated with laser light for separation. A method of releasing nitrogen, oxygen, or hydrogen contained in the layer as a gas and promoting separation between the element formation layer and the substrate may be used.

A transposition step can be performed more easily by combining the above peeling methods. In other words, laser irradiation, etching of the release layer with gas or solution, mechanical deletion with a sharp knife or scalpel, etc. to make the release layer and the element formation layer easy to peel off, Peeling can also be performed by force (by machine or the like).

The antenna may be provided so as to overlap with the memory element portion or may be provided around the memory element portion without overlapping. When overlapping, the entire surface may overlap, or a structure where a part overlaps may be used. The structure in which the antenna unit and the memory element unit overlap reduces the malfunction of the semiconductor device due to the effects of noise and other factors on the signal when the antenna communicates and fluctuations in electromotive force generated by electromagnetic induction. Is possible, and reliability is improved. In addition, the semiconductor device can be reduced in size.

As a signal transmission method in the semiconductor device capable of inputting / outputting non-contact data described above, an electromagnetic coupling method, an electromagnetic induction method, a microwave method, or the like can be used. The transmission method may be appropriately selected by the practitioner in consideration of the intended use, and an optimal antenna may be provided according to the transmission method.

For example, when an electromagnetic coupling method or an electromagnetic induction method (for example, 13.56 MHz band) is applied as a signal transmission method in a semiconductor device, an electromagnetic induction due to a change in magnetic field density is used, and thus a conductive layer that functions as an antenna. Are formed in a ring shape (for example, a loop antenna) or a spiral shape (for example, a spiral antenna).

In addition, when a microwave method (for example, UHF band (860 to 960 MHz band), 2.45 GHz band, or the like) is applied as a signal transmission method in a semiconductor device, the wavelength of an electromagnetic wave used for signal transmission is considered. The length of the conductive layer functioning as an antenna may be set as appropriate. For example, the conductive layer functioning as an antenna may be linear (for example, a dipole antenna), flat (for example, a patch antenna), or ribbon type. It can be formed into a shape or the like. Further, the shape of the conductive layer functioning as an antenna is not limited to a linear shape, and may be provided in a curved shape, a meandering shape, or a combination thereof in consideration of the wavelength of electromagnetic waves.

The conductive layer functioning as an antenna is formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, a plating method, or the like. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum An element selected from (Mo) or an alloy material or a compound material containing these elements as a main component is formed in a single layer structure or a laminated structure.

For example, when a conductive layer that functions as an antenna is formed using a screen printing method, a conductive paste in which conductive particles having a particle size of several nanometers to several tens of micrometers are dissolved or dispersed in an organic resin is selectively used. Can be provided by printing. Conductor particles include silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) and titanium (Ti). Any one or more metal particles, silver halide fine particles, or dispersible nanoparticles can be used. In addition, as the organic resin contained in the conductive paste, one or more selected from organic resins functioning as a binder of metal particles, a solvent, a dispersant, and a coating material can be used. Typically, an organic resin such as an epoxy resin or a silicone resin can be given. In forming the conductive layer, it is preferable to fire after extruding the conductive paste. For example, in the case where fine particles containing silver as a main component (for example, a particle size of 1 nm or more and 100 nm or less) is used as the material of the conductive paste, the conductive layer is obtained by curing by baking at a temperature range of 150 to 300 ° C. Can do. Further, fine particles mainly composed of solder or lead-free solder may be used. In this case, it is preferable to use fine particles having a particle diameter of 20 μm or less. Solder and lead-free solder have the advantage of low cost. In addition to the materials described above, ceramic, ferrite, or the like may be applied to the antenna.

Further, in the case where an electromagnetic coupling method or an electromagnetic induction method is applied and a semiconductor device provided with an antenna is provided in contact with a metal, a magnetic material having a permeability between the semiconductor device and the metal is used. It is preferable to provide it. When a semiconductor device provided with an antenna is provided in contact with a metal, an eddy current flows in the metal as the magnetic field changes, and the change in the magnetic field is weakened by the demagnetizing field generated by the eddy current, thereby reducing the communication distance. . Therefore, by providing a material having magnetic permeability between the semiconductor device and the metal, it is possible to suppress the eddy current of the metal and suppress the decrease in the communication distance. As the magnetic material, ferrite or metal thin film having high magnetic permeability and low high-frequency loss can be used.

In the case of providing an antenna, a semiconductor element such as a transistor and a conductive layer functioning as an antenna may be directly formed over one substrate, or the semiconductor element and the conductive layer functioning as an antenna may be provided separately. After being provided on the substrate, it may be provided by bonding so as to be electrically connected.

The memory element 441 and the transistor 442 use the present invention, and a channel formation region thereof is formed in an element region provided in one semiconductor layer. The memory element and the transistor are electrically insulated and separated by a first element isolation region having a high resistance and a second element isolation region in contact with the element region and having a conductivity type opposite to the source region and the drain region of the element region. ing. In this manner, when the present invention is used, the semiconductor layer can be separated into a plurality of element regions without being divided into islands, and a plurality of semiconductor elements can be manufactured. Accordingly, a step due to the end portion of the semiconductor layer does not occur, and the insulating layer is formed on the flat semiconductor layer, so that the coverage of the insulating layer is improved.

Therefore, according to the present embodiment, a highly reliable memory element in which defects such as a short circuit between the charge storage layer, the control gate electrode layer, the gate electrode layer and the semiconductor layer, and a leakage current due to a poor coating of the insulating layer are prevented. And a method for manufacturing such a semiconductor device can be provided. Therefore, further miniaturization and high integration can be performed in a semiconductor device having a memory element, and high performance of the semiconductor device can be achieved. In addition, since defects due to such a film shape defect are reduced, production can be performed with high yield even in the manufacturing process.

(Embodiment 7)
In this embodiment mode, a CMOS circuit and a memory for preventing a short circuit between a gate electrode layer and a semiconductor layer due to a poor coating of an insulating layer and a leakage current in a semiconductor element, and providing higher reliability An example of a semiconductor device including an element will be described with reference to drawings. A method for manufacturing the semiconductor device in this embodiment will be described in detail with reference to FIGS.

  Note that since the control transistor provided in the memory portion has a higher driving voltage than the transistor provided in the logic portion, the gate insulating layer of the transistor provided in the memory portion and the transistor provided in the logic portion are formed with different thicknesses. It is preferable to do. For example, a thin film transistor having a thin gate insulating layer is preferably provided when the driving voltage is small and variation in threshold voltage is small, and when the driving voltage is large and the gate insulating layer is required to have a high withstand voltage, the gate insulating layer is not provided. It is preferable to provide a thick thin film transistor.

  Therefore, in this embodiment, an insulating layer with a small thickness is formed for a transistor in a logic portion whose driving voltage is small and a variation in threshold voltage is small, and the withstanding voltage of the gate insulating layer is large because the driving voltage is large. An insulating layer having a large thickness is formed for a required transistor in the memory portion.

Silicon nitride oxide by a sputtering method, a PVD method (Physical Vapor Deposition), a low pressure CVD method (LPCVD method), or a CVD method (Chemical Vapor Deposition) such as a plasma CVD method as a base film over the substrate 100 having an insulating surface. An insulating layer 112a functioning as a base film is formed using the film to have a thickness of 10 to 200 nm (preferably 50 to 150 nm), and a silicon oxynitride film is used to stack the insulating layer 112b to a thickness of 50 to 200 nm (preferably 100 to 150 nm). Alternatively, heat-resistant polymers such as acrylic acid, methacrylic acid and derivatives thereof, polyimide, aromatic polyamide, polybenzimidazole, or siloxane resin may be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aryl group) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Moreover, resin materials such as vinyl resins such as polyvinyl alcohol and polyvinyl butyral, epoxy resins, phenol resins, novolac resins, acrylic resins, melamine resins, and urethane resins may be used. Alternatively, an organic material such as benzocyclobutene, parylene, fluorinated arylene ether, or polyimide, a composition material containing a water-soluble homopolymer and a water-soluble copolymer, or the like may be used. Moreover, an oxazole resin can also be used, for example, photocurable polybenzoxazole or the like can be used.

Further, a droplet discharge method, a printing method (a method for forming a pattern such as screen printing or offset printing), a coating method such as a spin coating method, a dipping method, a dispenser method, or the like can also be used. In this embodiment, the insulating layer 112a and the insulating layer 112b are formed by a plasma CVD method. As the substrate 100, a glass substrate, a quartz substrate, a metal substrate, or a stainless substrate on which an insulating layer is formed may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used, or a flexible substrate such as a film may be used. As the plastic substrate, a substrate made of PET (polyethylene terephthalate), PEN (polyethylene naphthalate), or PES (polyethersulfone) can be used, and as the flexible substrate, a synthetic resin such as acrylic can be used.

As the insulating layer functioning as a base film, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be used, and a single layer or a stacked structure of two layers or three layers may be used.

Next, a semiconductor layer is formed over the base film. The semiconductor layer may be formed to have a thickness of 25 to 200 nm (preferably 30 to 150 nm) by various means (such as sputtering, LPCVD, or plasma CVD). In this embodiment mode, it is preferable to use a crystalline semiconductor layer obtained by crystallizing an amorphous semiconductor layer by laser crystallization.

As a method for manufacturing the crystalline semiconductor layer, various methods (laser crystallization method, thermal crystallization method, thermal crystallization method using an element that promotes crystallization such as nickel) may be used. Further, the crystallinity can be increased by crystallizing a microcrystalline semiconductor by laser irradiation. In the case where an element for promoting crystallization is not introduced, the concentration of hydrogen contained in the amorphous semiconductor layer is set to 1 × by heating at 500 ° C. for 1 hour in a nitrogen atmosphere before irradiating the amorphous semiconductor layer with laser light. Release to 10 ²⁰ atoms / cm ³ or less. This is because when an amorphous semiconductor layer containing a large amount of hydrogen is irradiated with laser light, the amorphous semiconductor layer is destroyed. As the heat treatment for crystallization, a heating furnace, laser irradiation, irradiation with light emitted from a lamp (also referred to as lamp annealing), or the like can be used. There are RTA methods such as a GRTA (Gas Rapid Thermal Anneal) method and an LRTA (Lamp Rapid Thermal Anneal) method as heating methods. GRTA is a method for performing heat treatment using a high-temperature gas, and LRTA is a method for performing heat treatment with lamp light.

Further, in the crystallization step of crystallizing the amorphous semiconductor layer to form the crystalline semiconductor layer, an element for promoting crystallization (also referred to as a catalyst element or a metal element) is added to the amorphous semiconductor layer, and heat treatment ( Crystallization may be carried out at 550 ° C. to 750 ° C. for 3 minutes to 24 hours. As elements that promote crystallization, iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum One or more types selected from (Pt), copper (Cu), and gold (Au) can be used.

The method of introducing the metal element into the amorphous semiconductor layer is not particularly limited as long as the metal element can be present on the surface of the amorphous semiconductor layer or inside the amorphous semiconductor layer. For example, sputtering, CVD, A plasma treatment method (including a plasma CVD method), an adsorption method, or a method of applying a metal salt solution can be used. Among these, the method using a solution is simple and useful in that the concentration of the metal element can be easily adjusted. At this time, in order to improve the wettability of the surface of the amorphous semiconductor layer and to spread the aqueous solution over the entire surface of the amorphous semiconductor layer, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, hydroxy radical It is desirable to form an oxide film by treatment with ozone water or hydrogen peroxide.

In order to remove or reduce an element that promotes crystallization from the crystalline semiconductor layer, a semiconductor layer containing an impurity element is formed in contact with the crystalline semiconductor layer and functions as a gettering sink. As the impurity element, an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, a rare gas element, or the like can be used. For example, phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb ), Bismuth (Bi), boron (B), helium (He), neon (Ne), argon (Ar), Kr (krypton), and Xe (xenon) can be used. A semiconductor layer containing a rare gas element is formed over the crystalline semiconductor layer containing an element that promotes crystallization, and heat treatment (at 550 ° C. to 750 ° C. for 3 minutes to 24 hours) is performed. The element that promotes crystallization contained in the crystalline semiconductor layer moves into the semiconductor layer containing a rare gas element, and the element that promotes crystallization in the crystalline semiconductor layer is removed or reduced. After that, the semiconductor layer containing a rare gas element that has become a gettering sink is removed.

Laser irradiation can be performed by relatively scanning the laser and the semiconductor layer. In laser irradiation, a marker can be formed in order to superimpose beams with high accuracy and to control the laser irradiation start position and laser irradiation end position. The marker may be formed on the substrate simultaneously with the amorphous semiconductor layer.

When laser irradiation is used, a continuous wave laser beam (CW (continuous-wave) laser beam) or a pulsed laser beam (pulse laser beam) can be used. The laser beam that can be used here is a gas laser such as an Ar laser, a Kr laser, or an excimer laser, single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline ( (Ceramics) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta added as dopants A laser oscillated from one or more of laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser, or gold vapor laser as a medium can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonic laser beams of these fundamental waves, a crystal having a large grain size can be obtained. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. This laser can be emitted by CW or pulsed oscillation. When injected at a CW, the power density 0.01 to 100 MW / cm ² of about laser (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta, a laser using a medium added with one or more, an Ar ion laser, or a Ti: sapphire laser should oscillate continuously It is also possible to perform pulse oscillation at an oscillation frequency of 10 MHz or more by performing Q switch operation, mode synchronization, or the like. When a laser beam is oscillated at an oscillation frequency of 10 MHz or more, the semiconductor layer is irradiated with the next pulse after the semiconductor layer is melted by the laser and solidified. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor layer, so that crystal grains continuously grown in the scanning direction can be obtained.

When ceramic (polycrystal) is used as the medium, it is possible to form the medium in a free shape in a short time and at low cost. When a single crystal is used, a cylindrical medium having a diameter of several millimeters and a length of several tens of millimeters is usually used. However, when ceramic is used, a larger one can be made.

Since the concentration of dopants such as Nd and Yb in the medium that directly contributes to light emission cannot be changed greatly regardless of whether it is a single crystal or a polycrystal, there is a certain limit to improving the laser output by increasing the concentration. However, in the case of ceramic, since the size of the medium can be remarkably increased as compared with the single crystal, the output can be greatly improved.

Further, in the case of ceramic, a medium having a parallelepiped shape or a rectangular parallelepiped shape can be easily formed. When a medium having such a shape is used to cause oscillation light to travel in a zigzag manner inside the medium, the oscillation optical path can be made longer. As a result, amplification is increased and oscillation can be performed with high output. Further, since the laser beam emitted from the medium having such a shape has a quadrangular cross-sectional shape at the time of emission, it is advantageous for shaping into a linear beam as compared with a round beam. By shaping the emitted laser beam using an optical system, it is possible to easily obtain a linear beam having a short side length of 1 mm or less and a long side length of several mm to several m. Become. In addition, by irradiating the medium with the excitation light uniformly, the linear beam has a uniform energy distribution in the long side direction. Further, the laser may be irradiated with an incident angle θ (0 <θ <90 degrees) with respect to the semiconductor layer. This is because laser interference can be prevented.

By irradiating the semiconductor layer with this linear beam, the entire surface of the semiconductor layer can be annealed more uniformly. When uniform annealing is required up to both ends of the linear beam, it is necessary to devise measures such as shielding the energy attenuation portion using a slit.

Alternatively, the semiconductor layer may be irradiated with a laser beam in an inert gas atmosphere such as a rare gas or nitrogen. Accordingly, the surface roughness of the semiconductor can be suppressed by laser light irradiation, and variations in the threshold voltage of the transistor due to variations in interface state density can be suppressed.

The crystallization of the amorphous semiconductor layer may be a combination of heat treatment and crystallization by laser light irradiation, or may be performed multiple times by heat treatment or laser light irradiation alone.

The semiconductor layer thus obtained may be doped with a trace amount of an impurity element (boron or phosphorus) in order to control the threshold voltage of the thin film transistor. This doping of the impurity element may be performed on the amorphous semiconductor layer before the crystallization step. When an impurity element is doped in the state of the amorphous semiconductor layer, the impurity can be activated by heat treatment for subsequent crystallization. In addition, defects and the like generated during doping can be improved.

An impurity element is selectively added to the semiconductor layer which is a crystalline semiconductor layer, so that an element isolation region is formed. The semiconductor layer is separated into a plurality of element regions by the element isolation region. Mask layers 103a, 103b, 103c, and 103d are formed over the semiconductor layer, and an impurity element 104 that does not contribute to conductivity is added. By adding the impurity element 104 that does not contribute to conductivity, the element isolation regions 651a, 651b, 651c, 651d, 651e, 651f, 651g, 651h, and the element regions 102a, 102b insulated and isolated by the element isolation regions are formed in the semiconductor layer. , 102c and 102d are formed (see FIG. 5A).

Next, mask layers 652a, 652b covering part of the element regions 102a, 102b, 102c, 102d, the element isolation regions 651c, 651d, the element isolation regions 651a, 651b, 651e, 651f, 651g, 651h on the semiconductor layer. , 652c, and 652d, and an impurity element 653 imparting p-type conductivity is added. By adding the impurity element 653 imparting p-type conductivity, second element isolation regions 101a, 101b, 101c, 101d, 101e, and 101f that are p-type impurity regions are formed in the semiconductor layer (FIG. 5B). reference.). First element isolation regions 660a, 660b, 660c, 660d, 660e, and 660f are formed in a region to which the impurity element 653 imparting p-type is not added.

Next, element regions 102a, 102b, 102c, and 102d, first element isolation regions 660a, 660b, 660c, 660d, 660e, and 660f, and second element isolation regions 101a, 101b, 101c, and 101d are formed on the semiconductor layer. , 101e and 101f, mask layers 654a, 654b, 654c and 654d are formed, and an n-type impurity element 655 is added. By the addition of the impurity element 655 imparting n-type conductivity, second element isolation regions 656a and 656b which are n-type impurity regions are formed in the semiconductor layer (see FIG. 5C). First element isolation regions 661a and 661b are formed in a region to which the impurity element 655 imparting n-type conductivity is not added.

In this embodiment mode, the element isolation region and the element region are provided in the continuous semiconductor layer. Therefore, the first element isolation regions 660a, 660b, 660c, 660d, 660e, 660f, 661a, and 661b are provided in the semiconductor layer. , And second element isolation regions 101a, 101b, 101c, 101d, 101e, 101f, 656a, 656b, and element regions 102a, 102b, 102c, 102d that are insulated and isolated by the element isolation regions are continuous. Therefore, the surface has high flatness and does not have a steep step.

In this embodiment, in order to form a plurality of semiconductor elements over an insulating surface, a semiconductor layer is not separated into a plurality of island-shaped semiconductor layers, and a plurality of element regions functioning as semiconductor elements in one semiconductor layer As the element isolation region for electrically insulating and isolating the first and second element isolation regions having high resistance, the second element isolation region having a conductivity type opposite to the source and drain regions of the element region is formed. To do.

The plurality of element regions are provided around the element region so as to surround the second element isolation region which is an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region. A first element isolation region, which is a high resistance region, is provided adjacent to the outer side of the two element isolation regions. Therefore, the adjacent first element region and second element region are the second element isolation region in contact with the first element region, the first element isolation region, and the second element isolation in contact with the second element region. Adjacent through a region.

In the case where the source region and the drain region of the first element region and the second element region have the same electric type, for example, in the case of an n-type impurity region, the second element isolation region also has the opposite conductivity type to the element region. It becomes a p-type impurity region. On the other hand, the first element region and the second element are such that the source region and the drain region of the first element region are n-type impurity regions, and the source region and the drain region of the second element region are p-type impurity regions. When the regions are of the opposite conductivity type, the second element isolation region included in each region is also combined with the element regions, and the first element region side is a p-type impurity region, and the second element region side is an n-type impurity region. It becomes.

The first element isolation region adjacent to the element region via the second element isolation region is the first element that does not selectively contribute to conductivity in order to electrically isolate the elements in one semiconductor layer. It is formed by adding an impurity element.

As the first impurity element that does not contribute to conductivity (does not improve conductivity), at least one impurity element of oxygen, nitrogen, and carbon can be used. In the element isolation region to which the first impurity element is added, the conductivity decreases due to the mixing of the first impurity element that does not contribute to the conductivity, and also due to physical impact on the semiconductor layer at the time of addition (so-called sputtering effect). Increased resistance due to lower crystallinity. In the element isolation region with a high resistance, the field effect mobility is also reduced, so that the elements can be electrically isolated, while the region to which no impurity element is added maintains the field effect mobility that can function as an element. Therefore, it can be used as an element region.

The resistance of the first element isolation region is preferably 1 × 10 ¹⁰ Ω · cm or more, and the concentration of the first impurity element such as oxygen, nitrogen, or carbon is 1 × 10 ²⁰ cm ⁻³ or more and 4 × 10 ²² cm. Less than ^-3 is preferable.

The first element isolation region can be said to be amorphous because the crystallinity is lowered by the addition of the impurity element. On the other hand, since the element region is a crystalline semiconductor layer, when a semiconductor element is formed in the element region, the crystallinity of the channel formation region is higher than that of the first element isolation region, and high field effect mobility can be obtained as a semiconductor element. it can.

As the first impurity element added to the first element isolation region, a rare gas element such as argon (Ar), neon (Ne), krypton (Kr), or xenon (Xe) may be used. In addition to oxygen, nitrogen, and carbon, the addition of these rare gas elements, which are relatively large elements, can increase the physical impact on the semiconductor layer. The crystallinity of the element isolation region can be reduced.

The second element isolation region provided between the element region and the first element isolation region in contact with the element region is added with a second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region. Form.

The element region has a source region, a drain region, and a channel formation region. The source region and the drain region are impurity regions having one conductivity type (for example, an n-type impurity region or a p-type impurity region). A second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region is added to the second element isolation region, and the second element isolation region is used as a source region and a drain in the adjacent element region. The impurity region has a conductivity type opposite to that of the region. That is, when the source region and the drain region in the element region are n-type impurity regions, the adjacent second element isolation region is a p-type impurity region, and similarly, the source region and the drain region in the element region are p-type impurity regions. In some cases, the adjacent second element isolation region may be an n-type impurity region. The adjacent element region and the second element isolation region form a PN junction. Therefore, the element regions can be further insulated and separated by the second element isolation region provided between the element regions.

The present invention provides a first element isolation region which is a high resistance region by addition of a first impurity element that does not contribute to conductivity as an element isolation region for insulating and isolating element regions, and further, a source region and a drain region in the element region A semiconductor layer is separated into a plurality of element regions by providing a second element isolation region which is an impurity region by addition of a second impurity element imparting a reverse conductivity type. According to the present invention, since the element regions can be separated from each other by the effects of the first element isolation region and the second element isolation region, a higher element isolation effect can be obtained.

For the addition (introduction) of the impurity element in forming the first element isolation region and the second element isolation region, an ion implantation method, an (ion) doping method, or the like can be used.

Further, the element isolation region may have a concentration gradient of the first impurity element and the second impurity element. Of course, the first impurity element and the second impurity element may be added to the first and second element isolation regions at a substantially uniform concentration. That is, the concentration peak of the first impurity element and the second impurity element can be set as appropriate in the first and second element isolation regions. The second element isolation region may be an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region in contact with the second element isolation region. An impurity element imparting a mold may be contained. The second element isolation region may contain the first impurity element described above, and the second element isolation region may be added by adding the second impurity element to a part of the first element isolation region. It can also be formed.

The mask is removed, and the first insulating layer 105 is formed over the semiconductor layer, and the charge storage layer 106 is formed over the first insulating layer 105.

Since the first insulating layer 105 is formed over a semiconductor layer with high flatness, the first insulating layer 105 has good coverage and is less likely to have a shape defect. Therefore, defects such as a leakage current and a short circuit can be prevented in the charge storage layer 106 and the element region 102c formed over the first insulating layer 105. Therefore, the semiconductor device which is the nonvolatile semiconductor memory device of this embodiment is a highly reliable semiconductor device in which a short circuit between the charge storage layer and the semiconductor layer due to a coating failure of the first insulating layer and a defect such as a leakage current are prevented. It can be.

The first insulating layer 105 can be formed by performing heat treatment, plasma treatment, or the like on the semiconductor layer. For example, by performing oxidation treatment, nitridation treatment, or oxynitridation treatment on the semiconductor layer by high-density plasma treatment, the first insulating layer 105 that becomes an oxide film, a nitride film, or an oxynitride film is formed over the semiconductor layer, respectively. To do. In addition, you may form by plasma CVD method or a sputtering method.

For example, when a semiconductor layer containing Si as a main component is used as a semiconductor layer and oxidation or nitridation is performed by high-density plasma treatment, a silicon oxide layer or a silicon nitride layer is formed as the first insulating layer 105. Alternatively, after the semiconductor layer is oxidized by high-density plasma treatment, nitriding treatment may be performed by performing high-density plasma treatment again. In this case, a silicon oxide layer is formed in contact with the semiconductor layer, and a nitrogen plasma treatment layer is formed on or near the surface of the silicon oxide layer.

Here, the first insulating layer 105 is formed with a thickness of 1 to 10 nm, preferably 1 to 5 nm. For example, the semiconductor layer is oxidized by high-density plasma treatment to form a silicon oxide layer having a thickness of about 3 nm on the surface of the semiconductor layer, and then nitrided by high-density plasma treatment to be near or near the surface of the silicon oxide layer. A nitrogen plasma treatment layer is formed. Specifically, first, a silicon oxide layer is formed with a thickness of 3 nm to 6 nm on the semiconductor layer by plasma treatment in an oxygen atmosphere. Then, a nitrogen plasma processing layer having a high nitrogen concentration is provided on or near the surface of the silicon oxide layer by subsequently performing plasma processing in a nitrogen atmosphere. Here, a plasma treatment is performed in a nitrogen atmosphere to form a structure in which nitrogen is contained at a ratio of 20 to 50 atomic% at a depth of approximately 1 nm from the surface of the silicon oxide layer. In the nitrogen plasma treatment layer, silicon (silicon oxynitride) containing oxygen and nitrogen is formed. At this time, it is preferable that the oxidation treatment and the nitriding treatment by the high-density plasma treatment are continuously performed without being exposed to the atmosphere. By continuously performing the high-density plasma treatment, it is possible to prevent contamination from entering and improve production efficiency.

Note that in the case where the semiconductor layer is oxidized by high-density plasma treatment, an atmosphere containing oxygen (for example, oxygen (O ₂ ) or dinitrogen monoxide (N ₂ O) and a rare gas (He, Ne, Ar, Kr And at least one of Xe), oxygen, or dinitrogen monoxide and hydrogen (H ₂ ) and a rare gas atmosphere. On the other hand, in the case of nitriding a semiconductor layer by high-density plasma treatment, an atmosphere containing nitrogen (for example, an atmosphere containing nitrogen (N ₂ ) and a rare gas (containing at least one of He, Ne, Ar, Kr, and Xe)) Under nitrogen, hydrogen, and rare gas atmosphere, or NH ₃ and rare gas atmosphere).

As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. When the high-density plasma treatment is performed in a rare gas atmosphere, the first insulating layer 105 includes a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma treatment. In some cases, when Ar is used, the first insulating layer 105 may contain Ar.

The high-density plasma treatment is performed in an atmosphere of the above gas at an electron density of 1 × 10 ¹¹ cm ⁻³ or more and an electron temperature of plasma of 1.5 eV or less. More specifically, the electron density is 1 × 10 ¹¹ cm ^{−3 to} 1 × 10 ¹³ cm ⁻³ and the plasma electron temperature is 0.5 eV to 1.5 eV. Since the electron density of plasma is high and the electron temperature in the vicinity of an object to be processed (here, a semiconductor layer) formed on the substrate 100 is low, damage to the object to be processed can be prevented. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or higher, an oxide or a nitride film formed by oxidizing or nitriding an object to be processed using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1.5 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature lower than 100 degrees below the strain point of the glass substrate, the oxidation or nitridation treatment can be sufficiently performed. As a frequency for forming plasma, a high frequency such as a microwave (eg, 2.45 GHz) can be used.

In this embodiment, when an object to be processed is oxidized by high-density plasma treatment, a mixed gas of oxygen (O ₂ ), hydrogen (H ₂ ), and argon (Ar) is introduced. The mixed gas used here may be introduced with 0.1 to 100 sccm of oxygen, 0.1 to 100 sccm of hydrogen, and 100 to 5000 sccm of argon. Note that the mixed gas is preferably introduced at a ratio of oxygen: hydrogen: argon = 1: 1: 100. For example, oxygen may be introduced at 5 sccm, hydrogen at 5 sccm, and argon at 500 sccm.

In addition, when performing nitriding treatment by high-density plasma treatment, a mixed gas of nitrogen (N ₂ ) and argon (Ar) is introduced. The mixed gas used here may be introduced at 20 to 2000 sccm of nitrogen and 100 to 10,000 sccm of argon. For example, nitrogen may be introduced at 200 sccm and argon at 1000 sccm.

In this embodiment mode, the first insulating layer 105 formed over the semiconductor layer provided in the memory portion functions as a tunnel oxide film in a nonvolatile memory element completed later. Therefore, the thinner the first insulating layer 105 is, the easier it is for the tunnel current to flow, so that the memory can operate at high speed. In addition, the thinner the first insulating layer 105 is, the more charge can be stored in a charge storage layer formed later at a low voltage, so that power consumption of the semiconductor device can be reduced. Therefore, the first insulating layer 105 is preferably formed thin.

In general, there is a thermal oxidation method as a method for forming a thin insulating layer over a semiconductor layer. However, when a substrate having a sufficiently low melting point such as a glass substrate is used as the substrate 100, the first method is performed by the thermal oxidation method. It is very difficult to form the insulating layer 105. In addition, an insulating layer formed by a CVD method or a sputtering method includes defects inside the film, so that the film quality is not sufficient, and there is a problem that defects such as pinholes occur when the film thickness is thin. In addition, in the case where the insulating layer is formed by a CVD method or a sputtering method, the end of the semiconductor layer is not sufficiently covered, and the conductive layer and the like which are formed later on the first insulating layer 105 and the semiconductor layer are short-circuited. There is a case. Therefore, as shown in this embodiment mode, by forming the first insulating layer 105 by high-density plasma treatment, an insulating layer denser than an insulating layer formed by a CVD method, a sputtering method, or the like can be formed. As a result, high-speed operation and charge retention characteristics as a memory can be improved. Note that in the case where the first insulating layer 105 is formed by a CVD method or a sputtering method, after the insulating layer is formed, high-density plasma treatment is performed, and the surface of the insulating layer is oxidized, nitrided, or oxynitrided. It is preferable.

The charge storage layer 106 functioning as a floating gate can be formed using silicon, a silicon compound, germanium, or a germanium compound. As the silicon compound, silicon germanium, metal nitride, metal oxide, or the like containing silicon nitride, silicon nitride oxide, silicon carbide, germanium at a concentration of 10 atomic% or more can be used. A typical example of the germanium compound is silicon germanium. In this case, it is preferable that germanium is contained at 10 atomic% or more with respect to silicon. This is because if the germanium concentration is 10 atomic% or less, the effect as a constituent element is reduced, and the band gap is not effectively reduced.

The charge accumulation layer 106 is applied to the semiconductor device according to the present invention for the purpose of accumulating charges, but other materials can be applied as long as they have the same function. For example, a ternary semiconductor containing germanium may be used. Further, the semiconductor material may be hydrogenated. Further, it can be replaced with an oxide or nitride layer of germanium or a germanium compound as a function as a charge storage layer of the nonvolatile memory element.

Further, a metal nitride or a metal oxide can be used for forming the charge storage layer 106. As the metal nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium nitride, or the like can be used. As the metal oxide, tantalum oxide, titanium oxide, tin oxide, or the like can be used.

Alternatively, the charge storage layer 106 may be formed using a stacked structure of the above materials. When the above-described silicon or silicon compound, metal nitride or metal oxide layer is provided on the upper layer side of the layer formed of germanium or germanium compound, a barrier for water resistance and chemical resistance is provided in the manufacturing process. Can be used as a layer. Thereby, the handling of the substrate in the photolithography process, the etching process, and the cleaning process becomes easy, and the productivity can be improved. That is, the charge storage layer can be easily processed.

The first insulating layer 105 and the charge storage layer 106 are processed into desired shapes, so that the first insulating layer 107 and the charge storage layer 108 are formed over the element region 102c used as a memory element (see FIG. 5E). .) Further, a mask layer 120 is formed over the charge storage layer 108, and the charge storage layer 108 is selectively etched using the mask layer 120, whereby the charge storage layer 109 is formed (see FIG. 5F).

  Next, an impurity region is formed in a specific region of the element region 102d. Here, after removing the mask layer 120, mask layers 121a, 121b, 121c, 121d, 121e, and 121f are formed so as to selectively cover the element regions 102a, 102b, and 102c and part of the element region 102d. Impurity regions 122a and 122b are formed by introducing the impurity element 119 into the element region 102d which is not covered with the mask layers 121a to 121f (see FIG. 6A). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is introduced as an impurity element into the element region 102d.

Next, a second insulating layer 123 is formed so as to cover the element region 102d and the first insulating layer 107 and the charge storage layer 109 formed above the element region 102c.

The second insulating layer 123 is formed using silicon oxide, silicon nitride, silicon oxynitride (SiOxNy) (x> y> 0), silicon nitride oxide (SiNxOy) (x> y> 0) by a CVD method, a sputtering method, or the like. ) Or the like, and a single layer or a stacked layer. The second insulating layer 123 may be formed using aluminum oxide (AlOx), hafnium oxide (HfOx), or tantalum oxide (TaOx). For example, in the case where the second insulating layer 123 is provided as a single layer, a silicon oxynitride film or a silicon nitride oxide film is formed with a thickness of 5 to 50 nm by a CVD method. In the case where the second insulating layer 123 is provided in a three-layer structure, a silicon oxynitride film is formed as the first insulating layer, a silicon nitride film is formed as the second insulating layer, A silicon oxynitride film is formed as the insulating layer. Alternatively, germanium oxide or nitride may be used for the second insulating layer 123.

  Note that the second insulating layer 123 formed above the element region 102c functions as a control insulating layer in a nonvolatile memory element to be completed later, and the second insulating layer 123 formed above the element region 102d is It functions as a gate insulating layer in a transistor to be completed later.

  Next, a third insulating layer 135 is formed so as to cover the element regions 102a and 102b.

  The third insulating layer 135 is formed using any of the methods described in the method for forming the first insulating layer 105. For example, by performing oxidation treatment, nitridation treatment, or oxynitridation treatment on a semiconductor layer including the element regions 102a and 102b and the element isolation regions 101a, 101b, 101c, and 101d by high-density plasma treatment, silicon is formed on each of the semiconductor layers. A third insulating layer 135 to be an oxide film, a nitride film, or an oxynitride film is formed.

Here, the third insulating layer 135 is formed with a thickness of 1 to 20 nm, preferably 1 to 10 nm. For example, the semiconductor layer is oxidized by high-density plasma treatment to form a silicon oxide film on the surface of the semiconductor layer including the element regions 102a and 102b and the element isolation regions 101a, 101b, 101c, and 101d, and then the high-density plasma treatment is performed. A silicon oxynitride film is formed on the surface of the silicon oxide film by performing nitriding treatment. In this case, the surface of the second insulating layer 123 formed above the element regions 102c and 102d is also oxidized or nitrided to form an oxide film or oxynitride film. The third insulating layer 135 formed above the element regions 102a and 102b functions as a gate insulating layer in a transistor to be completed later.

Next, a conductive film is formed so as to cover the third insulating layer 135 formed above the element regions 102a and 102b and the second insulating layer 123 formed above the element regions 102c and 102d in the semiconductor layer. . Here, an example in which a first conductive film and a second conductive film are sequentially stacked as the conductive film is shown. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

As the first conductive film and the second conductive film, tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium It can be formed of an element selected from (Nb) or the like, or an alloy material or compound material containing these elements as main components. Alternatively, a metal nitride film obtained by nitriding these elements can be used. In addition, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used.

Here, the first conductive film is formed using tantalum nitride, and the second conductive film is formed using tungsten as a stacked structure. In addition, a single layer or laminated film selected from tungsten nitride, molybdenum nitride, or titanium nitride is used as the first conductive film, and a single film selected from tantalum, molybdenum, or titanium is used as the second conductive film. A layer or a laminated film can be used.

Next, the first conductive film and the second conductive film which are provided in a stacked manner are selectively removed by etching, so that part of the semiconductor layer above the element regions 102a, 102b, 102c, and 102e is removed. First conductive layer 124a, 124b, 124c, 124d and second conductive layers 125a, 125b, 125c, 125d functioning as gate electrode layers, respectively, are formed by leaving the first conductive film and the second conductive film. (See FIG. 6B). Note that the first conductive layer 124c and the second conductive layer 125c formed above the element region 102c provided in the memory portion function as a control gate electrode layer in a nonvolatile memory element completed later. The first conductive layers 124a, 124b, and 124d and the second conductive layers 125a, 125b, and 125d function as gate electrode layers in transistors that are completed later.

Next, mask layers 126a, 126b, 126c, 126d, and 126e are selectively formed so as to cover the element regions 102a, 102c, and 102d, and the mask layers 126a to 126e, the first conductive layer 124b, and the second conductive layer are formed. An impurity region is formed by introducing the impurity element 127 into the element region 102b using the layer 125b as a mask (see FIG. 6C). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, an impurity element (eg, boron (B)) having a conductivity type different from that of the impurity element introduced into the element region 102d in FIG. 6A is introduced. As a result, high-concentration impurity regions 132a and 132b for forming a source region or a drain region and a channel formation region 134 are formed in the element region 102b.

  Next, mask layers 128a, 128b, 128c, 128d, 128e, 128f, and 128g are selectively formed so as to cover the element region 102b, and the mask layers 128a to 128g and the first conductive layers 124a, 124c, 124d, Then, impurity regions are formed by introducing the impurity element 129 into the element regions 102a, 102c, and 102d using the second conductive layers 125a, 125c, and 125d as masks (see FIG. 6D). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is used as the impurity element.

In FIG. 6D, by introducing the impurity element 129, high-concentration impurity regions 130a and 130b for forming a source region or a drain region and a channel formation region 135a are formed in the element region 102a. In the element region 102c, high-concentration impurity regions 130c and 130d that form source regions or drain regions, low-concentration impurity regions 131a and 131b that form LDD regions, and a channel formation region 135b are formed. In the element region 102d, high-concentration impurity regions 130e and 130f that form source regions or drain regions, low-concentration impurity regions 131c and 131d that form LDD regions, and a channel formation region 135c are formed.

The low-concentration impurity regions 131a and 131b formed in the element region 102c are formed when the impurity element introduced in FIG. 6D penetrates the charge storage layer 109 functioning as a floating gate. Therefore, in the element region 102c, a channel formation region 135b is formed in a region overlapping with both the second conductive layer 125c and the charge storage layer 109, and is low in a region overlapping with the charge storage layer 109 and not overlapping with the second conductive layer 125c. Concentrated impurity regions 131a and 131b are formed, and high-concentration impurity regions 130c and 130d are formed in regions that do not overlap both the charge storage layer 109 and the second conductive layer 125c.

Next, an insulating layer 133 is formed so as to cover the second insulating layer 123, the third insulating layer 135, the first conductive layers 124 a to 124 d, and the second conductive layers 125 a to 125 d, and over the insulating layer 133 Wiring layers 136a, 136b, 136c, 136d, 136e, 136f, 136g, and 136h electrically connected to the high-concentration impurity regions 130a to 130f, 132a, and 132b formed in the element regions 102a, 102b, 102c, and 102d, respectively. It is formed (see FIG. 6E).

  The insulating layer 133 is formed by silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y> 0), silicon nitride oxide (SiNxOy) (x> y>) by CVD or sputtering. 0) and other oxygen- or nitrogen-containing insulating layers, carbon-containing films such as DLC (diamond-like carbon), organic materials such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, and acrylic, or siloxane materials such as siloxane resins It can be provided in a single layer or laminated structure.

  The wiring layers 136a to 136h are made of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), CVD, sputtering, or the like. An element selected from copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or an alloy containing these elements as a main component The material or compound material is formed as a single layer or a stacked layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The wiring layers 136a to 136h include, for example, a laminated structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, and a laminated structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride (TiN) film, and a barrier film. A structure should be adopted. Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Since aluminum and aluminum silicon have a low resistance value and are inexpensive, they are optimal materials for forming the wiring layers 136a to 136h. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor layer, the natural oxide film is reduced, so that the crystalline semiconductor layer is in good condition. Contact can be made.

Therefore, when the present invention is used, the semiconductor layer can be separated into a plurality of element regions without being divided into islands. Since the step due to the end portion of the semiconductor layer does not occur and the insulating layer is formed on the flat semiconductor layer, the coverage of the insulating layer is improved. Therefore, a semiconductor device which is a highly reliable nonvolatile semiconductor memory device in which defects such as a charge accumulation layer, a control gate electrode layer, a short-circuit between the gate electrode layer and the semiconductor layer and a leakage current due to a poor coating of the insulating layer are prevented, and A method for manufacturing such a semiconductor device can be provided. Therefore, further miniaturization and high integration can be performed in the semiconductor device, and high performance of the semiconductor device can be achieved. In addition, since defects due to such a film shape defect are reduced, production can be performed with high yield even in the manufacturing process.

  This embodiment can be implemented in combination with any of the other embodiments described in this specification.

(Embodiment 8)
In this embodiment mode, a CMOS circuit and a memory for preventing a short circuit between a gate electrode layer and a semiconductor layer due to a poor coating of an insulating layer and a leakage current in a semiconductor element, and providing higher reliability An example of another semiconductor device having an element will be described with reference to the drawings. A method for manufacturing a semiconductor device in this embodiment will be described in detail with reference to FIGS. The present embodiment is different from the semiconductor device of the seventh embodiment in that the shapes of the gate electrode layer and the control gate electrode layer are different. Is omitted.

Over a substrate 100 having an insulating surface, an insulating layer 112a and an insulating layer 112b functioning as a base film are stacked as a base film.

Next, the semiconductor layer 150 is formed over the base film. The semiconductor layer 150 may be formed by various means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) with a thickness of 25 to 200 nm (preferably 30 to 150 nm). In this embodiment mode, it is preferable to use a crystalline semiconductor layer obtained by crystallizing an amorphous semiconductor layer by laser crystallization.

The semiconductor layer thus obtained may be doped with a trace amount of an impurity element (boron or phosphorus) in order to control the threshold voltage of the thin film transistor. This doping of the impurity element may be performed on the amorphous semiconductor layer before the crystallization step. When an impurity element is doped in the state of the amorphous semiconductor layer, the impurity can be activated by heat treatment for subsequent crystallization. In addition, defects and the like generated during doping can be improved.

The mask is removed, and the first insulating layer 105 is formed over the semiconductor layer 150.

The first insulating layer 105 can be formed by performing heat treatment, plasma treatment, or the like on the semiconductor layer. For example, by performing oxidation treatment, nitridation treatment, or oxynitridation treatment on the semiconductor layer by high-density plasma treatment, the first insulating layer 105 that becomes an oxide film, a nitride film, or an oxynitride film is formed over the semiconductor layer, respectively. To do. In addition, you may form by plasma CVD method or a sputtering method.

For example, when a semiconductor layer containing Si as a main component is used as a semiconductor layer and oxidation or nitridation is performed by high-density plasma treatment, a silicon oxide layer or a silicon nitride layer is formed as the first insulating layer 105. Alternatively, after the semiconductor layer is oxidized by high-density plasma treatment, nitriding treatment may be performed by performing high-density plasma treatment again. In this case, a silicon oxide layer is formed in contact with the semiconductor layer, and a nitrogen plasma treatment layer is formed on or near the surface of the silicon oxide layer.

Here, the first insulating layer 105 is formed with a thickness of 1 to 10 nm, preferably 1 to 5 nm. For example, the semiconductor layer is oxidized by high-density plasma treatment to form a silicon oxide layer having a thickness of about 3 nm on the surface of the semiconductor layer, and then nitrided by high-density plasma treatment to be near or near the surface of the silicon oxide layer. A nitrogen plasma treatment layer is formed. Specifically, first, a silicon oxide layer is formed with a thickness of 3 nm to 6 nm on the semiconductor layer by plasma treatment in an oxygen atmosphere. Then, a nitrogen plasma processing layer having a high nitrogen concentration is provided on or near the surface of the silicon oxide layer by subsequently performing plasma processing in a nitrogen atmosphere. Here, a plasma treatment is performed in a nitrogen atmosphere to form a structure in which nitrogen is contained at a ratio of 20 to 50 atomic% at a depth of approximately 1 nm from the surface of the silicon oxide layer. In the nitrogen plasma treatment layer, silicon (silicon oxynitride) containing oxygen and nitrogen is formed. At this time, it is preferable that the oxidation treatment and the nitriding treatment by the high-density plasma treatment are continuously performed without being exposed to the atmosphere. By continuously performing the high-density plasma treatment, it is possible to prevent contamination from entering and improve production efficiency.

In this embodiment mode, the first insulating layer 105 formed over the semiconductor layer provided in the memory portion functions as a tunnel oxide film in a nonvolatile memory element completed later. Therefore, the thinner the first insulating layer 105 is, the easier it is for the tunnel current to flow, so that the memory can operate at high speed. In addition, the thinner the first insulating layer 105 is, the more charge can be stored in a charge storage layer formed later at a low voltage, so that power consumption of the semiconductor device can be reduced. Therefore, the first insulating layer 105 is preferably formed thin.

An impurity element is selectively added to the semiconductor layer which is a crystalline semiconductor layer through the first insulating layer 105, so that an element isolation region is formed. The semiconductor layer is separated into a plurality of element regions by the element isolation region. Mask layers 103a, 103b, 103c, and 103d are formed over the semiconductor layer, and an impurity element 104 that does not contribute to conductivity is added. By adding the impurity element 104 that does not contribute to conductivity, the element isolation regions 651a, 651b, 651c, 651d, 651e, 651f, 651g, 651h, and the element regions 102a, 102b insulated and isolated by the element isolation regions are formed in the semiconductor layer. , 102c, 102d are formed (see FIG. 7B).

Next, mask layers 652a, 652b covering part of the element regions 102a, 102b, 102c, 102d, the element isolation regions 651c, 651d, the element isolation regions 651a, 651b, 651e, 651f, 651g, 651h on the semiconductor layer. , 652c and 652d are formed, and an impurity element 653 imparting p-type conductivity is added through the first insulating layer 105. By adding the impurity element 653 imparting p-type conductivity, second element isolation regions 101a, 101b, 101c, 101d, 101e, and 101f that are p-type impurity regions are formed in the semiconductor layer (FIG. 7C). reference.). First element isolation regions 660a, 660b, 660c, 660d, 660e, and 660f are formed in a region to which the impurity element 653 imparting p-type is not added.

Next, element regions 102a, 102b, 102c, and 102d, first element isolation regions 660a, 660b, 660c, 660d, 660e, and 660f, and second element isolation regions 101a, 101b, 101c, and 101d are formed on the semiconductor layer. , 101e and 101f are formed, and mask elements 654a, 654b, 654c, and 654d are formed, and an impurity element 655 imparting n-type conductivity is added through the first insulating layer 105. By the addition of the impurity element 655 imparting n-type conductivity, second element isolation regions 656a and 656b which are n-type impurity regions are formed in the semiconductor layer (see FIG. 7D). First element isolation regions 661a and 661b are formed in a region to which the impurity element 655 imparting n-type conductivity is not added.

In this embodiment mode, the element isolation region and the element region are provided in the continuous semiconductor layer. Therefore, the first element isolation regions 660a, 660b, 660c, 660d, 660e, 660f, 661a, and 661b are provided in the semiconductor layer. , And second element isolation regions 101a, 101b, 101c, 101d, 101e, 101f, 656a, 656b, and element regions 102a, 102b, 102c, 102d that are insulated and isolated by the element isolation regions are continuous. Therefore, the surface has high flatness and does not have a steep step.

Since the impurity element is added to the semiconductor layer 150 through the first insulating layer 105 by a doping method or the like, physical energy at the time of adding the impurity element can be adjusted. Therefore, the added energy can be relaxed to such an extent that the semiconductor layer is not damaged such as destruction, and the crystallinity of the semiconductor layer can be selectively lowered to form an element isolation region. The first insulating layer 105 may be formed once again by removing an impurity element after introducing an impurity element and forming an element isolation region and an element region. Further, the re-formed insulating layer may be subjected to plasma treatment to densify the surface.

In this embodiment, in order to form a plurality of semiconductor elements over an insulating surface, a semiconductor layer is not separated into a plurality of island-shaped semiconductor layers, and a plurality of element regions functioning as semiconductor elements in one semiconductor layer As the element isolation region for electrically insulating and isolating the first and second element isolation regions having high resistance, the second element isolation region having a conductivity type opposite to the source and drain regions of the element region is formed. To do.

The plurality of element regions are provided around the element region so as to surround the second element isolation region which is an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region. A first element isolation region, which is a high resistance region, is provided adjacent to the outer side of the two element isolation regions. Therefore, the adjacent first element region and second element region are the second element isolation region in contact with the first element region, the first element isolation region, and the second element isolation in contact with the second element region. Adjacent through a region.

In the case where the source region and the drain region of the first element region and the second element region have the same electric type, for example, in the case of an n-type impurity region, the second element isolation region also has the opposite conductivity type to the element region. It becomes a p-type impurity region. On the other hand, the first element region and the second element are such that the source region and the drain region of the first element region are n-type impurity regions, and the source region and the drain region of the second element region are p-type impurity regions. When the regions are of the opposite conductivity type, the second element isolation region included in each region is also combined with the element regions, and the first element region side is a p-type impurity region, and the second element region side is an n-type impurity region. It becomes.

The first element isolation region adjacent to the element region via the second element isolation region is the first element that does not selectively contribute to conductivity in order to electrically isolate the elements in one semiconductor layer. It is formed by adding an impurity element.

As the first impurity element that does not contribute to conductivity (does not improve conductivity), at least one impurity element of oxygen, nitrogen, and carbon can be used. In the element isolation region to which the first impurity element is added, the conductivity decreases due to the mixing of the first impurity element that does not contribute to the conductivity, and also due to physical impact on the semiconductor layer at the time of addition (so-called sputtering effect). Increased resistance due to lower crystallinity. In the element isolation region with a high resistance, the field effect mobility is also reduced, so that the elements can be electrically isolated, while the region to which no impurity element is added maintains the field effect mobility that can function as an element. Therefore, it can be used as an element region.

The resistance of the first element isolation region is preferably 1 × 10 ¹⁰ Ω · cm or more, and the concentration of the first impurity element such as oxygen, nitrogen, or carbon is 1 × 10 ²⁰ cm ⁻³ or more and 4 × 10 ²² cm. Less than ^-3 is preferable.

The first element isolation region can be said to be amorphous because the crystallinity is lowered by the addition of the impurity element. On the other hand, since the element region is a crystalline semiconductor layer, when a semiconductor element is formed in the element region, the crystallinity of the channel formation region is higher than that of the first element isolation region, and high field effect mobility can be obtained as a semiconductor element. it can.

As the first impurity element added to the first element isolation region, a rare gas element such as argon (Ar), neon (Ne), krypton (Kr), or xenon (Xe) may be used. In addition to oxygen, nitrogen, and carbon, the addition of these rare gas elements, which are relatively large elements, can increase the physical impact on the semiconductor layer. The crystallinity of the element isolation region can be reduced.

The second element isolation region provided between the element region and the first element isolation region in contact with the element region is added with a second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region. Form.

The element region has a source region, a drain region, and a channel formation region. The source region and the drain region are impurity regions having one conductivity type (for example, an n-type impurity region or a p-type impurity region). A second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region is added to the second element isolation region, and the second element isolation region is used as a source region and a drain in the adjacent element region. The impurity region has a conductivity type opposite to that of the region. That is, when the source region and the drain region in the element region are n-type impurity regions, the adjacent second element isolation region is a p-type impurity region, and similarly, the source region and the drain region in the element region are p-type impurity regions. In some cases, the adjacent second element isolation region may be an n-type impurity region. The adjacent element region and the second element isolation region form a PN junction. Therefore, the element regions can be further insulated and separated by the second element isolation region provided between the element regions.

The present invention provides a first element isolation region which is a high resistance region by addition of a first impurity element that does not contribute to conductivity as an element isolation region for insulating and isolating element regions, and further, a source region and a drain region in the element region A semiconductor layer is separated into a plurality of element regions by providing a second element isolation region which is an impurity region by addition of a second impurity element imparting a reverse conductivity type. According to the present invention, since the element regions can be separated from each other by the effects of the first element isolation region and the second element isolation region, a higher element isolation effect can be obtained.

For the addition (introduction) of the impurity element in forming the first element isolation region and the second element isolation region, an ion implantation method, an (ion) doping method, or the like can be used.

Further, the element isolation region may have a concentration gradient of the first impurity element and the second impurity element. Of course, the first impurity element and the second impurity element may be added to the first and second element isolation regions at a substantially uniform concentration. That is, the concentration peak of the first impurity element and the second impurity element can be set as appropriate in the first and second element isolation regions. The second element isolation region may be an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region in contact with the second element isolation region. An impurity element imparting a mold may be contained. The second element isolation region may contain the first impurity element described above, and the second element isolation region may be added by adding the second impurity element to a part of the first element isolation region. It can also be formed.

Since the first insulating layer 105 is formed over a semiconductor layer with high flatness, the first insulating layer 105 has good coverage and is less likely to have a shape defect. Therefore, defects such as a leakage current and a short circuit can be prevented in the charge storage layer 106 and the element region 102c formed over the first insulating layer 105. Therefore, the semiconductor device which is the nonvolatile semiconductor memory device of this embodiment has defects such as a charge accumulation layer due to a coating failure of the first insulating layer, a short circuit between a control gate electrode layer to be formed later and the semiconductor layer, and a leakage current. The semiconductor device can be prevented with high reliability.

A charge storage layer 106 is formed over the first insulating layer 105 (see FIG. 7E).

The charge storage layer 106 can be formed using silicon, a silicon compound, germanium, or a germanium compound. As the silicon compound, silicon germanium, metal nitride, metal oxide, or the like containing silicon nitride, silicon nitride oxide, silicon carbide, germanium at a concentration of 10 atomic% or more can be used. A typical example of the germanium compound is silicon germanium. In this case, it is preferable that germanium is contained at 10 atomic% or more with respect to silicon. This is because if the germanium concentration is 10 atomic% or less, the effect as a constituent element is reduced, and the band gap is not effectively reduced.

The charge accumulation layer 106 is applied to the semiconductor device according to the present invention for the purpose of accumulating charges, but other materials can be applied as long as they have the same function. For example, a ternary semiconductor containing germanium may be used. Further, the semiconductor material may be hydrogenated. Further, it can be replaced with an oxide or nitride layer of germanium or a germanium compound as a function as a charge storage layer of the nonvolatile memory element.

Further, a metal nitride or a metal oxide can be used for forming the charge storage layer 106. As the metal nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium nitride, or the like can be used. As the metal oxide, tantalum oxide, titanium oxide, tin oxide, or the like can be used.

Alternatively, the charge storage layer 106 may be formed using a stacked structure of the above materials. When the above-described silicon or silicon compound, metal nitride or metal oxide layer is provided on the upper layer side of the layer formed of germanium or germanium compound, a barrier for water resistance and chemical resistance is provided in the manufacturing process. Can be used as a layer. Thereby, the handling of the substrate in the photolithography process, the etching process, and the cleaning process becomes easy, and the productivity can be improved. That is, the charge storage layer can be easily processed.

The first insulating layer 105 and the charge storage layer 106 are processed into desired shapes, so that the first insulating layer 107 and the charge storage layer 108 are formed over the element region 102c used as a memory element (see FIG. 7F). .) Further, a mask layer 120 is formed over the charge storage layer 108, and the charge storage layer 109 is selectively etched using the mask layer 120 to form the charge storage layer 109 (see FIG. 8A).

Next, a second insulating layer 123 is formed so as to cover the element region 102d and the first insulating layer 107 and the charge storage layer 109 formed above the element region 102c.

  Note that the second insulating layer 123 formed above the element region 102c functions as a control insulating layer in a nonvolatile memory element to be completed later, and the second insulating layer 123 formed above the element region 102d is It functions as a gate insulating layer in a transistor to be completed later.

  Next, a third insulating layer 135 is formed so as to cover the element regions 102a and 102b.

Next, a conductive film is formed so as to cover the third insulating layer 135 formed above the element regions 102a and 102b and the second insulating layer 123 formed above the element regions 102c and 102d in the semiconductor layer. . Here, an example in which a first conductive film and a second conductive film are sequentially stacked as the conductive film is shown. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

Next, the first conductive film and the second conductive film provided in a stacked manner are selectively removed by etching, so that part of the semiconductor layer above the element regions 102a, 102b, 102c, and 102d is removed. And the first conductive layers 154a, 154b, 154c, and 154d, and the second conductive layers 155a, 155b, 155c, and 155d, which function as gate electrode layers, respectively, are formed. (See FIG. 8B). Note that the first conductive layer 154c and the second conductive layer 155c formed above the element region 102c provided in the memory portion function as a control gate electrode layer in a nonvolatile memory element to be completed later. The first conductive layers 154a, 154b, and 154d and the second conductive layers 155a, 155b, and 155d function as gate electrode layers in transistors that are completed later.

  Next, mask layers 156a, 156b, 156c, 156d, and 156e are selectively formed so as to cover the element regions 102a, 102c, and 102d, and the mask layers 156a to 156e, the first conductive layer 154b, and the second conductive layer are formed. An impurity region is formed by introducing the impurity element 157 into the element region 102b using the layer 155b as a mask (see FIG. 8C). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, an impurity element (eg, boron (B)) is introduced. As a result, high concentration impurity regions 162a and 162b that form source regions or drain regions, low concentration impurity regions 164a and 164b that form LDD regions, and a channel formation region 165 are formed in the element region 102b.

  Next, mask layers 158a, 158b, 158c, 158d, 158e, 158f, and 158g are selectively formed so as to cover the element region 102b, and the mask layers 158a to 158g, the first conductive layers 154a, 154c, and 154d, Then, an impurity region is formed by introducing the impurity element 159 into the element regions 102a, 102c, and 102d using the second conductive layers 155a, 155c, and 155d as masks (see FIG. 8D). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is used as the impurity element.

  In FIG. 8D, by introducing an impurity element, high-concentration impurity regions 160a and 160b that form source regions or drain regions in the element region 102a, low-concentration impurity regions 161e and 161f that form LDD regions, and channels A formation region 167a is formed. In the element region 102c, high-concentration impurity regions 160c and 160d that form source regions or drain regions, low-concentration impurity regions 161a and 161b that form LDD regions, and a channel formation region 167b are formed. In the element region 102d, high-concentration impurity regions 160e and 160f that form source regions or drain regions, low-concentration impurity regions 161c and 161d that form LDD regions, and a channel formation region 167c are formed.

  Next, an insulating layer 163 is formed so as to cover the second insulating layer 123, the third insulating layer 135, the first conductive layers 154a to 154d, and the second conductive layers 155a to 155d, and the insulating layer 163 is formed over the insulating layer 163. Wiring layers 166a, 166b, 166c, 166d, 166e, 166f, 166g, 166h electrically connected to the high-concentration impurity regions 160a to 160f, 162a, 162b formed in the element regions 102a, 102b, 102c, 102d, respectively. It is formed (see FIG. 8E).

Therefore, when the present invention is used, the semiconductor layer can be separated into a plurality of element regions without being divided into islands. Since the step due to the end portion of the semiconductor layer does not occur and the insulating layer is formed on the flat semiconductor layer, the coverage of the insulating layer is improved. Therefore, a semiconductor device which is a highly reliable nonvolatile semiconductor memory device in which defects such as a short circuit between the charge storage layer, the control gate electrode layer, or the gate electrode layer and the semiconductor layer and a leakage current due to a poor coating of the insulating layer are prevented And a method for manufacturing such a semiconductor device can be provided. Therefore, further miniaturization and high integration can be performed in the semiconductor device, and high performance of the semiconductor device can be achieved. In addition, since defects due to such a film shape defect are reduced, production can be performed with high yield even in the manufacturing process.

  This embodiment can be implemented in combination with any of the other embodiments described in this specification.

(Embodiment 9)
In this embodiment mode, a CMOS circuit and a memory for preventing a short circuit between a gate electrode layer and a semiconductor layer due to a poor coating of an insulating layer and a leakage current in a semiconductor element, and providing higher reliability An example of another semiconductor device having an element will be described with reference to the drawings. A method for manufacturing a semiconductor device in this embodiment will be described in detail with reference to FIGS. The present embodiment is different from the semiconductor device of the seventh embodiment in that the shapes of the first insulating layer and the second insulating layer are different. The description is omitted.

In Embodiment Mode 9, a semiconductor device including the CMOS circuit and the memory element in this embodiment mode is manufactured up to the state of FIG.

  As shown in FIG. 9A, mask layers 170a, 170b, 170c, 170d, and 170e are selectively formed so as to cover the element regions 102a, 102c, and 102d, and the mask layers 170a to 170e and the first conductive layers are formed. An impurity region is formed by introducing the impurity element 171 into the element region 102b using the layer 154b and the second conductive layer 155b as masks (see FIG. 9A). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, an impurity element (eg, boron (B)) is introduced. As a result, impurity regions 172a and 172b are formed in the element region 102b.

Next, mask layers 173a, 173b, 173c, 173d, 173e, 173f, and 173g are selectively formed so as to cover the element region 102b, and the mask layers 173a to 173g, the first conductive layers 154a, 154c, 154d, Then, impurity regions are formed by introducing the impurity element 174 into the element regions 102a, 102c, and 102d using the second conductive layers 155a, 155c, and 155d as masks (see FIG. 9B). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is used as the impurity element.

  In FIG. 9B, impurity regions 175 a and 175 b are formed in the element region 102 a by introducing the impurity element 174. Impurity regions 175c and 175d are formed in the element region 102c. Impurity regions 175e and 175f are formed in the element region 102d.

  Next, the first insulating layer 107, the second insulating layer 123, and the third insulating layer 135 are selectively etched using the first conductive layers 154a to 154d and the second conductive layers 155a to 155d as a mask, Insulating layers 188a and 188b and insulating layers 189a, 189b and 189c are formed. First conductive layers 154a to 154d, second conductive layers 155a to 155d, charge storage layer 109, insulating layers 188a and 188b, and insulating layers (also referred to as sidewalls) 176a and 176b that are in contact with the side surfaces of the insulating layers 189a to 189c 176c, 176d, 176e, 176f, 176g, and 176h are formed.

  As shown in FIG. 10A, mask layers 178a, 178b, 178c, 178d, and 178e are selectively formed so as to cover the element regions 102a, 102c, and 102d, and the mask layers 178a to 178e and the first conductive layer are formed. An impurity region is formed by introducing the impurity element 179 into the element region 102b using the layer 154b, the second conductive layer 155b, and the insulating layers 176c, 176d, and 189a as masks (see FIG. 10A). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, an impurity element (eg, boron (B)) is introduced. As a result, high-concentration impurity regions 180a and 180b that form source or drain regions, low-concentration impurity regions 187a and 187b that form LDD regions, and a channel formation region 169 are formed in the element region 102b.

  Next, mask layers 181a, 181b, 181c, 181d, 181e, 181f, and 181g are selectively formed so as to cover the element region 102b, and the mask layers 181a to 181g, the first conductive layers 154a, 154c, 154d, Impurity regions are formed by introducing the impurity element 182 into the element regions 102a, 102c, and 102d using the second conductive layers 155a, 155c, and 155d and the insulating layers 176a, 176b, 176e, 176f, 176g, and 176h as masks (FIG. 10 (B)). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is used as the impurity element.

  In FIG. 10B, by introducing an impurity element, high-concentration impurity regions 183a and 183b that form source regions or drain regions in the element region 102a, low-concentration impurity regions 184a and 184b that form LDD regions, and channels A formation region 198a is formed. In the element region 102c, high-concentration impurity regions 183c and 183d forming a source region or a drain region, low-concentration impurity regions 184c and 184d forming an LDD region, and a channel formation region 198b are formed. In the element region 102d, high-concentration impurity regions 183e and 183f that form source regions or drain regions, low-concentration impurity regions 184e and 184f that form LDD regions, and a channel formation region 198c are formed.

  Next, insulating layers 199 and 186 are formed so as to cover the first conductive layers 154a to 154d, the second conductive layers 155a to 155d, and the insulating layers 176a to 176h, and the element region 102a is formed over the insulating layers 199 and 186. , 102b, 102c, and 102d, wiring layers 185a, 185b, 185c, 185d, 185e, 185f, 185g, and 185h that are electrically connected to the high concentration impurity regions 183a to 183f, 180a, and 180b, respectively, are formed (FIG. 10 (C)).

In this embodiment, in order to form a plurality of semiconductor elements over an insulating surface, a semiconductor layer is not separated into a plurality of island-shaped semiconductor layers, and a plurality of element regions functioning as semiconductor elements in one semiconductor layer As the element isolation region for electrically insulating and isolating the first and second element isolation regions having high resistance, the second element isolation region having a conductivity type opposite to the source and drain regions of the element region is formed. To do.

The plurality of element regions are provided around the element region so as to surround the second element isolation region which is an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region. A first element isolation region, which is a high resistance region, is provided adjacent to the outer side of the two element isolation regions. Therefore, the adjacent first element region and second element region are the second element isolation region in contact with the first element region, the first element isolation region, and the second element isolation in contact with the second element region. Adjacent through a region.

In the case where the source region and the drain region of the first element region and the second element region have the same electric type, for example, in the case of an n-type impurity region, the second element isolation region also has the opposite conductivity type to the element region. It becomes a p-type impurity region. On the other hand, the first element region and the second element are such that the source region and the drain region of the first element region are n-type impurity regions, and the source region and the drain region of the second element region are p-type impurity regions. When the regions are of the opposite conductivity type, the second element isolation region included in each region is also combined with the element regions, and the first element region side is a p-type impurity region, and the second element region side is an n-type impurity region. It becomes.

The first element isolation region adjacent to the element region via the second element isolation region is the first element that does not selectively contribute to conductivity in order to electrically isolate the elements in one semiconductor layer. It is formed by adding an impurity element.

As the first impurity element that does not contribute to conductivity (does not improve conductivity), at least one impurity element of oxygen, nitrogen, and carbon can be used. In the element isolation region to which the first impurity element is added, the conductivity decreases due to the mixing of the first impurity element that does not contribute to the conductivity, and also due to physical impact on the semiconductor layer at the time of addition (so-called sputtering effect). Increased resistance due to lower crystallinity. In the element isolation region with a high resistance, the field effect mobility is also reduced, so that the elements can be electrically isolated, while the region to which no impurity element is added maintains the field effect mobility that can function as an element. Therefore, it can be used as an element region.

The resistance of the first element isolation region is preferably 1 × 10 ¹⁰ Ω · cm or more, and the concentration of the first impurity element such as oxygen, nitrogen, or carbon is 1 × 10 ²⁰ cm ⁻³ or more and 4 × 10 ²² cm. Less than ^-3 is preferable.

The first element isolation region can be said to be amorphous because the crystallinity is lowered by the addition of the impurity element. On the other hand, since the element region is a crystalline semiconductor layer, when a semiconductor element is formed in the element region, the crystallinity of the channel formation region is higher than that of the first element isolation region, and high field effect mobility can be obtained as a semiconductor element. it can.

As the first impurity element added to the first element isolation region, a rare gas element such as argon (Ar), neon (Ne), krypton (Kr), or xenon (Xe) may be used. In addition to oxygen, nitrogen, and carbon, the addition of these rare gas elements, which are relatively large elements, can increase the physical impact on the semiconductor layer. The crystallinity of the element isolation region can be reduced.

The second element isolation region provided between the element region and the first element isolation region in contact with the element region is added with a second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region. Form.

The element region has a source region, a drain region, and a channel formation region. The source region and the drain region are impurity regions having one conductivity type (for example, an n-type impurity region or a p-type impurity region). A second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region is added to the second element isolation region, and the second element isolation region is used as a source region and a drain in the adjacent element region. The impurity region has a conductivity type opposite to that of the region. That is, when the source region and the drain region in the element region are n-type impurity regions, the adjacent second element isolation region is a p-type impurity region, and similarly, the source region and the drain region in the element region are p-type impurity regions. In some cases, the adjacent second element isolation region may be an n-type impurity region. The adjacent element region and the second element isolation region form a PN junction. Therefore, the element regions can be further insulated and separated by the second element isolation region provided between the element regions.

The present invention provides a first element isolation region which is a high resistance region by addition of a first impurity element that does not contribute to conductivity as an element isolation region for insulating and isolating element regions, and further, a source region and a drain region in the element region A semiconductor layer is separated into a plurality of element regions by providing a second element isolation region which is an impurity region by addition of a second impurity element imparting a reverse conductivity type. According to the present invention, since the element regions can be separated from each other by the effects of the first element isolation region and the second element isolation region, a higher element isolation effect can be obtained.

For the addition (introduction) of the impurity element in forming the first element isolation region and the second element isolation region, an ion implantation method, an (ion) doping method, or the like can be used.

Further, the element isolation region may have a concentration gradient of the first impurity element and the second impurity element. Of course, the first impurity element and the second impurity element may be added to the first and second element isolation regions at a substantially uniform concentration. That is, the concentration peak of the first impurity element and the second impurity element can be set as appropriate in the first and second element isolation regions. The second element isolation region may be an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region in contact with the second element isolation region. An impurity element imparting a mold may be contained. The second element isolation region may contain the first impurity element described above, and the second element isolation region may be added by adding the second impurity element to a part of the first element isolation region. It can also be formed.

Therefore, when the present invention is used, the semiconductor layer can be separated into a plurality of element regions without being divided into islands. Since the step due to the end portion of the semiconductor layer does not occur and the insulating layer is formed on the flat semiconductor layer, the coverage of the insulating layer is improved. Therefore, a semiconductor device which is a highly reliable nonvolatile semiconductor memory device in which defects such as a short circuit between the charge storage layer, the control gate electrode layer, or the gate electrode layer and the semiconductor layer and a leakage current due to a poor coating of the insulating layer are prevented And a method for manufacturing such a semiconductor device can be provided. Therefore, further miniaturization and high integration can be performed in the semiconductor device, and high performance of the semiconductor device can be achieved. In addition, since defects due to such a film shape defect are reduced, production can be performed with high yield even in the manufacturing process.

  This embodiment can be implemented in combination with any of the other embodiments described in this specification.

(Embodiment 10)
In the present embodiment, a semiconductor device for preventing defects such as a short circuit and a leakage current between a charge storage layer, a control gate electrode layer, and a semiconductor layer due to a poor coating of an insulating layer, and to provide higher reliability An example of another nonvolatile semiconductor memory device will be described with reference to the drawings.

In the memory elements shown in Embodiment Modes 2 to 9, an example in which a metal or a semiconductor material is used for the charge storage layer is shown. In this embodiment mode, an insulating layer or an insulating layer containing conductive particles or semiconductor particles such as silicon or germanium is used as the charge storage layer.

The charge storage layer is applied to the nonvolatile semiconductor memory device according to the present invention for the purpose of storing charges, but other materials can be applied as long as they have the same function. It can be formed using an insulating layer having a defect that traps charges in the film, or an insulating layer containing conductive particles or semiconductor particles such as silicon (also referred to as silicon) or germanium. Typical examples of such a material include a silicon compound and a germanium compound. Silicon compound added with oxygen as silicon compound, silicon oxide added with nitrogen, silicon nitride added with oxygen and hydrogen, silicon oxide added with nitrogen and hydrogen, germanium nitride, germanium oxide as germanium compounds And germanium nitride to which oxygen is added, germanium oxide to which nitrogen is added, germanium nitride to which oxygen and hydrogen are added, germanium oxide to which nitrogen and hydrogen are added, and the like. Further, the charge storage layer may contain germanium particles or silicon germanium particles.

In this embodiment, in order to form a plurality of semiconductor elements over an insulating surface, a semiconductor layer is not separated into a plurality of island-shaped semiconductor layers, and a plurality of element regions functioning as semiconductor elements in one semiconductor layer As the element isolation region for electrically insulating and isolating the first and second element isolation regions having high resistance, the second element isolation region having a conductivity type opposite to the source and drain regions of the element region is formed. To do.

The plurality of element regions are provided around the element region so as to surround the second element isolation region which is an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region. A first element isolation region, which is a high resistance region, is provided adjacent to the outer side of the two element isolation regions. Therefore, the adjacent first element region and second element region are the second element isolation region in contact with the first element region, the first element isolation region, and the second element isolation in contact with the second element region. Adjacent through a region.

In the case where the source region and the drain region of the first element region and the second element region have the same electric type, for example, in the case of an n-type impurity region, the second element isolation region also has the opposite conductivity type to the element region. It becomes a p-type impurity region. On the other hand, the first element region and the second element are such that the source region and the drain region of the first element region are n-type impurity regions, and the source region and the drain region of the second element region are p-type impurity regions. When the regions are of the opposite conductivity type, the second element isolation region included in each region is also combined with the element regions, and the first element region side is a p-type impurity region, and the second element region side is an n-type impurity region. It becomes.

The first element isolation region adjacent to the element region via the second element isolation region is the first element that does not selectively contribute to conductivity in order to electrically isolate the elements in one semiconductor layer. It is formed by adding an impurity element.

As the first impurity element that does not contribute to conductivity (does not improve conductivity), at least one impurity element of oxygen, nitrogen, and carbon can be used. In the element isolation region to which the first impurity element is added, the conductivity decreases due to the mixing of the first impurity element that does not contribute to the conductivity, and also due to physical impact on the semiconductor layer at the time of addition (so-called sputtering effect). Increased resistance due to lower crystallinity. In the element isolation region with a high resistance, the field effect mobility is also reduced, so that the elements can be electrically isolated, while the region to which no impurity element is added maintains the field effect mobility that can function as an element. Therefore, it can be used as an element region.

The resistance of the first element isolation region is preferably 1 × 10 ¹⁰ Ω · cm or more, and the concentration of the first impurity element such as oxygen, nitrogen, or carbon is 1 × 10 ²⁰ cm ⁻³ or more and 4 × 10 ²² cm. Less than ^-3 is preferable.

The first element isolation region can be said to be amorphous because the crystallinity is lowered by the addition of the impurity element. On the other hand, since the element region is a crystalline semiconductor layer, when a semiconductor element is formed in the element region, the crystallinity of the channel formation region is higher than that of the first element isolation region, and high field effect mobility can be obtained as a semiconductor element. it can.

As the first impurity element added to the first element isolation region, a rare gas element such as argon (Ar), neon (Ne), krypton (Kr), or xenon (Xe) may be used. In addition to oxygen, nitrogen, and carbon, the addition of these rare gas elements, which are relatively large elements, can increase the physical impact on the semiconductor layer. The crystallinity of the element isolation region can be reduced.

The second element isolation region provided between the element region and the first element isolation region in contact with the element region is added with a second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region. Form.

The element region has a source region, a drain region, and a channel formation region. The source region and the drain region are impurity regions having one conductivity type (for example, an n-type impurity region or a p-type impurity region). A second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region is added to the second element isolation region, and the second element isolation region is used as a source region and a drain in the adjacent element region. The impurity region has a conductivity type opposite to that of the region. That is, when the source region and the drain region in the element region are n-type impurity regions, the adjacent second element isolation region is a p-type impurity region, and similarly, the source region and the drain region in the element region are p-type impurity regions. In some cases, the adjacent second element isolation region may be an n-type impurity region. The adjacent element region and the second element isolation region form a PN junction. Therefore, the element regions can be further insulated and separated by the second element isolation region provided between the element regions.

The present invention provides a first element isolation region which is a high resistance region by addition of a first impurity element that does not contribute to conductivity as an element isolation region for insulating and isolating element regions, and further, a source region and a drain region in the element region A semiconductor layer is separated into a plurality of element regions by providing a second element isolation region which is an impurity region by addition of a second impurity element imparting a reverse conductivity type. According to the present invention, since the element regions can be separated from each other by the effects of the first element isolation region and the second element isolation region, a higher element isolation effect can be obtained.

For the addition (introduction) of the impurity element in forming the first element isolation region and the second element isolation region, an ion implantation method, an (ion) doping method, or the like can be used.

Further, the element isolation region may have a concentration gradient of the first impurity element and the second impurity element. Of course, the first impurity element and the second impurity element may be added to the first and second element isolation regions at a substantially uniform concentration. That is, the concentration peak of the first impurity element and the second impurity element can be set as appropriate in the first and second element isolation regions. The second element isolation region may be an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region in contact with the second element isolation region. An impurity element imparting a mold may be contained. The second element isolation region may contain the first impurity element described above, and the second element isolation region may be added by adding the second impurity element to a part of the first element isolation region. It can also be formed.

Therefore, when the present invention is used, the semiconductor layer can be separated into a plurality of element regions without being divided into islands. Since the step due to the end portion of the semiconductor layer does not occur and the insulating layer is formed on the flat semiconductor layer, the coverage of the insulating layer is improved. Therefore, a semiconductor device which is a highly reliable nonvolatile semiconductor memory device in which defects such as a short circuit between the charge storage layer, the control gate electrode layer and the semiconductor layer and a leakage current due to a poor coating of the insulating layer are prevented, and such A method for manufacturing a semiconductor device can be provided. Therefore, further miniaturization and high integration can be performed in the semiconductor device, and high performance of the semiconductor device can be achieved. In addition, since defects due to such a film shape defect are reduced, production can be performed with high yield even in the manufacturing process.

This embodiment can be implemented in combination with any of the other embodiments described in this specification.

(Embodiment 11)
In this embodiment, an example of a semiconductor device for preventing a short circuit between a gate electrode layer and a semiconductor layer due to a poor coating of an insulating layer and a leakage current in a semiconductor element and providing higher reliability Will be described with reference to the drawings.

In Embodiments 1 to 10, an example in which a semiconductor layer is provided over a substrate having an insulating surface has been described. However, in this embodiment, a semiconductor substrate such as Si or an SOI substrate is used instead of these thin film processes. Show.

An SOI (Silicon on Insulator) substrate in which a single crystal semiconductor layer is formed on an insulating surface is formed using a method of bonding wafers or a method called SIMOX in which an insulating layer is formed inside by implanting oxygen ions into a Si substrate. can do.

In this embodiment, in order to form a plurality of semiconductor elements over an insulating surface, a semiconductor layer is not separated into a plurality of island-shaped semiconductor layers, and a plurality of element regions functioning as semiconductor elements in one semiconductor layer As the element isolation region for electrically insulating and isolating the first and second element isolation regions having high resistance, the second element isolation region having a conductivity type opposite to the source and drain regions of the element region is formed. To do.

The plurality of element regions are provided around the element region so as to surround the second element isolation region which is an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region. A first element isolation region, which is a high resistance region, is provided adjacent to the outer side of the two element isolation regions. Therefore, the adjacent first element region and second element region are the second element isolation region in contact with the first element region, the first element isolation region, and the second element isolation in contact with the second element region. Adjacent through a region.

In the case where the source region and the drain region of the first element region and the second element region have the same electric type, for example, in the case of an n-type impurity region, the second element isolation region also has the opposite conductivity type to the element region. It becomes a p-type impurity region. On the other hand, the first element region and the second element are such that the source region and the drain region of the first element region are n-type impurity regions, and the source region and the drain region of the second element region are p-type impurity regions. When the regions are of the opposite conductivity type, the second element isolation region included in each region is also combined with the element regions, and the first element region side is a p-type impurity region, and the second element region side is an n-type impurity region. It becomes.

The first element isolation region adjacent to the element region via the second element isolation region is the first element that does not selectively contribute to conductivity in order to electrically isolate the elements in one semiconductor layer. It is formed by adding an impurity element.

As the first impurity element that does not contribute to conductivity (does not improve conductivity), at least one impurity element of oxygen, nitrogen, and carbon can be used. In the element isolation region to which the first impurity element is added, the conductivity decreases due to the mixing of the first impurity element that does not contribute to the conductivity, and also due to physical impact on the semiconductor layer at the time of addition (so-called sputtering effect). Increased resistance due to lower crystallinity. In the element isolation region with a high resistance, the field effect mobility is also reduced, so that the elements can be electrically isolated, while the region to which no impurity element is added maintains the field effect mobility that can function as an element. Therefore, it can be used as an element region.

The resistance of the first element isolation region is preferably 1 × 10 ¹⁰ Ω · cm or more, and the concentration of the first impurity element such as oxygen, nitrogen, or carbon is 1 × 10 ²⁰ cm ⁻³ or more and 4 × 10 ²² cm. Less than ^-3 is preferable.

The first element isolation region can be said to be amorphous because the crystallinity is lowered by the addition of the impurity element. On the other hand, since the element region is a crystalline semiconductor layer, when a semiconductor element is formed in the element region, the crystallinity of the channel formation region is higher than that of the first element isolation region, and high field effect mobility can be obtained as a semiconductor element. it can.

As the first impurity element added to the first element isolation region, a rare gas element such as argon (Ar), neon (Ne), krypton (Kr), or xenon (Xe) may be used. In addition to oxygen, nitrogen, and carbon, the addition of these rare gas elements, which are relatively large elements, can increase the physical impact on the semiconductor layer. The crystallinity of the element isolation region can be reduced.

The second element isolation region provided between the element region and the first element isolation region in contact with the element region is added with a second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region. Form.

The element region has a source region, a drain region, and a channel formation region. The source region and the drain region are impurity regions having one conductivity type (for example, an n-type impurity region or a p-type impurity region). A second impurity element imparting a conductivity type opposite to that of the source region and the drain region in the element region is added to the second element isolation region, and the second element isolation region is used as a source region and a drain in the adjacent element region. The impurity region has a conductivity type opposite to that of the region. That is, when the source region and the drain region in the element region are n-type impurity regions, the adjacent second element isolation region is a p-type impurity region, and similarly, the source region and the drain region in the element region are p-type impurity regions. In some cases, the adjacent second element isolation region may be an n-type impurity region. The adjacent element region and the second element isolation region form a PN junction. Therefore, the element regions can be further insulated and separated by the second element isolation region provided between the element regions.

The present invention provides a first element isolation region which is a high resistance region by addition of a first impurity element that does not contribute to conductivity as an element isolation region for insulating and isolating element regions, and further, a source region and a drain region in the element region A semiconductor layer is separated into a plurality of element regions by providing a second element isolation region which is an impurity region by addition of a second impurity element imparting a reverse conductivity type. According to the present invention, since the element regions can be separated from each other by the effects of the first element isolation region and the second element isolation region, a higher element isolation effect can be obtained.

For the addition (introduction) of the impurity element in forming the first element isolation region and the second element isolation region, an ion implantation method, an (ion) doping method, or the like can be used.

Further, the element isolation region may have a concentration gradient of the first impurity element and the second impurity element. Of course, the first impurity element and the second impurity element may be added to the first and second element isolation regions at a substantially uniform concentration. That is, the concentration peak of the first impurity element and the second impurity element can be set as appropriate in the first and second element isolation regions. The second element isolation region may be an impurity region having a conductivity type opposite to that of the source region and the drain region of the element region in contact with the second element isolation region. An impurity element imparting a mold may be contained. The second element isolation region may contain the first impurity element described above, and the second element isolation region may be added by adding the second impurity element to a part of the first element isolation region. It can also be formed.

Therefore, when the present invention is used, the semiconductor layer can be separated into a plurality of element regions without being divided into islands. Further, since the high temperature heat treatment is not performed, volume expansion of the element isolation region does not occur, and the flatness of the surface of the semiconductor layer (or the semiconductor substrate) is kept good. Since the step due to the end portion of the semiconductor layer does not occur and the insulating layer is formed on the flat semiconductor layer, the coverage of the insulating layer is improved. Therefore, a semiconductor device which is a highly reliable nonvolatile semiconductor memory device in which defects such as a charge accumulation layer, a control gate electrode layer, a short-circuit between the gate electrode layer and the semiconductor layer and a leakage current due to a poor coating of the insulating layer are prevented, and A manufacturing method of such a semiconductor device can be provided without performing a complicated process. Therefore, further miniaturization and high integration can be performed in the semiconductor device, and high performance of the semiconductor device can be achieved. In addition, since defects due to such a film shape defect are reduced, production can be performed with high yield even in the manufacturing process.

This embodiment can be implemented in combination with any of the other embodiments described in this specification.

(Embodiment 12)
In this embodiment, application examples of a semiconductor device including the above-described nonvolatile semiconductor memory device formed using the present invention and capable of inputting and outputting data without contact are described below with reference to the drawings. To do. A semiconductor device in which data can be input / output without contact is also referred to as an RFID tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag, an electronic tag, or a wireless chip depending on the application.

The semiconductor device 800 has a function of exchanging data without contact, and controls a high frequency circuit 810, a power supply circuit 820, a reset circuit 830, a clock generation circuit 840, a data demodulation circuit 850, a data modulation circuit 860, and other circuits. A control circuit 870, a memory circuit 880, and an antenna 890 are provided (FIG. 22A). The high-frequency circuit 810 is a circuit that receives a signal from the antenna 890 and outputs the signal received from the data modulation circuit 860 from the antenna 890, and the power supply circuit 820 is a circuit that generates a power supply potential from the received signal, and a reset circuit 830. Is a circuit that generates a reset signal, the clock generation circuit 840 is a circuit that generates various clock signals based on the reception signal input from the antenna 890, and the data demodulation circuit 850 demodulates the reception signal to control the circuit 870. The data modulation circuit 860 is a circuit that modulates the signal received from the control circuit 870. As the control circuit 870, for example, a code extraction circuit 910, a code determination circuit 920, a CRC determination circuit 930, and an output unit circuit 940 are provided. The code extraction circuit 910 is a circuit that extracts a plurality of codes included in the instruction sent to the control circuit 870, and the code determination circuit 920 compares the extracted code with a code corresponding to a reference. The CRC determination circuit 930 is a circuit that detects the presence or absence of a transmission error or the like based on the determined code.

Next, an example of operation of the above-described semiconductor device will be described. First, a radio signal is received by the antenna 890. The wireless signal is sent to the power supply circuit 820 via the high frequency circuit 810, and a high power supply potential (hereinafter referred to as VDD) is generated. VDD is supplied to each circuit included in the semiconductor device 800. The signal sent to the data demodulation circuit 850 via the high frequency circuit 810 is demodulated (hereinafter, demodulated signal). Further, a signal and a demodulated signal that have passed through the reset circuit 830 and the clock generation circuit 840 via the high frequency circuit 810 are sent to the control circuit 870. The signal sent to the control circuit 870 is analyzed by the code extraction circuit 910, the code determination circuit 920, the CRC determination circuit 930, and the like. Then, information on the semiconductor device stored in the memory circuit 880 is output in accordance with the analyzed signal. The output semiconductor device information is encoded through the output unit circuit 940. Further, the encoded information of the semiconductor device 800 passes through the data modulation circuit 860 and is transmitted on the radio signal by the antenna 890. Note that a low power supply potential (hereinafter referred to as VSS) is common in the plurality of circuits included in the semiconductor device 800, and VSS can be GND. Further, a nonvolatile semiconductor memory device or the like formed using the present invention can be applied to the memory circuit 880.

As described above, by transmitting a signal from the reader / writer to the semiconductor device 800 and receiving the signal transmitted from the semiconductor device 800 by the reader / writer, the data of the semiconductor device can be read.

Further, the semiconductor device 800 may be of a type in which the power supply voltage is supplied to each circuit by an electromagnetic wave without mounting the power source (battery), or each circuit is mounted by the electromagnetic wave and the power source (battery). It is good also as a type which supplies a power supply voltage to.

Next, an example of a usage pattern of a semiconductor device capable of inputting and outputting data without contact will be described. A reader / writer 3200 is provided on a side surface of the portable terminal including the display portion 3210, and a semiconductor device 3230 is provided on a side surface of the article 3220 (FIG. 22B). When a reader / writer 3200 is held over a semiconductor device 3230 provided in an item 3220, information about the product, such as a description of the product, such as the raw material and origin of the item, inspection results for each production process, distribution history, etc., on the display unit 3210 Is displayed. Further, when the product 3260 is conveyed by a belt conveyor, the product 3260 can be inspected using the reader / writer 3240 and the semiconductor device 3250 provided in the product 3260 (FIG. 22C). In this manner, by using a semiconductor device in the system, information can be easily acquired, and high functionality and high added value are realized.

In addition, a nonvolatile semiconductor memory device or the like which is a semiconductor device formed using the present invention can be used for electronic devices in various fields including a memory. For example, as an electronic device to which the nonvolatile semiconductor memory device of the present invention is applied, a camera such as a video camera or a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), Plays back recording media such as computers, game machines, portable information terminals (mobile computers, mobile phones, portable game machines or electronic books), and image playback devices (specifically DVDs (digital versatile discs)) equipped with recording media And an apparatus provided with a display capable of displaying the image). Specific examples of these electronic devices are shown in FIGS.

23A and 23B show a digital camera. FIG. 23B is a diagram showing the back side of FIG. This digital camera includes a housing 2111, a display portion 2112, a lens 2113, operation keys 2114, a shutter 2115, and the like. In addition, a nonvolatile memory 2116 that can be taken out is provided, and data captured by the digital camera is stored in the memory 2116. A nonvolatile semiconductor memory device or the like which is a semiconductor device formed using the present invention can be applied to the memory 1225.

FIG. 23C illustrates a mobile phone, which is a typical example of a mobile terminal. This mobile phone includes a housing 2121, a display portion 2122, operation keys 2123, and the like. In addition, the mobile phone includes a removable nonvolatile memory 2125, and data such as a phone number of the mobile phone, video, music data, and the like can be stored in the memory 2125 and played back. A nonvolatile semiconductor memory device or the like which is a semiconductor device formed using the present invention can be applied to the memory 2125.

FIG. 23D illustrates a digital player, which is a typical example of an audio device. A digital player shown in FIG. 23D includes a main body 2130, a display portion 2131, a memory portion 2132, an operation portion 2133, an earphone 2134, and the like. Note that headphones or wireless earphones can be used instead of the earphones 2134. As the memory portion 2132, a nonvolatile semiconductor memory device that is a semiconductor device formed using the present invention can be used. For example, by using a NAND nonvolatile memory with a recording capacity of 20 to 200 gigabytes (GB) and operating the operation unit 2133, video and audio (music) can be recorded and reproduced. Note that the display unit 2131 can reduce power consumption by displaying white characters on a black background. This is particularly effective in a portable audio device. Note that the nonvolatile semiconductor memory device provided in the memory portion 2132 may be removable.

FIG. 23E illustrates an electronic book (also referred to as electronic paper). This electronic book includes a main body 2141, a display portion 2142, operation keys 2143, and a memory portion 2144. Further, a modem may be incorporated in the main body 2141 or a configuration in which information can be transmitted and received wirelessly may be employed. As the memory portion 2144, a nonvolatile semiconductor memory device which is a semiconductor device formed using the present invention can be used. For example, by using a NAND nonvolatile memory with a recording capacity of 20 to 200 gigabytes (GB) and operating the operation key 2143, video and audio (music) can be recorded and reproduced. Note that the nonvolatile semiconductor memory device provided in the memory portion 2144 may be removable.

As described above, the applicable range of the semiconductor device of the present invention (particularly, a nonvolatile semiconductor memory device which is a semiconductor device formed using the present invention) is extremely wide, and it is used for electronic devices in a wide range of fields including a memory. It is possible.

(Embodiment 13)
According to the present invention, a semiconductor device that functions as a chip having a processor circuit (hereinafter also referred to as a processor chip, a wireless chip, a wireless processor, a wireless memory, or a wireless tag) can be formed. The semiconductor device of the present invention has a wide range of uses, such as banknotes, coins, securities, certificates, bearer bonds, packaging containers, books, recording media, personal items, vehicles, foods, clothing It can be used in health supplies, daily necessities, medicines and electronic devices.

  Since a semiconductor device having a memory element using the present invention can be freely transferred to various substrates, an inexpensive material can be selected as the substrate and can have a wide range of functions depending on the application. In addition, a semiconductor device can be manufactured at low cost. Therefore, the chip having a processor circuit according to the present invention also has features such as low cost, small size, thinness, and light weight, so it is suitable for a large amount of money, coins, etc., books that are often carried, personal items, clothes, etc. is there.

  Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, and the like, and can be provided with a chip 190 including a processor circuit (see FIG. 21A). The certificate refers to a driver's license, a resident's card, or the like, and can be provided with a chip 191 having a processor circuit (see FIG. 21B). Personal belongings refer to bags, glasses, and the like, and can be provided with a chip 197 including a processor circuit (see FIG. 21C). Bearer bonds refer to stamps, gift cards, and various gift certificates. Packaging containers refer to wrapping paper for lunch boxes, plastic bottles, and the like, and can be provided with a chip 193 including a processor circuit (see FIG. 21D). Books refer to books, books, and the like, and can be provided with a chip 194 including a processor circuit (see FIG. 21E). A recording medium refers to DVD software, video tape, or the like, and can be provided with a chip 195 including a processor circuit (see FIG. 21F). The vehicles refer to vehicles such as bicycles, ships, and the like, and can be provided with a chip 196 including a processor circuit (see FIG. 21G). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

The semiconductor device of the present invention is fixed to an article by being mounted on a printed board, pasted on a surface, embedded, or the like. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin, and is fixed to each article. Since the semiconductor device of the present invention realizes a small size, a thin shape, and a light weight, the design of the article itself is not impaired even after being fixed to the article. In addition, by providing the semiconductor device of the present invention in bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and if this authentication function is utilized, counterfeiting can be prevented. it can. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

4A and 4B are a top view and cross-sectional views of a semiconductor device of the present invention. 4A and 4B are a top view and cross-sectional views of a semiconductor device of the present invention. 4A and 4B are a top view and cross-sectional views of a semiconductor device of the present invention. 4A and 4B are a top view and cross-sectional views of a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 4A and 4B are a top view and cross-sectional views of a semiconductor device of the present invention. FIG. 10 illustrates an example of an equivalent circuit of a semiconductor device. FIG. 10 illustrates an example of an equivalent circuit of a semiconductor device. FIG. 10 illustrates an example of an equivalent circuit of a semiconductor device. FIG. 6 illustrates a top view of a semiconductor device of the present invention. FIG. 10 illustrates a cross-sectional view of a semiconductor device of the present invention. FIG. 6 illustrates a top view of a semiconductor device of the present invention. FIG. 10 illustrates a cross-sectional view of a semiconductor device of the present invention. FIG. 10 illustrates an example of a circuit block diagram of a semiconductor device. FIG. 6 illustrates a top view of a semiconductor device of the present invention. 8A and 8B illustrate an application example of a semiconductor device of the invention. 8A and 8B illustrate an application example of a semiconductor device of the invention. 8A and 8B illustrate an application example of a semiconductor device of the invention. 8A and 8B illustrate a writing operation of a semiconductor device. 10A and 10B illustrate erase and read operations of a semiconductor device. 4A and 4B are a top view and cross-sectional views of a semiconductor device of the present invention. 4A and 4B are a top view and cross-sectional views of a semiconductor device of the present invention.

Claims (7)

Having a substrate with an insulating surface;
A semiconductor layer including a first element isolation region, a second element isolation region, and an element region on the entire surface of the insulating surface;
The element region includes a source region, a drain region, and a channel formation region,
The first element isolation region is in contact with the second element isolation region;
The second element isolation region is in contact with the element region;
The first element isolation region includes at least one first impurity element selected from oxygen, nitrogen, and carbon;
The first element isolation region includes a rare gas element;
The second element isolation region includes a second impurity element that imparts a conductivity type opposite to that of the source region and the drain region to the second element isolation region,
The semiconductor device, wherein the first element isolation region has lower crystallinity than the channel formation region. In claim 1,
An insulating layer on the first element isolation region, the second element isolation region, and the element region; a conductive layer on the insulating layer;
The semiconductor device is characterized in that the conductive layer is provided over the first element isolation region, the second element isolation region, and the element region via the insulating layer. In claim 1 or claim 2,
A semiconductor device, wherein the second element isolation region is provided to surround the element region, and the first element isolation region is provided to surround the second element isolation region. Having a substrate with an insulating surface;
A semiconductor layer including a first element isolation region, a second element isolation region, a third element isolation region, a first element region, and a second element region on the entire surface of the insulating surface;
The first element region includes a first source region, a first drain region, and a first channel formation region,
The second element region includes a second source region, a second drain region, and a second channel formation region,
The first element isolation region is in contact with the second element isolation region and the brother 3 element isolation region;
The second element isolation region is in contact with the first element region;
The third element isolation region is in contact with the second element region;
The first source region, the first drain region, the second source region, and the second drain region have the same conductivity type;
The first element isolation region includes at least one first impurity element selected from oxygen, nitrogen, and carbon;
The first element isolation region includes a rare gas element;
The second element isolation region and the third element isolation region have a conductivity type opposite to that of the first source region, the first drain region, the second source region, and the second drain region. Including a second impurity element imparting to the second element isolation region and the third element isolation region,
The semiconductor device, wherein the first element isolation region has lower crystallinity than the first channel formation region and the second channel formation region. Having a substrate with an insulating surface;
A semiconductor layer including a first element isolation region, a second element isolation region, a third element isolation region, a first element region, and a second element region on the entire surface of the insulating surface;
The first element region includes a first source region, a first drain region, and a first channel formation region,
The second element region includes a second source region, a second drain region, and a second channel formation region,
The first element isolation region is in contact with the second element isolation region and the third element isolation region;
The second element isolation region is in contact with the first element region;
The third element isolation region is in contact with the second element region;
The first source region and the first drain region are n-type impurity regions,
The second source region and the second drain region are p-type impurity regions,
The first element isolation region includes at least one first impurity element selected from oxygen, nitrogen, and carbon;
The first element isolation region includes a rare gas element;
The second element isolation region includes an impurity element imparting p-type to the second element isolation region;
The third element isolation region includes an impurity element imparting n-type to the third element isolation region;
The semiconductor device, wherein the first element isolation region has lower crystallinity than the first channel formation region and the second channel formation region. In claim 4 or claim 5,
An insulating layer on the first element region, the second element region, the first element isolation region, the second element isolation region, and the third element isolation region;
A conductive layer on the insulating layer;
The conductive layer is disposed on the first element region, the second element region, the first element isolation region, the second element isolation region, and the third element isolation region via the insulating layer. A semiconductor device provided over the semiconductor device. 7. The concentration of the first impurity element included in the first element isolation region is 1 × 10 ²⁰ cm ⁻³ or more and less than 4 × 10 ²² cm ^{−3 according} to claim 1. A semiconductor device.

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