JP5252249B2 - Device manufacturing processing method - Google Patents

Description

  The present invention relates to a device manufacturing processing method, and more specifically, for example, a device including a photolithography process for manufacturing a semiconductor element, a liquid crystal display element, an imaging element such as a CCD (Charge Coupled Device), a thin film magnetic head, and the like. The present invention relates to a manufacturing processing method.

  Conventionally, for the purpose of improving the resolution of a device pattern transferred onto a substrate, a so-called multiple exposure method has been used in which the patterns of each of two or more reticles are superimposed and transferred onto the same region on the substrate. (For example, refer to Patent Document 1). According to this multiple exposure method, the deterioration of the transfer result of each reticle pattern can be compensated for each other, and a highly accurate device pattern can be formed on the substrate. In the multiple exposure method, after transferring the pattern on the first reticle onto the substrate, the first reticle is replaced with the second reticle, and the pattern on the second reticle is transferred onto the substrate. It is common to do.

  On the other hand, in order to meet the demand for miniaturization of device patterns, OPC (Optical Proximity Correction) masks designed with the optical proximity effect in mind as part of super-resolution technology (Resolution Enhancement Technology) A phase shift mask that uses a phase difference to achieve a high-contrast pattern on a substrate has been adopted (see, for example, Patent Document 2). By adding small figures to the corners of the mask pattern and changing the pattern size of dense areas and rough parts, the OPC mask results in a device pattern that is transferred onto the substrate as designed. It is designed for the purpose of doing.

  Using these masks reduces the amount of light in the fine pattern and the deterioration of the pattern image on the substrate due to the optical proximity effect caused by the interference of diffracted light from adjacent patterns. It will be possible to transfer well. However, recently, device patterns have become more complex, and it has been troublesome to design OPC masks and phase shift masks, and such masks are extremely expensive.

JP-A-10-209039 Japanese Patent No. 3128876

From the first viewpoint, the present invention provides a plurality of first masks in which a first divided pattern corresponding to a first portion of a device pattern transferred onto a substrate is formed under different conditions, and the first portion transcriptional state of a device pattern Previous SL on the substrate; different said device second division pattern corresponding to the second portion of the pattern is preparation step and providing a plurality of second mask formed at different conditions and information relating to the plurality of first, every second mask, or acquisition process and to get every various combinations of the said first mask second mask; based on the obtained information, said plurality with selecting a particular first mask from the first mask, selection step and selecting a particular second mask from the plurality of second mask; is a free Mude vice manufacturing processing method.

According to this, the device pattern transferred onto the substrate is divided into first and second divided patterns . The first and second divided patterns are simpler patterns than the original device pattern. For this reason, transferring the division pattern and finally forming the device pattern on the substrate reduces the influence of the optical proximity effect due to the pattern, rather than transferring the complicated device pattern directly to the substrate. Therefore, deterioration of the pattern transferred onto the substrate is reduced. In the present invention, a plurality of first masks formed under different conditions to compensate for the degradation of the first divided pattern , and similarly, a plurality of masks formed under different conditions to compensate for the degradation of the second divided pattern. The second mask is prepared. Among these masks, select rapidly a mask device pattern transfer accuracy is best on the substrate, by performing the transfer of the device pattern using the selected mask, the device pattern transfer accuracy The mask can be optimized quickly for the purpose of preventing deterioration.

From a second viewpoint, the present invention provides a plurality of first masks in which a first divided pattern corresponding to a first portion of a device pattern transferred onto a substrate is formed under different conditions, and the first portion second division pattern corresponding to the second portion of said different device patterns and is preparation step and providing a plurality of second mask formed at different conditions; the-prepared of the plurality of first mask The image of the first division pattern formed on the specific first mask selected from among the images and the second division formed on the specific second mask selected from among the plurality of prepared second masks A transfer process for simultaneously projecting an image of the pattern onto the substrate and transferring the device pattern.

According to this, since a simplified than the device pattern, it is simultaneously projected onto a plate an image of easily prehensible first and second divided patterns of transcriptional state onto the substrate, the transfer substrate Pattern deterioration is prevented, and the time required for pattern transfer is shortened, so that high-precision and high-throughput exposure is realized.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 shows a schematic configuration of a device manufacturing processing system according to an embodiment of the present invention. As shown in FIG. 1, a device manufacturing processing system 1000 is a system constructed in a device manufacturing factory for processing semiconductor wafers and manufacturing micro devices. As shown in FIG. 1, the device manufacturing processing system 1000 includes an exposure apparatus 100, a track 200 disposed adjacent to the exposure apparatus 100, a management controller 160, an analysis apparatus 500, and a host system 600. And a device manufacturing processing apparatus group 900.

  The exposure apparatus 100 is an apparatus that transfers a device pattern to a wafer coated with a photoresist. FIG. 2 shows a schematic configuration of the exposure apparatus 100. In the exposure apparatus 100, an illumination system 10 that emits exposure light IL1 and IL2, a reticle R1 on which a device pattern illuminated by the exposure light IL1 is formed, and a device pattern illuminated by the exposure light IL2 are formed. A reticle stage RST that holds the reticle R2 and a two-side telecentric projection optical system that projects a part of the device pattern formed on the reticles R1 and R2 illuminated by the exposure lights IL1 and IL2 onto the exposure surface of the wafer W. PL, a wafer stage WST for holding a wafer W to be exposed, and a main controller 20 for overall control thereof. Illumination lights IL1 and IL2 from the illumination system 10 are applied to a part of the reticles R1 and R2 held on the reticle stage RST, respectively. These irradiation areas are referred to as illumination areas IAR1 and IAR2. A device pattern including a circuit pattern and the like is formed on each of the reticles R1 and R2.

  Illumination lights IL1 and IL2 that have passed through illumination areas IAR1 and IAR2, respectively, enter a part of an exposed surface (wafer surface) of wafer W held on wafer stage WST via projection optical system PL, and enter there. Projected images of device patterns in the illumination areas IAR1 and IAR2 are formed. The areas on the wafer W are referred to as exposure areas IA1 and IA2, respectively. The exposed surface of the wafer W is coated with a photoresist, and the pattern of the projected image is transferred to portions corresponding to the exposure areas IA1 and IA2.

  Here, consider an XYZ coordinate system in which the coordinate axis along the optical axis of the projection optical system PL is the Z axis. Wafer stage WST holding wafer W can move on the XY plane, and shifts the exposed surface of wafer W in the Z-axis direction, in the θx (rotation around the X axis) direction, and in the θy (rotation around the Y axis). ) Direction. In addition, reticle stage RST holding reticles R1 and R2 can move in the XY plane in synchronization with wafer stage WST holding wafer W.

  As shown in FIG. 3, the device pattern on the reticles R1 and R2 passes through the illumination areas IAR1 and IAR2 by synchronous scanning according to the projection magnification of the projection optical system PL between the reticle stage RST and the wafer stage WST. In synchronization with this, the exposed surface of the wafer W passes through the exposure areas IA1 and IA2. As a result, all device patterns on the reticles R1 and R2 are transferred to a partial area (shot area) SA on the exposed surface of the wafer W. The exposure apparatus 100 repeats the above-described relative synchronous scanning of the reticle stage RST and stepping of the wafer stage WST holding the wafer W with respect to the exposure lights IL1 and IL2, thereby changing the device pattern on the reticles R1 and R2 to the wafer W. Transferred to the upper shot areas. That is, the exposure apparatus 100 is a scanning exposure (step-and-scan) type exposure apparatus.

  The main controller 20 controls the exposure amount control system for controlling the intensity (exposure amount) of the exposure light IL1 and IL2, the synchronous control of the reticle stages RST1 and RST2, and the wafer stage WST, and within the depth of focus of the projection optical system PL. Are provided with a stage control system for performing autofocus / leveling control (hereinafter simply referred to as focus control) for matching the surface of the wafer W and a lens control system for controlling the imaging state of the projection optical system PL.

  The exposure amount control system performs feedback control for controlling the exposure amount to match the target value based on detection values of various exposure amount sensors (not shown) capable of detecting the exposure amount.

  Among the stage control systems, a control system that performs synchronous control with both stages RST and WST is a synchronous control system, and the Z position of the stage position (exposed surface of the wafer W), the amount of rotation about the X axis, and the amount of rotation about the Y axis are set. The control system to be controlled is a focus control system.

  The synchronous control system performs feedback control based on the measurement value of the interferometer that measures the position of wafer stage WST and reticle stage RST under the XYZ coordinate system, and realizes position control and speed control of both stages RST and WST. doing.

  The exposure apparatus 100 is provided with a multipoint AF (autofocus) sensor that detects a focus / leveling shift on the wafer surface at a plurality of detection points. The stage control system detects the wafer surface height at, for example, nine detection points (9 channels) among the plurality of detection points of the multipoint AF sensor, and projects the wafer surface corresponding to the exposure areas IA1 and IA2 to the projection optical system. By performing feedback control so as to match the image plane of the system PL, focus / leveling control of the exposed surface of the wafer W is realized.

  The lens control system monitors the atmospheric pressure, the temperature in the chamber of the exposure apparatus 100, the exposure amount, and the temperature of the lens of the projection optical system. Based on the monitoring result, the magnification variation amount and the focus variation amount of the projection optical system are calculated. Based on the calculated amount of fluctuation, the best focus position and the magnification are controlled to follow the target value by adjusting the atmospheric pressure inside the projection optical system and adjusting the lens interval.

  The projection optical system PL is a double-sided telecentric optical system including an optical system including a plurality of, for example, about 10 to 20 refractive optical elements (lens elements) and a reflection mirror. Projection optical system PL projects partially inverted images of patterns in illumination areas IAR1 and IAR2 onto exposure areas IA1 and IA2 at a predetermined magnification. As shown in FIG. 3, the positional relationship between the illumination areas IAR1, IAR2, and the exposure areas IA1, IA2 is such that the entire device pattern on the reticles R1, R2 is transferred to the wafer by relative synchronous scanning of both stages RST, WST. The positional relationship is such that the image is transferred to the entire shot area on W.

  The operation of the exposure apparatus 100 can be adjusted to some extent by adjusting apparatus parameters. Control system parameters such as the gain of the control system, illumination conditions such as a coherence factor in the illumination system 10 are examples. The illumination condition is determined by the resolution required for the pattern to be exposed.

  The main controller 20 is a computer system that controls various components of the exposure apparatus 100. The main controller 20 is connected to a communication network constructed in the device manufacturing processing system 1000, and can send and receive data to and from the outside via the communication network.

  As described above, the exposure apparatus 100 transfers the device pattern onto the wafer W using the two reticles R1 and R2. On the reticles R1 and R2, a division pattern obtained by dividing the device pattern transferred to the shot area SA is formed. FIGS. 4A to 4C and FIGS. 5A to 5C show examples of device pattern division.

  4A and 5A show examples of device patterns such as memory cells transferred onto the wafer W. FIG. A device pattern DP shown in FIG. 4 (A) is shown in FIG. 4 (B), which is a pattern P1 composed of a combination of a rectangular isolated pattern and a thin line pattern connecting the rectangles at both ends, and FIG. 4 (C). The line and space pattern (L / S pattern) P2 can be divided. Further, the device pattern DP ′ shown in FIG. 5 (A) includes a pattern P1 ′ composed of a combination of thin line patterns connecting the rectangles at both ends shown in FIG. 5 (B), and L shown in FIG. 5 (C). / S pattern P2 ′ can be divided. Here, the device pattern is divided into a pattern having a high periodicity and a pattern having a slightly low periodicity.

  In the present embodiment, patterns P1 and P1 ′ as shown in FIGS. 4B and 5B are formed on the reticle R1, and FIGS. 4C and 5C are formed on the reticle R2. It is assumed that patterns P2 and P2 ′ as shown in FIG. Therefore, when scanning exposure is performed by the exposure apparatus 100 using these reticles R1 and R2, device patterns DP and DP as shown in FIG. 4A and FIG. 'Will be transcribed.

  In the present embodiment, an OPC mask or a phase shift mask can be employed as the reticles R1 and R2.

  The OPC mask is a mask using an optical proximity correction method (Optical Proximity Correction: OPC). Even if the mask on which the device pattern to be transferred is directly formed on the wafer W is miniaturized, an exposure pattern abnormality may occur due to insufficient light quantity in the fine pattern or the influence of light from the adjacent pattern. This phenomenon is called the optical proximity effect. In order to prevent these phenomena, a technique of adding a small figure to the corner of the mask pattern or changing the pattern size of a dense part and a rough part is an optical proximity correction method (Optical Proximity Correction: OPC). . In the OPC mask, for example, a step called a jog is created at the edge of the pattern, and the length and size of the jog are adjusted so that the shape of the exposure pattern on the wafer is close to the shape of the design pattern.

  On the other hand, the phase shift mask is, for example, a mask that gives a phase difference of 180 ° to transmitted light by using a transmissive portion of the mask pattern different from the adjacent transmissive portion. Therefore, the pattern light shielding portion is a mask intended to improve the pattern contrast on the image plane by canceling the diffracted transmitted lights having different phases by 180 ° and reducing the light intensity. As the phase shift mask, for example, there are various types such as Levenson type (substrate digging type, double digging type, shifter type), auxiliary pattern type, rim type, half tone type, and chrome-less type.

  Employing an OPC mask or a phase shift mask is one of the super-resolution techniques, and by using these masks, the pattern to be transferred and formed on the exposed surface of the wafer W can be miniaturized.

  6A to 6E show examples in which the OPC technique is applied to a rectangular pattern. The rectangular pattern SP2 shown in FIG. 6B is similar to the standard rectangular pattern SP1 shown in FIG. 6A and is larger than the pattern SP1. If the pattern SP1 is exposed, the OPC pattern is effective when the transfer pattern on the wafer W becomes smaller as a whole.

  Also, the patterns SP3 to SP5 shown in FIGS. 6C to 6E are rounded with the four corners of the pattern on the wafer W missing when the pattern SP1 is transferred onto the wafer W as it is. This is a pattern applied in such a case. Since the size and shape of the four corners differ depending on the case, one of the patterns SP3 to SP5 is adopted depending on the size and shape.

  An example of a pattern obtained by applying the OPC technique to the pattern BP1 shown in FIG. 7A is shown in FIG. As shown in FIG. 7B, the corner of the pattern BP2 extends in a rectangular shape with respect to the pattern BP1.

  An example of a pattern in which the OPC technique is applied to the frame-like pattern FP1 shown in FIG. 8A is shown in FIG. As shown in FIG. 8B, the pattern FP2 is a pattern in which the four corners of the pattern FP1 protrude in a rectangular shape.

  Patterns LP2 and LP3, which are application examples of the OPC technique to the L-shaped pattern LP1 shown in FIG. 9A, are shown in FIGS. 9B and 9C. Also, patterns BP2 ′, BP3 ′, BP4 ′, and BP5 ′, which are examples of application of the OPC technique to the line pattern BP1 ′ shown in FIG. 10A, are shown in FIGS. 10B to 10E. Has been. Generally, the pattern BP2 'is called a mask bias optimization type, and the pattern size is partially changed. The pattern BP3 'is called a hammerhead type, and is obtained by thickening both ends of the line pattern. The pattern BP4 'is called a serif type and is an extension of the four corners of the line pattern. The pattern BP5 'is an auxiliary pattern type to which an auxiliary pattern is added. In addition, for example, an OPC + phase shift type in which an OPC pattern such as patterns BP2 'to BP5' and a phase shift technique are combined can be adopted.

  In general, as the required resolution increases, the line tip extension / enlargement, mask bias optimization, hammerhead type, serif type, auxiliary pattern type, and OPC + phase shift type are often selected in this order. That is, it should be noted that the higher the resolution, the more complicated the OPC mask becomes, its data volume increases, and the reticle manufacturing cost increases.

  The patterns shown in FIGS. 6 (A) to 10 (E) can be adopted as partial patterns, that is, parts of the divided patterns formed on the reticles R1 and R2. For example, the patterns shown in FIGS. 6A to 10E can be adopted as the patterns of the divided patterns shown in FIGS. 4B and 5B.

  In exposure apparatus 100, a plurality of reticles that can be employed as reticles R1 and R2 are prepared.

  That is, a plurality of reticles on which patterns corresponding to the patterns P1 and P1 'shown in FIGS. 4B and 5B are formed are prepared. For patterns with low periodicity such as the patterns P1 and P1 ', the OPC technique is suitable. For example, in addition to the reticle in which the patterns P1 and P1 ′ are formed as they are, any of the patterns SP2 to SP5 shown in FIGS. 6B to 6E is employed instead of the patterns P1 and P1 ′. A plurality of reticles using the pattern BP2 shown in FIG. Of course, in addition to the OPC technique, a plurality of reticles adopting a phase shift technique can be prepared.

  These reticles are stocked in the exposure apparatus 100. In the present embodiment, a reticle that is actually used for transferring the device pattern shown in FIGS. 4A and 5A is selected from the plurality of reticles, and the selected reticle is used as the reticle R1. become.

  Also, a plurality of reticles on which patterns corresponding to the patterns P2 and P2 'shown in FIGS. 4C and 5C are formed are prepared. For patterns with high periodicity such as the patterns P2 and P2 ', the phase shift technique is suitable. These reticles can be, for example, reticles employing different phase shift techniques. Of course, OPC technology can also be adopted.

  The selection of the reticles R1 and R2 is performed in consideration of the combination with the pattern of the other reticles R2 and R1. For example, if the pattern on the reticle R2 is an L / S pattern as shown in FIG. 4C, the reticle R1 is selected depending on the line width, pitch, etc. of the L / S pattern. Thus, compatibility between reticles is also a selection condition.

  Incidentally, the device pattern DP shown in FIG. 4A and the device pattern DP ′ shown in FIG. 5A are different device patterns, but the pattern P2 and the pattern P2 ′ have the same L / S. Since it is a pattern, the reticle on which these patterns are formed can be shared. In this way, it is possible to reduce the manufacturing cost by reducing the total number of reticles.

  In this case, even if the design pitch and line width of the pattern P2 and the pattern P2 'are slightly different, for example, the reticle can be diverted by changing the magnification of the projection optical system PL.

  In any case, the number of reticles to be prepared can be reduced if the pattern of each reticle is the greatest common pattern of the device patterns of each product and each process.

  In the present embodiment, the device pattern is divided into a pattern having a high periodicity and a pattern having a relatively low periodicity. In this way, if the device pattern division patterns are classified according to certain rules, each reticle can be easily used in various processes and products, and OPC technology and phase can be applied to each pattern. The shift technique can be easily applied in a state where the effect of the pattern correction can be predicted. As a result, it is possible to minimize the number of reticles to be prepared when the exposure apparatus 100 transfers and forms a plurality of products and device patterns in a plurality of processes.

  Returning to FIG. 1, in the exposure apparatus 100, a reticle measurement / inspection instrument 130 for inspecting a reticle used for exposure before holding it on the reticle stage RST is provided. The reticle measurement / inspection instrument 130 measures the presence / absence of foreign matter attached to the device patterns of the reticles R1 and R2, the pattern size of the device pattern, and detects pattern defects. First, the reticle measurement / inspection instrument 130 scans the device patterns of the reticles R1 and R2 with a laser, detects the reflected light or scattered light, and removes foreign matter on the device pattern by changing the intensity of the reflected light or scattered light. To detect. The reticle measurement / inspection instrument 130 images the device pattern illuminated by the illumination lights IL1 and IL2, and measures the pattern line width or detects a pattern defect based on the imaging result.

  The reticle measurement / inspection device 130 determines whether there is a foreign object or a pattern defect on the device pattern (that is, detects an abnormality) based on the detection result of reflected light or scattered light or the imaging result of the device pattern. It has. In addition to the above-described abnormality detection, this information processing apparatus detects the position of the location where the abnormality is detected, the type of abnormality (foreign matter or defect), the size of the abnormal part, the number of occurrences of abnormality, and the like. These detection results, raw measurement data corresponding to detection signals of reflected light and scattered light, imaging signals of patterns, and the like are stored in a storage device (not shown). This information processing apparatus is connected to an external communication network, and can transmit / receive data to / from an external apparatus.

[truck]
The track 200 is disposed in contact with a chamber (not shown) surrounding the exposure apparatus 100. The track 200 mainly carries in and out the wafers with respect to the exposure apparatus 100 by a transfer line provided inside.

[Coater / Developer]
In the track 200, a coater / developer (C / D) 110 for applying and developing a resist is provided. The C / D 110 applies and develops a photoresist on the wafer W. The C / D 110 can observe these processing states and record the observation data as log data. Examples of observable processing states include resist coating film thickness uniformity, development module processing, PEB (Post-Exposure-Bake) temperature uniformity (hot plate temperature uniformity), wafer heating history management (after PEB processing) There are various states of avoiding over-baking and cooling plate). The processing state of the C / D 110 can also be adjusted to some extent by setting the device parameters. Such apparatus parameters include, for example, parameters related to uneven application of resist on the wafer W, such as apparatus parameters such as a set temperature, a rotation speed of the wafer W, a drop amount and a drop interval of the resist, and the like.

  The C / D 110 can operate independently of the exposure apparatus 100 and the wafer measurement / inspection instrument 120. The C / D 110 is disposed along the transport line of the track 200. Therefore, the wafer W can be transferred between the exposure apparatus 100 and the C / D 110 by this transfer line. Further, the C / D 110 is connected to a communication network in the device manufacturing processing system 1000, and can send and receive data to and from the outside. For example, the C / D 110 can output information on the process (information such as the trace data).

[Wafer measurement and inspection equipment]
In the track 200, a composite wafer measurement / inspection instrument 120 capable of performing various measurement / inspections on the wafer W before and after the exposure of the wafer W by the exposure apparatus 100 (that is, before and after) is provided. ing. Wafer measurement / inspection instrument 120 can operate independently of exposure apparatus 100 and C / D 110. The wafer measurement / inspection instrument 120 performs a pre-measurement / inspection process for performing measurement before exposure and a post-measurement / inspection process for performing measurement after exposure.

  In the pre-measurement inspection process, before the wafer W is transferred to the exposure apparatus 100, inspection for foreign matter on the wafer W, inspection of the resist film on the wafer W, and measurement for optimizing the exposure conditions in the exposure apparatus 100 are performed. Do. The measurement target of the pre-measurement / inspection process includes the surface shape of the wafer W before exposure. The wafer measurement / inspection instrument 120 can output the results of the preliminary measurement / inspection to the outside via a communication network in the system.

  On the other hand, in the post measurement inspection process, the line width and overlay error of the resist pattern on the wafer W after exposure (post facto) transferred by the exposure apparatus 100 and developed by the C / D 110, the wavefront aberration of the projection optical system PL, Measurement of illumination unevenness, wafer film inspection, wafer defect / foreign particle inspection, etc. Here, the wafer film inspection includes inspection of a film formed on the wafer W, film thickness unevenness, film defect, foreign matter, scratch, and the like.

  Further, the wafer measurement / inspection instrument 120 can also measure the relative positional deviation amount of the aberration measurement mark on the exposed test wafer for the aberration measurement of the projection optical system PL of the exposure apparatus 100. Yes.

  Also, the measurement state of the wafer measurement / inspection instrument 120 (for example, data that affects measurement errors such as alignment such as residual components when aligning the wafer for measurement) is recorded as log data. Can be done. This log data can also be output to the outside via a communication network. The wafer measurement / inspection instrument 120 can also adjust its measurement state to some extent by setting the apparatus parameters within an allowable range. Such apparatus parameters include, for example, parameters related to wafer alignment, which are preconditions for measurement, parameters relating to the focus state of the sensor, selection of wafer W to be measured, and parameters relating to selection of measurement shots. .

  The wafer measurement / inspection instrument 120 is disposed along the transport line of the track 200. Therefore, the wafer W can be transferred between the exposure apparatus 100, the C / D 110, and the wafer measurement / inspection instrument 120 by this transfer line. That is, the exposure apparatus 100, the track 110, and the wafer measurement / inspection instrument 120 are connected in-line to each other. Here, the in-line connection means that the apparatuses and the processing units in each apparatus are connected via a transfer device for automatically transferring the wafer W such as a robot arm or a slider. By this in-line connection, the transfer time of the wafer W among the exposure apparatus 100, the C / D 110, and the wafer measurement / inspection instrument 120 can be remarkably shortened.

  The exposure apparatus 100, the C / D 110, and the wafer measurement / inspection instrument 120 which are connected in-line can be regarded as one substrate processing apparatus (100, 110, 120) as a unit. The substrate processing apparatus (100, 110, 120) applies a photosensitive agent such as a photoresist to the wafer W, and images of the patterns of the reticles R1 and R2 on the wafer W coated with the photosensitive agent. An exposure process for projection exposure and a development process for developing the wafer W after the exposure process are performed. These steps will be described later.

  In the device manufacturing processing system 1000, a plurality of exposure apparatuses 100, C / Ds 110, and wafer measurement / inspection instruments 120 (that is, substrate processing apparatuses (100, 110, 120)) are provided. Each substrate processing apparatus (100, 110, 120) and device manufacturing processing apparatus group 900 is installed in a clean room in which temperature and humidity are controlled. In addition, data communication can be performed between devices via a predetermined communication network (for example, LAN: Local Area Network). This communication network is a so-called intranet communication network provided for a customer's factory, business office or company.

  In the substrate processing apparatus (100, 110, 120), a plurality of wafers W (for example, 20 wafers) are processed as one unit (referred to as a lot). In the device manufacturing processing system 1000, the wafer W is processed into a product by processing one lot as a basic unit. Therefore, the wafer process in the device manufacturing processing system 1000 is also referred to as lot processing.

  In this device manufacturing processing system 1000, the wafer measurement / inspection instrument 120 is placed in the track 200 and is connected inline to the exposure apparatus 100 and the C / D 110. However, the wafer measurement / inspection instrument 120 is out of the track 200. It may be arranged and configured offline with the exposure apparatus 100 and the C / D 110.

  As the hardware for realizing the information processing apparatus in the wafer measurement / inspection instrument 120 described above, for example, a personal computer can be employed. In this case, it is realized by executing a program executed by a CPU (not shown) of the information processing apparatus. The analysis program is supplied by a medium (information recording medium) such as a CD-ROM and is executed in a state where it is installed in the PC.

[Analyzer]
The analysis apparatus 500 is an apparatus that operates independently of the exposure apparatus 100 and the track 200. The analysis apparatus 500 is connected to a communication network in the device manufacturing processing system 1000, and can send and receive data to and from the outside. The analysis apparatus 500 collects various data (for example, processing contents of the apparatus) from various apparatuses via the communication network, and analyzes data related to processes on the wafer. As hardware for realizing such an analysis apparatus 500, for example, a personal computer can be employed. In this case, the analysis process is realized by executing an analysis program executed by a CPU (not shown) of the analysis apparatus 500. This analysis program is supplied by a medium (information recording medium) such as a CD-ROM and is executed in a state installed in a PC.

  The analysis apparatus 500 optimizes the processing conditions of a series of processes based on the measurement / inspection results of the wafer measurement / inspection instrument 120 and the reticle measurement / inspection instrument 130. Here, the processing conditions to be optimized differ depending on the comparison result, and the apparatus parameters of the above control systems of the exposure apparatus 100, the change of the reticles R1 and R2 to be selected, the C / D 110, and the wafer measurement inspection. The processing contents of the container 120 are various. In the analysis apparatus 500, various types of information obtained in the device manufacturing process performed so far are accumulated in a database provided therein, and the processing conditions are optimized by referring to the database as necessary. .

[Device manufacturing processing equipment group]
The device manufacturing processing apparatus group 900 includes a CVD (Chemical Vapor Deposition) apparatus 910, an etching apparatus 920, and CMP (Chemical Mechanical Polishing) which performs a chemical mechanical polishing and planarizes the wafer. : Chemical mechanical polishing) apparatus 930 and oxidation / ion implantation apparatus 940 are provided. The CVD apparatus 910 is an apparatus that generates a thin film on a wafer, and the etching apparatus 920 is an apparatus that performs etching on a developed wafer. The CMP apparatus 920 is a polishing apparatus that flattens the surface of the wafer by chemical mechanical polishing, and the oxidation / ion implantation apparatus 940 forms an oxide film on the surface of the wafer or introduces impurities at a predetermined position on the wafer. A device for injecting. Also, a plurality of CVD apparatuses 910, etching apparatuses 920, CMP apparatuses 930, and oxidation / ion implantation apparatuses 940 are provided in the same manner as the exposure apparatus 100 and the like, and a transfer path for enabling transfer of wafers between them is provided. Is provided. In addition to this, the device manufacturing processing apparatus group 900 includes apparatuses that perform probing processing, repair processing, dicing processing, packaging processing, bonding processing, and the like.

[Management controller]
The management controller 160 centrally manages the exposure process performed by the exposure apparatus 100, and manages the C / D 110 and the wafer measurement / inspection instrument 120 in the track 200 and controls their cooperative operation. As such a controller, for example, a personal computer can be adopted. The management controller 160 receives information indicating the progress status of processing and operations, information indicating processing results, and measurement / inspection results from each apparatus through a communication network in the device manufacturing processing system 1000, and The status of the entire production line is grasped, and each apparatus is managed and controlled so that the exposure process and the like are performed appropriately.

[Host system]
A host system (hereinafter referred to as “host”) 600 manages the entire device manufacturing processing system 1000 and controls the exposure apparatus 100, the track 110, the wafer measurement / inspection instrument 120, and the device manufacturing processing apparatus group 900. It is a computer. For the host 600, for example, a personal computer can be employed. The host 600 and other devices are connected via a wired or wireless communication network so that data communication can be performed between them. By this data communication, the host 600 realizes overall control of this system.

[Device manufacturing process]
Next, a flow of a series of processes in the device manufacturing processing system 1000 will be described. FIG. 11 shows a flowchart of this process. A series of processes of the device manufacturing processing system 1000 is scheduled and managed by the host 600 and the management controller 160. As described above, wafers are processed in lot units. Actually, however, the processing shown in FIG. 11 is repeated for each wafer in lot units, for example, in a pipeline manner.

  As shown in FIG. 11, first, in step 201, a reticle carried into the exposure apparatus 100 is selected. This selection is performed by the analysis apparatus 500. The exposure apparatus 100 is an exposure apparatus that can simultaneously transfer the patterns on the two reticles R1 and R2 onto the wafer W. Therefore, the analysis apparatus 500 acquires the design data of the patterns on the two reticles R1 and R2, that is, (the type of correction pattern by OPC and the type of phase shift mask) from the host 600 or the management controller 160. From the data, an appropriate reticle is selected to transfer the device pattern onto the wafer W.

  Here, the reticles R1 and R2 are measured and inspected by the reticle measuring / inspecting instrument 130 as necessary. Examples of the contents to be measured and inspected include a pattern defect and reticle flatness. The analysis apparatus 500 can acquire the data of the measurement / inspection result from the reticle measurement / inspection instrument 130, and can select the reticle to be used as the reticles R1 and R2 based on the data of the measurement / inspection result. For example, a combination of two reticles having substantially the same flatness, a combination of reticles having no pattern defect affecting each other, and the like are selected. In addition to the measurement inspection result data, the analysis apparatus 500 selects the reticles R1 and R2 and the reticle for the exposure performed in the exposure apparatus 100 performed in the past, stored in advance in an internal database. The reticles R1 and R2 may be selected with reference to the relationship with the exposure result of the wafer W when using R1 and R2.

  Based on the imaging result of the pattern, when the patterns on the two reticles R1 and R2 are transferred onto the wafer W at the same time, two optimized device patterns are expected to be transferred onto the wafer W. Select reticles R1 and R2. For example, when the reticles included in the group of reticles A on which the pattern with low periodicity is formed and the reticles included in the group of reticles B on which the pattern with high periodicity are combined are best. Select a set that can transfer the device pattern.

  In the next step 203, the two selected reticles are loaded onto the reticle stage RST as reticles R1 and R2, and the alignment of the reticles R1 and R2 (reticle alignment) and the baseline (off-axis alignment sensor (not shown)) are performed. ) And the distance from the reticle pattern center). By this preparation processing, the device pattern on the reticles R1 and R2 can be overlaid on the shot area already formed on the wafer W aligned on the wafer stage WST.

  Thereafter, processing on the wafer W is performed in parallel with the above steps 201 and 203. First, a film is formed on the wafer in the CVD apparatus 910 (step 205), the wafer W is transferred to the C / D 110, and a resist is applied on the wafer in the C / D 110 (step 207). Next, the wafer W is transferred to the wafer measurement / inspection instrument 120, and the wafer measurement / inspection instrument 120 selects a shot area selected as a measurement target from the plurality of shot areas of the previous layer already formed on the wafer W. Prior measurement inspection processing such as measurement of shot flatness (focus step in the shot area) and inspection of foreign matter on the wafer is performed (hereinafter referred to as measurement shot) (step 209). The number and arrangement of the measurement shots can be arbitrary, but can be, for example, eight shots on the outer periphery of the wafer. The measurement result of the wafer measurement / inspection instrument 120 (that is, the shot flatness of the measurement shot) is sent to the exposure apparatus 100 and the analysis apparatus 500. This measurement result is used for focus control during scanning exposure in the exposure apparatus 100.

  Subsequently, the wafer is transferred to the exposure apparatus 100, and exposure processing for transferring the circuit pattern on the reticles R1 and R2 onto the wafer W is performed by the exposure apparatus 100 (step 211). At this time, the exposure apparatus 100 monitors the exposure amount, synchronization accuracy, focus, and lens control error trace data during measurement shot exposure, and stores them as log data in an internal memory. Next, the wafer W is transferred to the C / D 110, and development processing is performed in the C / D 110 (step 213). Thereafter, post-measurement inspection processing such as measurement of the line width of the resist image, measurement of the line width of the device pattern transferred onto the wafer, and pattern defect inspection is performed (step 215).

  The wafer W is transferred from the wafer measurement / inspection instrument 120 to the etching apparatus 920, etched in the etching apparatus 920, impurity diffusion, wiring processing, film formation in the CVD apparatus 910, planarization in the CMP apparatus 930, oxidation / ion Ion implantation with the implantation apparatus 940 is performed as necessary (step 219). Then, the host 600 determines whether all processes are completed and all patterns are formed on the wafer (step 221). If this determination is denied, the process returns to step 205, and if affirmed, the process proceeds to step 223. In this manner, a series of processes such as film formation / resist application to etching are repeatedly performed for the number of steps, whereby circuit patterns are stacked on the wafer W, and a semiconductor device is formed.

  After the repetition process is completed, the probing process (step 223) and the repair process (step 225) are executed in the device manufacturing processing apparatus group 900. In step 227, when a memory failure is detected, in step 229, for example, a process of replacing with a redundant circuit is performed. The analysis apparatus 500 can also send information such as the location where the detected line width abnormality has occurred to an apparatus that performs probing processing and repair processing. In the inspection apparatus (not shown), the portion where the line width abnormality has occurred on the wafer W can be excluded from the processing target for the probing process and the repair process in units of chips. Thereafter, a dicing process (step 227), a packaging process, and a bonding process (step 229) are executed to finally complete a product chip. Note that the post-measurement inspection process in step 215 may be performed after the etching in step 219. In this case, line width measurement is performed on the etching image on the wafer W. It may be performed both after development and after etching. In this case, since the line width measurement is performed on both the resist image and the etching image, the processing state of the etching process can be detected based on the difference between the measurement results. It becomes like this.

  Next, analysis processing of the analysis apparatus 500 in the device manufacturing processing system 1000 will be described in detail. This process is started after the process of step 215 in FIG. 11 is performed. FIG. 12 shows a flow showing the flow of data communication in this analysis process. As shown in FIG. 12, in step 301, the analysis apparatus 500 acquires data on the pre-measurement inspection results of the reticles R 1 and R 2 of the reticle measurement / inspection instrument 130, log data of the exposure apparatus 100, and in step 215. Data of the post-measurement inspection result of the wafer W of the wafer measurement / inspection instrument 120 is acquired from the wafer measurement / inspection instrument 120. An analysis result in the analysis apparatus 500 is sent to the exposure apparatus 100. The exposure apparatus 100 changes the apparatus parameters of the exposure apparatus 100 or replaces the selected reticle based on the analysis result. Although not shown, the analysis result is also sent to the C / D 110 and the wafer measurement / inspection instrument 120 when it is necessary to adjust them.

  FIG. 13 shows a flowchart of the analysis process. As shown in FIG. 13, in step 501, wafer measurement / inspection result data is acquired, and in step 503, the wafer measurement / inspection result data is referenced to detect pattern defects on the wafer W or to detect pattern lines. It is determined whether or not the error of the width exceeds the allowable range and the processing state of the exposure apparatus 100 or the like needs to be corrected. If this determination is denied, the process proceeds to step 539, and if denied, the process proceeds to step 505. In step 505, a reticle inspection result is obtained. In the next step 507, the correlation between the reticle inspection result (reticle abnormality) and the wafer inspection result (wafer defect) is calculated. In step 509, the correlation is set in advance. It is calculated whether or not it is equal to or greater than the threshold value. If the determination in step 509 is negative, the process proceeds to step 511, and if the determination is positive, the process proceeds to step 517.

  In step 511, it is determined whether or not the reticle abnormality factor is a foreign substance. If this determination is denied, the process proceeds to step 513, and if affirmed, the process proceeds to step 515. In step 513, reticle replacement necessity is set as an analysis result, and in step 515, foreign substance removal necessity is set as an analysis result.

  On the other hand, in step 517, log data is acquired from the exposure apparatus 100. In step 519, the estimated line width is obtained by referring to a database in which the relationship between the log data and the line width is registered based on the log data. calculate. In the next step 521, it is determined whether or not the estimated value of the line width matches the actually measured value. Only when this determination is affirmed, the process proceeds to step 525, where the parameters of the control system of the exposure apparatus 100 are optimized with reference to a database or the like, and the optimization result is set as the analysis result. The processing conditions optimized here include not only the control system parameters in the exposure apparatus 100 but also the illumination conditions of the exposure apparatus 100 (exposure wavelength, projection optical system NA, illumination NA, illumination σ, illumination type, depth of focus), etc. Can also be included.

  In step 531, it is determined whether or not an abnormality is found in the processing contents of the C / D 110 and the measurement / inspection instruments 120 and 130. Only when this determination is affirmed, the process proceeds to step 533, and the adjustment necessity of the C / D 110 and the measurement / inspection instruments 120 and 130 is set as an analysis result.

  In the next step 537, reticle optimization processing is performed. The reticle optimization process will be described. Here, a reticle that improves the formation state of the device pattern on the wafer W is selected from a plurality of different reticles created by the OPC technique or the phase shift technique. More specifically, a portion where the pattern deviation from the design information is greater than or equal to a threshold is extracted from the wafer measurement inspection result data. Then, a reticle having a pattern in which the deviation is corrected is selected for a portion where the deviation is large. For example, when the pattern corresponding to the pattern SP1 shown in FIG. 6A is entirely small, when the reticle on which the pattern SP2 is formed is selected or when the four corners are missing, A reticle on which patterns SP3 to SP5 are formed is selected. Similarly, a reticle on which patterns such as those shown in FIGS. 8A to 10E are formed is selected as necessary. Then, the selection result is set as an analysis result.

  As described above, the pattern on the reticle is categorized, and the change of the image on the wafer W surface by changing the pattern makes it easy to effectively use the pattern image (resist image or etching image) on the wafer W. Selectable reticle can be adjusted. Further, if the past reticle and the exposure result when the reticle is used are registered in the database, the database may be referred to.

  After the determination in step 503 is denied, after the completion of steps 513, 515, and 537, the process proceeds to step 539, where various devices and analysis results (including setting without adjustment) are notified, and the process ends.

  Receiving the notification of the analysis result from the analysis apparatus 500, the exposure apparatus 100 and the C / D 110 adjust its processing state according to the analysis result. For example, in the exposure apparatus 100, apparatus parameters are adjusted, reticles are exchanged, and the like.

  As described in detail above, the device pattern transferred onto the wafer W is divided into several patterns. The divided pattern is a simpler pattern than the original device pattern. For this reason, when such a divided pattern is transferred and a device pattern is finally formed on the wafer W, the effect of the optical proximity effect due to the pattern is less than when a complicated device pattern is transferred onto the wafer W as it is. Therefore, the deterioration of the pattern transferred onto the wafer W is reduced. Further, in the present embodiment, a plurality of reticles are prepared in which several component patterns that compensate for the deterioration of individual divided patterns are formed. As described above, since the individual component patterns are simplified, a component pattern having the best device pattern transfer accuracy on the wafer W can be quickly selected from the reticles. Then, if the device pattern is transferred using the selected mask, the reticle can be quickly optimized for the purpose of preventing deterioration of the transfer accuracy of the device pattern.

  Further, according to the present embodiment, it is not necessary to apply the OPC technique or the phase shift technique to a complicated device pattern, so that the manufacturing costs of the reticles R1 and R2 can be reduced.

  Further, according to the present embodiment, a plurality of reticles for transferring the same pattern can be an OPC mask and a phase shift mask formed by several types of optical proximity effect correction methods. In this way, it is possible to prepare deformation patterns (OPC patterns and phase shifters) having different transfer characteristics for several wafers W with respect to the divided patterns.

  Further, according to the present embodiment, the analysis apparatus 500 acquires information on the actual transfer result of the device pattern on the wafer W in step 501. In this way, the reticle R can be selected based on the actual transfer result of the device pattern onto the wafer W.

  As described above, according to the present embodiment, reticles R1 and R2 are selected from a plurality of reticles on which individual division patterns obtained by dividing a device pattern transferred onto the wafer W into a plurality of divisions. Since the device pattern is transferred onto the wafer W using the selected reticle, high-precision exposure is realized.

  In addition, according to the present embodiment, the divided patterns formed on the two reticles R1 and R2 are simultaneously transferred onto the wafer W, so that the throughput is improved. In addition, according to the present embodiment, when selecting a reticle, information on the other reticle (for example, the pitch and line width of the L / S pattern, the OPC technique and phase shift technique used), and the like are taken into consideration. Therefore, even if the device pattern is divided, the transfer accuracy of the final device pattern onto the wafer W is kept high.

  In the present embodiment, a transmissive reticle is used, but a reflective reticle may be used. This is because even with such a mask, it is possible to use OPC technology or phase shift technology. Of course, patterns that can be adopted as parts are not limited to those described above.

  In the present embodiment, the exposure apparatus that projects the pattern images of the two reticles R1 and R2 onto the wafer W through the same projection optical system PL is used. However, through separate projection optical systems, An exposure apparatus that projects two pattern images onto the wafer W may be used.

  In addition, the exposure apparatus 100 according to the present embodiment transfers the device pattern onto the wafer W by the simultaneous double exposure of the pattern, but uses an exposure apparatus that can simultaneously perform the triple exposure and the quadruple exposure. Of course, it is also good.

  The exposure apparatus 100 according to the present embodiment uses an exposure apparatus that performs so-called multiple exposure that exposes a plurality of patterns simultaneously. However, the present invention is also applied to an exposure apparatus that performs multiple exposure by exchanging a reticle as needed. Of course you can.

  In this embodiment, the wafer measurement / inspection instrument 120 is connected in-line with the exposure apparatus 100 or the like, but the wafer measurement / inspection instrument is an off-line measurement / inspection instrument that is not connected in-line with the exposure apparatus 100 or the track 200. It may be.

  Further, as disclosed in JP-A-11-135400 and JP-A-2000-164504, a measurement stage equipped with a wafer stage for holding the wafer W, a reference member on which a reference mark is formed, and various photoelectric sensors. The present invention can also be applied to an exposure apparatus including the above.

  In the above embodiment, the step-and-scan type and step-and-repeat type projection exposure apparatus has been described. However, the present invention is not limited to these projection exposure apparatuses, and other proximity type exposure apparatuses such as a proximity type exposure apparatus. Needless to say, the present invention can also be applied to an exposure apparatus. The present invention can also be suitably applied to a step-and-stitch reduction projection exposure apparatus that combines a shot area and a shot area. As represented by this, the various apparatuses are not limited to those types.

  Further, the present invention can be applied to a twin stage type exposure apparatus having two wafer stages as disclosed in, for example, International Publications WO98 / 24115 and WO98 / 40791. Of course, the present invention can also be applied to an exposure apparatus using a liquid immersion method disclosed in, for example, International Publication WO99 / 49504. In this case, an exposure apparatus that locally fills the liquid between the projection optical system and the substrate is employed, but the present invention is disclosed in JP-A-6-124873, JP-A-10-303114, US Pat. The present invention is also applicable to an immersion exposure apparatus that performs exposure in a state where the entire exposed surface of a substrate to be exposed is immersed in a liquid as disclosed in the specification of US Pat. No. 5,825,043.

  The present invention is not limited to a semiconductor manufacturing process, and can be applied to a manufacturing process of a display including a liquid crystal display element. Line width in all device manufacturing processes, including the process of transferring the device pattern onto the glass plate, the manufacturing process of the thin film magnetic head, the manufacturing process of the imaging device (CCD, etc.), micromachine, organic EL, DNA chip, etc. Of course, the present invention can be applied to management.

  In the above embodiment, the analysis apparatus 500 is a PC, for example. That is, the analysis processing in the analysis apparatus 500 is realized by executing an analysis program on a PC. As described above, this analysis program may be installable on the PC via a medium, or may be downloadable to the PC via the Internet or the like. Of course, the analysis apparatus 500 may be configured by hardware.

  As described above, the device manufacturing processing method of the present invention is suitable for manufacturing a device.

It is a figure which shows schematic structure of the device manufacturing processing system which concerns on one Embodiment of this invention. It is a figure which shows schematic structure of exposure apparatus. It is a figure which shows the mode of the relative synchronous scanning of both the stages in exposure apparatus. 4A to 4C are diagrams illustrating an example (part 1) of a device pattern dividing method. FIG. 5A to FIG. 5C are diagrams illustrating an example (part 2) of the device pattern dividing method. 6A to 6E are diagrams for explaining an application example 1 of the OPC technique. FIGS. 7A and 7B are diagrams for explaining an application example 2 of the OPC technique. FIGS. 8A and 8B are diagrams for explaining an application example 3 of the OPC technique. FIG. 9A to FIG. 9C are diagrams for explaining an application example 4 of the OPC technique. FIG. 10A to FIG. 10E are diagrams for explaining an application example 5 of the OPC technique. It is a flowchart which shows the flow of a series of processes in a device manufacturing processing system. It is a figure which shows the flow of the data communication in the analysis process of an analyzer. It is a flowchart of an analysis process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Illumination system, 20 ... Main control apparatus, 100 ... Exposure apparatus, 110 ... C / D, 160 ... Management controller, 200 ... Track, 500 ... Analysis apparatus, 600 ... Host system, 900 ... Device manufacturing processing apparatus group, 1000 ... Device manufacturing processing system, BP1, BP2 ... Pattern, BP1 'to BP5' ... Pattern, DP ... Device pattern, FP1, FP2 ... Component pattern, IA1, IA2 ... Exposure area, IAR1, IAR2 ... Illumination area, IL1, IL2 ... Exposure light, PL ... projection optical system, R1, R2 ... reticle, RST ... reticle stage, SP1-SP5 ... pattern, W ... wafer, WST ... wafer stage.

Claims (9)

A first divided pattern corresponding to a first portion of a device pattern transferred onto a substrate has a plurality of first masks formed under different conditions, and a second portion of the device pattern different from the first portion. A preparation step of preparing a plurality of second masks in which corresponding second division patterns are formed under different conditions;
An acquisition step of acquiring information related to a transfer state of the device pattern on the substrate for each of the plurality of first and second masks or for each combination of the first mask and the second mask;
Selecting a specific first mask from the plurality of first masks based on the acquired information, and selecting a specific second mask from the plurality of second masks; Device manufacturing processing method including.   2. The preparation process according to claim 1, wherein at least one of the first divided pattern and the second divided pattern is a common pattern included in a plurality of different device patterns transferred onto the substrate. Device manufacturing processing method.   The conditions for forming the first division pattern and the conditions for forming the second division pattern include at least one of an application condition for the optical proximity effect correction technique and an application condition for the phase shift technique. The device manufacturing processing method according to claim 1 or 2. In the acquisition step,
Information on the transfer result of the device pattern obtained by transferring onto the substrate for each of the plurality of first masks and the plurality of second masks, or for each combination of the first mask and the second mask. The device manufacturing processing method according to claim 1, wherein the device manufacturing method is acquired.   5. The method according to claim 1, further comprising a transfer step of transferring the device pattern to the substrate using the specific first mask and the specific second mask. 6. Device manufacturing processing method. In the transfer step,
6. The device manufacturing method according to claim 5, wherein the first divided pattern and the second divided pattern are simultaneously transferred onto the substrate.   7. The device manufacturing processing method according to claim 6, wherein in the selection step, the specific second mask is selected in consideration of information on the first division pattern formed on the specific first mask. . A first divided pattern corresponding to a first portion of a device pattern transferred onto a substrate has a plurality of first masks formed under different conditions, and a second portion of the device pattern different from the first portion. A preparation step of preparing a plurality of second masks in which corresponding second division patterns are formed under different conditions;
The image of the first divided pattern formed on the specific first mask selected from the prepared plurality of first masks and the specified selected from the prepared plurality of second masks A transfer step of simultaneously projecting the image of the second divided pattern formed on the second mask onto the substrate and transferring the device pattern. 9. The device manufacturing processing method according to claim 8 , wherein, in the transfer step, the specific second mask is selected in consideration of information regarding the first division pattern formed on the specific first mask. .

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