JP5229271B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP5229271B2
JP5229271B2 JP2010115526A JP2010115526A JP5229271B2 JP 5229271 B2 JP5229271 B2 JP 5229271B2 JP 2010115526 A JP2010115526 A JP 2010115526A JP 2010115526 A JP2010115526 A JP 2010115526A JP 5229271 B2 JP5229271 B2 JP 5229271B2
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lid
case
semiconductor device
protrusion
base plate
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JP2011243798A5 (en
JP2011243798A (en
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哲生 黒田
学 松本
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to DE102011007228.4A priority patent/DE102011007228B4/en
Priority to CN201110104259.7A priority patent/CN102254878B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

本発明は、ケース内にゲルを充填してフタで封止した半導体装置に関し、特にゲルがフタの上に這い上がるのを防ぐことができる半導体装置に関する。   The present invention relates to a semiconductor device in which a case is filled with gel and sealed with a lid, and more particularly to a semiconductor device capable of preventing the gel from creeping up on the lid.

絶縁性を確保するために、半導体素子を実装したケース内にゲルを充填してフタで封止した半導体装置が用いられている（例えば、特許文献１参照）。   In order to ensure insulation, a semiconductor device in which a case in which a semiconductor element is mounted is filled with a gel and sealed with a lid is used (for example, see Patent Document 1).

特開２００４−１０３９３６号公報JP 2004-103936 A

ゲルを硬化させる時に、ケースとフタの隙間を通って毛細管現象によりゲルがフタの上に這い上がるという問題があった。   When the gel is cured, there is a problem that the gel crawls up on the lid through a gap between the case and the lid due to capillary action.

本発明は、上述のような課題を解決するためになされたもので、その目的は、ゲルがフタの上に這い上がるのを防ぐことができる半導体装置を得るものである。   The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device capable of preventing a gel from creeping on a lid.

本発明は、ベース板と、前記ベース板上に設けられたケースと、前記ケースの内壁に設けられた突起と、前記ケース内において前記ベース板上に設けられた半導体素子と、前記突起により保持され、前記半導体素子に接続された端子と、前記ケース内に充填されたゲルと、前記ケースに取り付けられ、前記半導体素子及び前記ゲルを封止するフタと、下端が前記ベース板に接し、上端が前記フタの下面に接して、前記ケースに対して前記フタを固定する柱とを備え、前記突起の上面と前記フタの下面は離れていることを特徴とする半導体装置である。   The present invention provides a base plate, a case provided on the base plate, a protrusion provided on the inner wall of the case, a semiconductor element provided on the base plate in the case, and held by the protrusion A terminal connected to the semiconductor element, a gel filled in the case, a lid attached to the case and sealing the semiconductor element and the gel, a lower end in contact with the base plate, and an upper end The semiconductor device includes a column that contacts the lower surface of the lid and fixes the lid to the case, and the upper surface of the protrusion and the lower surface of the lid are separated from each other.

本発明により、ゲルがフタの上に這い上がるのを防ぐことができる。   According to the present invention, it is possible to prevent the gel from creeping on the lid.

実施の形態１に係る半導体装置を示す断面図である。1 is a cross-sectional view showing a semiconductor device according to a first embodiment. 図１に示す半導体装置のケース内部を示す斜視図である。It is a perspective view which shows the case inside of the semiconductor device shown in FIG. 図１に示すケースに端子を取り付ける様子を示す斜視図である。It is a perspective view which shows a mode that a terminal is attached to the case shown in FIG. 比較例に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on a comparative example. 実施の形態１に係る半導体装置の変形例を示す断面図である。FIG. 6 is a cross-sectional view showing a modification of the semiconductor device according to the first embodiment. 図５に示す半導体装置のフタの下面側を示す斜視図である。It is a perspective view which shows the lower surface side of the lid | cover of the semiconductor device shown in FIG. 実施の形態２に係る半導体装置を示す断面図である。FIG. 6 is a cross-sectional view showing a semiconductor device according to a second embodiment.

本発明の実施の形態に係る半導体装置について図面を参照して説明する。同じ構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。   A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same components are denoted by the same reference numerals, and repeated description may be omitted.

実施の形態１．
図１は、実施の形態１に係る半導体装置を示す断面図である。図２は、図１に示す半導体装置のケース内部を示す斜視図である。図３は、図１に示すケースに端子を取り付ける様子を示す斜視図である。 Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment. FIG. 2 is a perspective view showing the inside of the case of the semiconductor device shown in FIG. FIG. 3 is a perspective view showing how a terminal is attached to the case shown in FIG.

ベース板１０上にマザーケース１２が設けられている。マザーケース１２の内壁に突起１４が設けられている。マザーケース１２内において、ベース板１０上に絶縁基板１６を介して半導体素子１８が設けられている。   A mother case 12 is provided on the base plate 10. A protrusion 14 is provided on the inner wall of the mother case 12. In the mother case 12, a semiconductor element 18 is provided on the base plate 10 via an insulating substrate 16.

図３に示すように、マザーケース１２の内壁に設けられた突起１４には、ピン端子２０及びネジブロック端子２２を自由に挿入できる。この突起１４によりピン端子２０及びネジブロック端子２２が保持されている。ピン端子２０及びネジブロック端子２２は、ワイヤ２４を介して半導体素子１８に接続されている。マザーケース１２内にシリコーンゲル２６が充填されている。マザーケース１２にフタ２８が取り付けられている。このフタ２８は、半導体素子１８及びシリコーンゲル２６を封止する。   As shown in FIG. 3, the pin terminal 20 and the screw block terminal 22 can be freely inserted into the protrusion 14 provided on the inner wall of the mother case 12. The pin 14 and the screw block terminal 22 are held by the protrusion 14. The pin terminal 20 and the screw block terminal 22 are connected to the semiconductor element 18 via a wire 24. A silicone gel 26 is filled in the mother case 12. A lid 28 is attached to the mother case 12. The lid 28 seals the semiconductor element 18 and the silicone gel 26.

さらに、本実施の形態では、マザーケース１２内に柱３０が設けられている。この柱３０の下端はベース板１０に接し、柱３０の上端はフタ２８の下面（ケース内面）に接している。この柱３０はマザーケース１２に対してフタ２８を固定する。この状態で、マザーケース１２の上面とフタ２８の上面が位置合わせされ、かつ突起１４の上面とフタ２８の下面は離れている。なお、製造及び組立の容易さのため、柱３０はフタ２８の下面に固定又は一体成型されていることが好ましい。   Further, in the present embodiment, a pillar 30 is provided in the mother case 12. The lower end of the column 30 is in contact with the base plate 10, and the upper end of the column 30 is in contact with the lower surface (case inner surface) of the lid 28. The pillar 30 fixes the lid 28 to the mother case 12. In this state, the upper surface of the mother case 12 and the upper surface of the lid 28 are aligned, and the upper surface of the protrusion 14 and the lower surface of the lid 28 are separated. For ease of manufacture and assembly, the column 30 is preferably fixed or integrally molded to the lower surface of the lid 28.

本実施の形態の効果について比較例と比較して説明する。図４は、比較例に係る半導体装置を示す断面図である。比較例では、マザーケース１２の内壁の突起１４によりフタ２８の底面を支えている。従って、シリコーンゲル２６を硬化させる時に、突起１４の上面とフタ２８の下面の隙間、及びマザーケース１２の内壁とフタ２８の外壁の隙間を通って、毛細管現象によりシリコーンゲル２６がフタ２８の上に這い上がる。   The effect of the present embodiment will be described in comparison with a comparative example. FIG. 4 is a cross-sectional view showing a semiconductor device according to a comparative example. In the comparative example, the bottom surface of the lid 28 is supported by the protrusion 14 on the inner wall of the mother case 12. Therefore, when the silicone gel 26 is cured, the silicone gel 26 passes through the gap between the upper surface of the protrusion 14 and the lower surface of the lid 28 and the gap between the inner wall of the mother case 12 and the outer wall of the lid 28 by capillarity. Crawling up.

一方、本実施の形態では、マザーケース１２とフタ２８の接触部分がシリコーンゲル２６の上面と離れている。そして、突起１４の上面とフタ２８の下面との間の空間３２がゲル溜まり部となる。このため、シリコーンゲル２６がフタ２８の上に這い上がるのを防ぐことができる。   On the other hand, in the present embodiment, the contact portion between the mother case 12 and the lid 28 is separated from the upper surface of the silicone gel 26. A space 32 between the upper surface of the protrusion 14 and the lower surface of the lid 28 becomes a gel reservoir. For this reason, it is possible to prevent the silicone gel 26 from creeping up on the lid 28.

図５は、実施の形態１に係る半導体装置の変形例を示す断面図である。図６は、図５に示す半導体装置のフタの下面側を示す斜視図である。柱３０の周囲において、柱３０と離間して、フタ２８の下面に壁３４が設けられている。柱３０を這い上がったシリコーンゲル２６がフタ２８の下面まで達しても、そのシリコーンゲル２６は壁３４を伝って下に落ちる。これにより、シリコーンゲル２６がフタ２８の上に這い上がるのを更に確実に防ぐことができる。   FIG. 5 is a cross-sectional view showing a modification of the semiconductor device according to the first embodiment. 6 is a perspective view showing the lower surface side of the lid of the semiconductor device shown in FIG. A wall 34 is provided on the lower surface of the lid 28 so as to be separated from the pillar 30 around the pillar 30. Even if the silicone gel 26 scooping up the pillar 30 reaches the lower surface of the lid 28, the silicone gel 26 falls down along the wall 34. Thereby, it can prevent more reliably that the silicone gel 26 crawls up on the lid | cover 28. FIG.

実施の形態２．
図７は、実施の形態２に係る半導体装置を示す断面図である。実施の形態１の柱３０の代わりに、本実施の形態ではゴムパッキン３６が設けられている。このゴムパッキン３６は、マザーケース１２の内壁とフタ２８の外壁との隙間を埋めつつ、マザーケース１２に対してフタ２８を固定する。これにより、シリコーンゲル２６がフタ２８の上に這い上がるのを防ぐことができる。 Embodiment 2. FIG.
FIG. 7 is a cross-sectional view showing the semiconductor device according to the second embodiment. In this embodiment, a rubber packing 36 is provided instead of the column 30 of the first embodiment. The rubber packing 36 fixes the lid 28 to the mother case 12 while filling a gap between the inner wall of the mother case 12 and the outer wall of the lid 28. Thereby, it is possible to prevent the silicone gel 26 from crawling on the lid 28.

また、ゴムパッキン３６によりマザーケース１２に対してフタ２８を固定する際に、突起１４の上面とフタ２８の下面が離れるようにすることが好ましい。これにより、シリコーンゲル２６がフタ２８の上に這い上がるのを更に確実に防ぐことができる。   Further, when the lid 28 is fixed to the mother case 12 by the rubber packing 36, it is preferable that the upper surface of the protrusion 14 and the lower surface of the lid 28 are separated from each other. Thereby, it can prevent more reliably that the silicone gel 26 crawls up on the lid | cover 28. FIG.

なお、ゴムパッキン３６がフタ２８に取り付けてあっても、マザーケース１２に取り付けてあっても、同様の効果が得られる。   The same effect can be obtained regardless of whether the rubber packing 36 is attached to the lid 28 or the mother case 12.

１０ ベース板
１２ マザーケース（ケース）
１４ 突起
１８ 半導体素子
２０ ピン端子（端子）
２２ ネジブロック端子（端子）
２６ シリコーンゲル（ゲル）
２８ フタ
３０ 柱
３４ 壁
３６ ゴムパッキン 10 Base plate 12 Mother case (case)
14 Protrusion 18 Semiconductor element 20 Pin terminal (terminal)
22 Screw block terminal (terminal)
26 Silicone gel (gel)
28 Lid 30 Pillar 34 Wall 36 Rubber packing

Claims (3)

ベース板と、
前記ベース板上に設けられたケースと、
前記ケースの内壁に設けられた突起と、
前記ケース内において前記ベース板上に設けられた半導体素子と、
前記突起により保持され、前記半導体素子に接続された端子と、
前記ケース内に充填されたゲルと、
前記ケースに取り付けられ、前記半導体素子及び前記ゲルを封止するフタと、
下端が前記ベース板に接し、上端が前記フタの下面に接して、前記ケースに対して前記フタを固定する柱とを備え、
前記突起の上面と前記フタの下面は離れていることを特徴とする半導体装置。 A base plate,
A case provided on the base plate;
A protrusion provided on the inner wall of the case;
A semiconductor element provided on the base plate in the case;
A terminal held by the protrusion and connected to the semiconductor element;
A gel filled in the case;
A lid attached to the case and sealing the semiconductor element and the gel;
A lower end in contact with the base plate, an upper end in contact with the lower surface of the lid, and a column for fixing the lid to the case;
The semiconductor device according to claim 1, wherein an upper surface of the protrusion and a lower surface of the lid are separated from each other. 前記柱の周囲において、前記柱と離間して、前記フタの下面に設けられた壁を更に備えることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, further comprising a wall provided on a lower surface of the lid so as to be separated from the pillar around the pillar. ベース板と、
前記ベース板上に設けられたケースと、
前記ケース内において前記ベース板上に設けられた半導体素子と、
前記ケース内に充填されたゲルと、
前記ケースに取り付けられ、前記半導体素子及び前記ゲルを封止するフタと、
前記ケースの内壁と前記フタの外壁との隙間を埋めつつ、前記ケースに対して前記フタを固定するゴムパッキンと、
前記ケースの内壁に設けられた突起と、
前記突起により保持され、前記半導体素子に接続された端子とを備え、
前記突起の上面と前記フタの下面は離れていることを特徴とする半導体装置。 A base plate,
A case provided on the base plate;
A semiconductor element provided on the base plate in the case;
A gel filled in the case;
A lid attached to the case and sealing the semiconductor element and the gel;
Rubber packing for fixing the lid to the case while filling a gap between the inner wall of the case and the outer wall of the lid ;
A protrusion provided on the inner wall of the case;
A terminal held by the protrusion and connected to the semiconductor element;
The semiconductor device according to claim 1 , wherein an upper surface of the protrusion and a lower surface of the lid are separated from each other .
JP2010115526A 2010-05-19 2010-05-19 Semiconductor device Active JP5229271B2 (en)

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JP2010115526A JP5229271B2 (en) 2010-05-19 2010-05-19 Semiconductor device
DE102011007228.4A DE102011007228B4 (en) 2010-05-19 2011-04-12 Semiconductor device
CN201110104259.7A CN102254878B (en) 2010-05-19 2011-04-15 Semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8524370B2 (en) 2005-12-23 2013-09-03 3M Innovative Properties Company Multilayer films including thermoplastic silicone block copolymers

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6848802B2 (en) * 2017-10-11 2021-03-24 三菱電機株式会社 Semiconductor device
JP6861622B2 (en) * 2017-12-19 2021-04-21 三菱電機株式会社 Semiconductor equipment and power conversion equipment
EP4270469A1 (en) * 2022-04-29 2023-11-01 Infineon Technologies AG Power semiconductor module

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4079511A (en) * 1976-07-30 1978-03-21 Amp Incorporated Method for packaging hermetically sealed integrated circuit chips on lead frames
DE3308720A1 (en) 1983-03-11 1984-09-13 Siemens AG, 1000 Berlin und 8000 München SEMICONDUCTOR COMPONENT WITH DISC-SHAPED HOUSING
JPS6329957A (en) * 1986-07-23 1988-02-08 Seiko Epson Corp Sealing type of semiconductor device
JPS63164345A (en) 1986-12-26 1988-07-07 Nec Corp Package for semiconductor integrated circuit
JPH02307250A (en) * 1989-05-23 1990-12-20 Mitsubishi Electric Corp Hybrid integrated circuit package
JP3357220B2 (en) 1995-07-07 2002-12-16 三菱電機株式会社 Semiconductor device
WO2002059969A1 (en) 2001-01-23 2002-08-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JP2004103936A (en) 2002-09-11 2004-04-02 Mitsubishi Electric Corp Power semiconductor device and manufacturing method thereof
EP1494278A1 (en) 2003-07-04 2005-01-05 Siemens Aktiengesellschaft Electronic power module with rubber seal, and corresponding manufacturing method
CN100361317C (en) * 2004-02-27 2008-01-09 矽品精密工业股份有限公司 Package of possessing support piece for packing light sensitive semiconductor
EP1768182B1 (en) 2005-09-27 2011-06-22 Semikron Elektronik GmbH & Co. KG Patentabteilung Semiconductor power module with overcurrent protection means
JP4242401B2 (en) * 2006-06-29 2009-03-25 三菱電機株式会社 Semiconductor device
CN101101880A (en) * 2006-07-03 2008-01-09 矽品精密工业股份有限公司 Heat-radiation type package structure and its method for making
JP4858336B2 (en) * 2007-07-10 2012-01-18 三菱電機株式会社 Power semiconductor device
DE102008051560A1 (en) 2007-10-18 2009-04-23 Infineon Technologies Ag Power module, particularly power semiconductor module, has housing with multiple receiving elements and carrier element, where elastic deformable cover is arranged on carrier element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8524370B2 (en) 2005-12-23 2013-09-03 3M Innovative Properties Company Multilayer films including thermoplastic silicone block copolymers

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DE102011007228B4 (en) 2019-08-22

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