JP5218539B2 - Timing extraction circuit of optical receiver using half frequency clock of data transmission rate and duty deviation countermeasure circuit of optical transceiver - Google Patents

Description

  The present invention relates to an optical transceiver, and more particularly, to a timing extraction circuit for an optical receiver that uses a ½ frequency clock of a data transmission rate in a high-speed optical communication system, and a duty shift countermeasure circuit for the optical transceiver.

  The trunk optical communication system connecting large cities and the like is required to have a larger capacity and a higher speed system in order to cope with advanced information in society such as moving image transmission and data transmission in the future. In a 3R repeater and a terminal station in an optical communication system, processing such as optical-electrical signal conversion, equalization amplification, timing clock extraction, and signal identification of an optical signal received by an optical signal receiving unit is performed. Usually, these functions are realized by an integrated circuit. In recent years, PLL (Phase Locked Loop) technology has been used for timing clock extraction because of easy integration.

  When an ultra-high-speed long-distance optical fiber transmission system such as 10 to 40 Gb / s is realized at an early stage, it is difficult to obtain sufficient high-speed characteristics for devices constituting an optical transceiver circuit at present. It is necessary to reduce the operation speed of the entire circuit by minimizing the circuit scale. The fastest operation speed is required for an optical transmission / reception circuit that directly handles a signal of transmission speed. Among them, a device that operates in synchronization with a clock signal is particularly susceptible to insufficient high-speed characteristics.

  FIG. 1 shows a configuration example of a conventional high-speed optical communication system.

  FIG. 1A, which is described in the example of the 10 Gb / s optical transmission system, extracts a clock signal having the same frequency as the transmission speed from the transmitted 10 Gb / s data signal, and identifies the data signal. 2 shows a configuration example of a high-speed optical communication system using a so-called same frequency clock extraction method.

  On the optical transmitter 10 side, a 10 G bit rate (BR) signal x-multiplexed by an x: 1 multiplexer (MUX) 11 is waveform-shaped by a D-flip / flop (DF / F) 15. Then, it is input to the optical modulator 13 via the driver 14. An optical signal from the laser diode 12 is modulated by a signal from the driver by an optical modulator 13, and is output to an optical transmission line 20 using an optical fiber as a 10 Gb / s optical modulation signal.

  On the other hand, on the optical receiver 30 side, the optical signal received from the optical transmission line 20 is photoelectrically converted by the photodiode 31, amplified by the amplifier 32, and then input to the identification circuit 34 and the timing extraction circuit 33. The timing extraction circuit 33 extracts the same 10 GHz clock signal as the transmission signal from the input signal. The identification circuit 34 samples the received data signal using the extracted clock signal, and identifies the logic level of the received data signal. Thereafter, the original signal x is restored by the 1: x separation circuit (DEMUX) 35.

  FIG. 1 (b) illustrating an example of a 40 Gb / s optical transmission system when the transmission rate is increased is a clock signal having a frequency that is half the transmission rate from the transmitted 40 Gb / s data signal. 1 shows a configuration example of a high-speed optical communication system using a so-called 1/2 frequency clock extraction system that extracts data signals and identifies data signals. Here, only differences from FIG. 1A described above will be described.

  First, on the transmitter 10 side, the D-flip / flop (DF / F) 15 for waveform shaping is deleted. The main reason is that it is difficult to manufacture a clocking device that operates normally at 40 Gb / s (bit width 25 ps) at present. As a result, in this example, a 1/2 frequency clock (BR / 2 = 20 GHz) is used, and the multiplexed signal from the multiplexing unit (MUX) 11 is selected and output at 40 Gb / s every half cycle of the clock. The data signal is extracted. The data signal directly drives the driver 14, and a 40 Gb / s data signal is output from the optical modulator 13 to the optical transmission line 20.

  Next, on the optical receiver 30 side, the timing extraction unit 36 extracts a 1/2 cycle clock signal (BR / 2 = 20 GHz) of the received data bit rate from the received 40 Gb / s data signal and outputs it. Then, by using the normal and inverted clock edge signals for each half cycle and the two identification units 37 and 38, a data signal of 2 bits for each clock cycle (1 bit for each half cycle = 40 Gb / s) is identified. To do. The two identified data signals are restored to the original signal x by the subsequent 2: x separation circuit (DEMUX) 39.

  FIG. 2 shows a circuit configuration example of the timing extraction unit 33 and the identification unit 34 using the same frequency clock extraction method in FIG. FIG. 4 is a timing chart showing an operation example of points corresponding to the numbers in each parenthesis in FIG. FIG. 3 shows a circuit configuration example of the timing extraction unit 36 and the identification units 37 and 38 using the ½ frequency clock extraction method in FIG. FIG. 5 is a timing chart showing an operation example of points corresponding to the numbers in each parenthesis in FIG. The basic operations will be briefly described below.

  The received data signal (1) is input to two-stage D-flip / flops 41 and 42 corresponding to the identification circuit 34 in FIG. 1A, and the clock rise from the lower PLL (Phase Lock Loop) circuit. A signal (3) synchronized with the clock by the edge signal and a 1-bit delayed signal (4) are generated. Similarly, the received data signal (1) is also input to the two-stage D-flip / flops 43 and 44. However, here, the preceding D-flip / flop 43 is latched by the clock falling edge signal, and the subsequent D-flip / flop 44 is latched by the clock rising edge signal. As a result, a synchronization signal (5) delayed by a half cycle from the synchronization signal (3) and a synchronization signal (6) delayed by a half cycle (same phase as the synchronization signal (4)) are generated. Next, an exclusive OR (EXOR) output signal (8) of the synchronization signals (4) and (6) and an EXOR output signal (7) of the synchronization signals (3) and (6) are obtained, respectively. These magnitude comparison signals by the comparison circuit 47 control a voltage controlled oscillator (VCO) 49 via a loop filter 48.

  Here, paying attention to the phase relationship between the rising and falling edges of the received data signal (1) and the falling edge of the clock signal (2), the EXOR output signals (7) and (8) depend on which edge comes first. ) That the output signal is different. As shown in FIG. 4A, when the falling edge of the clock output signal (2) from the VCO 49 is delayed from the switching edge of the received data signal (1) (phase delay), the synchronization signal (3) and The signal (6) is the same, and the EXOR output signal (7) is at a low level. On the other hand, as shown in FIG. 4B, when the falling edge of the clock output signal (2) from the VCO 49 is ahead of the switching edge of the received data signal (1) (phase advance), the synchronization signal ( The signals 4) and (6) are the same, and the EXOR output signal (8) is at a low level. On the other hand, when the input signal pattern is random and the mark ratio is ½, the average voltage of the EXOR output signal (8) becomes an intermediate value between the high level and the low level when the phase is delayed. On the contrary, in the phase advance, the average voltage of the EXOR output signal (7) becomes an intermediate value between the high level and the low level. Therefore, the phase relationship between the data signal and the clock signal can be detected by the difference in average voltage between the EXOR outputs (7) and (8). In this example, the magnitude comparison signal from the comparison circuit 47 using a binary phase comparison circuit controls the VCO 49 through a loop filter (low-pass filter) 48 so that each phase difference becomes zero. That is, in this example, the phase is controlled so that the falling edge of the clock output signal (2) always coincides with the switching edge of the received data signal (1), and signal identification is performed by the two edge signals before and after the falling edge. Done.

  Next, an example of circuit operation of the 1/2 frequency clock extraction method of FIGS. 3 and 5 will be described. Here, the oscillation center frequency of the VCO 50 is half the bit rate of the received data signal (1). The received data signal (1) is input to two D-flip / flops 51 and 52 corresponding to the identification circuits 37 and 38 of FIG. 1B, and the clock falling / rising edge signal from the lower PLL circuit. Signals (3) and (4) synchronized with each other are generated. Similarly, the received data signal (1) is also input to the D-flip / flop 53, where the clock signal output from the VCO 50 is T / 2 (1/4 clock cycle, T = half clock cycle). ) A signal (6) given through the delay circuit 54 and synchronized with the clock rising edge signal is generated.

  Thereafter, the exclusive OR (EXOR) output signal (8) of the synchronization signals (4) and (6) and the EXOR output signal (7) of the synchronization signals (3) and (6) are respectively obtained and compared. The point that the voltage controlled oscillator (however, 50) is controlled via the loop filter 48 by the magnitude comparison signal of the circuit 47 is the same as in FIG. As shown in FIG. 5A, when the rising edge of the quarter-cycle delayed clock signal (5) from the VCO 50 is delayed from the switching edge of the received data signal (1), the synchronization signals (3) and ( The signals of 6) are the same for 3/4 clock periods, and the EXOR output signal (7) is at a low level during that period. On the other hand, as shown in FIG. 5B, when the rising edge of the clock signal (5) from the VCO 50 is ahead of the switching edge of the received data signal (1), the synchronization signals (4) and (6) Are equal to each other for 3/4 clock cycles, and the EXOR output signal (8) becomes low level during that period. The magnitude comparison signal from the comparison circuit 47 controls the VCO 50 in the subsequent stage so that each phase difference is zero. That is, in this example, the phase is controlled so that the rising edge of the clock signal (5) always coincides with the switching edge of the received data signal (1), and signal identification is performed by the two edge signals before and after the rising edge. As described above, the 1/2 frequency clock extraction method has a great advantage in that a 1/2 frequency clock can be used with a hardware configuration almost similar to that of the same frequency clock method.

  However, in the 1/2 frequency clock extraction method, even when the data signal pattern has no problem in the conventional same frequency clock extraction method when comparing the phase of the clock signal and the data signal, the specific signal pattern “1100” is the same. There has been a problem that a phase comparison signal cannot be obtained if it is repeated continuously.

  6 and 7 show timing chart examples of two types of phase relationships A and B with respect to the signal pattern “1100” in question. FIGS. 6A and 6B respectively show the case of the phase delay and phase advance of the clock signal. In this example, the rising edge of the clock signal (5) is the change point (“ Since it is within the phase control range for “0” → “1” or “1” → “0”), a difference occurs in the level average value of the synchronization signals (7) and (8) (phase relationship A). Therefore, the phase control is performed so as to coincide with the switching edge of the received data signal (1) by comparing the levels of the synchronization signals (7) and (8) as in FIG. 5 described above. On the other hand, (c) and (d) of FIG. 7 also show the case of the phase delay and phase advance of the clock signal, respectively, but in this case, the rising edge of the clock signal (5) is the received data signal (1). Since they are at the same level transition point (“0” → “0” or “1” → “1”), the synchronization signals (7) and (8) have the same waveform and the same level average value (phase). Relationship B). Accordingly, phase detection is impossible during this period, and the PLL may be out of synchronization.

  In order to perform phase comparison in this way, a transition between high and low levels of the data signal is required. In the case of the 1/2 clock extraction method, all changes in the data signal are used for phase comparison as shown in FIGS. We do not mean that we use every other one. Therefore, phase detection is possible in the case of the phase relationship A in FIG. 6, but phase detection is impossible in the case of the phase relationship B in FIG. In order to cope with this, it is conceivable to scramble the data signal. However, in the example of the optical transmission system of 10 Gb / s, the “1100” pattern is actually used over 1528 bits (Bellcoregeneric requirements GR-1377-CORE, “ In the case of a system conforming to “SONET OC-192 Transport System Generic Criteria”), there is a possibility that the “1100” pattern may be continuously used for several thousand bits even in a higher-speed system. If the 1/2 clock extraction method is used for this, the above-described problems such as an increase in PLL phase deviation or out of synchronization occur.

  As another problem, in the system configuration that performs ultra-high speed optical communication of 40 Gb / s shown in FIG. 1B, the D--clocking is performed at the data transmission speed at the final stage of the optical transmitter 10. Waveform shaping by F / F is not performed. Therefore, problems as shown in FIGS. 8 and 9 occur.

  FIG. 8 shows a circuit configuration example of the output stage of the 2: 1 multiplexing circuit. FIG. 9 shows examples of signal waveforms in FIG. 8 and the relationship between them and the clock and data identification timing by the 1/2 clock extraction method on the optical receiver side.

  In FIG. 8, 20 Gb / s serial data (DATA 1) is input to the D-flip / flop 61, and 20 Gb / s serial data (DATA 2) is input to the D-flip / flop 62. In this example, the normal clock signal of the 20 GHz duty shifted clock signal shown in FIG. 9A is input to the clock terminal of the D-flip / flop 61, and the inverted clock signal is the clock of the D-flip / flop 62. Input to the terminal. The clock signal further controls a selector 64 via a delay circuit (T / 4 = 1/8 clock cycle) 63 that compensates for each operation delay time of the D-flip / flops 61, 62. Any one of the outputs from the two D-flip / flops 61 and 62 is switched every half clock cycle and selectively output. As a result, 40 Gb / s data is output from the selector 64, but as shown in FIG. 9B, a data signal with a duty shifted every other bit due to the duty shift of the clock signal is output. The

  When the received data is identified on the optical receiver 30 side by using the 1/2 clock extraction method, as shown in FIG. 9 (c), it is located at equal intervals before and after the central PLL phase-locked clock signal. There is a problem that the sampling margin at one of the data identification (sampling) points is lost. For this reason, even if one data identification phase is adjusted, there are two phase lock points in the 1/2 clock extraction method (duty “narrow” → “wide” or “wide” → “narrow” changes) Point) After all, the problem that the data identification phase deviates from the set point could not be solved.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a timing extraction circuit for an optical receiver that uses an improved 1/2 clock extraction method having a characteristic equivalent to that of a conventional same clock extraction method even for a specific signal pattern.

  Another object of the present invention is to provide a duty shift correspondence circuit that controls the discrimination phase automatically or by initial setting by discriminating the width of the duty of the received data signal in an optical receiver using a 1/2 clock extraction method. It is. At that time, a stricter identification phase setting is realized by independently adjusting the identification phase of the clock signal for identifying the data signal and the inverted clock signal.

  A further object of the present invention is to provide a duty shift countermeasure circuit that compensates the duty of a clock waveform used in a 2: 1 multiplexing circuit in an optical transmitter.

  According to the present invention, a PLL circuit including a phase comparison circuit that performs phase comparison between a data signal of a bit rate B (bit / s) and a clock signal of B / 2 (Hz) at an interval of 2 / B (sec) is used. A timing extraction circuit that detects that the phase comparison information output from the phase comparison circuit has been lost by receiving a data signal of a predetermined pattern, and a clock signal for maintaining synchronization by the detection. And a timing extraction circuit having a control circuit for controlling the phase. A timing extraction circuit using a PLL circuit including a phase comparison circuit that performs phase comparison between a data signal of a bit rate B (bit / s) and a clock signal of B / 2 (Hz) at intervals of 2 / B (sec). A timing extraction circuit having two phase comparison circuits having different comparison phases for one period (1 / B sec) of the data signal is provided for phase comparison of all data signals.

  According to the present invention, a PLL circuit including a phase comparison circuit that performs phase comparison between a data signal having a bit rate B (bit / s) and a clock signal having B / 2 (Hz) at an interval of 2 / B (sec) is provided. A duty determination circuit for determining a duty between input data before and after the point where the PLL circuit is synchronized, and a control circuit which controls a data identification phase before and after the point where the PLL circuit is synchronized based on the determination result. A circuit for dealing with duty deviation of the optical receiver is provided. The control circuit includes an initial phase setting circuit in which desired duty information is set, and the initial phase setting circuit compares the duty at the time of initial phase adjustment with the desired duty information to obtain a desired duty information. If the phase is synchronized in the same state as the information, the state is maintained. If the phase is synchronized in a state different from the desired duty information, the clock output of the voltage controlled oscillator of the PLL circuit is inverted. The control circuit independently adjusts the phase of the clock signal obtained by delaying the phase of the ½ cycle of the data signal and the phase of the clock signal, so that the clock signal for identifying the data signal and its inverted clock signal The identification phase is adjusted independently.

It is the figure which showed the structural example of the conventional high-speed optical communication system. It is the figure which showed an example of the same frequency clock extraction system. It is the figure which showed an example of the 1/2 frequency clock extraction system. 3 is a timing chart of FIG. It is a timing chart of FIG. 6 is a timing chart of phase relationship A. 5 is a timing chart of phase relationship B. It is the figure which showed the example of a circuit structure of the output stage of 2: 1 multiplex circuit. It is the figure which showed the example of a signal waveform. It is the figure which showed the 1st Example by this invention. It is an operation | movement principle figure of FIG. It is the figure which showed the specific application example (1) of the 1st Example. It is a timing chart of FIG. It is the figure which showed the specific application example (2) of the 1st Example. It is a timing chart of FIG. It is the figure which showed the specific application example (3) of the 1st Example. It is the figure which showed the 2nd Example by this invention. It is a timing chart (1) of FIG. It is a timing chart (2) of FIG. It is a timing chart (3) of FIG. It is a timing chart (4) of FIG. It is the figure which showed the 3rd Example by this invention. It is a timing chart (1) of FIG. It is a timing chart (2) of FIG. It is the figure which showed the specific example of application of the 3rd Example. FIG. 26 is a signal waveform diagram of FIG. 25. It is the figure which showed the 4th Example by this invention. It is a timing chart of FIG. It is the figure which showed the specific application example (1) of the 4th Example. It is the figure which showed the specific application example (2) of the 4th Example. It is the figure which showed the specific application example (3) of the 4th Example. It is a timing chart of FIGS. It is the figure which showed the 5th Example by this invention. It is the figure which showed the specific application example (1) of the 5th Example. It is the figure which showed the specific application example (2) of the 5th Example.

  FIG. 10 shows a first embodiment according to the present invention. FIG. 11 shows the operation principle of FIG. In this example, the phase relationship B described above is detected, and the phase of the clock signal is controlled so as to satisfy the phase relationship A. That is, the phase relationship B is corrected to the phase relationship A by inverting the clock signal. At present, in the data signal pattern mainly used in the 10 Gb / s optical transmission system, the continuation of 1100 patterns is periodically repeated, but since the number of bits in one repetition is an even number, the phase relationship A If the PLL is locked, the phase relationship B does not occur in subsequent cycles.

  10, the same reference numerals are assigned to the same components as those in FIG. The 1100-pattern continuous input countermeasure circuit 101 newly provided in this example is configured to use the logical sum signal of the synchronization signals (8) and (7) of the EXOR circuits 45 and 46 as the clock signal from the T / 2 delay circuit 54. D-flip / flop 104 latches with an inverted signal. When 1100 patterns are continuously input and the phase relationship is B as shown in FIG. 11A, the latch is performed at this timing as shown by the (x) mark in FIG. All the signals to be processed are low level signals. As a result, as shown in FIG. 11 (d), the output of the low-pass filter 105 in the next stage gradually decreases, and eventually falls below the reference potential of the comparator 106 to invert the output of the T-flip / flop 107 ( (F) of FIG. The EXOR circuit 102 provided in this example outputs an inverted clock signal by exclusive OR of the inverted signal and the clock signal. Due to the inversion of the clock signal, the PLL circuit operating in the phase relationship B in FIG. 7 transitions to the phase relationship A in FIG. Therefore, after that, even if 1100 patterns are continuously input, the normal synchronization state is maintained.

  12 to 19 show specific application examples of the first embodiment of the present invention.

  In FIG. 12, instead of using the EXOR circuit 102 in FIG. 11 in order to change the phase of the clock signal, an adder circuit 108 that directly controls the control voltage applied to the VCO 50 is used. The operation of FIG. 12 will be briefly described with reference to FIG. As shown in FIG. 13E, when 1100 patterns are continuously input and the output of the comparator 106 becomes high level, a slight constant is added to the control terminal of the VCO 50 via the adder circuit 108 in addition to the loop filter output. A voltage is applied ((f) of FIG. 13). Since the oscillation frequency of the VCO 50 is proportional to the control voltage, the frequency slightly shifts by a constant frequency while a constant voltage is applied. Since the output phase of the VCO 50 is proportional to the integral value of the control voltage, it gradually changes while the frequency is shifted. When the phase changes, the phase can be compared with the data signal, and a high level signal is generated in the OR circuit 103. As a result, as shown in FIGS. 13 (g) and 13 (h), the output of the comparator 106 becomes low and the oscillation frequency of the VCO returns to the original, but the phase of the clock signal is shifted by 180 degrees by the PLL. It stabilizes at.

  FIG. 14 shows the high-level pulses of the output signals (7) and (8) of the exclusive OR shown in FIG. 7 that are generated because the signals input to the EXOR circuits 45 and 46 are out of phase. The D-flip / flop 104 of the 1100 pattern continuous input countermeasure circuit 101 is made unnecessary by erasing by aligning the phases with the D-flip / flops 109 and 110 provided in FIG. This operation will be described with reference to the timing chart of FIG. 15. Since the D-flip / flops 109 and 110 latch the synchronization signals (4) and (6) of the previous stage with the clock inversion signal, the output thereof is the synchronization signal (13 ) And (14). Therefore, in the case of the phase delay of FIG. 15A, the synchronization signals (3) and (14) are equal, and therefore the exclusive OR output signal (7) is at a low level. On the other hand, in the case of the phase advance of FIG. 15B, the synchronization signals (13) and (14) are equal, and therefore the exclusive OR output signal (8) is at a low level. As a result, the D-flip / flop 104 provided for sampling the point indicated by the mark (x) in FIG. 7 becomes unnecessary. Further, FIG. 16 is provided with delay circuits 111 and 112 in place of the D-flip / flops 109 and 110 of FIG. Therefore, the operation timing is the same as in FIG.

  FIG. 17 shows a second embodiment according to the present invention. In this example, even in the 1/2 clock extraction method, all changes in the data signal are used for phase comparison. That is, both phase relationships A and B are detected. In FIG. 17, a D-flip / flop 121 is newly added and an inverted signal of the clock signal (5) is input thereto. In FIG. 3, the remaining data of every other bit for which no change in the data signal has been detected. It also detects signal changes. Therefore, EXOR circuits 122 and 123 are added, and an OR for obtaining a logical sum signal of the output signals (10) and (11) and the output signals (8) and (9) of the conventional EXOR circuits 45 and 46 is added. Circuits 124 and 125 are also added. The operation of this example will be described using the timing charts of FIGS. FIG. 18 shows a case where the clock signal is delayed. In addition to the case of FIG. 5 described above, the synchronization signal (7) is generated by the falling edge signal of the clock signal (5).

  Thereafter, the EXOR output signal (10) of the synchronization signals (3) and (7) and the EXOR output signal (11) of the synchronization signals (4) and (7) are respectively obtained. The relationship between the EXOR output signals (10) and (11) is the same as the relationship between the EXOR output signals (8) and (7) ((8) and (9) in this example) in FIG. Level differences occur. Therefore, these OR output signals (12) and (13) also have a similar level difference. Further, even when the clock signal shown in FIG. 19 is advanced, the same level difference as in FIG. 5B is generated in the OR output signals (12) and (13). Therefore, it can be seen that the same phase control as in FIG. 3 is possible with the circuit configuration of FIG. 20 and 21 show timing charts of the phase relationship A and the phase relationship B corresponding to FIGS. 6 and 7, respectively. As is apparent from FIG. 21, it can be seen that in this embodiment, one of them always has the phase relationship A. Accordingly, in both FIGS. 20 and 21, there is a level difference that can be phase controlled in the OR output signals (12) and (13).

  As described above, in the clock extraction circuit using the PLL that extracts the clock signal having a frequency that is 1/2 the bit rate of the data signal, even when 1100 continues in the input signal pattern, the clock extraction circuit of the present invention is used. By using it, a stable PLL operation can be realized. In addition, the use of a 1/2 clock extraction circuit can alleviate the requirement for high-speed characteristics to the device.

  FIG. 22 shows a third embodiment of the present invention. FIG. 23 is a timing chart showing an operation example of points corresponding to symbols in parentheses in FIG. In this embodiment, the optical receiver 30 discriminates the width of the duty of the received data signal and automatically controls the identification phase of the received data.

  22 and 27, each circuit block having 2xx added to the reference symbol is newly added for this example, and other than that, the 1/2 clock extraction method of FIG. The circuit configuration is the same. Hereinafter, the operation will be described focusing on the newly added portion. The received data signal (A) is input to D-flip / flops 51 and 52 constituting two identification circuits, and signals (B) and (C) synchronized with clock rising / falling edge signals from the PLL circuit, respectively. Is generated. The received data signal (A) is also input to the D-flip / flop 53 and the newly added D-flip / flop 203. The clock signal from the PLL circuit passes through the D-flip / flop 53 via a delay circuit 54 that gives a fixed delay of 1/4 clock cycle and variable phase shifters 201 and 202 controlled by the output of a comparator 208 described later. The signal (D) synchronized with the rising edge signal of the clock signal (G) to which the variable phase φ is added is obtained from the D-flip / flop 53, and from the D-flip / flop 203, A signal (I) synchronized with the rising edge signal of the clock signal (H) from which the variable phase φ is subtracted is obtained.

  The EXOR circuits 45 and 46, the low-pass filters 48 and 48 ', and the comparator 47 operate in the same manner as in the conventional example shown in FIGS. 3 and 5. Therefore, the PLL circuit has the rising edge signal of the clock signal (G) as the received data signal (A). It operates to match the switching edge of. Note that the two low-pass filters 48 and 48 ′ are obtained by individually providing the common loop filter 48 in FIG. 3 on each input side of the comparator 47, and there is no difference in the operation of the PLL circuit. On the other hand, the newly added EXOR circuits 204 and 205, the low-pass filters 206 and 207, and the comparator 208 determine the width of the duty of the received data signal (A), and determine the phase of the variable phase shifters 201 and 202 in the next stage. By changing the amount of transition, the identification phase of received data is automatically controlled. Here, the EXOR circuit 204 outputs an exclusive OR output signal (E) of the synchronization signals (B) and (I), and the EXOR circuit 205 outputs an exclusive logic of the synchronization signals (C) and (I). A sum output signal (F) is obtained.

  FIG. 23 shows an example of a timing chart in a state before the variable phase shifters 201 and 202 are controlled by the output of the comparator 208 (φ and −φ = 0). Therefore, when the PLL is synchronized, the falling edge signal of the clock signal (H), which is an inverted signal of the clock signal (G), coincides with the switching edge of the received data signal (A). FIG. 23A shows a case where the PLL is synchronized with a change point of the duty “Narrow” → “Wide” of the received data signal (A). In this case, the average signal level (output of the low-pass filter 206) of the output signal (E), which is an exclusive OR of the synchronization signals (B) and (I), is high, and the synchronization signals (C) and (I) The average signal level of the exclusive OR output signal (F) (the output of the low pass filter 207) is lower than that. On the other hand, FIG. 23B shows a case where the PLL is synchronized with a change point of the duty “wide” → “narrow” of the received data signal (A). In this case, the average signal level (output of the low-pass filter 206) of the output signal (E), which is the exclusive OR of the synchronization signals (B) and (I), is low as opposed to (a) in FIG. The average signal level (output of the low-pass filter 207) of the output signal (F) of the exclusive OR of the synchronization signals (C) and (I) becomes higher. In this way, the difference between the two average signal levels is detected by the comparator 208 in the next stage, so that the PLL has a duty “narrow” → “wide” or “wide” → “narrow” of the received data signal (A). It can be determined which of the change points is synchronized.

  FIG. 24 shows the operation of the present invention of the clock signals (G) and (H) by the variable phase shifters 201 and 202 when synchronized with the changing point of duty “narrow” → “wide” shown in FIG. An example is shown. In the initial state of (i), φ and −φ = 0 as in FIG. 23A, so that the inverted signal of the clock signal (G) becomes the clock signal (H) as it is. In this case, as described in (a) of FIG. 23, the average signal level of the exclusive OR signal (E)> the average signal level of the exclusive OR signal (F), and the comparator 208 in (ii). As shown in the figure, the variable phase shifter 201 is controlled to generate the clock signal (G ′) in which the phase amount Φ is decreased (T / 2−Φ) from the duty “narrow”, and the variable phase shifter 202 is controlled on the contrary. Then, the clock signal (H ′) is generated by adding the phase amount Φ to the duty “wide” (T / 2 + Φ). As a result, since the PLL controls to resynchronize the clock signal (G ′) as shown in (iii), the data identification signals (sampling signals) before and after the resynchronized clock signal (G ″) are respectively Shifted to the center of “narrow” and “wide” data bit widths.

  As described above, the clock signal (G) and (G) input to the D-flip / flops 53 and 203 by the output signal of the comparator 208 corresponding to the duty “narrow” → “wide” or “wide” → “narrow”. H) transits in the opposite direction, and the clock signal (G) is resynchronized by the PLL, whereby the data identification phase is automatically and optimally controlled. This operation is repeated until the output of the comparator 208 is inverted, and finally the discrimination phase is controlled to the center of the received waveform with a shifted duty. The same applies when the duty of the initial phase is synchronized between “wide” and “narrow”. However, the relationship of adjustment of the phase amount Φ by the variable phase shifter 201 is opposite to the above.

  25 and 26 show specific application examples of the third embodiment of FIG. In FIG. 25, one duty adjustment circuit 209 is used in place of the two variable phase shifters 201 and 202 in FIG. FIG. 26 shows an example of the configuration of the duty adjustment circuit 209. Here, the DC bias of the clock signal is simply varied by the output signal of the comparator 208. Since the input logic determination threshold value on the D-flip / flops 53 and 203 side is constant, the duty of the clock signal is varied by changing the DC bias. As shown in FIG. 25, the clock signal (G) of the D-flip / flop 53 and the inverted clock signal (H) of the D-flip / flop 203 are in an opposite phase relationship while the clock signal with the DC bias simply changed is kept as it is ( (φ and -φ).

  27 to 33 show a fourth embodiment of the present invention. FIG. 27 is a timing chart showing the basic configuration of the fourth embodiment of the present invention, and FIG. 28 is a timing chart showing an operation example of points corresponding to symbols in parentheses in FIG. FIG. 29 and subsequent figures show specific application examples. In this embodiment, the optical receiver 30 determines the width of the duty and matches the initial phase setting.

  As shown in FIG. 27, the basic configuration of this embodiment is the same as that of FIG. That is, the D-flip / flop 203, the EXOR circuits 204 and 205, the low-pass filters 206 and 207, and the comparator 208 determine whether the duty of the received data signal (A) is wide or narrow. However, in this example, the identification phase of the received data is not automatically controlled by this, and as a simple measure, one of the duty between “wide” → “narrow” or “narrow” → “wide” is initially set. Set the initial phase as the phase. The initial adjustment information is given as a reference potential for the newly provided comparator 210. Accordingly, for example, when the initial phase setting is between “wide” and “narrow”, the comparator 210 is set when the PLL is locked between “wide” and “narrow” which is the same as the initial phase setting by turning on the power of the optical receiver 30 or the like. The output of the comparator 210 is kept at a low level, and when the PLL is locked between “narrow” and “wide” different from the initial phase setting, the output of the comparator 210 becomes high level. This level signal controls the inverter 212 via the switch 211 and inverts the clock signal from the VCO 50 when locked between “wide” and “narrow” different from the initial phase setting. As a result, the PLL locks between “wide” and “narrow”, which is the same as the initial phase setting. Since the above operation only needs to be performed once after the phase synchronization is established, an operation switch 211 by manual operation or program control is provided in this example, and the switch is turned on only once after synchronization is detected. FIG. 28 shows the case where the initial phase setting is between “wide” and “narrow”, and FIG. 28A shows that the initial phase is locked between “narrow” and “wide” which is different from the initial phase setting. FIG. 28B shows the case where the inverter 212 is enabled by the output of the comparator 210 to invert the clock signal, and as a result, the same phase as the initial phase setting is locked between “wide” and “narrow”. The case where it was made to show is shown.

  29 to 31 show three examples of the adjustment configuration of the initial phase. In either case, adjustment is performed in a state where the rising edge of the clock delayed by T / 2 is always kept in synchronization with the switching edge of the received data signal (A) based on the conventional configuration of FIG. In FIG. 29, the phase shifter 213 is given only to the clock signal of the D-flip / flop 52 so that the identification phase of the clock signal for identifying the data signal and the identification phase of the inverted clock signal can be adjusted independently and strictly. The phase of the output signals (B) and (C) between the D-flip / flops 52 and 51 is adjusted by another variable delay circuit 54 '. FIG. 30 shows a configuration in which the identification phase between the clock signal for identifying the data signal and its inverted clock signal is varied using the duty adjustment circuit 214 similar to that described above with reference to FIGS. ing. FIG. 31 shows a configuration for obtaining the same effect as in FIG. 29 by providing the variable phase shifter 215 only on the input side of the received data signal (A) of the D-flip / flop 52. FIG. 32A shows an example of the timing chart of FIGS. 29 and 30, and FIG. 32B shows an example of the timing chart of FIG. By combining these initial adjustments with the fourth embodiment of FIG. 27, it is possible to easily cope with the duty of the received data signal between “wide” → “narrow” or “narrow” → “wide”.

  FIG. 33 shows a fifth embodiment of the present invention. Here, a duty compensation circuit 221 or 222 for compensating the duty of the clock waveform is provided on the optical transmitter 10 side in the 2: 1 multiplexing circuit of FIG. 8 described above. As a result, it is possible to eliminate a duty shift every other bit of the transmission waveform itself. 34 and 39 show specific circuit configuration examples of the duty compensation circuit 221 or 222. FIG. In FIG. 34, a simple RC average value detection circuit 224 detects the average value of the transmission data signal to vary the DC bias, thereby compensating the duty of the transmission waveform. In FIG. 35, the duty of the clock signal is compensated by using a simple band-pass filter 226 and a DC cut capacitive coupling 227.

  As described above, according to the present invention, by using the clock extraction circuit of the present invention, a higher-speed optical receiver circuit can be realized at an early stage without requiring improvement of the high-speed characteristics of the device. Further, according to the present invention, it is possible to suppress the error rate deterioration due to the discriminating phase shift caused by the shift of the duty every other bit which occurs in the configuration in which the optical transmitter is not subjected to the waveform shaping by the data transmission rate clock.

Claims (4)

A PLL circuit including a phase comparison circuit that performs phase comparison between a data signal of a bit rate B (bit / s) and a clock signal of B / 2 (Hz) at intervals of 2 / B (sec);
A duty determination circuit for determining a duty between input data before and after the point where the PLL circuit is synchronized;
A control circuit for controlling a phase for data identification with respect to the data signal before and after the PLL circuit is synchronized based on the determination result;
A circuit for dealing with duty deviation of an optical receiver, characterized by comprising: The control circuit has an initial phase setting circuit in which duty information at the time of initial phase adjustment is set,
The initial phase setting circuit compares the duty information at the time of initial phase adjustment with the output of the duty determination circuit, and maintains the state if the phase is synchronized in the same state as the duty information at the time of initial phase adjustment. The circuit according to claim 1, wherein the clock output of the voltage controlled oscillator of the PLL circuit is inverted if the phase is synchronized in a state different from the duty information at the time of phase adjustment. The PLL circuit discriminates input data every other bit using a clock signal of 1/2 frequency of the data transmission rate and its inverted clock signal, and delays the phase of the data signal by 1/2 cycle. In accordance with the result of comparing the average value of the exclusive OR of the data identified by the above and the data identified by the clock signal and the inverted clock signal, phase synchronization,
The duty determination circuit is configured to perform an exclusive OR of data identified by an inverted clock signal of a clock signal obtained by delaying a half cycle phase of the data signal and data identified by the clock signal and the inverted clock signal. Based on the result of comparing the average values, the duty between input data before and after the point where the PLL circuit is synchronized is determined as “narrow” → “wide” or “wide” → “narrow”
The circuit according to claim 1, wherein the control circuit controls the clock signal obtained by delaying the phase of a half cycle of the data signal and the phase of the inverted clock signal in opposite directions based on the determination result.   By independently adjusting the phase of the clock signal obtained by delaying the phase of the half cycle of the data signal and the phase of the clock signal, the identification phase of the clock signal for identifying the data signal and the inverted phase of the inverted clock signal can be independently set. 4. The circuit of claim 3, wherein the circuit is adjusted.

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