JP2006253808A - Optimum phase identification circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optimum phase identification circuit capable of optimizing the phase relation between a data signal and a clock signal, independently of the variations in the duty factor of the data signal received. <P>SOLUTION: The optimum phase identifying circuit, for extracting the clock signal from the received data signal and optimizing the phase relation between the data signal and the clock signal in the case of identifying and recovering the data through the use of the clock signal, is provided with a branching means 2 for branching the received data signal; a clock extracting means 3 for extracting the clock signal from the data signals, branched and outputted from the branch means 2; a duty detection means for detecting the duty factor of the data signals branched and outputted from the branch means 2; a phase adjustment means 5 for receiving an output of the clock extract means 3 and an output of the duty detection means 4 so as to control the phase of the clock signal, in accordance with the output signal of the duty detection means 4; and a D-type flip-flop 6 for receiving the output of the branch means 2 and the output of the phase adjustment means 5 to identify the data signal received. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an optimum phase identification circuit that optimizes the phase relationship between a data signal and a clock signal when a clock signal is extracted from a received data signal and data is identified and reproduced using the clock signal.

  In an identification circuit in the optical receiver of the optical communication system, the data signal is converted into a binary digital signal of 0 or 1. When converting to such a digital signal, a clock signal obtained by extracting from the received data signal is required, and the timing of the clock signal is optimally set to a phase that minimizes the bit error rate of the data signal. The Normally, the eye pattern of the data signal input to the identification circuit becomes narrow due to the influence of nonlinear effects caused by transmission through the optical fiber, and therefore there is no sufficient margin for the timing of the clock signal. In addition, in order to respond to the increase in communication volume due to the rapid increase in Internet demand in recent years, technological development for increasing the speed of data signals such as 10 Gbit / sec or 40 Gbit / sec is progressing. Timing margin is reduced.

  In recent years, a PLL has been adopted as a clock extraction means in order to realize miniaturization and power saving of an optical receiver. Since the frequency characteristics of each device constituting the optical transceiver changes slightly with changes in ambient temperature and power supply voltage, the duty of the data signal input to the clock extraction means changes. When the PLL is used as the clock extraction means, there is a problem that the phase relationship between the data signal and the clock signal changes with the change in the duty of the data signal, and as a result, the identification phase shifts from the optimum value.

  Therefore, there is known a timing extraction circuit that optimally controls the phase relationship between the data signal and the clock signal even when the duty of the data signal varies (see, for example, Patent Document 1). The timing extraction circuit includes a phase detection circuit that detects a duty variation of the data signal, and a clock signal generation unit that generates a clock signal that can optimally control the phase relationship with the data signal even when the duty of the data signal varies. The phase detection circuit includes an edge detection circuit that detects the rising and falling edges of the data signal and outputs an edge signal, and a D-type flip-flop that compares the phase of the output and the clock signal. . Thus, the phase of the clock signal becomes the center of the data signal regardless of the duty of the data signal, and the phase relationship between the data signal and the clock signal is optimally controlled.

Japanese Patent Laid-Open No. 11-122232 (FIG. 14)

  By the way, the conventional edge detection circuit constitutes a phase comparator together with a D-type flip-flop in the PLL that is a timing extraction circuit, and a delay circuit that delays the data signal for a predetermined time, exclusive of the data signal and the output signal of the delay circuit This is an EXOR circuit that generates an edge signal having a pulse at the rise and fall of a data signal by performing a logical OR operation. Therefore, the conventional edge detection circuit has a problem that a high-speed operation higher than the data signal speed is required. Similarly, the conventional edge detection circuit has a problem that a higher speed operation is required when the data signal modulation method is RZ (Return to Zero). Further, there is a problem that phase comparison in the conventional edge detection circuit is not performed correctly due to insufficient operating band of the EXOR circuit, and PLL feedback control becomes unstable.

  The present invention has been made to solve the above problems, and to obtain an optimum phase identification circuit capable of optimizing the phase relationship between a data signal and a clock signal without depending on the duty fluctuation of the received data signal. With the goal.

  An optimum phase identification circuit according to the present invention is an optimum phase identification circuit for extracting a clock signal from a received data signal and optimizing the phase relationship between the data signal and the clock signal when identifying and reproducing data using the clock signal. A branching unit for branching the received data signal; a clock extracting unit for extracting a clock signal from the data signal branched and output from the branching unit; and a duty detection for detecting the duty of the data signal branched and output from the branching unit A phase adjusting means for receiving the output of the clock extracting means and the output of the duty detecting circuit as input and controlling the phase of the clock signal in accordance with the output signal of the duty detecting means; the output of the branching means and the phase adjusting means The D-type flip-flow is used to identify the received data signal. Characterized in that a flop.

  According to the present invention, the data at the input of the D-type flip-flop can be obtained without using a circuit that operates at a speed higher than the speed of the received data signal inside the PLL constituting the clock extraction means, and without depending on the duty fluctuation of the received data signal. An identification circuit that stably optimizes the phase relationship between the signal and the extracted clock signal can be obtained.

Embodiments of the present invention will be described below with reference to the drawings.
Embodiment 1 FIG.
The optimum phase identification circuit according to the first embodiment of the present invention is an identification circuit that extracts a clock signal by using a PLL from a received data signal without using a circuit that operates at a speed higher than the speed of the data signal inside the PLL. By simply detecting the duty fluctuation of the received data signal as an analog signal and controlling the phase of the extracted clock signal by the phase adjusting means according to the detected signal, the data signal at the input of the D-type flip-flop as the discriminator The phase relation of the clock signal is optimized.

  FIG. 1 is a block diagram showing a configuration of an optimum phase identification circuit according to Embodiment 1 of the present invention. The optimum phase identification circuit according to the first embodiment shown in FIG. 1 receives a received data signal from a data input terminal 1, and branches from a branching means 2 that branches into three, and a data signal that is branched and output via the branching means 2. The clock signal is extracted by the clock extraction unit 3 that extracts a clock signal, for example, a PLL, the duty detection unit 4 that detects the duty of the data signal branched and output through the branch unit 2 as an analog signal, and the clock extraction unit 3 The phase adjustment means 5 for controlling the phase of the clock signal according to the output signal of the duty detection means 4, and the data signal branched and output via the branching means 2 is 0 or 1 2 depending on the clock signal output from the phase adjustment means 5 A D-type flip-flop (hereinafter referred to as D-FF) 6 for converting the digital signal into a value is provided.

  Next, the operation will be described. A data signal inputted from the data input terminal 1 is inputted to the branching means 2 and outputted to the clock extracting means 3, the duty detecting means 4 and the D-FF 6. Note that a buffer having a fanout number of 3 may be used as an alternative to the branching means 2.

  Here, FIG. 2 is a block diagram showing a configuration of a PLL (Phase Locked Loop) which is an example of the clock extracting means 3. The PLL that is the clock extracting means 3 corresponds to a phase comparator 10 that performs phase comparison between the data signal and the output clock signal of the VCO 12, and an output signal of the phase comparator 10 that is a phase advance or delay between the two signals. A low-pass filter (hereinafter referred to as LPF) 11 that passes and outputs only a low-frequency component included in the signal to be output, and the output of the LPF 11 is input as a control voltage and oscillates at a frequency corresponding to the control voltage. A voltage controlled oscillator (hereinafter referred to as a VCO) 12 is provided. The VCO 12 oscillates at a frequency corresponding to the control voltage and is branched into two branches, one being input to the phase comparator 10 and the other being input to the phase adjusting means 5. Is done. Thus, the feedback control of the PLL continues until the control voltage of the VCO 12 becomes constant.

  When the rising change point of the extracted clock signal, which is the output of the PLL, is synchronized with the change point of the data signal and the D-FF 6 operates at the rising change point of the clock signal, phase adjustment is performed between the PLL output and the D-FF 6. A variable phase shifter as an example of the means 5 is required. As the variable phase shifter, an electric type or a varicap type can be considered. The phase amount in the variable phase shifter is 180 ° when the data signal has an ideal NRZ (Non Return to Zero) waveform, and 90 ° when the data signal has an ideal RZ waveform. This situation is shown in the timing chart of FIG.

  That is, FIG. 3 is a timing chart showing an operation at a fixed delay of a variable phase shifter that is an example of the phase adjusting means 5, and the phase of the received data signal and the extracted clock signal when the NRZ format 0/1 alternating pattern is in phase. An extracted clock signal that is 180 ° shifted and an extracted clock signal that is 90 ° out of phase with the extracted clock signal when the received data signal is a 0/1 alternating pattern in the RZ format are shown.

  Since the phase of the extracted clock signal, which is the output of the PLL, is synchronized with the change point of the data signal, when the phase amount of the variable phase shifter is fixed, if the duty of the data signal changes, the clock at the input of the D-FF 6 The phase of the signal deviates from the optimum value. FIG. 4 is a timing chart showing the phase relationship between the received data signal and the extracted clock signal in the D-FF 6 when a 0/1 alternating pattern in the NRZ format is input to the D-FF 6 as a received data signal. FIG. 4 shows that the optimum phase is set when the duty is 100%, but deviates from the optimum phase when the duty varies from 100%. Therefore, the duty variation of the data signal is detected by the duty detection means 4, and the phase of the clock signal extracted by the PLL is controlled by the variable phase shifter according to the detected signal, so that the data signal at the input of the D-FF 6 It is necessary to optimize the phase relationship of the clock signal.

  FIG. 5 is a block diagram showing the configuration of the duty detection means 4. That is, as shown in FIG. 5, the duty detection means 4 includes a peak detection circuit 7 for detecting a peak value of the received data signal waveform, an average circuit 8 for detecting the area of the received data signal waveform, and the peak detection. A CPU 9 is provided as a calculation means for calculating the ratio between the output signal of the circuit 7 and the output signal of the average circuit 8.

  FIG. 6 is an operation principle diagram of the duty detection means 4. FIG. 6 shows a case where the output signal of the peak detection circuit 7 is constant regardless of the duty fluctuation of the received data signal waveform. In this case, when the duty of the received data signal waveform is reduced, the output signal of the average circuit 8 is reduced and the output value of the CPU 9 is also reduced. Further, when the duty of the received data signal waveform is increased, the output signal of the average circuit 8 is increased and the output value of the CPU 9 is also increased.

  In the duty detection means 4, a diode which is a passive component is generally used as the peak detection circuit 7, and the speed required for the diode is equivalent to the speed of the data signal. Further, as the average circuit 8, a charge pump circuit composed of a capacitor which is a passive component is known, and a signal required for the charge pump circuit is equal to the speed of the data signal. Therefore, according to the present invention, the duty fluctuation of the data signal can be easily detected by using a passive component that operates at the same speed as the data signal.

  The variable phase shifter, which is an example of the phase adjusting means 5, controls the phase of the clock signal extracted by the PLL according to the output signal of the duty detection circuit 4 and optimizes the phase relationship between the data signal and the clock signal at the input of the D-FF 6. Can be made.

  As described above, the optimum phase identification circuit according to the first embodiment of the present invention uses the PLL as the clock extraction unit 3 to extract the clock signal from the received data signal. By simply detecting the duty fluctuation of the received data signal as an analog signal without using a circuit that operates at a speed higher than the speed, and controlling the phase of the clock signal extracted by the PLL according to the detected signal with a variable phase shifter, D -Stable optimization of the phase relationship between the data signal and the clock signal at the input of the FF 6 is possible.

Embodiment 2. FIG.
The optimum phase identification circuit according to the second embodiment of the present invention is an identification circuit that extracts a clock signal by using a PLL from a received data signal, without using a circuit that operates at a speed higher than the speed of the data signal inside the PLL. The phase relationship between the data signal and the clock signal at the input of the D-FF can be easily detected as a digital signal, and the phase of the extracted clock signal is controlled by a variable phase shifter according to the detected signal. Optimization.

  FIG. 7 is a block diagram showing the configuration of the optimum phase identification circuit according to Embodiment 2 of the present invention, which is the same configuration as that of Embodiment 1 shown in FIG. The difference from FIG. 1 is the duty detection means. The duty detection means 4 in FIG. 1 detects the duty detection as an analog signal, but the duty detection means 16 in FIG. 7 detects it as a digital signal.

  FIG. 8 is a block diagram showing a configuration of duty detection means 16 according to Embodiment 2 of the present invention. The duty detection unit 16 shown in FIG. 8 is based on an edge detection circuit 13 that detects rising and falling change points of a received data signal, and a time between the change points based on a high-speed clock output from the high-speed clock source 15. Counter circuit 14 for counting the output, a high-speed clock source 15 for outputting a high-speed clock, and a CPU 9 as an arithmetic means for detecting a duty fluctuation from a change in the number of counts using the output of counter circuit 15 as an input.

  Next, the operation of the duty detection means 16 when the received data signal is a 0/1 alternating pattern in the NRZ format will be described with reference to FIG. The counter circuit 14 determines the number of high-speed clocks output from the high-speed clock source 15 sufficiently earlier than the received data signal between the rising change point and the falling change point of the data signal that is the output of the edge detection circuit 13. By counting, the duty of the data signal is detected. The CPU 9 receives the output of the counter circuit 15 as an input and detects the duty fluctuation from the change in the count number. For example, in FIG. 9, when the duty is 100% (duty = 100%), the count number of the high-speed clock is 9. When the duty is smaller than 100% (duty <100%), the count number of the high-speed clock is 7, and the CPU 9 advances the phase of the clock signal by one cycle of the high-speed clock using a variable phase shifter. When the duty is larger than 100% (duty> 100%), the count number of the high-speed clock is 11, and the CPU 9 delays the phase of the clock signal by one cycle of the high-speed clock using a variable phase shifter. As described above, the output signal of the CPU 9 is optimally maintained in a stable state by controlling the variable phase shifter which is an example of the phase adjusting unit 5.

  In the second embodiment, since the duty fluctuation of the received data signal is detected digitally, there is an advantage that the signal processing in the CPU 9 is easy.

  As described above, according to the optimum phase identification circuit according to the second embodiment of the present invention, in the identification circuit that extracts the clock signal from the data signal by applying the PLL, a circuit that operates at a speed higher than the speed of the data signal is provided inside the PLL. The data signal at the input of the D-FF 6 is detected by simply detecting the duty fluctuation of the data signal received without using it as a digital signal and controlling the phase of the clock signal extracted by the PLL according to the detected signal with a variable phase shifter. It is possible to optimize the phase relationship between the clock signal and the clock signal stably. The duty detection circuit 16 has a clock sufficiently faster than the data signal, but since it is outside the PLL, the PLL feedback control is performed stably.

Embodiment 3 FIG.
The optimum phase identification circuit according to the third embodiment of the present invention is received without using a circuit that operates at a speed higher than the speed of the data signal in the PLL in the identification circuit that extracts the clock signal from the data signal by applying the PLL. By simply detecting the duty variation of the data signal as an analog signal, and adding an offset signal to the VCO control voltage, the phase of the clock signal extracted by the PLL according to the detection signal, at the input of the D-FF (identifier) This optimizes the phase relationship between the data signal and the clock signal stably.

  FIG. 10 is a block diagram showing the configuration of the optimum phase identification circuit according to the third embodiment of the present invention. The configuration is the same as that of FIG. 1 except for the connection destination of the output signal of the duty detection circuit 4. FIG. 11 is a block diagram showing the configuration of the PLL according to Embodiment 3 of the present invention.

  Next, the operation will be described. The operation of the duty detection circuit 4 is the same as that of the first embodiment, but the controlled object is different, and is the VCO 12 in FIG. In FIG. 11, the phase of the clock signal extracted by the PLL is controlled by adding an offset signal to the VCO control voltage and changing the lock point of the phase comparator 10.

  The third embodiment has an advantage that the phase variable amount required for the variable phase shifter which is an example of the phase adjusting means 5 can be reduced.

  Thus, according to the optimum phase identification circuit according to the third embodiment of the present invention, in the identification circuit that extracts the clock signal from the data signal by application of the PLL, a circuit that operates at a speed higher than the speed of the data signal is provided inside the PLL. By simply detecting the duty fluctuation of the received data signal as an analog signal without using it, and adding the offset signal to the VCO control voltage with the phase of the clock signal extracted by the PLL according to the detected signal, the input of the D-FF 6 It is possible to stably optimize the phase relationship between the data signal and the clock signal.

Embodiment 4 FIG.
The optimum phase identification circuit according to the fourth embodiment of the present invention is an identification circuit that extracts a clock signal by using a PLL from a received data signal without using a circuit that operates at a speed higher than the speed of the data signal in the PLL. The D-FF (discriminator) can easily detect the duty fluctuation of the received data signal as a digital signal and add an offset signal to the VCO control voltage based on the phase of the clock signal extracted by the PLL. The phase relationship between the data signal and the clock signal at the input is stably optimized.

  FIG. 12 is a block diagram showing a configuration of an optimum phase identification circuit according to the fourth embodiment of the present invention. In the third embodiment shown in FIG. 10, the duty detection circuit of the duty detection circuit 4 shown in FIG. In contrast to the configuration, the fourth embodiment is different in the configuration of the duty detection circuit 16 shown in FIG. 8, and the other configurations are the same.

  The fourth embodiment has an advantage that the signal processing in the CPU 9 is easy because the detection of the duty fluctuation of the received data signal is performed digitally. Further, there is an advantage that the phase variable amount required for the variable phase shifter 5 can be reduced.

  Thus, according to the optimum phase identification circuit according to the fourth embodiment of the present invention, in the identification circuit that extracts the clock signal from the data signal by applying the PLL, a circuit that operates at a speed higher than the speed of the data signal is provided inside the PLL. By simply detecting the duty fluctuation of the received data signal as a digital signal without using it, and adding the offset signal to the VCO control voltage with the phase of the clock signal extracted by the PLL according to the detected signal, the input of the D-FF 6 It is possible to stably optimize the phase relationship between the data signal and the clock signal. The duty detection circuit 16 has a clock sufficiently faster than the data signal, but since it is outside the PLL, the feedback control of the PLL is performed stably.

Embodiment 5. FIG.
The optimum phase identification circuit according to the fifth embodiment of the present invention is an identification circuit having two PLLs that lock at the rising change point and the falling change point of the received data signal, and adds the output signals of the two PLLs. In the case where the duty of the received data signal is changed by amplifying the output signal of the adding means by the amplifying means and inputting it to the D-FF (identifier) as a clock signal, the duty detecting means is Without use, the phase relationship between the data signal and the clock signal at the input of the D-FF (discriminator) is stably optimized.

  FIG. 13 is a block diagram showing a configuration of an optimum phase identification circuit according to Embodiment 5 of the present invention. The optimum phase identification circuit according to the fifth embodiment shown in FIG. 13 includes a branching unit 2 similar to those in the first to fourth embodiments and a D-FF 6, and corrects the data signal branched and output from the branching unit 2. The buffer means 17 for outputting the phase output and the negative phase output signal, and the clock signal is extracted from the normal phase output and the negative phase output signal of the data signal via the buffer means 17, for example, the PLL shown in FIG. Two clock extracting means 3 composed of PLLs that lock at the rising change point and falling change point of the signal, an adding means 18 for adding the output signals of the two clock extracting means 3, and an output signal of the adding means 18 as inputs. The D-FF 6 receives the received data signal from the binary signal of 0 or 1 according to the clock signal that is the output of the amplifier 19. Into a barrel signals.

  Next, the operation of the fifth embodiment of the present invention when the received data signal is in the NRZ format 0/1 alternating pattern will be described with reference to FIG. The phase of the clock signal obtained by adding the output signals of the two PLLs using the adding means 18 is always in the middle of the data signal waveform.

  In the fifth embodiment, when the duty of the received data signal changes, the phase relationship between the data signal and the clock signal at the input of the D-FF (identifier) is optimized without using the duty detection means. There is an advantage that it can be stabilized.

  Thus, according to the optimum phase identification circuit according to the fifth embodiment of the present invention, the identification circuit having two PLLs (clock extraction means 3) that locks at the rising change point and the falling change point of the received data signal. 2, the output signals of the two PLLs are added by the adding means 18, the output signal of the adding means 18 is amplified by the amplifying means 19, and then input to the D-FF 6 as a clock signal. When the duty changes, the phase relationship between the data signal and the clock signal at the input of the D-FF 6 can be optimized without using the duty detection means.

It is a block diagram which shows the structure of the optimal phase identification circuit based on Embodiment 1 of this invention. It is a block diagram which shows the structure of PLL in Embodiment 1 and 3 of this invention. 6 is a timing chart showing an operation at the time of a fixed delay of a variable phase shifter that is an example of a phase adjusting unit 5; It is the timing chart which showed the phase of the clock signal accompanying the duty change of the received data signal in the input of D-FF6. It is a block diagram which shows the structure of the duty detection circuit in Embodiment 1 and 3 of this invention. It is an operation principle diagram of the duty detection circuit in the first and third embodiments of the present invention. It is a block diagram which shows the structure of the optimal phase identification circuit based on Embodiment 2 of this invention. It is a block diagram which shows the structure of the duty detection circuit in Embodiment 2 and 4 of this invention. It is an operation principle diagram of the duty detection circuit in the second and fourth embodiments of the present invention. It is a block diagram which shows the structure of the optimal phase identification circuit based on Embodiment 3 of this invention. It is a block diagram which shows the structure of PLL in Embodiment 2 and 4 of this invention. It is a block diagram which shows the structure of the optimal phase identification circuit based on Embodiment 4 of this invention. It is a block diagram which shows the structure of the optimal phase identification circuit based on Embodiment 5 of this invention. It is an operation | movement principle figure of Embodiment 5 of this invention.

Explanation of symbols

  1 data input terminal, 2 branching means, 3 clock extracting means, 4 duty detecting means, 5 phase adjusting means, 6 D-FF, 7 peak detecting circuit, 8 average circuit, 9 CPU, 10 phase comparator, 11 LPF, 12 VCO, 13 edge detection circuit, 14 counter circuit, 15 high-speed clock source, 16 duty detection means, 17 buffer means, 18 addition means, 19 amplification means.

Claims (7)

In the optimum phase identification circuit that optimizes the phase relationship between the data signal and the clock signal when extracting the clock signal from the received data signal and identifying and reproducing the data using the clock signal,
Branching means for branching the received data signal;
Clock extraction means for extracting a clock signal from the data signal branched and output from the branch means;
Duty detection means for detecting the duty of the data signal branched from the branch means;
A phase adjusting unit that receives the output of the clock extraction unit and the output of the duty detection circuit as input, and controls the phase of the clock signal according to the output signal of the duty detection unit;
An optimum phase identification circuit comprising: a D-type flip-flop that receives the output of the branching unit and the output of the phase adjustment unit as inputs and identifies a received data signal. The optimum phase identification circuit according to claim 1,
An optimum phase identification circuit using a PLL as the clock extracting means. The optimum phase identification circuit according to claim 1 or 2,
The duty detection means includes a peak detection means for detecting a peak value of the waveform of the received data signal, an average means for detecting an area of the waveform of the received data signal, an output signal of the peak detection means, and an average of the average means An optimum phase identification circuit comprising: an arithmetic means for calculating an output signal ratio. The optimum phase identification circuit according to claim 1 or 2,
The duty detection means includes an edge detection means for detecting rising and falling change points of the received data signal, a high-speed clock source for outputting a high-speed clock, an output of the edge detection means, and an output of the high-speed clock source. And a counter means for counting the time between data change points, and an arithmetic means for detecting a duty fluctuation from a change in the number of counts using the output of the counter means as an input. Identification circuit. The optimum phase identification circuit according to any one of claims 1 to 4,
The optimum phase identification circuit, wherein the phase adjusting means is a variable phase shifter that controls the phase of the extracted clock signal output from the clock extracting means. In the optimum phase identification circuit according to claim 5,
The phase adjusting means controls the phase of the extracted clock signal output from the clock extracting means by adding an offset signal to a control voltage of a VCO (Voltage Controlled Oscillator) constituting the PLL. Identification circuit. In the optimum phase identification circuit that optimizes the phase relationship between the data signal and the clock signal when extracting the clock signal from the received data signal and identifying and reproducing the data using the clock signal,
Branching means for branching the received data signal;
Buffer means for outputting a normal phase output and a reverse phase output signal of the data signal branched and output from the branch means;
Two clock extraction means for extracting a clock signal from the normal phase output and the reverse phase output signal of the data signal via the buffer means;
Adding means for adding the output signals of the two clock extracting means;
Amplifying means for amplifying the output signal of the adding means;
An optimum phase identification circuit comprising: a D-type flip-flop that receives the output of the branching unit and the output of the amplifying unit as input and identifies a received data signal.

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