JP3522673B2 - Clock recovery circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit for extracting a clock from a serial data signal, and more particularly to a clock recovery circuit for realizing an optical receiver excellent in jitter tolerance.

[0002]

2. Description of the Related Art FIG. 8 is a diagram showing an example of a conventional clock recovery circuit (reference: CRHogge, JR., "A Se1f Corr").
ecting Clock Recovery Circuit ", Jounal of Lightwave
Tech., Vo1, LT-3, No.6,1985, p1323). The conventional clock recovery circuit is composed of a linear phase comparator 2, a loop filter 3, and a voltage controlled oscillator (hereinafter abbreviated as VCO) 4. The "linear" of the linear phase comparator 2 will be referred to as such in order to be clearly distinguished from the "discrete" type phase comparator. The "linear" type phase comparator has the function of outputting a signal containing a DC voltage component proportional to the phase difference, whereas the "discrete" type phase comparator determines the phase shift direction and detects the shift direction. It has the function of outputting only (lead / lag). Generally, a clock recovery circuit using a linear phase comparator is widely used because it has a better jitter characteristic than a clock recovery circuit using a discrete phase comparator.

Many configurations have been proposed for the linear phase comparator 2, but the configuration shown in FIG. 8 is the most widely known. That is, the input data Din is transferred to D via the data input terminal 1.
Type flip-flop (hereinafter abbreviated as D-FF) 9 is input. Further, the output signal of the VCO 4 passes through the buffer 6 and triggers the D-FF 9. As a result, a signal obtained by retiming the input data Din with the clock CLK appears at the output of the D-FF 9. An exclusive OR gate (hereinafter referred to as EXOR) between Din and the retimed signal.
(Abbreviated as) 13 input. With this EX
The OR 13 outputs a signal (phase pulse signal 15) having a pulse width proportional to the phase difference between Din and CLK.

On the other hand, the signal retimed by the D-FF 9 is also input to the D-FF 10 and re-timed again by the inverted output of the buffer 6. D-FF
The output of 9 and the output of D-FF10 are connected to the input of EXOR14. Since the two signals input to the EXOR 14 are both retimed by the output of the VCO 4, the pulse width of the output of the EXOR 14 becomes constant regardless of the phase difference between Din and CLK. This pulse width is EX
Since the pulse width of the output of the OR 13 is fixed to an intermediate value in the range of changing values, the output signal of the EXOR 14 can be used as the reference signal of the phase pulse signal 15 (reference pulse signal 16). The adder 19 calculates and outputs the difference between the phase pulse signal 15 and the reference pulse signal 16,
This signal is the phase comparison output of the linear phase comparator 2.

If re-timed data is required, the output of D-FF 9 or D-FF 10 may be used. In FIG. 8, the output of the D-FF 10 is connected to the data output terminal 34 and sent to the outside.

The phase comparison output 17 of the linear phase comparator 2 is band-limited by passing through the loop filter 3 and then sent to the VCO 4. The output of the VCO 4 is connected to the clock output terminal 5 and, at the same time, is returned to the linear phase comparator 2 so that phase synchronization is established between Din and CLK.

FIG. 9 is a waveform diagram showing the operation of the conventional clock recovery circuit. The Din signal (a) given to the input terminal 1 is retiming (c) by the CLK signal (b).
Then the Din signal (a) and the retimed signal (c)
A phase pulse signal (f) is obtained from Further, the reference pulse signal (g) is obtained by further retiming the retimed signal (c) with the inverted CLK signal (d). The difference (h) between the phase pulse signal (f) and the reference pulse signal (g) becomes the phase comparison output of the linear phase comparator 2.

In FIG. 9 (I), the phase of the CLK signal is Din.
This is the operation when the vehicle is ahead of the signal. The pulse width of the phase pulse signal (f) is shorter than the pulse width of the reference pulse signal (g), and the DC component of the phase comparison output 17 is negative. FIG. 9 (III) shows the operation when the phase of the CLK signal is delayed with respect to the Din signal. The pulse width of the phase pulse signal (f) is longer than the pulse width of the reference pulse signal (g), and the DC component of the phase comparison output 17 is positive. FIG. 9 (II) shows the operation when the phase relationship between the CLK signal and the Din signal is optimum. The optimum phase relationship is D-FF9
This is because the phase relationship is such that the center of the Din signal is punched out at the rising edge of the CLK signal, and the phase relationship has the largest phase margin for the D-FF 9. This phase relationship is defined as zero phase difference.
In this case, the pulse width of the phase pulse signal (f) matches the pulse width of the reference pulse signal (g), and the DC component of the phase comparison output 17 becomes zero.

The output of the phase comparison output 17 is passed through the loop filter 3 to cut unnecessary harmonic components, and then V
It is input to CO4 and controls its oscillation frequency. VCO
The output of 4 is returned to the linear phase comparator 2 as the CLK signal, so that the phase synchronization is established between Din and CLK.

FIG. 10 is a diagram showing the phase comparison characteristic of the linear phase comparator 2 (the relationship between the Din-CLK phase difference and the average voltage of the linear phase comparison output 17). FIG. 10 shows the case where the transition density coefficient (hereinafter, abbreviated as DF) of the input data Din is 0.5 and 0.25. The value of DF is the highest DF = 0. When Din is an alternating signal of 0/1.
5 and DF <0.5 in the case of PN (pseudo noise) signal or normal data transmission. Since the average voltage of the linear phase comparator output 17 is kept substantially constant during the operation of the clock recovery circuit (when locked), the Din-CLK phase difference has an influence when the value of DF changes during the operation. The value will be changed upon receipt. In that case, the degree of the influence depends on the value of the Din-CLK phase difference itself. That is, when the Din-CLK phase difference shown in (II) is close to zero, the Din-CLK phase difference is less likely to be affected by the change in the value of DF, and when the Din-CLK phase difference is zero, there is no effect. Disappear. On the other hand, Din-C
If the absolute value of the LK phase difference becomes large, it will be greatly affected. That is, the optimum point (II) of the Din-CLK phase relationship is optimal in the sense that the Din punching phase margin by CLK in the D-FF 9 is maximum, and the Din-CLK phase difference is affected by DF. It can be said that it is optimal in the sense that it is the only phase relationship that does not exist. Also, the average voltage of the linear phase comparator output 17
There is a point [optimal point (II)] where the in-CLK phase difference is not affected by DF.

FIG. 11 is a diagram showing the relationship between the free-running frequency of the VCO 4 and the average voltage of the linear phase comparator output 17. V
The free-running frequency of CO4 has a range (lock range) in which clock reproduction is possible, but as described above, the average voltage of the linear phase comparator output 17 which is not affected by DF exists only at the point, The free-running frequency of the VCO 4 whose comparison characteristic is not affected by DF also exists only at the point (center of the lock range).

[0012]

As described above,
In the conventional clock recovery circuit shown in FIG. 8, the free-running frequency of the VCO 4 whose phase comparison characteristic is not affected by DF exists only at points. Let us consider a case where the free-running frequency of the VCO 4 is (I) higher than the optimum point (II) (FIG. 11). In this case, the average voltage of the output 17 of the linear phase comparator maintains its synchronous state by lowering its value. As a result, as shown as (I) in FIG.
The n-CLK phase difference greatly changes depending on the value of DF. This means that the punching timings of the D-FF 9 and the D-FF 10 are largely modulated by the DF. As a result, in addition to the phase of the reproduced clock Cout being modulated by the DF, the phase of the retimed reproduced data Dout is also modulated by the DF. Thus, by DF, Co
When the phase of ut or the phase of Dout is modulated, there arises a problem that a new generation of jitter occurs or the tolerance against the jitter included in the input data Din decreases. Also, DF
Since the lock range and the pull-in range shift due to the difference between the two, there is a possibility that a sufficient pull-in range can be obtained only for the DF in a specific range. In order to avoid the above problems, it is necessary to adjust the free-running frequency of the VCO 4 to the optimum point, and the free-running frequency of the VCO 4 changes over time and environmental changes (temperature change, power supply voltage change, input data amplitude). It is necessary to provide compensation means so that it will not be affected by However, individual adjustment of the VCO at the time of shipment requires enormous labor, and it is practically difficult to compensate for the secular change of the free-running frequency of the VCO 4.

The present invention has been made to solve the problems of the prior art as described above, and is affected by the transition density coefficient (DF) of the input data Din even when the free-running frequency of the VCO is shifted. No circuit operation (D-FF
An object of the present invention is to provide a clock recovery circuit capable of punching timing, jitter characteristics, etc.).

[0014]

DISCLOSURE OF THE INVENTION The present invention provides a conventional clock recovery circuit, a discrete phase comparator for discriminating the lead / lag of the phase of the CLK signal with respect to the Din signal, and an output signal of the discrete phase comparator. The main feature is to add an offset voltage generator that gives a narrower band limitation than the loop filter and add the output of this offset voltage generator to the loop. Conventional clock recovery circuits use only one of either a linear or discrete phase comparator, while the clock recovery circuit of the present invention uses both linear and discrete phase comparators. That is different. In the present invention, the phase lead / lag discrimination threshold of the discrete phase comparator is set to the optimum Din for the linear phase comparator.
By setting the -CLK phase relationship (phase difference of zero), the discrete phase comparator gives an offset voltage to the VCO so that the Din-CLK phase relationship becomes the optimum phase relationship. Therefore, even when the free-running frequency of the VCO deviates from the optimum point, the action of the offset voltage causes the Din-C
An effect is obtained in which the LK phase difference is attracted and fixed near the optimum point. Further, as a result, even if the free-running frequency of the VCO deviates from the optimum point, the punching timing in the D-FF can be kept constant regardless of the value of DF. In particular, when the band of the offset voltage generator is made sufficiently narrower than the band of the loop filter, the dynamic characteristics of the clock recovery circuit are determined by the linear phase comparator, and the discrete phase comparator uses the Din-CLK. It has only the effect of giving an offset voltage to the VCO so that the phase relationship becomes the optimum phase relationship. Therefore, the clock recovery circuit of the present invention can maintain the Din-CLK phase relationship at the optimum point while maintaining the feature of low jitter which is the feature of the linear phase comparator.

As described above, in the present invention, since the offset voltage is applied to the VCO by the discrete phase comparator so that the input-clock phase relationship is optimum for the linear phase comparator, the free-running frequency of the VCO is the optimum point. Even if it deviates from it, it is attracted to the optimum point and fixed. Therefore, while maintaining the excellent low jitter characteristics of the circuit of the conventional configuration, VC
A clock recovery circuit is realized in which the circuit operation is not affected by the transition density coefficient of the input even if the free-running frequency of O shifts.
The lock range can be expanded.

[0016]

FIG. 1 is a block diagram showing a first embodiment of the present invention. In this embodiment, the linear phase comparator 2, the loop filter 3, the VCO 4, the discrete phase comparator 2 are used.
6, an offset voltage generator 41, and an adder 24. The linear phase comparator 2 has a function of outputting a signal including a DC voltage component proportional to the phase difference between the input data Din and the clock CLK, and the discrete phase comparator 26 outputs the input data Din.
It has a function of determining the phase shift direction of in and the clock CLK and outputting only the shift direction (lead / lag). In this embodiment, the discrete phase comparator 26 and the offset voltage generator 41 are added to the conventional clock recovery circuit (FIG. 8), and the output of the offset voltage generator 41 is returned to the loop via the adder 24. Is.

Hereinafter, the discrete phase comparator 26 will be referred to as the D-FF 20.
And the loop filter 3 by a lag lead filter, and the offset voltage generator 41 by the integrator 22.
An example case will be described below. The CLK signal is input to the data terminal D of the D-FF 20, and the Din signal from the data input terminal 1 is input to the trigger input terminal. Di
If CLK is low when n rises (that is, C
The output of the D-FF 20 becomes low when the phase of LK is advanced, and becomes high when CLK is high at the time when Din rises (that is, when the phase of CLK is delayed).
The threshold value of the phase relationship at which the output of the D-FF 20 is inverted matches the phase difference of zero, that is, the optimum phase relationship of the linear phase comparator 2 described in the related art.

The integrator 22 imposes a narrower band limit on the output signal of the D-FF 20 than the loop filter 3 and outputs the signal, and gives an offset voltage to the VCO via the adder 24. If the phase difference between CLK and Din is close to zero, D-
High and low alternately appear in the output of the FF 20, and the mark ratio thereof becomes approximately 50%, so that the output of the integrator 22 becomes approximately zero and does not affect the VCO 4. On the other hand, C
When there is a phase difference between LK and Din, D-FF2
The 0 output is fixed to high or low, and accordingly, the output of the integrator 22 changes its value with a predetermined time constant (= reciprocal of the band). Since the output voltage of the integrator 22 acts on the VCO 4 as an offset voltage, the phase difference between CLK and Din decreases. When the phase difference between CLK and Din approaches zero,
The output of the D-FF 20 becomes alternately high and low at a certain mark ratio, and the value of the output of the integrator 22 is kept stable. The integrator 22 has two input terminals, such as an integrator using an operational amplifier, and integrates and outputs a voltage proportional to the difference between the voltages applied to both input terminals. Vessels are preferred.

FIG. 2 is a time chart showing the operation of this embodiment. First, the state immediately after the establishment of synchronization will be described.
The output 21 of the discrete phase comparator 26 is the input data Din
Its output is switched to high or low depending on the phase relationship between (a) and the clock CLK (b). CL shown in (I)
It outputs low when the K phase is advanced, and outputs high when the CLK phase shown in (III) is delayed,
In the case of the optimum phase relationship shown in (II) (zero phase difference between CLK and Din), either high or low (undefined) is output.

In any of (I) to (III),
The output voltage (offset voltage) of the offset voltage generator 41 (= integrator 22) starts to change in the direction of the output 21 of the discrete phase comparator 26 according to its time constant. By inputting this offset voltage to the VCO 4, the phase relationship between CLK and Din changes in a decreasing direction. As a result, the time Din
The phase difference between (e) and CLK (f) is almost zero in any case of (I) to (III) [Fig. 2 (e),
(F)], the offset voltage gradually approaches different values for each of (I) to (III). After that, the offset voltage keeps a different value for each of (I) to (III), but this is kept by the output 21 of the discrete phase comparator 26 transiting between high and low (FIG. 2).
(G)). In the case of (I), the mark rate is <50%, and (II)
In the case of (3), the mark ratio is about 50%, and in the case of (III), the mark ratio is> 50%. Therefore, different offset voltages can be generated in each case.

The reason why such a transition occurs is that the VCO 4 is feedback-controlled by the binary output of the discrete phase comparator 26. The time scale at which this transition occurs is approximately the time constant of the offset voltage generator 41. If this time constant is made large enough, that is,
If the band of the offset voltage generator 41 is made sufficiently narrow, the dynamic characteristics (pull-in range, jitter tolerance, etc.) of this clock recovery circuit are the same as those of the conventional clock recovery circuit using the linear phase comparator 2. Become.

FIG. 3 is a diagram showing changes over time in the output voltage of the loop filter 3 and the output voltage of the offset voltage generator 41. In order to explain the process of generating the offset voltage, V
The case where the free-running frequency of CO4 deviates to a lower frequency than the optimum frequency is described. Input data D at time t0
When in is given, the output voltage of the loop filter 3 having a small time constant (that is, a wide band) changes rapidly, and lock is established at time t1. At this point, the free-running frequency of the VCO 4 is deviated to a low frequency, so that the phase of CLK is delayed from the phase of Din as shown in FIG. It is shifting. After the time point t1 when the lock is established, the discrete phase comparator 2
The output of 6 is fixed high and the offset voltage generator 41
Output voltage changes to the positive side with a large time constant (narrow band).

Since the phase comparison coefficient (the ratio of the input phase difference and the output average voltage in the phase comparator) is significantly larger in the discrete phase comparator than in the linear phase comparator, the time constant of the offset voltage generator 41 elapses. By a later time, the phase difference between Din and CLK decreases to near zero, the output of loop filter 3 asymptotically approaches zero, and the output voltage of offset voltage generator 41 asymptotically approaches a positive voltage. After that, the output of the discrete phase comparator 26 transits between high and low on the time scale of the time constant of the offset voltage generator 41. Here, by continuing the transition at a mark ratio exceeding 50%, the output voltage of the offset voltage generator 41 maintains a certain positive voltage.

FIG. 4 shows phase comparison characteristics (relationship between the Din-CLK phase difference and the adder output 25) when the linear phase comparator 2 and the discrete phase comparator 26 are regarded as one phase comparator. The transition density coefficient (DF) of the input data Din is set to 0.
The case of 5 and 0.25 is shown. FIG. 4 shows a phase comparison characteristic after a lapse of a time longer than the time constant of the offset voltage generator 41, and the phase comparison characteristic of the linear phase comparator 2 alone (the above-mentioned 10). Compared with the phase comparison characteristic of the linear phase comparator 2 alone (FIG. 10 above), the VCO 4 has a high free running frequency (I) and a low free running frequency (III).
It can be seen that the n-CLK phase difference decreases to near zero. This is because even if the free-running frequency of the VCO 4 shifts to some extent, the Din-CLK phase difference is fixed near the optimum point.
It means that it is not affected by F.

FIG. 5 is a diagram showing the relationship between the free-running frequency of the VCO 4 and the average voltage of the linear phase comparator output 17. Figure 5
Indicates the relationship after a lapse of a time longer than the time constant of the offset voltage generator 41, and the relationship of only the linear phase comparator 2 with respect to an input change having a time scale shorter than this (for example, immediately after lock is established). (FIG. 11). Compared with the conventional relationship (FIG. 11 above), the discrete phase comparator 2
Due to the addition of 6, a region (a flat region in the center) where the average voltage of the output 17 of the linear phase comparator hardly changes even when the free-running frequency of the VCO 4 changes appears. Within this region, the Din-CLK phase difference is close to zero and is not affected by DF. Then, the lock range is expanded by the frequency range corresponding to this region.

FIG. 6 is a diagram showing the relationship between the free-running frequency of the VCO 4 and the average voltage of the output 21 of the discrete phase comparator. FIG. 6 also shows the relationship after a lapse of a time longer than the time constant of the offset voltage generator 41, and for the input change whose time scale is shorter than this, the output 2 of the discrete phase comparator is
The average voltage of 1 does not follow. When the free-running frequency of the VCO 4 is higher than the optimum value (I), the output 2 of the discrete phase comparator
The average voltage of 1 drops, giving a negative offset voltage to VCO 4. On the contrary, when the free-running frequency of the VCO 4 is lower than the optimum value (III), the average voltage of the output 21 of the discrete phase comparator rises and gives the VCO 4 a positive offset voltage.

The region where the free-running frequency of the VCO 4 can be compensated by the above offset voltage is the increment of the lock range,
In this region, the Din-CLK phase difference is close to zero. If the free-running frequency of the VCO 4 shifts beyond this range, the average voltage of the output 17 of the linear phase comparator has a non-zero value because the Din-CLK phase difference is not zero, and the lock is generated. Will be maintained.

The configuration of the linear phase comparator 2 is not limited to that shown in FIG. That is, the D-FF 10 can be realized by a delay circuit (reference: CRHogge, JR., "A
Se1f Correcting Clock Recovery Circuit ", Jounal of
Lightwave Tech., Vo1, LT-3, No.6,1985, p1323), and the delay circuit has Din instead of the output of D-FF9.
You may make it input directly. Also, EXOR1
3, the linear phase comparator 40 in which the EXOR 14 is changed to a logical product gate (reference document: Japanese Patent Laid-Open No. 2000-68991)
In FIG. 12 described above, there is a problem that the free-running frequency of the VCO 4 in which the phase comparison characteristic is not influenced by DF exists only at the point, but this linear phase comparator 40
By applying the first embodiment as
Even if the free-running frequency of 4 shifts, it is compensated by the offset voltage, and the effect that the Din-CLK phase difference is kept near the optimum point is obtained.

Further, in the first embodiment, the case where the loop filter 3 is realized by the lag lead filter has been described as an example, but the loop filter 3 may be an easy filter or an active filter. However, the lag lead filter is superior to the lag filter in that the band and the damping factor can be set independently. In addition, the lag-lead filter does not require a wide-band operational amplifier as compared with an active filter, and has a feature that it is easy to achieve high integration and low power consumption especially in the application of clock reproduction of a high bit rate signal in optical communication. . It should be noted that the use of the active filter has an advantage that the lock range is generally expanded as compared with the case of using the lag lead filter. However, in the present invention, the offset voltage generator 41 has an effect of expanding the lock range. There is no benefit to using active filters.

FIG. 7 is a diagram showing a second embodiment of the present invention. The present embodiment has a linear phase comparator 2, a loop filter 3, a VCO 4, a discrete phase comparator 26, an offset voltage generator 41, an adder 24, a lock detector 27, a sweep signal generator 33, a switch (path selector). It is composed of 29. This embodiment is the same as the lock detector 2 of the first embodiment.
7 and the sweep signal generator 33 are added.
The operation at the time of lock is the same as that of the first embodiment, but the function of the sweep signal generator 33 to generate the sweep signal and sweep the VCO 4 at the time of unlock is added to the first embodiment.

A wide pull-in range can be obtained by adding the sweep function. Since the sweep signal needs to be generated only when unlocked, a lock detector 27 for determining lock or unlock is added. As the configuration of the lock detector 27, a D-FF punching type, a beat signal detecting type and the like are widely known. The D-FF punching type can be configured by a D-FF and a DC detector. That is, a signal obtained by phase-shifting CLK by 90 degrees is D-
It is input to the data input terminal of the FF and Din is input to the trigger input terminal of the D-FF. When locked, the D-FF outputs either high or low fixedly, whereas when unlocked, the D-FF alternately outputs high and low. This utilizes a phenomenon in which the phase relationship between CLK and Din becomes invisible when unlocked. Then, when the output of the D-FF is DC-detected by the DC detector, it becomes almost zero when locked, whereas a high detection level is obtained when unlocked. Therefore, it is possible to determine lock / unlock depending on the detection level.

On the other hand, the beat signal detection type is a method for directly detecting the beat signal appearing at the output of the phase comparator (the frequency of the difference between the CLK frequency and the frequency corresponding to the Din bit rate) when unlocked by direct-current detection. . Also with this method, it is possible to determine whether the signal is locked or unlocked depending on the detection level. The sweep signal generator 33 is the lock detector 27.
Generates a sweep signal and detects VC
Sweep C4. The sweep signal generator 33 can be easily realized by an analog oscillator. The analog oscillator can be configured by connecting the integrator 22 and the Schmitt trigger inverter 31 in a loop as shown in FIG. 7, for example.
The switch 29 switches the path according to the output of the lock detector 27 to select a path.
1 and 30 are connected, and when unlocked, paths 30 and 32
And connect. Therefore, in the locked state, the operation of this embodiment is exactly the same as that of the first embodiment, whereas
When unlocked, the sweep signal generator 33 causes the sweep signal (see FIG. 7).
In the above configuration, a triangular wave) is generated to sweep VCO4. Thereby, a wide pull-in range can be obtained. Note that the switch 29 may be any switch as long as it selects a path, and may be a selector using a digital gate. Also,
The Schmitt trigger inverter 31 may be any Schmitt trigger circuit having a hysteresis characteristic for input and output,
In addition to a digital gate having a Schmitt trigger characteristic, a hysteresis comparator may be used.

In this embodiment, since the sweep signal generating circuit 33 that operates when unlocked and the offset voltage generator 41 that operates when locking are common, a comparison is made with a case where both circuits are configured separately. It is characterized by a small circuit scale and low power consumption. In addition, the present embodiment can obtain a wider pull-in range than the first embodiment.

[0034]

The clock recovery circuit of the present invention dynamically maintains the excellent jitter characteristic of the clock recovery circuit using only the linear phase comparator, while statically maintaining the input data Din.
The phase relationship between the clock CLK and the clock CLK can be fixed at the optimum point. As a result, the operation of the clock recovery circuit (D-FF punching timing, jitter characteristics, etc.) is not affected by the transition density coefficient (DF) of the input data Din even when the free-running frequency of the VCO is shifted.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the present embodiment.

FIG. 3 is a diagram showing changes over time in the output voltage of the loop filter 3 and the output voltage of the offset voltage generator 41.

FIG. 4 is a phase comparison characteristic diagram when the linear phase comparator 2 and the discrete phase comparator 26 are regarded as one phase comparator.

FIG. 5: Free running frequency of VCO 4 and linear phase comparator output 1
7 is a relationship diagram with the average voltage of 7.

FIG. 6 Free running frequency of VCO 4 and discrete phase comparator output 2
FIG. 3 is a relational diagram with the average voltage of 1.

FIG. 7 is a circuit diagram showing a second embodiment of the present invention.

FIG. 8 is a circuit diagram showing an example of a conventional clock recovery circuit.

FIG. 9 is a diagram showing an operation of a conventional clock recovery circuit.

10 is a phase comparison characteristic diagram of the linear phase comparator 2. FIG.

FIG. 11 is a relationship diagram between the free-running frequency of the VCO 4 and the average voltage of the linear phase comparator output 17.

FIG. 12 is a diagram showing another configuration example of a linear phase comparator.

[Explanation of symbols]

1 ... Data input terminal 2 ... Linear phase comparator 3 ... Loop filter 4 ... Voltage controlled oscillator (VCO) 5 ... Clock output terminal 6 ... Buffer 7 ... Non-inverted output of buffer 6 8 ... Inverted output of buffer 6 9 ... D type Flip-flop (D-FF) 10 ... D-type flip-flop (D-FF) 11 ... D-FF 9 output 12 ... D-
Output 13 of FF10 ... Exclusive OR gate (EXOR) 14 ... Exclusive OR gate (EXOR) 15 ... EX
Output 16 of OR 13 ... Output of EXOR 14 17 ... Output of linear phase comparator 2 18 ... Output of loop filter 3 19 ... Adder 20 ... D-type flip-flop (D-FF) 21 ... Output 22 of discrete phase comparator 26 ... Integrator 23 ... Output of offset voltage generator 41 24 ... Adder 25 ... Output of adder 24 26 ... Discrete phase comparator 27 ... Lock detector 28 ... Output of lock detector 27 29 ... Switch 30 ... Offset voltage generator 41 input 31 ... Schmitt trigger inverter 32 ... Schmitt trigger inverter 31 output 33 ... Sweep signal generator 34 ... Data output terminal 35 ... AND gate 36 ... AND gate 37 ... AND gate 35 output 38 ... AND gate 36 output 39 ... buffer 40 ... linear phase comparator 41 ... offset voltage generator

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP 58-107727 (JP, A) JP 60-113530 (JP, A) JP 52-4153 (JP, A) JP 6- 303131 (JP, A) JP 5-129942 (JP, A) JP 11-122099 (JP, A) JP 59-219025 (JP, A) JP 10-256901 (JP, A) JP-A-4-256218 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03L ⁷ /06-7/14 H04L 7/02

Claims (4)

(57) [Claims] 1. A voltage controlled oscillator whose oscillation frequency is controlled by a voltage, and a phase difference between an output signal of the voltage controlled oscillator and an input signal from an input terminal is detected, and a DC voltage component proportional to the phase difference is included. A first phase comparator which outputs a signal; a second phase comparator which determines a phase shift direction of an output signal of the voltage controlled oscillator with respect to an input signal from an input terminal and outputs the phase shift direction; A loop filter that extracts a component of a predetermined band or less from the output signal of the first phase comparator, and an offset voltage generator that extracts a component of a narrower band than the band of the loop filter from the output signal of the second phase comparator The output of the loop filter and the output of the offset voltage generator are input, and the voltage addition result of both signals is sent as a voltage for controlling the voltage controlled oscillator. An adder, a clock recovery circuit, characterized in that it comprises a lock detection to determine the synchronization state of the clock recovery circuit
Sweep signal when the lock detector and the lock detector are judged to be unlocked.
Signal to generate a sweep signal to sweep the voltage controlled oscillator
And a sweep signal generator, the sweep signal generator and the offset voltage generator.
Comprised of a yumit trigger circuit and a path selector,
The route selector is used when the lock detector determines that it is locked.
The output of the second phase comparator and the offset voltage
Connect to the raw instrument input and the lock detector unlocks and
If it is determined that the Schmitt trigger circuit output and the
Characterized by connecting to the input of the fusing voltage generator
Clock recovery circuit. 2. The clock recovery circuit according to claim 1, wherein the offset voltage generator is an integrator. 3. The clock recovery circuit according to claim 1, wherein the loop filter is a lag lead filter. 4. The clock regenerating circuit according to claim 1, wherein the second phase comparator is a D-type flip-flop.