JP5218326B2 - Manufacturing method of semiconductor substrate having parallel pn junction structure - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor substrate having a parallel pn junction structure in which an n-type semiconductor region and a p-type semiconductor region are alternately and repeatedly joined.

In a silicon epitaxial wafer obtained by vapor phase epitaxial growth of a silicon single crystal thin film on a silicon single crystal substrate (hereinafter also referred to as a semiconductor substrate), the grown silicon single crystal thin film (hereinafter also referred to as a silicon epitaxial layer or simply an epitaxial layer) is used. A technique is known in which an ion implantation layer of an impurity element is formed by an ion implantation method, and another epitaxial layer is formed to form a buried layer.
Here, when a semiconductor substrate is manufactured by performing epitaxial growth, an impurity-added region that is long in the depth direction (hereinafter referred to as a vertical-added region) is formed in order to manufacture elements such as a power MOSFET and a vertical bipolar transistor. It may be necessary to form a parallel pn junction structure. In the planar type MOSFET, the in-plane of the impurity doped region is the main current path, but by forming the longitudinally doped region, current can be conducted in the layer thickness direction of the region, and the element is turned on. There is an advantage that resistance can be reduced.

As a method for forming such a deep vertical addition region, Patent Document 1 discloses a method of repeatedly forming an epitaxial layer growth step and an ion implantation step. In this case, however, the number of steps is likely to increase. There is a fault that tends to lead to cost increase.
Therefore, Patent Documents 2, 3, and 4 describe a technique in which a trench (groove) is formed by etching on the main surface of a silicon single crystal substrate, and an epitaxial layer is grown so as to fill the trench to form a longitudinally added region. Is disclosed. In this method, when the epitaxial growth of, for example, a p-type semiconductor in the trench is completed, silicon swells (steps of 1 to several μm) and polysilicon are formed on the trench opening and the mask oxide film on the surface of the semiconductor substrate. In addition, since the mask oxide film remains, it is necessary to polish the substrate surface to remove the mask oxide film and polysilicon and to flatten the surface.

  Regarding this planarization treatment, Patent Document 2 describes that the substrate surface after epitaxial growth is polished by a CMP (Chemical Mechanical Polishing) method. Patent Document 3 describes that the mask oxide film used for forming the trench is also used as a polishing stopper film for planarizing the substrate, and the substrate surface is polished by CMP. . In addition to polishing by the CMP method, a method of etching the substrate surface by dry etching is known. Patent Document 4 describes that silicon etching is performed using a mask oxide film at the time of forming a trench as an etch stop layer.

Further, in Patent Document 5, the mask oxide film used for forming the trench is used as a polishing stopper film when polishing the substrate surface, and after removing the polysilicon once, the mask oxide film is removed with HF or the like. A technique for flattening the surface by polishing again the surface step corresponding to the mask oxide film thickness is disclosed.
A device such as a MOSFET is formed on the surface of a semiconductor substrate polished by a planarization process. Therefore, it is important that there is little contamination of the substrate surface after polishing as described above. In addition, it is necessary to manage the thickness (cut thickness) of the substrate surface to be removed by polishing, and it is important that the flatness of the manufactured semiconductor substrate surface is high.

FIG. 4 shows a flowchart of a method for manufacturing a semiconductor substrate having a conventional parallel pn junction structure as described above.
As shown in FIG. 4, in the conventional manufacturing, first, for example, a first conductivity type semiconductor layer 102 is formed on an n-type silicon single crystal substrate 101 (FIG. 4A), and the first conductivity type semiconductor layer is formed. A mask oxide film 103 is formed on 102 to form a trench 104 after patterning (FIG. 4B), and a second conductivity type semiconductor region 105 is formed by buried epitaxial growth in the trench 104 (FIG. 4C). . Polishing is performed until the mask oxide film 103 left as a polishing stopper film is exposed in order to remove the bulge of the epitaxial layer generated at this time and flatten it (FIG. 4D). Then, the mask oxide film 103 is removed by etching or the like to expose the device formation surface (FIG. 4E).

JP 2001-139399 A JP 2000-340578 A JP 2001-196573 A JP 2001-168327 A JP-A-2005-57142

  However, even if the surface is flattened using the mask oxide film as a polishing stopper film, it corresponds to the dent (dishing) or the thickness of the mask oxide film as shown in FIGS. A step remains. Furthermore, even if the mask oxide film is removed to remove the step and then polished again, it is difficult to flatten the surface where the step has occurred once. There is a problem that it cannot be eliminated and the flatness does not increase.

  Further, since the mask oxide film is used as the polishing stopper film, the mask oxide film used for forming the trench groove is epitaxially grown for filling the trench with the mask oxide film remaining on the substrate surface. There is also a problem that defects due to thermal stress between the mask oxide film and silicon are generated in the epitaxial layer, resulting in a decrease in crystallinity and, consequently, device characteristics.

  The present invention has been made in view of the above problems, and has a parallel pn junction structure capable of manufacturing a semiconductor substrate having a device formation surface with good crystallinity and high flatness while preventing contamination. An object is to provide a method for manufacturing a semiconductor substrate.

  In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor substrate having a parallel pn junction structure in which a first conductivity type semiconductor region and a second conductivity type semiconductor region are alternately and repeatedly joined, A step of preparing a silicon single crystal substrate to be epitaxially grown, a step of forming a first conductivity type semiconductor layer by epitaxially growing a first conductivity type semiconductor on the prepared silicon single crystal substrate, and the first conductivity type formed above. Forming a trench in the type semiconductor layer, and epitaxially growing a second conductivity type semiconductor on the first conductivity type semiconductor layer in which the trench is formed, thereby forming a second conductivity type semiconductor region in the trench. , Forming a second conductive type semiconductor layer on the first conductive type semiconductor layer, and removing the silicon single crystal substrate And a degree, to provide a method of manufacturing a semiconductor substrate having a parallel pn junction structure, characterized in that the said removing silicon single crystal substrate side surface of the device formation surface.

Thus, by removing the epitaxially grown silicon single crystal substrate and using the surface on the silicon single crystal substrate side as the device formation surface, the flat surface reflecting the flatness of the silicon single crystal substrate is defined as the device formation surface. can do. Further, since it is not necessary to etch and polish different materials such as oxide film and silicon, p-type and n-type simultaneously, unevenness due to the difference in etching rate and strength does not occur, and a device formation surface with high flatness is obtained. be able to. Furthermore, since the device formation surface is not exposed until the silicon single crystal substrate is removed, there is almost no contamination due to polishing, etching or the like. Moreover, since it is not necessary to leave the mask oxide film on the epitaxial growth surface and perform the epitaxial growth, the epitaxial layer to be grown can be formed with good crystallinity.
As described above, according to the method for manufacturing a semiconductor substrate having a parallel pn junction structure of the present invention, a semiconductor substrate having a device formation surface with good crystallinity and high flatness can be manufactured while preventing contamination.

At this time, before the step of forming the first conductive semiconductor layer, an etch stop layer is formed on the silicon single crystal substrate, and the first conductive semiconductor layer is formed on the etch stop layer. Is preferred.
In this way, by forming an etch stop layer on the silicon single crystal substrate, the substrate can be removed reliably and easily while maintaining the flatness of the device forming surface by etching when removing the silicon single crystal substrate. can do.

At this time, a p-type substrate is prepared as the prepared silicon single crystal substrate, an n-type epitaxial layer is formed as the etch stop layer, and at least the etch stop layer is exposed in the step of removing the silicon single crystal substrate. In this case, electrochemical etching is preferably performed.
As described above, in the step of forming the n-type epitaxial layer as the etch stop layer and removing the silicon single crystal substrate, at least the etch stop layer is exposed, and the electrochemical etching is performed, so that the n-type epitaxial layer can be reliably formed. In addition, since the etching can be stopped, a device forming surface with high flatness can be obtained more reliably. In addition, since the first conductivity type semiconductor is epitaxially grown on the n-type epitaxial layer formed as the etch stop layer, the first conductivity type semiconductor layer having high flatness and good crystallinity can be formed.

At this time, in the step of removing the silicon single crystal substrate, the silicon single crystal substrate is ground to a thickness of 10 to 30 μm, and then the electrochemical etching is performed to expose the etch stop layer. preferable.
Thus, the silicon single crystal substrate can be efficiently removed by grinding the silicon single crystal substrate to a thickness of 10 to 30 μm and then performing an electrochemical etching to expose the etch stop layer. Further, since the etch stop layer is exposed by electrochemical etching, the flatness can be maintained reliably and easily.

Before performing the electrochemical etching, it is preferable to cover the second conductive semiconductor layer with a protective film in advance.
Thus, by covering the second conductive type semiconductor layer with the protective film in advance, it is possible to prevent the surface of the second conductive type semiconductor layer from being etched and roughened or contaminated during the electrochemical etching. A higher quality semiconductor substrate can be manufactured.

  As described above, according to the method for manufacturing a semiconductor substrate having a parallel pn junction structure of the present invention, it is possible to manufacture a semiconductor substrate having a device formation surface with good crystallinity and high flatness while preventing contamination. .

It is a flowchart which shows an example of the embodiment of the manufacturing method of the semiconductor substrate which has a parallel pn junction structure of this invention. It is a cross-sectional SEM photograph of the semiconductor substrate manufactured in the Example. It is a cross-sectional SEM photograph of the semiconductor substrate manufactured in the comparative example. It is a flowchart which shows an example of the manufacturing method of the semiconductor substrate which has the conventional parallel pn junction structure.

Hereinafter, although the manufacturing method of the semiconductor substrate which has a parallel pn junction structure of this invention is demonstrated in detail, referring an figure as an example of an embodiment, this invention is not limited to this.
FIG. 1 is a flowchart showing an example of an embodiment of a method for manufacturing a semiconductor substrate having a parallel pn junction structure according to the present invention.

In the manufacturing method of the present invention, as shown in FIG. 1A, a silicon single crystal substrate 10 to be epitaxially grown is prepared.
At this time, the silicon single crystal substrate 10 to be prepared is not particularly limited, but a p-type substrate is prepared when electrochemical etching is used when removing the silicon single crystal substrate 10 in a later step.

Next, as shown in FIG. 1B, an etch stop layer 11 is preferably formed on the silicon single crystal substrate 10.
Thus, by forming the etch stop layer, it can be easily removed by etching while maintaining high flatness of the surface when removing the silicon single crystal substrate in a later step. At this time, the etch stop layer 11 having a thickness of 1 to 5 μm can be easily removed when the device formation surface is exposed.

  The etch stop layer 11 formed at this time is not particularly limited as long as the etching rate is significantly lower than that of the used substrate and the etching can be substantially stopped after the substrate is removed. In order to use electrochemical etching, when a p-type substrate is prepared as the silicon single crystal substrate 10, it is preferable to form an n-type epitaxial layer as the etch stop layer 11. Thereby, the first conductivity type semiconductor layer having good crystallinity can be grown on the n-type epitaxial layer in a later step.

  As another etch stop layer 11 that can be used in the manufacturing method of the present invention, for example, a high-concentration boron layer is formed on the silicon single crystal substrate 10, so that the etching rate differs from that of the silicon single crystal substrate. It functions as a good etch stop layer.

Next, as shown in FIG. 1C, the first conductivity type semiconductor layer 12 is formed by epitaxially growing the first conductivity type semiconductor.
The first conductive semiconductor layer 12 formed at this time is not particularly limited, and is, for example, a p-type epitaxial having a thickness of 20 to 60 μm and a resistivity of 0.5 to 3.0 Ωcm from the breakdown voltage characteristics of the device to be manufactured. A layer can be formed.

Next, as shown in FIG. 1D, a trench 13 is formed in the first conductivity type semiconductor layer 12.
As a method of forming the trench 13, for example, an oxide film having a thickness of about 1 μm is formed on the surface of the first conductivity type semiconductor layer by a thermal oxidation method or a CVD (chemical vapor deposition) method as a mask. Then, the oxide film in the trench formation region is removed by photolithography technology to form an oxide film pattern for trench formation, and then anisotropic such as plasma etching, RIE (reactive ion etching), anisotropic wet etching, etc. A trench can be formed by etching. The mask at this time is not limited to the oxide film, and for example, a nitride film can be formed. In this case, in the present invention, it is not necessary to use a mask at the time of trench formation as a polishing stopper film or the like in a subsequent process, and it is preferable to remove the mask after the trench formation in order to perform good epitaxial growth.

Next, as shown in FIG. 1 (e), the second conductivity type semiconductor is epitaxially grown to form the second conductivity type semiconductor region 17 in the trench 13, and the second conductivity type semiconductor region 12 is formed on the first conductivity type semiconductor layer 12. A two-conductivity type semiconductor layer 19 is formed.
For example, while adjusting the growth temperature in the range of 850 to 1100 ° C., the epitaxial growth is continued after the trench 13 is filled with the second conductivity type semiconductor and the second conductivity type semiconductor region 17 is formed. A second conductive type semiconductor layer 19 is grown on the type semiconductor layer 12 until a predetermined thickness is reached. The thickness of the second conductive type semiconductor layer 19 formed at this time is not particularly limited, and the second conductive type semiconductor layer 19 may be grown so as to cover the first conductive type semiconductor layer 12.

Next, as shown in FIG. 1F, the silicon single crystal substrate 10 is removed.
The removal method is not particularly limited. For example, the holding substrate 18 for reinforcing the mechanical strength is attached to the second conductive semiconductor layer 19 side in advance, and then the silicon single crystal substrate 10 is ground. It can be removed by polishing, etching or the like. The holding substrate 18 does not need to be bonded when the second conductive semiconductor layer 19 is formed thick. However, in consideration of the time for epitaxially growing the second conductive semiconductor layer 19 and the like, the second conductive semiconductor 18 The production efficiency is better when the layer 19 is formed thin and the holding substrate 18 is bonded.

At this time, when the etch stop layer 11 is formed, the silicon single crystal substrate 10 is removed by first grinding the silicon single crystal substrate 10 to a thickness of 10 to 30 μm and then performing etching. It is preferable to expose the etch stop layer 11.
In this way, by performing etching after grinding to the above thickness, the working efficiency is remarkably improved, and finally, the etching stop is caused by etching to remove the substrate. The flatness of the resulting surface is not deteriorated.

In addition, when a p-type substrate is prepared as the silicon single crystal substrate 10 and an n-type epitaxial layer is formed as the etch stop layer 11, electrochemical etching may be performed when the etch stop layer 11 is exposed. preferable. The method of this electrochemical etching is not particularly limited, and the surface to be etched is immersed in an alkaline solution such as KOH, and electrochemical etching is performed by applying a predetermined voltage between the substrate and the alkaline solution. As a result, when the etching proceeds and the n-type epitaxial layer is exposed to the alkaline solution, an SiO ₂ film is formed on the surface and the etching stops.
As described above, in the case of electrochemical etching, the etching can be surely stopped by the etch stop layer, and the exposed surface reflects the shape of the interface between the silicon single crystal substrate and the n-type epitaxial layer. Therefore, the flatness is very high.

At this time, it is preferable to previously cover the second conductive semiconductor layer 19 with a protective film 16 made of a material that is not etched in an alkaline solution, for example, before electrochemical etching.
As a result, it is possible to reliably prevent the second conductive semiconductor layer from being etched. Therefore, the work for etching becomes easier, and batch processing of a plurality of sheets simultaneously improves productivity and further manufacture. The quality of the semiconductor substrate is also improved.

  Further, when a high-concentration boron layer is formed as the etch stop layer 11, for example, when the etch stop layer 11 (high-concentration boron layer) is exposed, for example, ethylenediamine and pyrocatechol mixed solution (EDP), NaOH solution Alternatively, etching of the silicon single crystal substrate 10 using a KOH solution causes an etch stop in a high-concentration boron layer with an extremely low etching rate, so that the flatness of the surface that forms the device is maintained high. However, the silicon single crystal substrate can be removed. Also in this case, it is preferable to form the protective film 16 on the second conductive semiconductor layer 19 side.

Then, as shown in FIG. 1G, the etch stop layer 11 and the like are removed by etching or the like, and the semiconductor substrate 15 having the device formation surface 14 is manufactured.
Thus, according to the present invention, in order to flatten the device formation surface finally obtained as in the prior art, the uneven surface is ground, polished, etched, or the oxide film and silicon portion of different materials, p It is not necessary to polish the n-type and the like at the same time, and moreover, since the flatness of the silicon single crystal substrate is reflected, a semiconductor substrate having a very high flatness of the device formation surface can be manufactured efficiently and reliably. be able to. In addition, since the device forming surface is not exposed when removing the substrate using polishing, etching, or the like, the device forming surface is not contaminated by polishing or the like.

  As described above, according to the method for manufacturing a semiconductor substrate of the present invention, it is possible to manufacture a semiconductor substrate having a parallel pn junction structure with high flatness and good crystallinity with high productivity while preventing contamination. it can.

EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.
(Example)
A semiconductor substrate was manufactured by the process shown in FIG.
First, a p-type silicon single crystal substrate 10 is prepared (FIG. 1A), an n-type silicon epitaxial layer 11 having a thickness of 3 μm is formed thereon (FIG. 1B), and a thickness is further formed thereon. A p-type silicon epitaxial layer 12 having a thickness of 40 μm and a resistivity of 2 Ωcm was formed (FIG. 1C).

Next, a mask oxide film was formed on the p-type silicon epitaxial layer 12, and a trench 13 was formed by photolithography and plasma etching (FIG. 1D). The mask oxide film was removed after the trench formation.
Next, an n-type silicon epitaxial layer 19 was formed, and an n-type semiconductor region 17 was formed by buried epitaxial growth in the trench (FIG. 1E).
Next, the holding substrate 18 is adhered and pasted to the n-type silicon epitaxial layer 19 side, and further the protective film 16 is formed. Then, the silicon single crystal substrate 10 is ground to a thickness of 20 μm, and then the ground surface is KOH. The silicon single crystal substrate 10 was removed by immersion in a solution and electrochemical etching (FIG. 1 (f)).

Finally, the n-type silicon epitaxial layer 11 and the protective film 16 were removed to manufacture the semiconductor substrate 15 having the device forming surface 14 (FIG. 1G).
FIG. 2 is a cross-sectional SEM photograph (FIG. 2A) and an enlarged view (FIG. 2B) of the device-forming semiconductor substrate manufactured in the example, and a cross-section in which crystal defects are observed by performing selective etching. An SEM photograph (FIG. 2 (c)) is shown.

(Comparative example)
A semiconductor substrate was manufactured by the process shown in FIG.
First, a p-type silicon single crystal substrate 101 was prepared, and an n-type epitaxial layer 102 was formed thereon (FIG. 4A). Thereafter, a mask oxide film 103 was formed in the same manner as in the example to form a trench 104 (FIG. 4B). Thereafter, n-type silicon was epitaxially grown to fill the trench 104, thereby forming an n-type semiconductor region 105 (FIG. 4C). Next, the rising of the n-type semiconductor region 105 was polished until the mask oxide film 103 was exposed (FIG. 4D), and then the mask oxide film 103 was removed with HF.
3 is a cross-sectional SEM photograph (FIG. 3A) and an enlarged view (FIG. 3B) of the semiconductor substrate for device formation manufactured in the comparative example, and a cross-section in which crystal defects are observed by performing selective etching. A SEM photograph (FIG.3 (c)) is shown.

As shown in FIGS. 2A and 2B, the semiconductor substrate manufactured in the example has no unevenness and high flatness. Furthermore, as shown in FIG. 2C, almost no defects were detected by selective etching.
On the other hand, as shown in FIGS. 3A and 3B, the semiconductor substrate manufactured in the comparative example has a step difference in the thickness of the mask oxide film, and after the selective etching shown in FIG. 3C is performed. In this case, many dislocations were generated near the surface due to the stress of the mask oxide film and silicon due to the temperature during epitaxial growth.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

10 ... Silicon single crystal substrate, 11 ... Etch stop layer,
12 ... 1st conductivity type semiconductor layer, 13 ... Trench, 14 ... Device formation surface,
15 ... Semiconductor substrate, 16 ... Protective film, 17 ... Second conductivity type semiconductor region,
18 ... holding substrate, 19 ... second conductivity type semiconductor region.

Claims (5)

A method of manufacturing a semiconductor substrate having a parallel pn junction structure in which a first conductivity type semiconductor region and a second conductivity type semiconductor region are alternately and repeatedly joined, comprising:
Preparing a silicon single crystal substrate to be epitaxially grown;
Forming a first conductivity type semiconductor layer by epitaxially growing a first conductivity type semiconductor on the prepared silicon single crystal substrate;
Forming a trench in the formed first conductive semiconductor layer;
A second conductivity type semiconductor is epitaxially grown on the first conductivity type semiconductor layer in which the trench is formed to form a second conductivity type semiconductor region in the trench, and a second conductivity type semiconductor region is formed on the first conductivity type semiconductor layer. Forming a two-conductivity-type semiconductor layer;
Removing the silicon single crystal substrate,
A method of manufacturing a semiconductor substrate having a parallel pn junction structure, wherein the removed silicon single crystal substrate side surface is used as a device formation surface.   Before the step of forming the first conductive semiconductor layer, an etch stop layer is formed on the silicon single crystal substrate, and the first conductive semiconductor layer is formed on the etch stop layer. A method for manufacturing a semiconductor substrate having a parallel pn junction structure according to claim 1.   A p-type substrate is prepared as the silicon single crystal substrate to be prepared, an n-type epitaxial layer is formed as the etch stop layer, and at least the etch stop layer is exposed in the step of removing the silicon single crystal substrate. The method for manufacturing a semiconductor substrate having a parallel pn junction structure according to claim 2, wherein chemical etching is performed.   In the step of removing the silicon single crystal substrate, the silicon single crystal substrate is ground to a thickness of 10 to 30 μm, and then the electrochemical etching is performed to expose the etch stop layer. A method for manufacturing a semiconductor substrate having the parallel pn junction structure according to claim 3.   5. The method of manufacturing a semiconductor substrate having a parallel pn junction structure according to claim 3, wherein the second conductive semiconductor layer is covered with a protective film in advance before the electrochemical etching.

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