JP5218015B2 - Data decompressor - Google Patents

Description

  The present invention relates to a data decompression apparatus that compresses image data and stores it in a memory, reads the compressed data from the memory, and performs decompression processing.

  For example, in a printing apparatus such as a printer apparatus, a data decompression apparatus that performs compression processing on image data, stores compressed data in the memory, reads data from the memory, and performs decompression processing in order to effectively use the memory. It is used. When performing this data decompression processing, it is determined in what unit the data is compressed, for example, in units of 1 byte, from the memory, to determine what compression format, compressed data, or non-compressed data. Decompression processing is performed according to the read data order.

Patent Document 1 has also been proposed as a method for restoring compressed data.
JP 2006-268251 A

  However, in the conventional data decompression process (restoration process), it is necessary to change the configuration of the decompression circuit in order to improve the processing speed. For example, it is necessary to take measures to increase the speed by taking into account the wiring and changing the process of the ASIC equipped with the control circuit. Furthermore, when the expansion circuit is changed, the power consumption increases.

  Accordingly, the present invention provides a data decompression device that performs decompression processing of compressed data at high speed without increasing power consumption by referring to compression information relating to compressed data stored in a memory and efficiently restoring the compressed data. It is to provide.

The above object is achieved, according to the first invention, the non-compressed data, the compressed data, a first storage means for storing said compressed information of uncompressed data and the compressed data, decompresses the compressed data to the decompression data and expansion means for a detection means for detecting a sequence of the non-compressed data based on the compression information, and restoring means for restoring together the non-compressed data consecutive Ri detected by said detecting means, said extension second storage means for storing the non-compressed data decompressed data and is the recovered, which is extended by the means, the second storage means stored said extension data and the restored the output uncompressed data This can be achieved by providing a data decompression device having an output means.

Further, the problem according to the second invention, the non-compressed data, the compressed data that specifies the repetition of data located immediately before the first for storing said compressed information of uncompressed data and the compressed data storage means, and expanding means for expanding the compressed data into decompressed data, and detection means for the compressed data based on the compression information to detect the state stored alongside after the non-compressed data, said detecting means storing a restoring means for compressing data to be designated to restore the number of times the uncompressed data obtained by adding 1 to the number of iterations to specify, the decompressed data and the restored the uncompressed data in the detected the repeated Ri by the second storage means, the data decompression device and an output means for outputting the second said extension data and the restored the uncompressed data is stored in the storage means It can be achieved by providing.

  According to a third aspect of the present invention, the above object can be achieved by providing a data decompression device in which the compression information of the compressed data is stored as flag data in the first storage means.

  According to a fourth aspect of the present invention, the object can be achieved by providing a data decompression device in which the compressed data is stored in the first storage means in succession to the compression information.

Further, according to the above-mentioned problems is the fifth invention, and uncompressed data, and compressed data, wherein the processing the compressed information of the non-compressed data and the compressed data is stored in the first memory means, said compressed data a process of extending the extension data, and processing for detecting a sequence of the non-compressed data based on the compression information, a process of restoring together the non-compressed data consecutive Ri detected by said detecting means, said a process of storing the decompressed data and the restored the uncompressed data in the second storage means, and outputting the expanded data and the restored the uncompressed data is stored in said second storage means This can be achieved by providing a program for causing a computer to execute.

Furthermore, according to the above-mentioned problems is the sixth invention, the non-compressed data, the compressed data that specifies the repetition of data located immediately before the non-compressed data and the first storage means and the compression information of the compressed data a process of storing in a process of extending the compressed data into decompressed data, and processing the compressed data based on the compression information to detect the state stored alongside after the non-compressed data, the detection processing specifying a said detected repeatedly Ri by the number compressed data obtained by adding 1 to the repeat count to specify the processing for restoring the uncompressed data, the decompression processing by extension data and the restored processed the non a process of storing the compressed data in the second storage means, and outputting the expanded data and the restored the uncompressed data is stored in said second storage means It can be achieved by providing a program for causing a computer to execute.

  According to the present invention, continuous uncompressed data can be restored together, and when the sequence of the same data as the previous uncompressed data is detected, the uncompressed data is included as continuous data. Data can be decompressed and the data restoration speed can be increased.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram of the data decompression circuit of this embodiment. Note that the data decompression circuit of this example is connected to the CPU 2 via the PCI bus, and the CPU 2 is further connected to the memory 3. The memory 3 stores, for example, compressed image data, and the CPU 2 functions as a memory controller, reads the image data from the memory 3, and transmits it to the data decompression circuit.

The data decompression circuit 1 is roughly divided into four circuit blocks. The decompression circuit 7 is connected to a first-in first-out (FIFO) 4, a data selector 5 and a reference table 6, a data generation buffer 8, and a subsequent FIFO 9. It consists of
The pre-stage FIFO 4 is a buffer that temporarily holds image data read from the memory 3 under the control of the CPU 2, and stores compressed data to be decompressed read from the memory 3.

  FIG. 2 is a diagram showing a circuit configuration of the preceding FIFO 4 and the data selector 5. The pre-stage FIFO 4 captures data according to the control of the decompression input FIFO controller 13. Note that the input bit width and the output bit width of the first-stage FIFO 4 do not need to be the same. In this example, the input of the first-stage FIFO 4 corresponds to the bus width to which the first-stage FIFO 4 is connected, that is, the 32-bit width PCI bus. Get the width data. On the other hand, the output of the first-stage FIFO 4 generally has a data width required by the decompression circuit 7, for example, an 8-byte width. However, in this example, the output width is not 8 bytes but 9 bytes, that is, 72 bits wide, and will be described with these 9 bytes. The reason is that the flag part corresponds to 1 byte and the encoded data part 8 bytes. That is, the data width including the flag portion and the encoded data portion is set to a data width that can be read at a time.

  The data input to the first-stage FIFO 4 is arranged in units of 8 bits, and a flag 1 byte and subsequent 8 bytes of encoded data are sequentially selected as shown in FIG. 3 and converted into 72-bit width data.

  FIG. 4 shows a circuit configuration of the decompression circuit 7. The decompression circuit 7 is a circuit for decompressing (restoring) the encoded data (compressed data) supplied from the data selector 5. The decompression circuit 7 is connected to the reference table 6 and receives 8-bit flag data and compressed data “1” to “8” from the data selector 5. The compression formats of the compressed data “1” to “8” are three types: an uncompressed type, a repeat type indicating the continuation of the immediately preceding data, and a pointer type indicating the same data sequence as several bytes before.

  The uncompressed type is data for which there is no data to be referred to in the reference table 6, and is the same data as before being encoded. The repeat type is data that continuously refers to the data stored last in the table, and is data that encodes information indicating how many times the same data is repeated. Furthermore, the pointer type is data in which several bytes of the same data exist from a specific part of the table, and is data obtained by encoding information indicating the same number of data as the specific part.

  FIG. 5 is a diagram showing the data structure of the compressed data input to the decompression circuit 7. FIG. 4A is a diagram showing a specific configuration of compressed data. The first byte is flag data, and eight compressed data (and uncompressed data) are recorded after the flag data. As shown in FIG. 4B, the flag data is 1-byte 8-bit data, where data “0” indicates uncompressed data and data “1” indicates compressed data.

  For example, when the first flag data (# 1) is the flag “0”, the first (# 1) data of 8 compressed data (and uncompressed data) is 1 byte (8 bits) uncompressed. It is data. The data structure shown in FIG. 5C shows an example of the uncompressed data, and is described as the original data.

  On the other hand, when the first flag data (# 1) is the flag “1”, the first (# 1) data of the 8 compressed data and the non-compressed data is 1-byte (8-bit) compressed data. . In this case, there are two types, the above-described repeat type when the upper 2 bits of the compressed data are “11”, and the pointer type when the upper 2 bits are not “11”.

  In the pointer type, as shown in FIG. 4D, the upper 5 bits record data at the matching start position, and the lower 3 bits record the length data of the matching character string. On the other hand, in the case of the repeat type, as shown in FIG. 5E, the upper 2 bits are “11” and the lower 6 bits are length information in which the same data continues.

  FIG. 6 is a diagram showing a circuit configuration of the data generation buffer 8. The data generation buffer 8 includes F / Fs 8a-1 to 8a-8, four selectors 10a to 10d, a data generation buffer controller 11, and a counter 12. The data generated by the expansion circuit 7 is converted into F / F 8a-1. The data stored in .about.8a-8 and the data expanded by the control of the data generation buffer controller 11 are transferred to the subsequent FIFO 9.

  FIG. 7 is a diagram showing the configuration of the post-stage FIFO 9, in which data written in byte units is read in word units, dual port memories 14a-14d, write address counters 15a-15d, read address counter 16, and comparison The device 17 is configured. The processing operation of each circuit will be described later.

In the above configuration, the processing operation of this example will be described below.
First, the compressed data read from the memory 3 is input to the preceding FIFO 4. The decompression input FIFO controller 13 performs input control of compressed data input in units of 32 bits, inputs 32-bit compressed data to the preceding FIFO 4 according to the input of the write signal (WR) from the decompression input FIFO controller 13, and reads the read signal (RD). ), 8 bits × 4 (4 bytes) data is output to the selectors 5-0 to 5-8 constituting the data selector 5.
The compressed data input process is performed based on an input of an Empty signal described later.

  FIG. 4 shows the input logic when compressed data is input to each of the selectors 5-0 to 5-8 in accordance with a select signal output from the decompression input FIFO controller 13. The decompression input FIFO controller 13 has a counter (not shown) that counts up every time 32-bit compressed data is input, and performs ring counting of 0 to 8 shown in FIG. The decompression input FIFO controller 13 sequentially outputs a select signal to the selectors 5a-0 to 5a-8 corresponding to the count value, and the corresponding F / F (flip-flop) 5b-0 corresponding to 8-bit (1 byte) data. Transfer to ~ 5b-8.

  For example, data of 0 to 7 bits (first 8 bits in 32 bits) shown in the figure is input to the F / F 5b-0 via the selector 5a-0, and 8 to 15 bits (next 8 bits in 32 bits). Is input to the F / F 5b-1 via the selector 5a-1, and the following 16 to 23 bits (the next 8 bits in 32 bits) and 24 to 31 bits (the last 8 bits in 32 bits) are Then, the signals are input to the F / Fs 5b-2 and 5b-3 via the selectors 5a-2 and 5a-3 (a shown in FIG. 3).

  Next, the next 32-bit data supplied from the memory 3 is 0 to 7 bits (first 8 bits of the 32 bits) input to the F / F 5b-4 via the selector 5a-4, and 8 to 8 bits. Data of 15 bits (the next 8 bits in 32 bits) is input to the F / F 5b-5 via the selector 5a-5, and the following 16 to 23 bits (the next 8 bits in 32 bits) and 24 to 31 bits (32 bits) The last 8 bits of the data are input to the F / Fs 5b-6 and 5b-7 via the selectors 5a-6 and 5a-7 (b shown in FIG. 3).

  Further, the next 32-bit data supplied from the memory 3 is 0 to 7 bits (first 8 bits of the 32 bits) input to the F / F 5b-8 via the selector 5a-8 (see FIG. 3). C) and 72-bit (9 bytes) data are arranged in F / F5b-0 to F / F5b-8. The meanings of “flag” and compressed data “1” to “8” in F / F 5b-0 to 5b-8 shown in FIG. 3 are held in F / F 5b-0 to 5b-8 by the first processing described above. Data to be displayed. Note that data according to the logic shown in FIG. 3 is input to the F / Fs 5b-0 to 5b-8.

  Next, the decompression circuit 7 performs decompression processing on the data input to the F / Fs 5b-0 to 5b-8. 8 to 10 are flowcharts for explaining processing of the decompression circuit 7. First, according to the flowchart shown in FIG. 8, it is determined whether 9 bytes of data are held in the F / Fs 5b-0 to 5b-8 (step (hereinafter referred to as S) 1). Here, when 9 bytes of data are held in the F / Fs 5b-0 to 5b-8 (S1 is YES), an initial value (n = 1) is set (S2, State01).

  Next, it is determined whether the n, n + 1th is the non-compressed + repeat type (S3). That is, the flag information that is the first 1-byte (8-bit) data held in the F / F 5b-0 is referred to, and the n and n + 1 bit data are analyzed to determine whether the data is uncompressed + repeat type data. To do. In the first process, the data of the first bit and the second bit in 8 bits are referred to and it is determined whether the data is non-compressed + repeat type data.

  Here, if the data of the first bit and the second bit is non-compressed + repeat type data (S3 is YES), the process proceeds to the process shown in FIG. On the other hand, if the data of the first bit and the second bit is not uncompressed + repeat type data (S3 is NO), it is determined whether the data (flag) of the nth bit (first bit) indicates compression ( S4).

  If the data (flag) of the first bit indicates compression (S4 is YES), the process proceeds to the process shown in FIG. On the other hand, if the first bit data does not indicate compression (S4 is NO), the process proceeds to judgment (S5). That is, when the n-th bit (first bit) indicates non-compressed data, the processing after judgment (S5) is executed, the continuous non-compressed data is read to the decompression circuit 7, and decompression processing is performed.

  For example, in the determination (S5), when the n + 1th bit (second bit) indicates compressed data (S5 is YES), the nth byte (first byte) data is written to the data generation buffer 8 , N is set to n + 1 (S6, State02).

  That is, the decompression circuit 7 reads the compressed data “1” from the F / F 5b-1, and writes the compressed data “1” (however, this data is uncompressed data) to the data generation buffer 8.

  On the other hand, when the determination (S5) indicates that the n + 1 bit (second bit) is also uncompressed data (S5 is NO), the data of the n + 2 bit (third bit) is the compressed data. If the n + 2 bit (3rd bit) is also compressed data (YES in S7), the data of n to n + 1 bytes (1st and 2nd bytes) is written to the data generation buffer 8 and n Is set to n + 2 (S8, State03). That is, the decompression circuit 7 reads the compressed data “1” and “2” from the F / Fs 5b-1 and 5b-2, and the compressed data “1” and “2” (but this data is also uncompressed) to the data generation buffer 8. Data).

  Further, in the determination (S7), when the n + 2 bit (3rd bit) is also uncompressed data (S7 is NO), it is further determined whether the n + 3 bit (4th bit) data is compressed data (S9). ), If the n + 3th bit (the 4th bit) is also compressed data (YES in S9), the nth to n + 2nd byte (1st to 3rd byte) data is written to the data generation buffer 8, and n is set to n + 4 ( S10, State04). That is, the decompression circuit 7 reads the compressed data “1” to “3” from the F / Fs 5b-1 to 5b-3, and the compressed data “1” to “3” (however, this data is also uncompressed). Data).

Thereafter, similar processing is performed, and continuous uncompressed data is written to the data generation buffer 8 (S11 to S18, State05 to 08). When all the compressed data “1” to “8” are non-compressed data (NO in S17), the compressed data “1” to “8” are read from the F / Fs 5b-1 to 5b-8, and the data generation buffer The compressed data “1” to “8” are written to 8 (S19, State09). The uncompressed data written to the data generation buffer 8 is specifically written to the F / Fs 8a-1 to 8a-8 shown in FIG.
By processing in this way, continuous decompression processing of uncompressed data can be performed quickly.

  Further, in the above determination (S5, S7,... S17), it is determined whether the n value at each determination point is 8, 7,... 2, and if it is a matching numerical value, the corresponding processing (S6, S8) ,... S18) is executed. This is because there is no data (flag) to be referenced beyond the matching numerical value. Therefore, for example, in the determination (S5), when n = 8, the uncompressed data of the 8th byte is written to the data generation buffer 8 (F / F8a-8), and after the processing of (n + 1) is performed by the processing (S6) N = 9 is determined (S20), and the process returns to the process (S3). For example, in the determination (S7), when n = 7, the 7th and 8th bytes of uncompressed data are written to the data generation buffer 8 (F / F 8a-7, 8a-8), and the process of (S8) is performed as n + 2. N = 9 is determined after the operation is performed (S20), and the process returns to the process (S3). Thereafter, the same processing is performed.

  On the other hand, in the above-described determination (S4), if the nth bit (first bit) indicates compression (S4 is YES), the process proceeds to the process shown in FIG. In the flowchart shown in FIG. 10, the processing of S1 to S4 is the same processing as the flowchart shown in FIG. Therefore, the process after judgment (S4) is demonstrated. That is, in the determination (S4), if the n-th bit (first bit) indicates compression (S4 is YES), it is determined whether the upper 2 bits of the n-th compressed data is “11” (S21). If the upper 2 bits are “11” (S21 is YES), repeat type expansion processing is performed (S22, State11).

  For example, if the upper 2 bits of the second compressed data is “11”, the decompression process is performed using the immediately preceding compressed data “1”. In this case, the compressed data “1” is read from the F / F 5b-1, and the compressed data “1” is written to the data generation buffer 8 (F / F 8a-2). If the upper 2 bits of the third compressed data is “11”, the data decompression process of the previous compressed data “2” is repeated, the compressed data “2” is read from the F / F 5b-2, and the data generation buffer The compressed data “2” is written into 8 (F / F8a-3). Thereafter, corresponding to the value of n, the immediately preceding compressed data is repeatedly written in the data generation buffer 8 to perform decompression data creation processing.

  By processing in this way, when the same data as the previous data is repeated, the data expansion process can be performed efficiently. Each time the repeat type expansion process is executed, n is incremented by 1 (S24), n = 9 is determined (S25), and the process is repeated until n = 9.

  Next, even when the nth bit of the flag data indicates compression (S4 is YES), if the upper 2 bits of the nth compressed data is not “11” (S21 is NO), the pointer type decompression processing (S23, State12).

  For example, when the upper 2 bits of the nth compressed data is “10”, the nth lower 5 bits of data are referred to, the data of the match start position indicated by the upper 5 bits of data is referred to, and the corresponding Data corresponding to the byte indicated by the lower 3 bits of data from the match start position is read to the decompression circuit 7 and written to the data generation buffer 8. For example, when the lower 3 bits of data are “000”, 2 bytes of data from the match start position are written into the data generation buffer 8. If the lower 3 bits of data are “111”, 9 bytes of data from the match start position are written into the data generation buffer 8.

  By processing in this way, when the same continuous data as the previous continuous data is repeated, the data expansion process can be performed efficiently.

  Next, a description will be given of the case where the nth bit and the (n + 1) th bit data are uncompressed + repeat type data (S3 is YES) in the above-described determination (S3). In this case, the process proceeds to the process shown in FIG. In the flowchart shown in FIG. 9, the processing of S1 to S3 is the same processing as the flowchart shown in FIG. Therefore, the process after judgment (S3) is demonstrated. That is, in the determination (S3), when the nth and n + 1th bits (for example, the first and second bits) are non-compressed + repeat type data, the nth data is represented by the number of consecutive times +1 indicated by the compressed data. Are written in the data generation buffer 8 (S26).

  For example, when n = 1, the first data is written into the data generation buffer 8 (F / F 8b-2) for the number of consecutive times (one time) indicated by the compressed data. For example, when n = 2, the second data is written in the data generation buffer 8 (F / F 8b-2) for the number of consecutive times (one time) indicated by the compressed data (NO in S27 and S28). The above processing is repeatedly executed until n becomes 9 (State10, S28 is YES).

By performing processing in this way, it is possible to efficiently perform repeat type data decompression processing following uncompressed data.
The data generated by the decompression circuit 7 is input to the data generation buffer 8 (F / Fs 8a-1 to 8a-8) by the above processing, and the image data decompressed through the selectors 10a to 10d thereafter is the subsequent FIFO 9 Sent to.

FIG. 11 is a flowchart for explaining the transmission process, and explains the process of the data generation buffer controller 11. FIG. 12 is a diagram for explaining the selection logic of the selectors 10a to 10d according to the control of the data generation buffer controller 11.
First, a data write instruction from the decompression circuit 7 is determined (step (hereinafter referred to as ST) 1), and data to the subsequent FIFO 9 is selected based on the value of the counter 12 and the number of bytes of data read from the decompression circuit 7. Then, data is written to the subsequent FIFO 9 (ST2). This process is the first data transfer, and the decompression input FIFO controller 13 determines the selectors 10a to 10d to be selected according to the number of bytes to be written in the subsequent FIFO 9.

  For example, when only 1-byte data is transferred for the first time, the selector 10a is selected, and the data is transferred from the F / F 8a-1 to the dual port memory 14a (a shown in FIG. 12). When transferring 2 bytes of data for the first time, the selectors 10a and 10b are selected, and the data is transferred from the F / Fs 8a-1 and 8a-2 to the dual port memories 14a and 14b (b shown in FIG. 12). ). Similarly, the case of transferring 3 bytes of data for the first time and the case of transferring 4 bytes of data are as shown in c and d of FIG.

  Next, it is determined whether the number of bytes for writing data is “4” or less (ST3). As described above, when data of 4 bytes or less is transferred for the first time (ST3 is YES), the counter value is set to the current counter value + the number of bytes input from the decompression circuit 7 (ST5). For example, in the case of a shown in FIG. 12, the counter value of the counter 12 is “1” (0 + 1). In the case of b shown in the figure, the counter value is “2” (0 + 2). In the case of c shown in the figure, the counter value is “3” (0 + 3). In the case of d shown in the figure, the counter value is Returns to “0”.

  On the other hand, in the above determination (ST3), when the number of bytes to which data is written is “4” or more (NO in ST3), the value of the counter 12 and the data read from the decompression circuit 7 are transferred to transfer the second data. From the number of bytes, data for the subsequent FIFO 9 is selected (ST4).

  In this case, as shown in FIG. 12, for example, when transferring data of only 1 byte for the second time, the selector 10a is selected, and data of 1 byte is transferred from the F / F 8a-1 to the dual port memory 14a. (F shown in FIG. 11). When transferring 2 bytes of data for the second time, the selectors 10a and 10b are selected, and the data is transferred from the F / Fs 8a-1 and 8a-2 to the dual port memories 14a and 14b (see g shown in FIG. 11). ). The case of transferring 3 bytes of data for the first time and the case of transferring 4 bytes of data are as indicated by h and i in FIG.

  Although the above description is for the case where the counter value is “0”, the case where the counter value is “1” is as shown in FIG. 12 j, and the case where the counter value is “2” is shown in FIG. The case where the counter value is “3” is as indicated by l in FIG.

  FIG. 13 is a time chart when data is transferred from the decompression circuit 7 and data is written in the subsequent FIFO 9. Note that the example in the figure shows processing when the number of bytes read from the decompression circuit 7 is “1” bytes, “2” bytes, “3” bytes, “4” bytes,. In this case, the count value of the counter 12 is first counted up to “1” by the first “1” byte data transfer, counted up to “3” by the next “2” byte data transfer, and then the next “ It becomes “2” (3 + 3-4) by data transfer of 3 ”bytes.

  The write address counters 15a to 15d are incremented each time data is transferred to the corresponding dual port memories 14a to 14d. For example, when "3" bytes of data are transferred, the counter value of the write address counter 15a is counted. Is “2”, the counter value of the write address counter 15b is “2”, the counter value of the write address counter 15c is “1”, and the counter value of the write address counter 15b is also “1”.

  When data is transferred to all of the dual port memories 14a to 14d, the data input to the dual port memories 14a to 14d is transferred to, for example, an engine control unit (not shown). At this time, the RD address counter 16 is incremented by one.

  The comparator 17 compares the count values of the WR address counter 15d and the RD address counter 16, and outputs a Full signal or an Empty signal. The Empty signal is output when the count value of the WR address counter 15d matches the count value of the RD address counter 16, the data of the dual port memories 14a to 14d is read, and the dual port memories 14a to 14d are empty. The data generation buffer controller 11 and the decompression input FIFO controller 13 are notified. On the other hand, the Full signal is output when the count value of the WR address counter 15d plus (+) 1 matches the count value of the RD address counter 16, and data is input to all the dual port memories 14a to 14d. Output when requesting data read from the port memories 14a to 14d.

By processing as described above, when non-compressed data continues, the continuous non-compressed data can be transferred to the subsequent FIFO 9 together, and the data following the non-compressed data is the same as the previous uncompressed data. In some cases, the data decompression process can be efficiently executed by transferring the same uncompressed data to the subsequent FIFO 9 for the number of times that the same uncompressed data continues. Therefore, the compressed data can be decompressed at a higher speed.
Further, it is not necessary to change the decompression circuit, and an increase in power consumption can be suppressed.

  In the flowchart shown in FIG. 13, the case where data reading from the decompression circuit is 4 bytes or less has been described. However, in actuality, the continuation of uncompressed data or the continuation of the same data may exceed 4 bytes. As a time chart in that case, FIG. 14 shows an example in which 8-byte data continues.

  In this case, since the count value of the counter 12 repeats “8” and the write address counters 15a to 15d transfer the data every 8 bytes to the corresponding dual port memories 14a to 14d, all the write address counters 15a to 15d Repeat the same count value.

  The time chart shown in FIG. 15 shows the timing at which only the data writing speed to the subsequent FIFO 9 is doubled. In this case, it can be seen that the overall processing speed is improved as compared with the examples shown in FIGS. In other words, the entire data transfer speed can be improved only by improving the data writing speed to the post-stage FIFO 9, and this is a high-speed support for only a part of the circuit. The constraint conditions can be relaxed rather than increasing the speed, and the portion operating at a higher speed can be narrowed down, so that the influence on the power consumption can be minimized.

  In the description of the above embodiment, the output width of the first-stage FIFO 4 is 9 bytes, that is, 72 bits. As described above, this is because the flag portion is 8 bytes of encoded data. Any number of bytes may be used if the data width is such that the combined data of the flag and the encoded data portion can be read at once. Furthermore, a plurality of flags and a plurality of encoded data groups may be used.

  In the above description of the embodiment, the input and output data buses are connected to the 32-bit PCI bus. However, any access type data bus may be used.

It is a block diagram of a data decompression circuit of the printing apparatus of the present embodiment. It is a figure which shows the circuit structure of a front | former stage FIFO and a data selector. It is a figure explaining the example of a data conversion which selects 1 byte of flags, and the subsequent encoded data 8 bytes sequentially. It is a circuit block diagram explaining a decompression circuit. It is a figure explaining the data format of compression data. It is a figure which shows the circuit structure of a data generation buffer. It is a figure which shows the structure of a back | latter stage FIFO. It is a flowchart explaining an expansion | extension process. It is a flowchart explaining an expansion | extension process. It is a flowchart explaining an expansion | extension process. It is a flowchart explaining the process of a data generation buffer controller. It is a figure explaining the data which a selector selects according to control of a data generation buffer controller. It is a time chart at the time of transferring data from a decompression circuit and writing data in a subsequent FIFO. It is a time chart at the time of transferring data from the decompression circuit and writing continuous 8-byte data in the subsequent FIFO. It is a time chart at the time of doubling only the data writing speed to the post-stage FIFO.

Explanation of symbols

1 ... Data decompression circuit 2 ... CPU
3 ... Memory 4 ... Previous FIFO
5... Data selectors 5a-0 to 5a-8..Selectors 5b-0 to 5b-8..F / F
7: Decompression circuit 8: Data generation buffer 8a-0 to 8a-8, F / F
9: Post-stage FIFO
10a to 10d, selector 11, data generation buffer controller 12, counter 13, decompression input FIFO controllers 14a to 14d, dual port memories 15a to 15d, write address counter 16, read address counter 17, comparison vessel

Claims (6)

And uncompressed data, and compressed data, a first storage means for storing said compressed information of uncompressed data and the compressed data,
Decompression means for decompressing the compressed data into decompressed data;
Detecting means for detecting a sequence of the non-compressed data based on the compression information,
And restoring means for restoring together the non-compressed data consecutive Ri detected by said detecting means,
Second storage means for storing the decompressed data decompressed by the decompressing means and the decompressed uncompressed data;
And output means for outputting the expanded data and the restored the uncompressed data is stored in said second storage means,
A data decompression device comprising: And non-compressed data, a first storage means for storing the compressed data that specifies the repetition of data located immediately before, and the compressed information of the non-compressed data and the compressed data,
Decompression means for decompressing the compressed data into decompressed data;
Detecting means for detecting a state in which the compressed data based on the compression information is stored in line after the non-compressed data,
And restoring means for restoring the number of times the uncompressed data compressed data obtained by adding 1 to the repeat count to specify that specifies the repetition Ri detected by said detecting means,
Second storage means for storing the decompressed data and the restored uncompressed data ;
And output means for outputting the expanded data and the restored the uncompressed data is stored in said second storage means,
A data decompression device comprising:   The data decompression apparatus according to claim 1 or 2, wherein the compression information of the compressed data is stored in the first storage means as flag data.   The data decompression apparatus according to claim 1, 2, or 3, wherein the compressed data is stored in the first storage means continuously with the compression information. And uncompressed data, and compressed data, a process of storing and said compressed information of uncompressed data and the compressed data in the first storage means,
Processing to decompress the compressed data into decompressed data;
A process for detecting a sequence of the non-compressed data based on the compression information,
A process for restoring together the non-compressed data consecutive Ri detected by said detecting means,
A process of storing the decompressed data decompressed by the decompressing means and the decompressed uncompressed data in a second storage means;
Processing for outputting the decompressed data and the decompressed uncompressed data stored in the second storage means;
A program that causes a computer to execute. And uncompressed data, and the compressed data that specifies the repetition of data located immediately before a process of storing said compressed information of uncompressed data and the compressed data in the first storage means,
Processing to decompress the compressed data into decompressed data;
A process of detecting a state in which the compressed data based on the compression information is stored in line after the non-compressed data,
A process for restoring the number of times the uncompressed data compressed data obtained by adding 1 to the repeat count to specify that specifies the repetition Ri detected by the detection process,
A process of storing the decompressed data and the decompressed uncompressed data in a second storage unit;
Processing for outputting the decompressed data and the decompressed uncompressed data stored in the second storage means;
A program that causes a computer to execute.