JP5217570B2 - Memory device and memory control method - Google Patents

Description

  The present invention relates to a memory device, and more particularly to a memory device and a method for storing a redundant code for improving data reliability such as error correction.

  As a related technique, for example, Patent Document 1 discloses that an efficient memory between a payload and a redundancy can be obtained by dynamically changing a usable redundancy according to a change in an error rate using a variable-length error correction code. A system and method for enabling allocation is disclosed. That is, as shown in FIG. 8, the data stored by the user and the error correction code are stored in different areas, and the error correction code is variable depending on the situation. 16 bytes (bytes) per data, and a data part (201) and an ECC (Error Checking and Correcting Code or Error Corrcting (Correction) Code) part (202) are stored in separate areas, respectively. Since the section (202) has a variable length, it is possible to set a code having a high correction capability such as 2 bytes or 4 bytes in the ECC. In the example shown in FIG. 8, the ECC has a 2-byte configuration.

JP 2003-131954 A

  It is assumed that the disclosure of Patent Document 1 is incorporated herein by reference. The following is an analysis of the related art according to the present invention.

  In the memory configuration shown in FIG. 8, since the required number of ECC (error correction code) bits can be increased with respect to the number of bits of data to be stored, high correction capability is provided. Has the following problems.

  The first problem is that, when used for memory control, correction processing at the time of data read / write or when an error occurs becomes complicated, and the access speed of the memory becomes slow. The configuration of FIG. 8 cannot be realized by an extension of a general memory read / write circuit, and has a special circuit configuration. This is because, in the memory management having the configuration shown in FIG. 8, the data part and the error correction code (ECC code) part are arranged at different addresses.

  Even when reading the data part (201), it is necessary to perform memory access to both the data part (201) and the ECC part (202), and these two addresses are completely different addresses. Therefore, it cannot be read continuously. For this reason, it is necessary to access each of them individually, and it is necessary to specify a circuit for temporarily storing an address and data itself and a byte position of the read ECC code. Therefore, the configuration of FIG. 8 requires a circuit configuration different from a general circuit, and the circuit configuration becomes complicated.

  The second problem is that when the memory area storing the ECC fails, the influence range of the failure is wide, and it takes a long time to recover the data, leading to a decrease in reliability. This is because the ECC (202) is stored together in a memory area different from the data part (201). If a memory area that stores ECCs collectively fails, a plurality of ECCs cannot be read. For example, when 8 words of ECC of the data part are stored in 1 word of memory storing ECC, the worst case is a memory failure of 1 word of memory storing ECC, and the ECC of data of 8 words can be read. There will be no. Thus, the influence range for one failure is large.

  As another related technique, for example, a configuration in which a data part (301) and an ECC part (302) are stored in one word as shown in FIG. 9 is conventionally known. In this configuration, a memory can be configured with an inexpensive DIMM configured by a 72-bit general-purpose DIMM (Dual Inline Memory Module) or the like, and is frequently used. However, in the case of the configuration of FIG. 9, the number of bytes for storing the ECC code is small, and the number of bytes to be stored is limited, so that a certain level of reliability can be obtained, but this is applied to a memory with higher reliability. Can not.

  For example, when two 72-bit general-purpose DIMMs are arranged in parallel (parallel 144 bits), one word has a maximum of 16 bytes (128 bits) of data and 2 bytes (16 bits) of ECC (error correction code). This is because ECC can only be defined up to 2 bytes.

  If it is necessary to set the ECC to 4 bytes, a 72-bit general-purpose DIMM must be operated in parallel (72 x 4 bits), and the number of pins on the memory control side Increases and increases costs.

  Therefore, an object of the present invention is to provide a high-speed and high-reliability apparatus and method that can use a general-purpose DIMM product and correct data including a chip failure.

  In order to solve the above-described problems, the invention disclosed in the present application is generally configured as follows.

  According to one aspect of the present invention, means for designating the length of a redundant code for data stored in the memory, and the data and the redundant code corresponding to the data are arranged in the memory so that they exist in one word. An apparatus comprising means is provided.

  In the present invention, a configuration may be provided that includes means for storing trailer information when an address of a data storage destination of the memory reaches a predetermined value.

In one aspect of the present invention, one word corresponds to a write request for p-byte wide data and a q-byte wide redundant code (p and q are predetermined positive integers) associated with the data. And
When storing in a memory having a redundant code area having a data width of one word of r bytes (where r is a positive integer r <p) and s bytes (where s is a positive integer s <q),
The data width of one word in the memory is (r + s−q) bytes, the redundant code width is treated as q bytes,
The value ADR_PLUS × (q−s) obtained by multiplying the integer value ADR_PLUS of the value {ADR_SRC / (r + s−q)} by dividing the start address ADR_SRC of the write data by (r + s−q) and (q−s) to ADR_SRC. Calculate the added address ADR_MEM,
Among the p bytes of data, [{ADR_SRC + (r + s−q)} − ADR_MEM] bytes of data from the address ADR_MEM after the operation to the address ADR_SRC + (r + s−q) −1 are stored.
The redundant code of (q−s) bytes among the redundant code of q bytes is stored from the address {ADR_SRC + (r + s−q)}, and the remaining s bytes of the redundant code of q bytes are stored as the redundant code of s bytes. Stored in the code area,
The remaining p-[{ADR_SRC + (r + s-q)}-ADR_MEM] bytes of the p-byte data are stored from ADR_SRC + (r + s-q) + (q-s) = ADR_SRC + r, that is, from the next word. Then, in the memory to which data is written, writing is performed so that the redundant code corresponding to the data and at least a part of the data are arranged in the same word.

In the present invention, in response to a read request for data in which 1 word is p bytes wide and a q byte wide redundant code (p and q are predetermined positive integers) related to the data,
Data is read from a memory having a redundant code area having a data width of one byte of r bytes (where r is a positive integer r <p) and s bytes (where s is a positive integer s <q), When returning read data as a response,
The data width of one word in the memory is (r + s−q) bytes, the redundant code width is treated as q bytes,
The value ADR_PLUS × (q−s) obtained by multiplying the integer value ADR_PLUS of the value {ADR_SRC / (r + s−q)} by dividing (Q + s) the start address ADR_SRC of the read data by (r + s−q) is set to ADR_SRC. Calculate the added address ADR_MEM,
Of the p-byte data, [{ADR_SRC + (r + s-q)}-ADR_MEM] bytes of data are read from the calculated address ADR_MEM to the address ADR_SRC + (r + s−q) −1, and the remaining p − [{ADR_SRC + ( r + s−q)} − ADR_MEM] bytes of data are read from ADR_SRC + (r + s−q) + (q−s) = ADR_SRC + r, that is, read from the next word, and one word restores p bytes of data. ,
Among the q-byte redundant codes, a (q-s) -byte redundant code from the address {ADR_SRC + (r + s-q)} is read, and the remaining s bytes of the q-byte redundant code are read as the s-byte redundant code. Read from the code area, restore q bytes of data,
The restored one word returns p-byte data and q-byte data as read data to the request source.

  According to the present invention, there is provided a memory access method for designating the length of a redundant code for data stored in the memory and arranging the data and the redundant code corresponding to the data in the memory so as to exist in one word. The

  According to the present invention, for a redundant code of a specified length, the data and the redundant code corresponding to the data are arranged in the memory so that both exist in one word. DIMM products can be used, data correction including chip failure can be performed, and high speed and high reliability can be realized.

  The above-described present invention will be described below with reference to the accompanying drawings in order to explain in more detail. In the present invention, in accordance with the length of a designated redundant code such as ECC (error correction code), data and a redundant code corresponding to the data are arranged in a memory so that both are present in one word. . For data processing devices that require high reliability such as server devices and disk array devices for the purpose of data maintenance by performing memory correction using redundant codes such as ECC (Error Correction Code) to improve data reliability Applicable. Furthermore, according to the present invention, in a memory control circuit that can use an off-the-shelf general-purpose DIMM, it is possible to correct data including a chip failure, and an error of 8-bit correction or 16-bit correction that cannot be performed by a general general-purpose DIMM. A correction code can be applied to achieve high speed and high reliability. Hereinafter, description will be made with reference to examples.

  FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. Referring to FIG. 1, the memory device according to this embodiment includes a request input unit (1), a reply output unit (2), a correction capability setting circuit (3), an address calculation circuit (4), and data division. A synthesis unit (5), a memory control circuit (6), a memory (7), and a data restoration circuit (8) are provided.

  The correction capability setting circuit (3) defines the number of ECC (error correction code) bytes to be defined on the memory (7). The correction capability setting circuit (3) statically notifies each circuit of the correction capability. The correction capability is set via an external interface (not shown), or is set semi-fixed in the correction capability setting circuit (3).

  The address calculation circuit (4) analyzes an access address to the memory (7) that enters the memory control circuit (6) and performs an address calculation.

  The address calculation circuit (4) adds the addresses corresponding to the number of bytes notified from the correction capability setting circuit (3), and passes the address to the memory control circuit (6).

  The data division and synthesis circuit (5) analyzes the data to the memory (7) that enters the memory control circuit (6), and obtains it from the calculation results from the correction capability setting circuit (3) and the address calculation circuit (4). Based on the received information, data division / configuration change is performed.

  As shown in FIGS. 3A, 3B, and 3C, as will be described later, the data division synthesis circuit (5) performs data processing on the memory (7) including the ECC (error correction code). Save data with memory mapping.

  The memory control circuit (6) processes a read / write operation of data in the memory space designated by the address arithmetic circuit (4) with respect to the memory (7). The memory control circuit (6) controls a memory (7) such as a DIMM.

  The data restoration circuit (8) restores the data read from the memory (7) to a normal state with respect to the data request source. The data restoration circuit (8) reshapes the data stored in the memory (7) into appropriate data of the data request source, checks the validity of the data by ECC (error correction code), and performs ECC. Data restoration by (error correction code) is performed.

  The correction capability setting circuit (3) transfers the number of ECC (error correction code) bytes to each circuit. For example, when two general-purpose DIMMs are used in parallel, 16 bytes of data and 2 bytes of ECC can be mounted. Therefore, in the correction capability setting circuit (3), an ECC (error correction code) byte The number is set to a value of 2 bytes or more. In the error correction setting circuit (3), the number of ECC (error correction code) bytes is set dynamically without dynamically changing.

  In this embodiment, when the ECC byte length is 4 bytes, the correction capability setting circuit (3) transmits “4” to each circuit.

  A case where a data transfer request (20) from the data transfer source (request request source) to the memory is input to the request input unit (1) will be described.

  In the address arithmetic circuit (4), a value obtained by subtracting “2” from “4” supplied from the correction capability setting circuit (3) (“2” is the ECC storage portion of the general-purpose DIMM constituting the memory (7)). Address conversion is performed using (corresponding to 2 bytes of capacity). The address conversion is as follows.

  ADR_PLUS = INT (ADR_SRC / (data length of one word (18 bytes−4))) (1)

  ADR_MEM = ADR_SRC + (ADR_PLUS * (ECC byte length−2)) (2)

However, in (1) and (2)
ADR_SRC is the address of the transfer source (the address when actually trying to write to the memory),
ADR_PLUS is a differential address for conversion to an actual memory address,
ADR_MEM is the access address on the actual memory,
It is.

  From the above equations (1) and (2), the address calculation circuit (4) calculates an address ADR_MEM to be accessed to the memory (7).

  The data dividing / synthesizing circuit (5) shifts the data by the value of the lower 4 bits of the address ADR_MEM (for example, shifts the data to the upper byte side), and then divides by the value of 1 word stored in the memory (7). . This division is performed up to the number of bytes of one word in the maximum memory minus 2, that is, 16-2 = 14 bytes. In one word, the divided data and the ECC (error correction code) of the data are always included. Both are paid. That is, the sum of the number of bytes of divided data (14 bytes) and the number of bytes of ECC (error correction code) (4 bytes) always fits in one word (= 16 bytes + 2 bytes) of DIMM.

  As described above, in this embodiment, since the byte width of the ready-made DIMM (1 word = 16 bytes + 2 bytes) is not exceeded, an inexpensive memory can be used.

  In the data division / synthesis circuit (5), since the ECC (error correction code) is arranged at the same word position as the data, the memory control circuit (6) can access the data and the ECC ( Error correction code).

  In the present embodiment, since the original data is divided, it is necessary to access a plurality of word positions. Generally, however, in DDR2-DIMM and other memories, continuous addresses are also used. Supports burst transfer that enables a series of operations (multiple accesses) in one process. When the data is divided into a plurality of continuous words by the burst transfer process, high-speed data transfer is performed.

  The operation of this embodiment will be outlined below. The request input unit (1) receives a request (command) (20) from a data request source (request request source). The request (20) entering the request input unit (1) is not particularly limited, but a general-purpose interface such as a general PCI (Peripheral Component Interconnect) -X bus or PCI-Express is used.

  The correction capability setting circuit (3) is a circuit that presents the number of ECC (error correction code) bytes, but has a value that can be changed statically because the value is stored semi-fixed internally in the external interface. . A case will be described in which a DIMM in which one word is 16 bytes (data) +2 bytes (ECC) is used, and ECC (error correction code) is 4 bytes. In this case, 14 bytes (data) +4 bytes (ECC).

  The request input unit (1) divides the memory access requested address (21) and data (31), and the address (21) is transferred to the address arithmetic circuit (4). The processing image of the request request source is 16 bytes (data) +4 bytes (ECC) as shown in FIG. For example, it is assumed that the address is ADR_SRC = 0020h (where h indicates hexadecimal expression).

  When the address arithmetic circuit (4) receives the address (21) (ADR_SRC = 0020h) from the request input unit (1), the number of ECC (error correction code) code bytes received from the correction capability setting circuit (3) = Based on 4 bytes, the address is calculated from the equations (1) and (2).

  From ADR_SRC = 0020h, ADL_PLUS = 0020h / (18-4) = 32/14 = 2

  ADR_MEM = 0020h + (2 * (4-2)) = 0024h

  The data division synthesis circuit (5) receives the calculation result (ADR_MEM = 0024h) from the address calculation circuit (4), and performs the division / shift operation on the data according to the lower 4 bits information (= 0100b) of the address (ADR_MEM). And adjust to the target data. In this case, a total of 16 bytes of data from the original source address ADR_SRC = 0020h to the address 002Fh is shifted to the upper 4 bytes side. The byte data at address 0020h moves to address 0024h bytes. As shown in FIG. 3B, the original 16-byte data is divided into 10-byte data from address 0024h to address 002Dh and 6-byte data from address 0030h to address 0035h after the shift. Of the original 4-byte ECC, 2 bytes are stored in 2 bytes of addresses 002Eh and 002Fh, and stored in 2 bytes of DIMM corresponding to 16-byte data from 0020h, as shown in FIG. Stored as E2.

  As shown in FIG. 3C, the original data width: 16 bytes and ECC: 4 bytes (D2, E2) are stored in a 1 word data width: 16 bytes, ECC: 2 bytes DIMM. It is converted into a format of width: 14 bytes and ECC: 4 bytes (18 bytes in total) and written. In FIG. 3, the same data conversion, data division, original data width: 16 bytes, ECC: 4 bytes (D0, E0), (D1, E1), (D3, E3). The memory storage form is shown.

  The memory access operation of this embodiment shown in FIG. 3 is as follows. One word has a data width of 1 byte in response to a write request for data of p bytes wide (p = 16 in FIG. 3) and a redundant code (ECC) of q bytes wide (q = 4) related to the data. When storing in a memory having an ECC area of r bytes (r = 16) and s bytes (s = 2), the data width of one word in the memory is (r + s−q) bytes (16 + 4-2 = 14), the ECC width is handled as q bytes (4 bytes), and the leading value ADR_SRC of the write data is divided by (r + s−q) to the integer value ADR_PLUS of {ADR_SRC / (r + s−q)} (q− An address ADR_MEM obtained by adding a value ADR_PLUS × (q−s) multiplied by s) to ADR_SRC is calculated. Of the p-byte (16-byte) data (D2), [{ADR_SRC + (r + s-q)}-ADR_MEM] bytes of data from the calculated address ADR_MEM to the address ADR_SRC + (r + s-q) -1 are stored. (Q-s) bytes (2 bytes) of q-byte ECC is stored from address {ADR_SRC + (r + s-q)} (0020h + 000Eh), and the remaining s bytes of q-byte ECC are stored in s bytes Store in the ECC area. The remaining p-[{ADR_SRC + (r + s-q)}-ADR_MEM] bytes (6 bytes) of the p-byte data is converted into ADR_SRC + (r + s-q) + (q-s) = ADR_SRC + r, that is, Store from word. In this way, writing is performed so that the ECC corresponding to the data is arranged in the same word as the data in the data write destination memory.

  When the data transfer request source request (20) is to read data from the memory, the data restoration circuit (8) receives the data read from the memory control circuit (6).

  The data restoration circuit (8) checks the read ECC and corrects the error when a correctable error occurs. At the same time, the address calculation result obtained from the address calculation circuit (4). Data is restored based on (24), and a reply (30) for the request source is generated by the reply output unit (2).

  FIG. 2 is a flowchart showing a write operation in one embodiment of the present invention. The number of ECC bytes is set in advance (step S1). As described above, this setting is not dynamically changed but is set statically when existing as a system. Here, the number of bytes of ECC is 4 bytes. That is, in this embodiment, it is not assumed that the ECC byte length is dynamically varied.

  When a request is received from the data request source (step S2), the address calculation circuit (4) calculates the address ADR_MEM according to the above equations (1) and (2) (step S3). The address calculation in the address calculation circuit (4) is an address calculation for changing the data portion from 16 bytes per word to 14 bytes per word. By calculating and adding the difference to the request source address Indicates the address position when one word is 14 bytes.

For example, when an access to the request source address 10h occurs, the internal address ADR_MEM is 12h from the above equations (1) and (2). That is,
ADR_PLUS = 10h / 14 = 16/14 = 1
ADR_MEM = 10h + 1 * (4-2) = 12h

  Further, when an access to the request request source address 0020h occurs, the address ADR_MEM of the address arithmetic circuit (4) is 0024h. The address ADR_MEM is incremented by 02h every time 14 bytes are added.

  As for the data, when access to the address 0020h of the request request source occurs, it is necessary to shift (shift) 4 bytes as the address, so the data is rounded as 14 bytes per word while shifting the data by 4 bytes ( Step S4).

  Further, the ECC at this time is not processed as it is, and is added to the above 14 bytes to generate data as 18 bytes per word (step S5).

  Writing to the memory (7) is performed (step S6).

  As a result, the address and the data position can be matched, and data can be written into the memory using a general memory circuit.

  FIG. 4 is a flowchart for explaining the read operation according to the embodiment of the present invention. FIG. 5 is a diagram for explaining the data and ECC format of the memory read operation. FIG. 5A is a processing image of the request request source as in FIG. In the following, it is assumed that the request request source makes a read request for data (D2, E2) at address (ADR_SRC) 0020h.

  In FIG. 4, the step S11 for setting the ECC byte width, the step S12 for receiving a request, and the step S13 for calculating an address are the same as steps S1 to S3 for a write operation, and thus description thereof is omitted.

  In the read operation, using the address ADR_MEM (0024h) calculated in step S13, as shown in FIG. 5B, data (16 bytes) D2 and ECC (4 bytes) E2 are read from the memory (7). Perform (step S14).

  Then, the data is shifted to the position indicated by ADR_SRC (step S15). In this case, first, 10-byte data from ADR_MEM = 0024h to 002Dh is shifted by 4 bytes to the lower side.

  Further, in order to restore from 14 bytes to 16 bytes per word, as shown in FIG. 5C, the request request source is concatenated with data of the next word (6-byte data from 0030h to 0035h). Reply data to is generated (step S16).

  Data is replied to the request request source (step S17).

  Further, in the above processing, it is not necessary to regenerate ECC or regenerate data, and the circuit configuration is simplified.

  FIG. 6 is a diagram showing the configuration of the second exemplary embodiment of the present invention. In this embodiment, a trailer generation circuit (10) is added to the configuration of FIG. In the calculation result of the address calculation circuit (4), the trailer generation circuit (10) is moved to embed a sector number, a flag for each processing, etc. in a certain block unit.

  The trailer generation circuit (10) operates when the address operation result becomes a constant value, and embeds the trailer data in the data by embedding the sector number and the like written in the memory (7).

  FIG. 7 shows a case where data is stored in a data string of 14 bytes per word and 4 bytes of ECC. This shows the write state (103) to the memory with respect to the data format (101) from the request request source. When the data is realigned to 1 word = 14 bytes, the trailer ( TRL) (104).

  The trailer (TRL) (104) can be used to insert a CRC (Cyclic Redundancy Check) operation of D0 to D6, or to set D0 to D6 as one sector and embed a sector number. 104) is embedded in the memory (7). By embedding CRC in the trailer (TRL) (104), a check by ECC and a check by CRC and a double check can be performed, and a highly reliable memory device can be constructed.

  The operational effects of the present embodiment will be described. According to the present embodiment, since the bit width of ECC (error correction code) can be arbitrarily set, an ECC code of 4 bytes or more such as 4 bytes or 8 bytes can be mounted, and the correction capability of the memory is improved. Thus, a highly reliable memory device can be realized.

  In data reading / writing, data and error correction codes such as ECC are stored at the same word position, so that the above-described effects can be expected, but the circuit can be constructed with a simple circuit configuration and is inexpensive. Can be provided.

  Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

It is a figure which shows the structure of the implementation example of this invention. It is a flowchart of the write operation of the memory in one implementation example of the present invention. It is a figure explaining the write-in operation in one implementation example of the present invention. It is a flowchart of the read of the memory in one implementation example of the present invention. It is a figure explaining read operation in one example of realization of the present invention. It is a figure which shows the structure of the other implementation example of this invention. It is a figure explaining the preservation | save form of the memory in the other Example of this invention. It is a figure explaining the preservation | save form of the memory in related technology 1. FIG. It is a figure explaining the preservation | save form of the memory in related technology 2. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Request input part 2 Reply output part 3 Correction capability setting circuit 4 Address arithmetic circuit 5 Data division synthesis circuit 6 Memory control circuit 7 Memory 8 Data restoration circuit 10 Trailer generation circuit 20 Instruction (address, data, etc.) from request request source
21 Request address 22 Number of bytes of ECC code from correction capability setting circuit 23 Address operation result 24 Address operation result 26 Write data and ECC code 27 Read data and ECC code 28 Memory access address and data 29 Restored data 30 Request request source Reply data to be returned 31 Write data 101 Data format 102 Write data 103 for split generation processing ECC data 104 Trailer 201 Data portion 202 ECC portion (ECC code)
301 Data 302 ECC part (ECC code)

Claims (7)

Means for specifying the length of the redundant code for the data stored in the memory;
Means for arranging in a memory such that data and a redundant code corresponding to the data are present in one word;
With
In response to a write request for 1 byte of data having a p-byte width and a q-byte-wide redundant code (p and q are predetermined positive integers) associated with the data,
When storing in a memory having a redundant code area having a data width of one word of r bytes (where r is a positive integer r <p) and s bytes (where s is a positive integer s <q),
The data width of one word in the memory is (r + s−q) bytes, the redundant code width is treated as q bytes,
The value ADR_PLUS × (q−s) obtained by multiplying the integer value ADR_PLUS of the value {ADR_SRC / (r + s−q)} by dividing the start address ADR_SRC of the write data by (r + s−q) and (q−s) to ADR_SRC. Means for calculating the added address ADR_MEM;
Among the p bytes of data, [{ADR_SRC + (r + s−q)} − ADR_MEM] bytes of data from the address ADR_MEM after the operation to the address ADR_SRC + (r + s−q) −1 are stored.
The redundant code of (q−s) bytes among the redundant code of q bytes is stored from the address {ADR_SRC + (r + s−q)}, and the remaining s bytes of the redundant code of q bytes are stored as the redundant code of s bytes. Stored in the code area,
The remaining p-[{ADR_SRC + (r + s-q)}-ADR_MEM] bytes of the p-byte data are stored from ADR_SRC + (r + s-q) + (q-s) = ADR_SRC + r, that is, from the next word. Means to
The memory device, wherein the data is written so that the redundant code corresponding to the data and at least a part of the data are arranged in the same word.   The memory device according to claim 1, wherein the redundant code includes an error correction code.   3. The memory device according to claim 1, further comprising means for storing trailer information when an address of a data storage destination of the memory reaches a predetermined value.   4. The memory device according to claim 3, wherein the trailer information includes CRC (Cyclic Redundancy Code) information or sector information. In response to a read request for data in which 1 word is p bytes wide and a q byte wide redundant code (p and q are predetermined positive integers) related to the data,
Data is read from a memory having a redundant code area having a data width of one byte of r bytes (where r is a positive integer r <p) and s bytes (where s is a positive integer s <q), When returning read data as a response,
The data width of one word in the memory is (r + s−q) bytes, the redundant code width is treated as q bytes,
The value ADR_PLUS × (q−s) obtained by multiplying the integer value ADR_PLUS of the value {ADR_SRC / (r + s−q)} by dividing (Q + s) the start address ADR_SRC of the read data by (r + s−q) is set to ADR_SRC. Means for calculating the added address ADR_MEM;
Of the p-byte data, [{ADR_SRC + (r + s-q)}-ADR_MEM] bytes of data are read from the calculated address ADR_MEM to the address ADR_SRC + (r + s−q) −1, and the remaining p − [{ADR_SRC + ( r + s−q)} − ADR_MEM] bytes of data are read from ADR_SRC + (r + s−q) + (q−s) = ADR_SRC + r, that is, read from the next word, and one word restores p bytes of data. ,
Among the q-byte redundant codes, a (q-s) -byte redundant code from the address {ADR_SRC + (r + s-q)} is read, and the remaining s bytes of the q-byte redundant code are read as the s-byte redundant code. Means for reading from the code area and restoring q bytes of data,
The memory device according to claim 1, wherein the restored one word returns p-byte data and q-byte data as read data to the request source. In response to a write request for 1 byte of data having a p-byte width and a q-byte-wide redundant code (p and q are predetermined positive integers) associated with the data,
When storing in a memory having a redundant code area having a data width of one word of r bytes (where r is a positive integer r <p) and s bytes (where s is a positive integer s <q),
The data width of one word in the memory is (r + s−q) bytes, the redundant code width is treated as q bytes,
The value ADR_PLUS × (q−s) obtained by multiplying the integer value ADR_PLUS of the value {ADR_SRC / (r + s−q)} by dividing the start address ADR_SRC of the write data by (r + s−q) and (q−s) to ADR_SRC. Calculate the added address ADR_MEM,
Among the p bytes of data, [{ADR_SRC + (r + s−q)} − ADR_MEM] bytes of data from the address ADR_MEM after the operation to the address ADR_SRC + (r + s−q) −1 are stored.
The redundant code of (q−s) bytes among the redundant code of q bytes is stored from the address {ADR_SRC + (r + s−q)}, and the remaining s bytes of the redundant code of q bytes are stored as the redundant code of s bytes. Stored in the code area,
The remaining p-[{ADR_SRC + (r + s-q)}-ADR_MEM] bytes of the p-byte data are stored from ADR_SRC + (r + s-q) + (q-s) = ADR_SRC + r, that is, from the next word. And
A memory control method for performing writing so that a redundant code corresponding to the data and at least a part of the data are arranged in the same word in the memory to which data is written. In response to a read request for data in which 1 word is p bytes wide and a q byte wide redundant code (p and q are predetermined positive integers) related to the data,
Data is read from a memory having a redundant code area having a data width of one byte of r bytes (where r is a positive integer r <p) and s bytes (where s is a positive integer s <q), When returning read data as a response,
The data width of one word in the memory is (r + s−q) bytes, the redundant code width is treated as q bytes,
The value ADR_PLUS × (q−s) obtained by multiplying the integer value ADR_PLUS of the value {ADR_SRC / (r + s−q)} by dividing (Q + s) the start address ADR_SRC of the read data by (r + s−q) is set to ADR_SRC. Calculate the added address ADR_MEM,
Of the p-byte data, [{ADR_SRC + (r + s-q)}-ADR_MEM] bytes of data are read from the calculated address ADR_MEM to the address ADR_SRC + (r + s−q) −1, and the remaining p − [{ADR_SRC + ( r + s−q)} − ADR_MEM] bytes of data are read from ADR_SRC + (r + s−q) + (q−s) = ADR_SRC + r, that is, read from the next word, and one word restores p bytes of data. ,
Among the q-byte redundant codes, a (q-s) -byte redundant code from the address {ADR_SRC + (r + s-q)} is read, and the remaining s bytes of the q-byte redundant code are read as the s-byte redundant code. Read from the code area, restore q bytes of data,
7. The memory control method according to claim 6 , wherein the restored one word returns p-byte data and q-byte data to the request source as read data.

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