JPH11212873A - Operating method for computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the high secrecy for every memory system or memory chip just with addition of a simple circuit by using a means which decides an address where the overhead data are first detected among those block addresses by a secret algorithm within a page that is first read out of every block. SOLUTION: When a power supply is turned on, a memory system reads the head pages out of all blocks. At the same time, the head address of the data on the head page of every block is calculated by means of a secret algorithm A 4a. Then a block management table is produced from the head page data on the block. Furthermore, the original data are read out for calculating the head addresses of data on the following pages and stored (in an internal RAM of a CPU 3, for example). Then the commands of sector read, sector write, etc., are executed. In this command execution mode, the data head address of every page is calculated by means of the algorithm A 4a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a processor and a method of operating a computer system including a memory system using a nonvolatile memory. More specifically, an ATA card, SSFDC (Solid St)
ate Floppy Disk Card Foru
m) In a computer system using a card, an operation method of a computer system with higher secrecy is provided.

[0002]

2. Description of the Related Art FIG. 16 shows an internal data structure of a certain block 170 according to a conventional method. Here, block 170 is divided into N pages. Generally 1
Page is 512 bytes of data transfer unit from host
It corresponds to. 171 is the first page of the block 170 located at the first address, 172 is the next page, and 173 is the last page located at the last address. The page is composed of M bytes, and contains user data 175 and overhead data 177 inside the page. User data 175 and overhead data 177 are L bytes and M, respectively.
-Size of L bytes. As shown in FIG. 16, the overhead data is usually located at the end of each page, and the user data section and the overhead section are clearly divided.

[0003]

In the conventional method, the overhead data is always located at the end of each page, and the user data section and the overhead section are clearly divided.

[0004] This is advantageous in that ECC processing is easy and management data can be easily searched. However, if you look directly into the memory, the contents may be easily analyzed. Therefore, to achieve a high level of confidentiality,
Complex and sophisticated encryption was required. I / f with host
Some people think that confidentiality should be provided, but that is not enough. There is a risk that the memory chip will be removed and analyzed alone. Also, for example, SSFDC (Soli
d State Floppy Disk Card
Since the card proposed by Forum does not include a flash memory, data to be written to the flash memory in the SSFDC card must be encrypted in order for a system using the card to have confidentiality. In addition, in order to add a copy protection function and a function of partially preventing reading and writing in the future, the confidentiality of management data stored in each page unit becomes more important. However, conventional methods are not suitable for providing a high degree of confidentiality.

[0005]

According to the method of operating a computer system according to the first aspect of the present invention, after the memory system is turned on, in each block, the overhead data is firstly read in the page P1 to be read first in each block. It is characterized by having means for determining the appearing address A1 from the address of the block by a secret algorithm. According to the present invention, by adding a simple circuit, it is possible to obtain a high degree of secrecy in a memory system or a memory chip unit.

In the method for operating a computer system according to the second aspect of the present invention, the page P1 to be read first is read in each block after the memory system is turned on.
A means for determining a plurality of candidates for the address A1 in which the overhead data first appears from the address of the block by using a secret algorithm, and determining a correct address from the plurality of candidates for the address using ECC. It is characterized by. According to the present invention, by adding a simple circuit, it is possible to obtain a high degree of secrecy in a memory system or a memory chip unit.

According to a third aspect of the present invention, the page P1 to be read first is read in each block after the power of the memory system is turned on.
First, a special pattern determined by a secret algorithm from an address of the block is written in an address A1 where the overhead data appears first, and a means for determining the address A1 by detecting the pattern is provided. Features. According to the present invention, by adding a simple circuit, it is possible to obtain a high degree of secrecy in a memory system or a memory chip unit.

According to the method for operating a computer system according to the fourth aspect of the present invention, the addresses A0 and P0 of the page P1 to be read first after the memory system is turned on.
1 is characterized in that it has means for determining the address A1 where the overhead data first appears in the management data dedicated data. According to the present invention, by adding a simple circuit, it is possible to obtain a high degree of secrecy in a memory system or a memory chip unit.

According to a fifth aspect of the present invention, in the method for operating a computer system, the J
After converting the temporary code of J + K bits composed of bits and K bits composed of the overhead data into a different J + K bit code, the data is written to a page, the data read from the page is divided into J + K bits, and the original J + K By performing inverse conversion to bit data, a high degree of secrecy can be obtained for each memory system or memory chip.

In the method of operating a computer system according to claim 6 of the present invention, after the memory system is turned on, in each block, an address at which overhead data appears first in a page other than a page to be read first is stored in the memory system. After the power is turned on, in each block, an address at which the overhead data first appears in a page to be read first, or a secret algorithm is determined based on the overhead data. According to the present invention, by adding a simple circuit, it is possible to obtain a high degree of secrecy in a memory system or a memory chip unit.

According to a seventh aspect of the present invention, in the method of operating a computer system, the order of data from a head address of a page to an address at which overhead data appears first is reversed. According to the present invention, it is a simple method, but the analysis is more difficult because the data at the head of each page and the head of the user data are different, and it is possible to obtain high confidentiality in a memory system or a chip unit. Become.

According to the method of operating a computer system of the present invention, the overhead data in the page is divided and arranged in a plurality of parts, and the arrangement method is determined by a secret algorithm. I do.
According to the present invention, although it is a simple method, the arrangement pattern of the overhead data can be considered innumerably, so that the analysis becomes very difficult, and it is possible to obtain a high degree of secrecy in a memory system or a chip unit. .

According to a ninth aspect of the present invention, there is provided a method of operating a computer system, wherein write data is received from a processor to a write buffer and an ECC operation is performed at the same time. According to the present invention, since ECC data has already been calculated at the time of writing to a memory, overhead data can be arranged at an arbitrary position without reading extra memory.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG.
10 is an example of a memory system according to the inventions described in 2, 7, and 9. The configuration will be described.

The memory system shown in FIG. 1 includes an interface 1 with a processor, a read / write buffer 2 used for transmitting / receiving data to / from the processor, a one-chip CPU 3 for controlling the memory system,
Secret algorithm A4a, secret algorithm B4b, F
ECC for ensuring the reliability of data in flash memory
Circuit 5, interface with Flash memory 6,
It comprises a flash memory 7. Here, the flash memory is a nonvolatile floating gate memory array generally used widely in ATA cards and the like.
One.

The memory system sends and receives processor data and commands through an interface 1 with the processor. Interface with processor 1
Is generally PCMCIA.

The read / write buffer 2 temporarily stores write data when writing from the processor,
When reading data from the processor, data read from the Flash memory is stored. Actually, the read / write buffer 2 exists inside the RAM which the one-chip CPU 3 can directly read and write.

The one-chip CPU 3 has a built-in ROM for storing programs and a RAM for work. Further, a DMA controller used for data transfer between the interface 1 with the processor and the read / write buffer 2 or data transfer between the read / write buffer 2 and the flash memory 7 is also included. The one-chip CPU 3 analyzes commands from the processor, controls read / write of the flash memory, and performs a part of encryption processing.

The secret algorithm circuit 4 is used for calculating the head data address of each sector. The ECC circuit 5 has functions of error correction and error detection in order to increase the reliability of data in the memory.

The flash memory 7 consists of a single chip or a plurality of chips.

FIG. 4 shows the flash used in this embodiment.
2 shows a data format inside the memory 7. FIG.
Indicates the data structure inside one block 40 that can be erased at one time. One block 40 is divided into N pages. Generally, one page corresponds to 512 bytes of a data transfer unit from the processor. 41 is the first page of the block 40 located at the first address, 42 is the next page, and 43 is the last page located at the last address. The page is composed of MByte. User data 4 inside the page
8, 47 and overhead data 46 are included, and the present invention is characterized in that these two pieces of information are mixed. 44 is the head position of the overhead data 46;
This is an address indicating the number of bytes. An address 45 indicates the head position of the overhead data of the next page 42. These locations change from page to page, which makes analysis of management data difficult and increases the confidentiality of the memory system.

(Operation of Embodiment 1) First, FIG. 15 shows an outline of the overall flow of the processing of the memory system. First, when the power is turned on, the memory system performs processing 150 for reading the first page of all blocks. At this time, Example 1
Then, using the secret algorithm A4a, the head address of the data of the head page of the block is calculated.

FIG. 22 shows a simple example of the secret algorithm A. Flash to create multiple address candidates
A random value is generated from a table by combining the lower order of the physical address of the block and a constant (0 to 3). Further, randomization is performed by simple calculation. At the time of writing, an address is selected according to the number of times of writing after POWEROn. FIG. 23 shows a case where this algorithm is realized by hardware. It is desirable that these processes be performed by hardware in consideration of the performance of a CPU which is usually used, but can be realized by a relatively simple circuit as shown in FIG.
(Multiplication is realized by an adder).

Next, a block management table is created from the head page data of the block read in 150, and the original data for calculating the head address of the data of the subsequent pages is read out (for example, the internal R
A process 151 for storing (in AM) is performed. The original data for calculating the head address of the data of the subsequent pages may be the head address of the data of the head page of the block, or may be included in one of the management data of the head page of the block. The head address of the data of the top page of the block is also stored (for example, in the internal RAM of the CPU 3) because it is used later. The block management table is an address (eg, Logica) of user data indicated by a command from the processor.
l Block Address or the head, cylinder, and sector numbers) and the actual block addresses of the Flash memory.

Next, command processing 152 such as sector read and sector write is executed. When executing a command to read / write the flash memory such as a sector read or a sector write, the data head address of each page is calculated by the secret algorithm 4a.

Next, a more detailed processing flow will be described.

FIG. 9 shows in more detail the procedure for reading the first sector of a block in the process 150.
First, a process 108 of calculating a candidate for the head address of data from the address of the Flash memory by the secret algorithm 4 is executed. Here, n + 1 address candidates are STCDADR0 to STCDADRn. The number of candidates for the start address may not be a plurality, but it is desirable to have a plurality of candidates to make analysis more difficult, and to select arbitrarily.

Next, a process 109 for reading data by STCDADR0 is performed. This reading procedure is the same as the reading procedure of other pages. This will be described later in detail. Next, it is checked whether the ECC of the read data is correct. If it is correct, it indicates that the head address has been correctly selected, and the reading process of the head sector of the block is terminated. If not correct, a process 110 of reading data from the next address STCDADR1 is performed. Similarly, if the ECC is not correct, the next address candidate is used. If all the address candidates are not correct, the block is defective and stored as a bad block and is not used in the subsequent processing.

FIG. 7 shows the ECC generation processing, which is the first half of the sector writing, included in the processing 152, in more detail. First, a process 100 for transferring data from the processor to the memory system is performed. The data transfer unit may be every word or every byte. Then E
The calculation of CC is performed for each data transfer unit. In a conventional memory system, the ECC operation uses data as Flash
h was performed while writing to the memory. In the present invention, user data 48 and 47 and overhead data 4
Since the writing is performed with the number 6 mixed, the ECC operation cannot be performed during the writing. Therefore, almost at the same time as the processing 100 of data transfer from the processor to the memory system,
The CC processing 101 is performed. Next, data write processing 102 is performed on the read / write buffer 2. However, these processes 100, 101, and 102 are performed almost simultaneously in hardware. The above processing is performed in units of data transfer from the processor (for example, 512 bytes).
e), and the process proceeds to the next process of writing from the read / write buffer 2 to the flash memory.

FIG. 11 shows the writing process to the flash memory in more detail. First, a process 118 of calculating the head address of the data of each sector from the original data for calculating the head address of the data by the secret algorithm B4b is performed.

FIG. 24 shows a simple implementation example of the secret algorithm B. A random value is written in the original data according to the number of times of writing after POWERON. Therefore, randomizing this value again is based on the secret algorithm A
For when was decrypted. In this algorithm,
The original data is randomized to first generate an address where overhead data appears.

Next, processing 1 for setting [sector data start address + read / write buffer 2 start address] as the DMA start address of the DMA controller
Perform step 19. Next, the DMA transfer address change is decr
The processing 120 for setting the element is performed. This is to prevent the top of the page from being coincident with the top of the user data and to reverse the arrangement of the data in the first half of the user data. This makes it difficult to predict the beginning of the data on each page.

Next, processing 121 for transferring the data in the read / write buffer 2 to the start address of the sector data
Perform Next, a process 122 for transferring overhead data is performed. In this embodiment, the overhead data of each page is stored together at one location. Next, processing 12 for transferring the remaining user data
Execute 3. As for the remaining user data, the order of the data may be reversed as in the first half of the user data, or may be left as it is.

FIG. 13 shows the reading process from the Flash memory in more detail. First, in the same manner as the write process, a process 131 of calculating the head address of the data of each sector from the original data for calculating the head address of the data by the secret algorithm B4b is performed. Next, [the start address of the data of the sector + the start address of the read / write buffer 2] is set to D of the DMA controller.
Processing 132 for setting the MA start address;
A change 133 in the A transfer address executes a process 133 for setting it to decrement. This is because the first half of the user data is written in reverse order. Next, a process 134 of transferring the data of the read / write buffer 2 to the head address of the data of the sector is executed. Next, a process 135 for transferring the overhead data is executed. Next, a process 135a for transferring the remaining user data is executed.

FIG. 8 shows the ECC generation processing at the time of sector reading in more detail. First, hardware (or software) setting processing 1 for selecting whether data to be read is user data or overhead data 1
Execute 03. This is actually performed simultaneously with the processing of FIG. 13 described above, and can be easily set by software. Next, the hardware performs a process 104 of storing the data in the read / write buffer 2 if the user data is set, and a process 1 of transferring the data to the overhead area if the overhead data is set.
Perform 05. 105, the management data is stored in the management data area, and the ECC data is stored in the ECC area (R
AM or a register). The ECC calculation is executed only in the process of 104. 104, 10
It is appropriate that the processing of step 5 is performed by hardware, but processing by software is also possible.

User data is stored in sector units (512 B
When it becomes (yte), the reading is terminated and the ECC is checked. If the ECC is correct, the process proceeds to the next process (data transfer to the processor). If the ECC is not correct, error processing such as error correction is performed.

(Embodiment 2) FIG. 2 shows an example of a molly system according to the third aspect of the present invention. The configuration will be described.

The memory system shown in FIG. 2 includes an interface 10 with a processor, a read / write buffer 11 used when transmitting / receiving data to / from the processor, and a one-chip CPU for controlling the memory system.
12, secret algorithm A13a, secret algorithm B
13b, an ECC circuit 16 for ensuring the reliability of the data of the flash memory, an interface 18 with the flash memory, a flash memory 19, and a flash memory for reading and writing data of the flash memory.
Descramble Scrambler / Des
Crawler 17, used when writing or reading the head of data on the first page of a block,
It comprises a random number generation circuit 14 and a head pattern detection circuit 15.

Reference numerals 11, 12, 16, 18, and 19 are the same as 2, 3, 5, 6, and 7 in FIG. The secret algorithm B13b is the same as the secret algorithm B4b in FIG.

FIG. 5 shows the flash used in this embodiment.
2 shows a data format inside the memory 19. FIG. 5 shows the data structure inside one block 50 that can be erased at one time. The physical configuration inside one block 50 is the same as that of one block 40. 51 is the first page of the block 50 located at the first address, 52 is the next page, and 53 is the last page located at the last address. The page is composed of MByte. The page contains user data 59 and 57, overhead data 56, and a leading pattern 58 which is a part of the data.
The feature is that two pieces of information, ie, 9, 57 and overhead data are mixed. Reference numeral 54 denotes an address indicating the number of bytes at the head of the overhead data 46. 55 is an address indicating the head position of the overhead data of the next page 52. These locations change from page to page, which makes analysis of management data difficult and increases the confidentiality of the memory system.

(Operation of Second Embodiment) First, FIG. 15 shows an outline of the overall flow of the processing of the memory system. First, when the power is turned on, the memory system performs processing 150 for reading the first page of all blocks. At this time, in the second embodiment, the head of the data of the first page of the block is Fl
Read the data from the Ash memory (Descra
(After mble) is checked, and a special pattern is detected by searching by the leading pattern detection circuit 15.

Next, a block management table is created from the head page data of the block read in 150, and the original data for calculating the head address of the data of the subsequent pages is read out (for example, the internal R
A process 151 for storing (in AM) is performed. The original data for calculating the head address of the data of the subsequent pages may be the head address of the data of the head page of the block, or may be included in one management data of the head page of the block. Since the head address of the data of the first page of the block is also used in the subsequent pages, (for example, C
(To the internal RAM of PU3).

Next, command processing 152 such as sector read and sector write is executed. In execution of a command for reading / writing the flash memory such as a sector read / sector write, a secret algorithm B13b
To calculate the data head address of each page.

Next, a more detailed processing flow will be described.

FIG. 10 shows in more detail the procedure for reading the first sector of a block in the process 150. First, a process 112 of calculating the head pattern of data from the address of the Flash memory by the secret algorithm A13a is executed. Next, read 1 word or 1 byte at a time from Flash memory.
Then, a series of processes 113, 114, and 115 for performing a ramble and checking the coincidence with the above-mentioned leading pattern are performed. This pattern search is performed by the leading pattern detection circuit 15. When the patterns match, processing 116 for reading data of one page is performed. Normally, the head pattern is not at the head of the page, so after reading from the head pattern to the end of the page, the head pattern is read again from the head. Next, the ECC of the data for one page is checked to confirm that the leading pattern is correct. Since the head position of the data in the first sector of the block is determined at random, it is difficult to analyze. The pattern also changes for each block.

As described above, the method of detecting the head of the data of the head sector by the pattern is more difficult to analyze than the method of calculating the address of the flash memory by the secret algorithm in the first embodiment. In any case, even if the head of the data of the first page is found, the position of the head of the data of the following page is not known.

Writing to the first sector of a block is performed as follows.

The start position (address) of the pattern is determined by the random number generation circuit 14.

The user data is written in reverse order from the head to the head of the pattern.

Write a pattern.

Write overhead data.

Write the user data.

ECC generation processing (FIGS. 7 and 8)
The process of writing to the h memory (FIG. 11) and the process of reading from the flash memory (FIG. 13) are almost the same as in the first embodiment.

The only difference in the above processing is that when writing to the flash memory, scrambling is performed to improve confidentiality, and therefore, when reading is performed, descrambling is performed.

(Embodiment 3) FIG. 3 shows an example of a molly system according to the eighth aspect of the present invention. The configuration will be described.

The memory system shown in FIG. 3 includes an interface 20 with a processor, a read / write buffer 21 used for transmitting and receiving data to and from the processor, and a one-chip CPU for controlling the memory system.
22, secret algorithm A23a, secret algorithm B
23b, a secret algorithm C23c, an ECC circuit 24 for ensuring the reliability of data in Flash memory, Fl
Flash memory interface 31, Flash
A random number generation circuit 25, a top pattern detection circuit 26, a random number generation circuit 25 for use when writing or reading the head of the data of the first page of the block, And a selector 29 for selecting read / write data of a memory, and an overhead data mixing timing generation circuit 28.

20, 21, 22, 23a, 23b, 2
4, 25, 26, 30, 31, and 32 respectively correspond to 1 in FIG.
0, 11, 12, 13a, 13b, 16, 14, 15,
Similar to 17, 18, and 19.

FIG. 6 shows the flash used in this embodiment.
2 shows a data format inside the memory 32. FIG. 6 shows the data structure inside one block 60 that can be erased at one time. The physical configuration inside one block 60 is the same as that of one block 40. 61 is the first page of the block 60 located at the first address, 62 is the next page, and 63 is the last page located at the last address. The page is composed of MByte. Inside the page, user data 69 and overhead data 66, 67, 68, which are finely divided,
The head pattern 65 as a part thereof is included, and this embodiment is characterized in that overhead data is dispersed and mixed in user data.

In this embodiment, the overhead data is divided into three parts, but this may be decomposed in any manner. As the most advanced method, a method of dispersing in units of bytes can be considered. By distributing and arranging the overhead data in this manner, confidentiality can be further improved. Since a very large number of overhead data distribution methods (dispersion patterns) can be selected, it becomes very difficult to analyze.

Reference numeral 64 denotes an address indicating the number of bytes at the head of the overhead data 66. 64a is an address indicating the head position of the overhead data of the next page 62. These locations change from page to page, which makes analysis of management data difficult and increases the confidentiality of the memory system.

(Operation of Embodiment 3) FIG. 15 shows an outline of the overall flow of the processing of the memory system.
As for the fifth embodiment, the third embodiment is not different from the second embodiment, and thus the description is omitted.

FIG. 12 shows the procedure for writing to the Flash memory in detail. First, from the original data for calculating the head address of the data, the processing 124 for calculating the head address of the data of each sector by the secret algorithm B23b is performed, and then the data transfer start processing 125 is performed. Next, use the following procedure to change the word or B
Data is processed in ye units.

Process 126: Overhead data or user data is selected by the secret algorithm C23c. That is, how the overhead data is distributed is determined by the secret algorithm C23c from the head address of the data of each sector. (The simplest distribution method is a method of arranging overhead data at equal intervals).

FIG. 25 shows a simple implementation example of the secret algorithm C. First, four interval length data randomized based on the address A1 at which the overhead data appears is generated. Overhead data is written by 1 BYTE at intervals of the number of bytes of this interval length data. Since there are only four interval length data, the same pattern is repeated.

This processing is executed by the overhead data mixing timing generation circuit 28.

Processes 127, 128 and 129: Transfer the user data or overhead data to the flash memory interface 31 according to the result of process 126.

This processing is performed by the selector 29, the management data buffer 27, and the ECC circuit 24.

Process 130: The write data of 31 is S
is crumbled.

This processing is performed by Scrambler / Desc.
This is performed by the rambler 30.

The above processing is performed by one byte or one word at a time. Therefore, it is preferable to perform the processing by hardware in consideration of the processing speed, but the processing can be performed by software.

The above processing is performed for one page (for example, 528 B
y)), and the write processing for one sector is completed.

FIG. 14 shows the procedure for reading data from the Flash memory in detail. First, from the original data for calculating the head address of the data, the process 136 of calculating the head address of the data of each sector by the secret algorithm B23b is performed, and then the data reception start process 137 is performed. Next, data is processed in units of words or bytes in the following procedure.

Process 142: The read data of 31 is D
Escrambled.

This processing is performed by Scrambler / Desc.
This is performed by the rambler 30.

Process 138: Overhead data or user data is selected by the secret algorithm C23c. That is, how the overhead data is distributed is determined by the secret algorithm C23c from the head address of the data of each sector. (The simplest distribution method is a method of arranging overhead data at equal intervals).

This processing is executed by the overhead data mixing timing generation circuit 28.

Processes 139, 140, 141: Transfer the user data or overhead data from the flash memory interface 31 to one of the ECC circuit 24, the management data buffer 27, and the read / write buffer 21 according to the result of the process 138.

This processing is performed by the selector 29, the management data buffer 27, and the ECC circuit 24.

The above processing is performed by one byte or one word at a time. Therefore, it is preferable to perform the processing by hardware in consideration of the processing speed, but the processing can be performed by software.

The above processing is performed for one page, and the reading processing for one sector is completed.

(Embodiment 4) The configuration of an example of a molly system according to the fourth aspect of the present invention is substantially shown in FIG. FIG.
The difference between this and the actual configuration is that there is no secret algorithm corresponding to the secret algorithm A4a and the secret algorithm B4b in FIG. 1 and there is another algorithm D instead.

FIG. 17 shows the internal structure of the flash memory of the example of the molly system according to the fourth aspect of the present invention, and the method of searching for the address of overhead data. First, the entire flash memory 202 is divided into a management data dedicated section 200 and a data section 201. 201
Contains user data and overhead data in a form divided for each page. Also, in the management data dedicated unit 200, the physical address (chip n) of the page where overhead data is read first after the power is turned on.
o. , Block no. Page no. ) And the LBA (Logical) corresponding to the data in the page
Block Address) is recorded.

(Operation of Embodiment 4) The procedure for reading overhead data after power-on is as follows.

The physical address and LBA of the page 203 to be read first are read from the management data dedicated unit 200.

As shown in FIG. 18, the secret algorithm D
, The overhead data 2 of the first page 203
Find the address where 04 is stored.

When the overhead data 204 is read, the physical address of the next page 205 and the LBA
Is stored.

2. Similarly to the above, the address where the overhead data 206 of the next page 205 is stored is obtained by the secret algorithm D.

FIG. 26 shows a simple implementation example of the secret algorithm D. The address A1 where the overhead data first appears is generated by randomizing the sum of the LBA and the physical address of the Flash block or page.

When the overhead data 206 is read out, the physical address of the next page 207 and the LBA
Is contained.

Thereafter, overhead data of all necessary pages is read out by the same processing. To write the physical address and LBA of the next page in the overhead data of each page, do the following.

1. First, when writing, always
A spare area of one page or one block is secured in the flash memory.

[0092] 2. Therefore, when writing one page or one block, the next write page block can be determined as a spare area. At the time of writing, the next page, that is, the physical address and LBA of the spare area, is written in the overhead data.

The data in the management data dedicated section 200 also needs to be rewritten. However, since it is only when the page 203 to be read first is rewritten, the frequency is very low and the load is small.

(Embodiment 5) FIG. 21 shows an example of a memory system according to the fifth aspect of the present invention. The configuration will be described.

The memory system shown in FIG. 21 has an interface 300 with a processor and a read / write buffer 30 used for transmitting and receiving data to and from the processor.
1. One-chip CPU 302 for controlling the memory system, ECC circuit 303 for ensuring the reliability of data in Flash memory, interface 307 with Flash memory, Flash memory 308,
A management data buffer 304 for temporarily storing management data of the page, and a selector 30 for inputting / outputting either ECC data or management data as overhead data
5. Code conversion unit 306 that converts or reverse-converts data when writing to and reading from Flash
Consists of

301, 302, 303, 307, 308
Are 10, 11, 12, 16, 18, 19 in FIG.
Is the same as

FIG. 19 shows a more detailed configuration of the code conversion unit. User data 31 for one page in the figure
The overhead data 311 for 0 and 1 page are not included in the code conversion unit, but are illustrated for explanation. That is, the code conversion unit includes the temporary code register 312, the code conversion table 314, and the inverse conversion table 3
13

The temporary code register 312 stores 1 bit (K bit) of overhead and user data 3
Two bits (J bits) are temporarily stored. The code conversion table 314 converts the input from the temporary code register 312 at the time of writing to Flash, and outputs Flash write data (33 bits). At the time of Flash reading, the code reverse conversion table 313 reversely converts the Flash read data and outputs data (33 bits) to the temporary register 312. The conversion table and the inverse conversion table do not necessarily need to be tables, and may be a circuit having a conversion function or high-speed software.

In this embodiment, the user data is composed of 32 bits, and the overhead data is composed of 1 bit, which constitutes a 33-bit temporary code. However, this is not particularly specified. However, the configuration of a normal Flash memory is such that the user data section 512B and the overhead section are 1
6B, the ratio of the number of bits of the user data portion to the number of bits of the overhead data may be larger than 32; 1. That is, values such as 33: 1, 34: 1, and 35: 1 can be selected.

(Operation of Fifth Embodiment) Flash for One Page
The operation of writing to h is as follows.

First, the first two bytes of the user data are loaded into the temporary register 312. At the same time, the first bit of the overhead data is also loaded into the temporary register 312.

The ECC must have already been determined at this time. Therefore, the calculation of ECC is completed before the writing operation is started, for example, by calculating when receiving the writing data from the processor. Similarly, management data for another page is prepared in advance and stored in the management data buffer 304 together with the ECC data. In the figure, overhead data is loaded at the top of the temporary register 312, but may be loaded anywhere. Next, the code conversion table 314 converts the input from the temporary code register 312 into a code,
It outputs the write data (33 bits) of the lash. With this, 33 bits of write data are prepared, but writing of Flash is performed in units of bytes or a plurality of bytes. Therefore Flash interface 3
At 07, the data is buffered and written in byte units or multiple byte units. Hereinafter, similarly, write 512B + 1
The writing of 6B ends.

Similarly, the reading operation from Flash for one page is as follows.

First, the first 33-bit data from Flash is converted by the inverse conversion table 313 and loaded into the temporary code register 312. At this time, Fla
Since data read from the sh is in units of bytes or plural bytes, the data is buffered by the Flash interface 307 and divided into 33 bits. Overhead data 1 of temporary code register 312
The bits are transferred to the management data buffer 304, and the 32 bits of user data are transferred to the internal RAM of the CPU 302 or the read / write buffer 301. At this time, the ECC calculation is performed on the data transferred from the temporary code register 312. When one page of data is read, the EC stored in the management data buffer
The C data is compared with the calculation result of the ECC circuit 303. Perform error checking or error correction.

As described above, the ECC is performed on the code-converted data. Therefore, the effect of ECC is reduced when errors in data are enlarged by code conversion. To avoid this, a stronger EC
There is a method of adopting C. For example, a method using ECC which is strong against a burst error like the method by Reed-Solomon is used. In addition, there is a method of using a special code conversion, which suppresses the expansion of errors. FIG. 20 shows a very simple example.

In this conversion example, when the bit 32 is 1, the bits 31-0 are inverted. Therefore, even if an error occurs in bit 31-0, the number of bits of the error remains the same after code conversion. However, if an error occurs in bit 32, the error is magnified. If the bit 32 of the data 400 in FIG. Therefore, since the temporary code register data 403 becomes 402, the error is expanded to a 31-bit error.
However, such extreme cases can be distinguished from normal errors. That is, when there are extremely many errors, the ECC is checked without inverting the data by inferring that the inversion condition is wrong. If the number of errors is sufficiently small, the number of errors at that time is determined to be an actual error. In this manner, correct error correction can be performed by examining the data.

Since this example is too simple and can be easily analyzed, it is necessary to select bits to be inverted and to make the conditions of the inversion more complicated by setting the inversion condition to a bit pattern. .

[0108]

As described above, according to the method for operating a computer system of the present invention, a high degree of secrecy can be obtained for each memory system or memory chip by adding a simple circuit. .

In the present invention, means for reversing the order of data from the top address of a page to the address where overhead data appears first is provided, and the top data of each page and the top of user data are made inconsistent. , Making analysis more difficult.

In the present invention, the overhead data in the page is distributed and divided into a plurality of parts, and the arrangement is determined by a secret algorithm. As a result, the arrangement pattern of the overhead data is innumerable, and the analysis becomes very difficult.

Further, the present invention has means for performing ECC operation at the same time as receiving write data from the processor to the write buffer. Thus, when writing to the memory, the ECC data has already been calculated, so that the overhead data can be arranged at an arbitrary position without reading the extra memory.

Further, in the present invention, a high degree of confidentiality can be obtained in a memory system or a memory chip unit by coding data to be written into a nonvolatile memory by combining bits of user data and bits of overhead data. Things become possible.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing one embodiment of the present invention (Example 1).

FIG. 2 is a system configuration diagram showing one embodiment of the present invention (Example 2).

FIG. 3 is a system configuration diagram showing one embodiment of the present invention (Example 3).

FIG. 4 is a data format in a memory according to one embodiment of the present invention (Embodiment 1);

FIG. 5 is a data format in a memory according to one embodiment of the present invention (Example 2).

FIG. 6 shows a data format in a memory according to one embodiment of the present invention (third embodiment).

FIG. 7 is an ECC generation flowchart (when writing to a memory).

FIG. 8 is an ECC generation flowchart (when reading from a memory).

FIG. 9 is a reading flowchart immediately after power-on of a leading sector.

FIG. 10 is a reading flowchart immediately after power-on of a leading sector.

FIG. 11 is a flowchart for writing to a memory.

FIG. 12 is a flowchart of writing to a memory (overhead data is automatically mixed in).

FIG. 13 is a flowchart of reading from a Flash memory.

FIG. 14 is a flowchart of reading from a Flash memory (overhead data is automatically separated).

FIG. 15 is a flowchart of the overall flow of a memory system process.

FIG. 16 shows a data format in a memory according to a conventional method.

FIG. 17 is an explanatory diagram of an overhead data address search method according to one embodiment of the present invention.

FIG. 18 is a flowchart of an overhead data address determining method according to one embodiment of the present invention;

FIG. 19 is a detailed configuration diagram of a code conversion unit according to one embodiment of the present invention.

FIG. 20 is a code table of a code conversion example according to one embodiment of the present invention;

FIG. 22 shows a secret algorithm (4) according to an embodiment of the present invention.
a).

FIG. 23 is a hardware configuration diagram (4a) of a secret algorithm according to one embodiment of the present invention;

FIG. 24 shows a secret algorithm (4) according to an embodiment of the present invention.
b).

FIG. 25 shows a secret algorithm (4) according to an embodiment of the present invention.
c).

FIG. 26 shows a secret algorithm (D) according to one embodiment of the present invention.

[Explanation of symbols]

1, 10, 20, 300: Interface with processor 2, 11, 21, 301: Read / write buffer 12, 22, 302: One-chip CPU 4a, 13a, 23a: Secret algorithm A 4b , 13b, 23b... Secret algorithm B 5, 16, 24, 303 ECC circuit 6, 18, 31, 307 Flash memory interface 19, 32, 308 Flash memory 14, 25 Random number generation circuit 15, 26 Head pattern detection circuit 17, Scrambler / Descrambler 23c: Secret algorithm C 27: Management data buffer 28: Overhead data mixing timing generation circuit 29: Selector for selecting read / write data 40, 50, 60 Flash memory One block 41, 51, the first page 52 in the 611 block 52, the next page 53, the first page in the 621 block The last page 54 located at the last address 54, the top position 55 of the overhead data, the overhead data of the next page Head position 56, 66, 67, 68 overhead data 47, 48, 57, 59, user data 65 head data overhead pattern 200 management data dedicated section 201 data section 202, entire flash memory 304 management data buffer 305 overhead data Selector 306 Code conversion unit 312 Temporary code register 313 Reverse conversion table 314 Code conversion table

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] March 13, 1998

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Brief description of drawings

[Correction method] Change

[Correction contents]

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing one embodiment of the present invention (Example 1).

FIG. 2 is a system configuration diagram showing one embodiment of the present invention (Example 2).

FIG. 3 is a system configuration diagram showing one embodiment of the present invention (Example 3).

FIG. 4 is a data format in a memory according to one embodiment of the present invention (Embodiment 1);

FIG. 5 is a data format in a memory according to one embodiment of the present invention (Example 2).

FIG. 6 shows a data format in a memory according to one embodiment of the present invention (third embodiment).

FIG. 7 is an ECC generation flowchart (when writing to a memory).

FIG. 8 is an ECC generation flowchart (when reading from a memory).

FIG. 9 is a reading flowchart immediately after power-on of a leading sector.

FIG. 10 is a reading flowchart immediately after power-on of a leading sector.

FIG. 11 is a flowchart for writing to a memory.

FIG. 12 is a flowchart of writing to a memory (overhead data is automatically mixed in).

FIG. 13 is a flowchart of reading from a Flash memory.

FIG. 14 is a flowchart of reading from a Flash memory (overhead data is automatically separated).

FIG. 15 is a flowchart of the overall flow of a memory system process.

FIG. 16 shows a data format in a memory according to a conventional method.

FIG. 17 is an explanatory diagram of an overhead data address search method according to one embodiment of the present invention.

FIG. 18 is a flowchart of an overhead data address determining method according to one embodiment of the present invention;

FIG. 19 is a detailed configuration diagram of a code conversion unit according to one embodiment of the present invention.

FIG. 20 is a code table of a code conversion example according to one embodiment of the present invention;

FIG. 21 is a system configuration diagram showing one embodiment of the present invention (Example 5).

FIG. 22 shows a secret algorithm (4) according to an embodiment of the present invention.
a).

FIG. 23 is a hardware configuration diagram (4a) of a secret algorithm according to one embodiment of the present invention;

FIG. 24 shows a secret algorithm (4) according to an embodiment of the present invention.
b).

FIG. 25 shows a secret algorithm (4) according to an embodiment of the present invention.
c).

FIG. 26 shows a secret algorithm (D) according to one embodiment of the present invention.

[Description of Signs] 1, 10, 20, 300: Interface with Processor 2, 11, 21, 301: Read / Write Buffer 12, 22, 302: One-chip CPU 4a, 13a, 23a,. Secret algorithm A 4b, 13b, 23b Secret algorithm B 5, 16, 24, 303 ECC circuit 6, 18, 31, 307 Interface with Flash memory 19, 32, 308 Flash memory 14, 25 Random number generation circuit 15, 26 Top Pattern detection circuit 17, Scrambler / Descrambler 23c ... Secret algorithm C 27 ... Management data buffer 28 ... Overhead data mixing timing generation circuit 29 ... Selector for selecting read / write data 40, 50, 60Fl 1 block of sh memory 41, 51, the first page in 611 block 52, the next page of the top in 621 block 53, 63 The last page located at the last address 54, the top position of overhead data 55, the next page Head data 56, 66, 67, 68 overhead data 47, 48, 57, 59, user data 65 overhead data head pattern 200 management data dedicated section 201 data section 202, entire flash memory 304 management data buffer 305 Overhead data selector 306 Code conversion unit 312 Temporary code register 313 Reverse conversion table 314 Code conversion table

Claims (9)

[Claims] 1. A system comprising a processor and a memory system,
The memory system includes a non-volatile floating gate memory array, the non-volatile floating gate memory array is divided into blocks, the memory arrays in the blocks can be erased simultaneously, and the blocks are transferred from the processor. The memory system is divided into pages having a memory capacity corresponding to one unit of data to be written, and user data and overhead data are written to the same page, and one unit of write data is received from the processor. In a computer system having a write buffer, after the memory system is powered on, in each block, an address A1 at which the overhead data appears first in a page P1 to be read first. Characterized in that it has means for determining by a secret algorithm from the address of the serial block,
An operation method of the computer system. 2. A system comprising a processor and a memory system,
The memory system includes a non-volatile floating gate memory array, the non-volatile floating gate memory array is divided into blocks, the memory arrays in the blocks can be erased simultaneously, and the blocks are transferred from the processor. The memory system is divided into pages each having a memory capacity corresponding to one unit of data, and user data and overhead data are written on the same page, and one unit of write data is received from the processor. In a computer system having a write buffer, in the block P1 to be read first in each block after the power of the memory system is turned on, an address A1 where the overhead data appears first is read. The number of candidates determined by a secret algorithm from the address of the block, Error the correct address from a plurality of candidates of the address Corr
The method of operating the computer system, further comprising: means for determining by using an action check (hereinafter, referred to as ECC). 3. A system comprising a processor and a memory system,
The memory system includes a non-volatile floating gate memory array, the non-volatile floating gate memory array is divided into blocks, the memory arrays in the blocks can be erased simultaneously, and the blocks are transferred from the processor. The memory system is divided into pages having a memory capacity corresponding to one unit of data to be written, and user data and overhead data are written to the same page, and one unit of write data is received from the processor. In a computer system having a write buffer, after the power of the memory system is turned on, in each block, at the address A1 where the overhead data appears first in the page P1 to be read first. The address of the serial block previously written a special pattern determined by a secret algorithm, the address A by detecting the pattern
1. A method for operating the computer system, comprising: 4. A system comprising a processor and a memory system,
The memory system includes a non-volatile floating gate memory array, wherein the memory array is divided into pages having a memory capacity corresponding to one unit of data transferred from the processor, and one unit of data from the processor is divided into pages. A computer system, wherein the memory system has a write buffer for receiving write data, wherein the memory system has at least one dedicated management data portion in the memory array to which only management data is written; In other parts of the array, user data and overhead data are written to the same page, and after the memory system is powered on, the address A0 of the page P1 to be read first and the overhead in the page P1 first. And wherein the address A1 that data appears to have the means for determining the data of the management data only unit, the operation method of the computer system. 5. A system comprising a processor and a memory system,
The memory system includes a non-volatile floating gate memory array, wherein the memory array is divided into pages having a memory capacity corresponding to one unit of data transferred from the processor, and one unit of data is written from the processor. In order to receive data, the memory system has a write buffer.In a computer system, at the time of writing to the memory system, the memory system is composed of J bits composed of the user data and K bits composed of the overhead data. Create a temporary code of J + K bits and replace the temporary code with a different J + K
After code conversion into bit codes, writing to the page and reading from the memory system,
A method for operating a computer system, comprising: means for dividing data read from the page into J + K bits, performing inverse conversion, and returning the original data to J + K bits. 6. An apparatus according to claim 1, wherein an address A2 at which overhead data first appears in a page other than said page P1 in said block is assigned to said page P1.
Address A where the overhead data first appears
1 or a method of operating a computer system, wherein the method is determined by a secret algorithm based on overhead data of the page P1. 7. A computer system operating method according to claim 1, wherein the order of data from the top address of the page to the address where overhead data appears first is reversed. 8. The method according to claim 1, wherein the overhead data in the page is distributed and arranged in a plurality of parts, and the layout method is such that the overhead data first appears in the address A1 or the page. A method for operating a computer system, wherein the method is determined by a secret algorithm based on P1 overhead data. 9. The computer system operation method according to claim 1, wherein an ECC operation is performed while receiving write data from said processor to said write buffer.