JP5217158B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP5217158B2
JP5217158B2 JP2006328397A JP2006328397A JP5217158B2 JP 5217158 B2 JP5217158 B2 JP 5217158B2 JP 2006328397 A JP2006328397 A JP 2006328397A JP 2006328397 A JP2006328397 A JP 2006328397A JP 5217158 B2 JP5217158 B2 JP 5217158B2
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impurity
region
conductivity type
surface density
impurity region
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JP2007235095A (en
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健 宮嶋
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Denso Corp
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Denso Corp
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Priority to DE200710004616 priority patent/DE102007004616B4/en
Priority to DE102007063840.1A priority patent/DE102007063840B3/en
Priority to US11/699,579 priority patent/US8106453B2/en
Priority to CN2007100073746A priority patent/CN101013724B/en
Priority to CN201210100028.3A priority patent/CN102623349B/en
Priority to CN2013100986196A priority patent/CN103258853A/en
Publication of JP2007235095A publication Critical patent/JP2007235095A/en
Priority to US13/307,878 priority patent/US8421154B2/en
Priority to US13/769,902 priority patent/US8659082B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Description

本発明は、スーパージャンクション構造を有する半導体装置に関するものである。 The present invention relates to semiconductor equipment having a super junction structure.

スーパージャンクションＭＯＳＦＥＴの基板は、特許文献１のように、トランジスタ形成領域に一種類のＰＮコラム対が繰り返し配置されて構成される。その結果、通常のＭＯＳＦＥＴに比べ、ドリフト抵抗低減によるオン抵抗の低減及び高速スイッチングが可能である。
特開２００４−１４６６８９号公報 The substrate of the super junction MOSFET is configured by repeatedly arranging one type of PN column pair in the transistor formation region as disclosed in Patent Document 1. As a result, the on-resistance can be reduced and high-speed switching can be achieved by reducing the drift resistance as compared with a normal MOSFET.
JP 2004-14689A

ところが、高速スイッチングが可能である反面、オンからオフへの切換時にドレイン・ソース間電流が急激に遮断されることで、ドレイン・ソース間電圧が著しく跳ね上がり、破壊耐量低下やラジオノイズ発生等の問題が生じている。   However, high-speed switching is possible, but drain-source current is suddenly interrupted when switching from on to off, causing drain-source voltage to jump significantly, causing problems such as reduced breakdown resistance and generation of radio noise. Has occurred.

本発明は、上記問題点に着目してなされたものであり、その目的は、オンからオフへの切換時における電圧の跳ね上がりを抑制することができる半導体装置を提供することにある。 The present invention has been made in view of the above problems, its object is to provide a semiconductor equipment which can suppress a jump of the voltage when switching from ON to OFF.

上記の課題を解決するために、請求項１に記載の発明では、半導体基板において、電流が流れる方向に延びる第１導電型の不純物領域と、同じく電流が流れる方向に延びる第２導電型の不純物領域とが、電流が流れる方向に直交する方向に隣接して交互に配置され、オン時に前記第１導電型の不純物領域と前記第２導電型の不純物領域からなるコラム対における前記第１導電型の不純物領域がドリフト層となって電流が流れるとともにオフ時に前記第１導電型の不純物領域と第２導電型の不純物領域との界面から空乏層が広がる、スーパージャンクション構造を有する半導体装置であって、半導体装置のアクティブ領域の全域において、隣り合う第１導電型の不純物領域の幅および隣り合う第２導電型の不純物
領域の幅および隣り合う第１導電型の不純物領域の不純物濃度および隣り合う第２導電型の不純物領域の不純物濃度の少なくとも１つを異ならせた不均一領域をもたせることによって、前記コラム対の、電流が流れる方向に直交する方向での不純物面密度を不均一化した半導体装置を要旨とする。 In order to solve the above problems, in the invention according to claim 1, in the semiconductor substrate, the first conductivity type impurity region extending in the direction in which the current flows and the second conductivity type impurity extending in the direction in which the current flows. The first conductivity type in the column pair consisting of the first conductivity type impurity region and the second conductivity type impurity region are alternately arranged adjacent to each other in a direction perpendicular to the direction in which the current flows. A semiconductor device having a super junction structure in which a depletion layer extends from an interface between the impurity region of the first conductivity type and the impurity region of the second conductivity type when the impurity region is a drift layer and current flows and is turned off. The width of the adjacent first conductivity type impurity region and the adjacent second conductivity type impurity in the entire active region of the semiconductor device
By providing a non-uniform region in which at least one of the width of the region, the impurity concentration of the adjacent first conductivity type impurity region, and the impurity concentration of the adjacent second conductivity type impurity region is different , current and gist of the semiconductor device was non-uniform impurity surface density in the direction perpendicular to the flow direction.

請求項１に記載の発明によれば、オンからオフへの切換時（スイッチングのオフ時）に、第１導電型の不純物領域と第２導電型の不純物領域からなるコラム対（ＰＮコラム対）の完全空乏化するタイミングが、電流が流れる方向に直交する方向でずれる。これにより、オンからオフへの切換時における電圧の跳ね上がりを抑制することができる。   According to the first aspect of the present invention, when switching from on to off (when switching is off), a column pair (PN column pair) composed of the first conductivity type impurity region and the second conductivity type impurity region. The timing of complete depletion of is deviated in a direction perpendicular to the direction of current flow. Thereby, the jump of the voltage at the time of switching from on to off can be suppressed.

詳しくは、請求項２に記載のように、各第１導電型の不純物領域の幅を等しくするとともに各第２導電型の不純物領域の幅を等しくし、前記不均一領域として、隣り合う第１導電型の不純物領域の不純物濃度および隣り合う第２導電型の不純物領域の不純物濃度を異ならせた領域をもたせることによって、前記コラム対の、電流が流れる方向に直交する方向での不純物面密度を不均一化するとよい。あるいは、請求項３に記載のように、各第１導電型の不純物領域の幅を等しくするとともに各第２導電型の不純物領域の幅を等しくし、さらに、各第２導電型の不純物領域の不純物濃度を等しくし、前記不均一領域として、隣り合う第１導電型の不純物領域の不純物濃度を異ならせた領域をもたせることによって、前記コラム対の、電流が流れる方向に直交する方向での不純物面密度を不均一化するとよい。あるいは、請求項４に記載のように、各第１導電型の不純物領域の不純物濃度を等しくするとともに各第２導電型の不純物領域の不純物濃度を等しくし、さらに、各第２導電型の不純物領域の幅を等しくし、前記不均一領域として、隣り合う第１導電型の不純物領域の幅を異ならせた領域をもたせることによって、前記コラム対の、電流が流れる方向に直交する方向での不純物面密度を不均一化するとよい。 Specifically, as described in claim 2 , the widths of the first conductivity type impurity regions are made equal and the widths of the second conductivity type impurity regions are made equal to each other . By providing a region in which the impurity concentration of the conductivity type impurity region is different from the impurity concentration of the adjacent second conductivity type impurity region, the impurity surface density of the column pair in the direction perpendicular to the direction in which the current flows is reduced. It should be non- uniform. Alternatively, as described in claim 3 , the widths of the first conductivity type impurity regions are equalized, the widths of the second conductivity type impurity regions are equalized, and the second conductivity type impurity regions of the second conductivity type are further equalized. Impurities in a direction perpendicular to the direction of current flow of the column pair are provided by making the non-uniform regions have regions in which the impurity concentrations of the adjacent first conductivity type impurity regions are different from each other . It is preferable to make the surface density non- uniform. Alternatively, as described in claim 4 , the impurity concentration of each first conductivity type impurity region is made equal, the impurity concentration of each second conductivity type impurity region is made equal, and each second conductivity type impurity is further made equal Impurities in a direction perpendicular to the direction of current flow of the column pair are obtained by making the widths of the regions equal and providing regions with different widths of adjacent first conductivity type impurity regions as the non-uniform regions. It is preferable to make the surface density non- uniform.

請求項５に記載のように、請求項１〜４のいずれか１項に記載の半導体装置において、不純物面密度を場所により不均一化すべく、不純物面密度として、二種類とし、かつ、耐圧が最大となる不純物面密度に対し高不純物面密度側と低不純物面密度側に等しいずれ量となる不純物面密度を設定すると、素子耐圧が局所的に低下するのを防止することができ
る。 As described in claim 5 , in the semiconductor device according to any one of claims 1 to 4 , in order to make the impurity surface density non-uniform depending on the location, there are two types of impurity surface densities, and the withstand voltage is By setting the impurity surface density that is equal to the maximum impurity surface density to the high impurity surface density side and the low impurity surface density side, it is possible to prevent the device breakdown voltage from being locally reduced.

請求項６に記載のように、請求項１〜４のいずれか１項に記載の半導体装置において、不純物面密度を場所により不均一化すべく、不純物面密度として、三種類以上とし、かつ、耐圧が最大となる不純物面密度に対し高不純物面密度側と低不純物面密度側に等しいずれ量となる不純物面密度を設定するとともに、その間に挟まれた領域に残りの不純物面密度を設定すると、素子耐圧が局所的に低下するのを防止することができる。 As described in claim 6 , in the semiconductor device according to any one of claims 1 to 4 , in order to make the impurity surface density non-uniform depending on the location, the impurity surface density is set to three or more types, and When the impurity surface density is set to be equal to the high impurity surface density side and the low impurity surface density side, and the remaining impurity surface density is set in the region between them Therefore, it is possible to prevent the device breakdown voltage from being locally reduced.

（第１の実施の形態）
以下、本発明を具体化した第１の実施形態を図面に従って説明する。
図１は、本実施形態における半導体装置の縦断面図である。本半導体装置は縦型ＭＯＳＦＥＴであって、縦方向に電流が流れる。即ち、縦方向が電流が流れる方向であり、横方向が電流が流れる方向に直交する方向である。 (First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a longitudinal sectional view of a semiconductor device according to this embodiment. This semiconductor device is a vertical MOSFET, and a current flows in the vertical direction. That is, the vertical direction is the direction in which current flows, and the horizontal direction is the direction orthogonal to the direction in which current flows.

Ｎ＋シリコン基板１の上にシリコン層２が形成され、シリコン層２の上にＮ型シリコン層３が形成されている。この積層構造体により半導体基板が構成され、半導体基板でのシリコン層２において、縦方向に延びるＮ型の不純物領域（Ｎコラム）４と、同じく縦方向に延びるＰ型の不純物領域（Ｐコラム）５とが横方向に隣接して交互に配置されている。Ｎ型の不純物領域４とＰ型の不純物領域５とからコラム対（ＰＮコラム対）が構成されている。これにより、スーパージャンクション構造が形成されている。そして、オン時にＰＮコラム対におけるＮ型不純物領域４がドリフト層となって電流が流れるとともにオフ時にＮ型不純物領域４とＰ型不純物領域５との界面から空乏層が広がることになる。 A silicon layer 2 is formed on the N + silicon substrate 1, and an N-type silicon layer 3 is formed on the silicon layer 2. This stacked structure constitutes a semiconductor substrate. In the silicon layer 2 of the semiconductor substrate, an N-type impurity region (N column) 4 extending in the vertical direction and a P-type impurity region (P column) extending in the vertical direction are also provided. 5 are alternately arranged adjacent to each other in the horizontal direction. The N-type impurity region 4 and the P-type impurity region 5 constitute a column pair (PN column pair). Thereby, a super junction structure is formed. The N-type impurity region 4 in the PN column pair becomes a drift layer when the switch is turned on and a current flows, and a depletion layer spreads from the interface between the N-type impurity region 4 and the P-type impurity region 5 when the switch is turned off.

前述のＮ型シリコン層３においてＰ型のチャネル形成領域６がＰ型の不純物領域５に達するように形成されている。Ｐ型のチャネル形成領域６内において表層部にはＮ型ソース領域７が形成されている。Ｎ型シリコン層３の上面においてＰ型のチャネル形成領域６が露出する部位にはゲート絶縁膜としてのゲート酸化膜８を介してゲート電極９が形成されている。ゲート電極９はシリコン酸化膜１０にて被覆されている。Ｎ型シリコン層３の上面においてソース電極１１が形成され、このソース電極１１はソース領域７およびチャネル形成領域６と電気的に接続されている。Ｎ＋シリコン基板１の下面（裏面）にはドレイン電極１２が形成されている。 In the aforementioned N-type silicon layer 3, the P-type channel formation region 6 is formed so as to reach the P-type impurity region 5. An N-type source region 7 is formed in the surface layer portion within the P-type channel formation region 6. A gate electrode 9 is formed on a portion of the upper surface of the N-type silicon layer 3 where the P-type channel formation region 6 is exposed via a gate oxide film 8 as a gate insulating film. The gate electrode 9 is covered with a silicon oxide film 10. A source electrode 11 is formed on the upper surface of the N-type silicon layer 3, and the source electrode 11 is electrically connected to the source region 7 and the channel forming region 6. A drain electrode 12 is formed on the lower surface (back surface) of the N + silicon substrate 1.

そして、ソース電極１１をグランド電位にするとともにドレイン電極１２に正の電位を印加した状態においてゲート電極９に正の電位を印加することにより、トランジスタがオンとなる。トランジスタ・オン時においては、図１に示すように、ドレイン電極１２からＮ＋シリコン基板１、Ｎ型不純物領域４、Ｎ型領域（３）、チャネル形成領域６におけるゲート電極９と対向する部位（反転層）、ソース領域７を通してソース電極１１に電流が流れる。 The transistor is turned on by applying a positive potential to the gate electrode 9 in a state where the source electrode 11 is set to the ground potential and a positive potential is applied to the drain electrode 12. When the transistor is turned on, as shown in FIG. 1, the portion (from the drain electrode 12 to the N + silicon substrate 1, the N-type impurity region 4, the N-type region (3), and the channel formation region 6 facing the gate electrode 9 ( Current flows to the source electrode 11 through the inversion layer) and the source region 7.

一方、トランジスタ・オンの状態（ソース電極１１をグランド電位、ドレイン電極１２を正の電位、ゲート電極９を正の電位にした状態）からゲート電極９をグランド電位にすると、トランジスタがオフとなり、図２に示すように、Ｎ型不純物領域４とＰ型不純物領域５との界面から空乏層が広がる。   On the other hand, when the gate electrode 9 is set to the ground potential from the transistor-on state (the source electrode 11 is set to the ground potential, the drain electrode 12 is set to the positive potential, and the gate electrode 9 is set to the positive potential), the transistor is turned off. As shown in FIG. 2, a depletion layer spreads from the interface between the N-type impurity region 4 and the P-type impurity region 5.

ここで、本実施形態においては、半導体基板でのトランジスタのアクティブ領域（トランジスタ形成領域）における、ＰＮコラム対の横方向での不純物面密度を場所により不均一化している。つまり、横方向での両領域４，５の不純物の総量（面密度）を場所により異ならせている。具体的には、図１において、各Ｎ型不純物領域４の幅Ｗ４を一定にし、各Ｐ型不純物領域５の幅Ｗ５も一定にし、Ｎ型不純物領域４の不純物濃度をＮ１，Ｎ２，Ｎ３の三種類とし、Ｐ型不純物領域５の不純物濃度をＰ１，Ｐ２，Ｐ３の三種類としている。   Here, in this embodiment, the impurity surface density in the lateral direction of the PN column pair in the active region (transistor formation region) of the transistor on the semiconductor substrate is made non-uniform depending on the location. That is, the total amount (surface density) of the impurities in both regions 4 and 5 in the lateral direction is varied depending on the location. Specifically, in FIG. 1, the width W4 of each N-type impurity region 4 is made constant, the width W5 of each P-type impurity region 5 is made constant, and the impurity concentration of the N-type impurity region 4 is set to N1, N2, N3. There are three types, and the impurity concentration of the P-type impurity region 5 is three types P1, P2, and P3.

このようにして、各Ｎ型不純物領域４の幅Ｗ４を等しくするとともに各Ｐ型不純物領域５の幅Ｗ５を等しくし、さらに、Ｎ型不純物領域４の不純物濃度およびＰ型不純物領域５の不純物濃度を、横方向において場所により異ならせることによって、ＰＮコラム対の、横方向での不純物面密度を場所により不均一化している。   In this way, the width W4 of each N-type impurity region 4 is made equal, the width W5 of each P-type impurity region 5 is made equal, and the impurity concentration of the N-type impurity region 4 and the impurity concentration of the P-type impurity region 5 are also made. Is made different depending on the location in the lateral direction, whereby the impurity surface density in the lateral direction of the PN column pair is made non-uniform depending on the location.

これにより、図２に示すように、不純物濃度の違いにより、図中破線で示す空乏層の広がり速度が異なり（濃度が低いほど速い）、かつ、Ｐ型とＮ型の不純物面密度のバランスが場所により異なる。そのため、ＰＮコラム対が完全空乏化するタイミングが面内（横方向）でずれ、すべてのＰＮコラム対が同時にオフするのが防止される。その結果、図３に示すように、オンからオフへの切換時におけるドレイン・ソース間電流Ｉｄｓについての変化率（ｄＩ／ｄｔ）を小さくしてオンからオフへの切換時におけるドレイン・ソース間電圧Ｖｄｓの跳ね上がりを抑止することができる。   As a result, as shown in FIG. 2, the spread speed of the depletion layer indicated by the broken line in the figure differs depending on the impurity concentration (the lower the concentration, the faster), and the balance between the P-type and N-type impurity surface densities is balanced. Varies by location. Therefore, the timing at which the PN column pairs are completely depleted is shifted in the plane (lateral direction), and all PN column pairs are prevented from being turned off simultaneously. As a result, as shown in FIG. 3, the rate of change (dI / dt) in the drain-source current Ids at the time of switching from on to off is reduced to reduce the drain-source voltage at the time of switching from on to off. The jump of Vds can be suppressed.

図１９は、比較のためのスーパージャンクションＭＯＳＦＥＴにおける縦断面図である。図１９において、不純物濃度Ｎ１のＮ型不純物領域（Ｎコラム）４と、不純物濃度Ｐ１のＰ型不純物領域（Ｐコラム）５のみの一種類のＰＮコラム対を、アクティブ領域（トランジスタ形成領域）に配置しており、場所によらず同じ構成（Ｎ１とＰ１）のＰＮコラム対でスーパージャンクション構造が構成されている。そして、トランジスタのオンからオフへの切換時（スイッチングのオフ時）には図２０に示すように空乏化の開始後に各コラム対で同じように空乏化が進み、図２１に示すように各コラム対で同じように空乏化が更に進み、図２２に示すように各コラム対で同時に空乏化が完了する。この動作の際に図２３に示すように、オンからオフへの切換時においてドレイン・ソース間電流Ｉｄｓについての変化率（ｄＩ／ｄｔ）が大きく、ドレイン・ソース間電圧Ｖｄｓの跳ね上がりが発生する。   FIG. 19 is a longitudinal sectional view of a super junction MOSFET for comparison. In FIG. 19, an N-type impurity region (N column) 4 having an impurity concentration N1 and a single PN column pair having only a P-type impurity region (P column) 5 having an impurity concentration P1 are used as an active region (transistor formation region). The super junction structure is composed of PN column pairs having the same configuration (N1 and P1) regardless of the location. When the transistor is switched from on to off (when switching is off), depletion progresses in the same way in each column pair after the start of depletion as shown in FIG. 20, and each column as shown in FIG. The depletion progresses in the same manner in pairs, and the depletion is completed simultaneously in each column pair as shown in FIG. During this operation, as shown in FIG. 23, the change rate (dI / dt) of the drain-source current Ids is large when switching from on to off, and the drain-source voltage Vds jumps up.

これに対し本実施形態では、不純物濃度がＮ１，Ｎ２，Ｎ３のＮ型不純物領域（Ｎコラム４、不純物濃度がＰ１，Ｐ２，Ｐ３のＰ型不純物領域（Ｐコラム）５から構成されており、そのため、二種類以上のＰＮコラム対でスーパージャンクション構造を構成することにより、隣り合うＰＮコラム対の組み合わせは複数種でき、アクティブ領域（トランジスタ形成領域）においてＰ型Ｎ型の不純物面密度のバランスが場所により異なる。これにより、トランジスタのオンからオフへの切換時（スイッチングのオフ時）に、ＰＮコラム対が完全空乏化するタイミングをトランジスタ形成面内（横方向）でずらすことができるため、すべてのトランジスタセルが同時にオフするのを防ぎ、図３に示したようにオンからオフへの切換時におけるドレイン・ソース間電圧Ｖｄｓの跳ね上がりを抑止できる。つまり、不純物面密度が異なる二種類以上のＰＮコラム対を用いることで、完全空乏化のタイミングをアクティブ領域でずらすことによって、ドレイン・ソース間電流Ｉｄｓについての変化率（ｄＩ／ｄｔ）を小さくし、ドレイン・ソース間電圧Ｖｄｓの跳ね上がりを防ぐことができる。   In contrast, in this embodiment, the N-type impurity region (N column 4 having an impurity concentration of N1, N2, and N3, and the P-type impurity region (P column) 5 having an impurity concentration of P1, P2, and P3) are formed. Therefore, by constructing a super junction structure with two or more types of PN column pairs, a plurality of combinations of adjacent PN column pairs can be made, and the balance of the P-type N-type impurity surface density in the active region (transistor formation region) can be achieved. As a result, the timing at which the PN column pair is completely depleted when the transistor is switched from on to off (when switching is off) can be shifted within the transistor formation plane (lateral direction). The transistor cells are prevented from turning off at the same time, and the drain at the time of switching from on to off as shown in FIG. -The jump of the source-to-source voltage Vds can be suppressed, that is, by using two or more types of PN column pairs with different impurity surface densities, the timing of complete depletion is shifted in the active region, so that the drain-source current Ids Change rate (dI / dt) can be reduced, and the rise of the drain-source voltage Vds can be prevented.

上記実施形態によれば、以下のような効果を得ることができる。
スーパージャンクション構造を有する半導体装置（縦型ＭＯＳＦＥＴ）において、半導体装置のアクティブ領域における、コラム対の、横方向での不純物面密度を場所により不均一化したので、オンからオフへの切換時（スイッチングのオフ時）に、Ｎ型不純物領域４とＰ型不純物領域５からなるコラム対（ＰＮコラム対）の完全空乏化するタイミングが横方向でずれる。これにより、オンからオフへの切換時における電圧の跳ね上がりを抑制することができる。 According to the above embodiment, the following effects can be obtained.
In a semiconductor device (vertical MOSFET) having a super junction structure, the impurity surface density in the lateral direction of the column pair in the active region of the semiconductor device is made uneven depending on the location, so when switching from on to off (switching) The timing at which the column pair (PN column pair) composed of the N-type impurity region 4 and the P-type impurity region 5 is completely depleted shifts in the horizontal direction. Thereby, the jump of the voltage at the time of switching from on to off can be suppressed.

また、一般的なパワーＭＯＳＦＥＴにおいてはスイッチング時に発生するライジオノイズを抑制すべくゲート抵抗を大きくすることでゲート入力波形をなまらせて対応していたが、発熱が大きくなり、製品の小型化が制限されていた。また、スーパージャンクションＭＯＳＦＥＴでは完全空乏化時の電圧の跳ね上がりが問題となるため、ゲート波形制御だけではラジオノイズ対策ができなかった。これに対し、コラム対の不純物面密度を場所により不均一化することにより、スーパージャンクション素子でのラジオノイズの低減を図ることができ、しかも発熱が増加することなく実現できる。
（第２の実施の形態）
次に、第２の実施の形態を、第１の実施の形態との相違点を中心に説明する。 In addition, in general power MOSFETs, the gate input waveform was smoothed by increasing the gate resistance to suppress the riser noise generated during switching, but this increased heat generation and limited product size reduction. It was. Further, in the super junction MOSFET, a voltage jump at the time of complete depletion becomes a problem, and therefore, radio noise countermeasures cannot be performed only by gate waveform control. On the other hand, by making the impurity surface density of the column pair non-uniform depending on the location, it is possible to reduce the radio noise in the super junction element, and it can be realized without increasing heat generation.
(Second Embodiment)
Next, the second embodiment will be described focusing on the differences from the first embodiment.

図４は、図１に代わる本実施形態における半導体装置の縦断面図である。本半導体装置も縦型ＭＯＳＦＥＴであって、かつ、スーパージャンクション構造を有している。
各Ｎ型不純物領域４の幅Ｗ４を一定にし、各Ｐ型不純物領域５の幅Ｗ５も一定にし、Ｎ型不純物領域４の不純物濃度をＮ１，Ｎ２，Ｎ３の三種類とし、Ｐ型不純物領域５の不純物濃度をＰ１の一種類としている。つまり、図１と異なる点は、Ｎ型不純物領域（Ｎコラム）４の濃度はＮ１，Ｎ２，Ｎ３の三種類であり、Ｐ型不純物領域（Ｐコラム）５の濃度はＰ１一種類である。 FIG. 4 is a longitudinal sectional view of a semiconductor device according to the present embodiment that replaces FIG. This semiconductor device is also a vertical MOSFET and has a super junction structure.
The width W4 of each N-type impurity region 4 is made constant, the width W5 of each P-type impurity region 5 is also made constant, the N-type impurity region 4 has three types of impurity concentrations N1, N2, and N3. Is one type of P1. That is, the difference from FIG. 1 is that the N-type impurity region (N column) 4 has three concentrations N1, N2, and N3, and the P-type impurity region (P column) 5 has one concentration P1.

このようにして、各Ｎ型不純物領域４の幅Ｗ４を等しくするとともに各Ｐ型不純物領域５の幅Ｗ５を等しくし、さらに、各Ｐ型不純物領域５の不純物濃度を等しくし、さらには、Ｎ型不純物領域４の不純物濃度を横方向において場所により異ならせることによって、コラム対の横方向での不純物面密度を場所により不均一化している。   In this way, the width W4 of each N-type impurity region 4 is made equal, the width W5 of each P-type impurity region 5 is made equal, the impurity concentration of each P-type impurity region 5 is made equal, and further, N By making the impurity concentration of the type impurity region 4 different depending on the location in the lateral direction, the impurity surface density in the lateral direction of the column pair is made non-uniform depending on the location.

これにより、図５に示すように、トランジスタのオンからオフへの切換時（スイッチングのオフ時）において、図中破線で示す空乏層の広がりについて、ＰＮコラム対が完全空乏化するタイミングをトランジスタ形成面内（横方向）でずらすことができるため、オンからオフへの切換時における電圧の跳ね上がりを抑制することができる。   Thus, as shown in FIG. 5, when the transistor is switched from on to off (when switching is off), the timing at which the PN column pair is fully depleted with respect to the spread of the depletion layer indicated by the broken line in the figure is formed. Since it can be shifted in the plane (lateral direction), it is possible to suppress a voltage jump at the time of switching from on to off.

このように、Ｎ型不純物領域（Ｎコラム）４のみの不純物濃度を変えても、あるいは、Ｐ型不純物領域（Ｐコラム）５のみの不純物濃度を変えてもよい。
（第３の実施の形態）
次に、第３の実施の形態を、第１の実施の形態との相違点を中心に説明する。 Thus, the impurity concentration of only the N-type impurity region (N column) 4 may be changed, or the impurity concentration of only the P-type impurity region (P column) 5 may be changed.
(Third embodiment)
Next, the third embodiment will be described with a focus on differences from the first embodiment.

図６は、図１に代わる本実施形態における半導体装置の縦断面図である。本半導体装置も縦型ＭＯＳＦＥＴであって、かつ、スーパージャンクション構造を有している。
Ｎ型不純物領域４の不純物濃度をＮ１の一種類とし、Ｐ型不純物領域５の不純物濃度をＰ１の一種類とし、各Ｐ型不純物領域５の幅Ｗ５を一定にし、Ｎ型不純物領域４の幅Ｗ４については三種類としている。 FIG. 6 is a longitudinal sectional view of a semiconductor device according to the present embodiment, which replaces FIG. This semiconductor device is also a vertical MOSFET and has a super junction structure.
The impurity concentration of the N-type impurity region 4 is one type of N1, the impurity concentration of the P-type impurity region 5 is one type of P1, the width W5 of each P-type impurity region 5 is constant, and the width of the N-type impurity region 4 There are three types of W4.

このようにして、各Ｎ型不純物領域４の不純物濃度を等しくするとともに各Ｐ型不純物領域５の不純物濃度を等しくし、さらに、各Ｐ型不純物領域５の幅Ｗ５を等しくし、さらには、Ｎ型不純物領域４の幅Ｗ４を横方向において場所により異ならせることによって、コラム対の横方向での不純物面密度を場所により不均一化している。   In this way, the impurity concentration of each N-type impurity region 4 is made equal, the impurity concentration of each P-type impurity region 5 is made equal, the width W5 of each P-type impurity region 5 is made equal, and further, N By making the width W4 of the type impurity region 4 different depending on the location in the lateral direction, the impurity surface density in the lateral direction of the column pair is made non-uniform depending on the location.

これにより、図７に示すように、トランジスタのオンからオフへの切換時（スイッチングのオフ時）において図中破線で示す空乏層の広がりについて、ＰＮコラム対が完全空乏化するタイミングをトランジスタ形成面内（横方向）でずらすことができるため、オンからオフへの切換時における電圧の跳ね上がりを抑制することができる。   As a result, as shown in FIG. 7, when the transistor is switched from on to off (when switching is turned off), the timing at which the PN column pair is fully depleted with respect to the spread of the depletion layer indicated by the broken line in the figure is the transistor formation surface. Since it can be shifted inwardly (laterally), it is possible to suppress a voltage jump at the time of switching from on to off.

次に、本スーパージャンクション構造を有する半導体基板の製造方法について説明する。
図８に示すように、Ｎ型半導体基板としてのＮ型シリコンウェハ２０を用意し、当該ウェハ２０に対しウェハ面内において図９に示すようにマスク２１を用いてイオンエッチングを行ってトレンチ２２を形成する。トレンチを形成する際に、トレンチ２２の溝幅Ｗｔは一様で（一定にし）、残し幅Ｗｓが二種類以上となるようにする。 Next, a method for manufacturing a semiconductor substrate having the super junction structure will be described.
As shown in FIG. 8, an N-type silicon wafer 20 is prepared as an N-type semiconductor substrate, and ion etching is performed on the wafer 20 using a mask 21 in the wafer surface as shown in FIG. Form. When forming the trench, the groove width Wt of the trench 22 is uniform (constant), and the remaining width Ws is set to two or more types.

その後、図１０に示すように、Ｎ型シリコンウェハ２０の上に、Ｐ型のエピタキシャル膜２３を形成してトレンチ２２をエピタキシャル膜２３で埋め込む。その後、Ｎ型シリコンウェハ２０の主面側（上面側）、つまり、エピタキシャル膜２３の上面側を研磨して平坦化する。この研磨はシリコンウェハ２０が露出するまで行う。さらに、図１１に示すように、Ｎ型シリコンウェハ２０の上面にＮ型エピタキシャル膜２４を形成する。なお、Ｎ型シリコンウェハ２０の上面にＮ型エピタキシャル膜２４を形成する代わりに、Ｎ型シリコンウェハ２０の上面にイオン注入してＮ型の表面シリコン層を形成してもよい。   Thereafter, as shown in FIG. 10, a P-type epitaxial film 23 is formed on the N-type silicon wafer 20 and the trench 22 is buried with the epitaxial film 23. Thereafter, the main surface side (upper surface side) of the N-type silicon wafer 20, that is, the upper surface side of the epitaxial film 23 is polished and flattened. This polishing is performed until the silicon wafer 20 is exposed. Further, as shown in FIG. 11, an N-type epitaxial film 24 is formed on the upper surface of the N-type silicon wafer 20. Instead of forming the N type epitaxial film 24 on the upper surface of the N type silicon wafer 20, ions may be implanted into the upper surface of the N type silicon wafer 20 to form an N type surface silicon layer.

また、Ｎ型シリコンウェハ２０の裏面（下面）をトレンチ２２近傍まで研磨し、この研磨面にＮ＋シリコン基板を貼り合わせる。なお、Ｎ型シリコンウェハ２０の裏面の研磨およびＮ＋シリコン基板の貼り合わせに代わり、Ｎ型シリコンウェハ２０の裏面（下面）からイオン注入してＮ型シリコンウェハ２０の裏面にＮ＋シリコン層を形成してもよい。 Further, the back surface (lower surface) of the N-type silicon wafer 20 is polished to the vicinity of the trench 22 and an N + silicon substrate is bonded to the polished surface. Instead of polishing the back surface of the N-type silicon wafer 20 and bonding the N + silicon substrate, ions are implanted from the back surface (lower surface) of the N-type silicon wafer 20 to form an N + silicon layer on the back surface of the N-type silicon wafer 20. It may be formed.

このように形成した半導体基板（スーパージャンクション構造を有する半導体基板）を用いて図６に示す縦型ＭＯＳＦＥＴを製造する。つまり、Ｐ型チャネル形成領域６、Ｎ型ソース領域７、ゲート酸化膜８、ゲート電極９、シリコン酸化膜１０、ソース電極１１、ドレイン電極１２を形成する。このようにして、図６のスーパージャンクションＭＯＳＦＥＴが完成する。   The vertical MOSFET shown in FIG. 6 is manufactured using the semiconductor substrate thus formed (semiconductor substrate having a super junction structure). That is, the P-type channel formation region 6, the N-type source region 7, the gate oxide film 8, the gate electrode 9, the silicon oxide film 10, the source electrode 11, and the drain electrode 12 are formed. In this way, the super junction MOSFET of FIG. 6 is completed.

他の製造方法として、図１２に示すように、Ｎ型エピタキシャル膜４ａ，４ｂ，４ｃ，４ｄ，４ｅの成膜と、イオン注入（および拡散）によるＰ型不純物領域５を繰り返してＰＮコラム対を作ってもよい。つまり、Ｎ＋シリコン基板１上にＮ型エピタキシャル膜４ａを形成し、このＮ型エピタキシャル膜４ａの所定領域にＰ型不純物領域５を形成し、引き続き、Ｎ型エピタキシャル膜４ａの上にＮ型エピタキシャル膜４ｂを形成し、このＮ型エピタキシャル膜４ｂにＰ型不純物領域５を形成し、以後これを繰り返して、Ｎ型不純物領域４およびＰ型不純物領域５を縦方向に延設する。 As another manufacturing method, as shown in FIG. 12, N-type epitaxial films 4a, 4b, 4c, 4d, and 4e are formed and a P-type impurity region 5 is repeatedly formed by ion implantation (and diffusion) to form a PN column pair. You can make it. That is, the N type epitaxial film 4a is formed on the N + silicon substrate 1, the P type impurity region 5 is formed in a predetermined region of the N type epitaxial film 4a, and then the N type epitaxial film 4a is formed on the N type epitaxial film 4a. A film 4b is formed, a P-type impurity region 5 is formed in the N-type epitaxial film 4b, and thereafter this is repeated to extend the N-type impurity region 4 and the P-type impurity region 5 in the vertical direction.

また、図９における残し幅Ｗｓを変えるのではなく溝幅Ｗｔを変えてもよい。即ち、残し幅Ｗｓは一様で（一定にし）、トレンチ２２の溝幅Ｗｔが二種類以上となるようにしてもよい。
（参考例）
次に、参考例を、第１の実施の形態との相違点を中心に説明する。 Further, instead of changing the remaining width Ws in FIG. 9, the groove width Wt may be changed. That is, the remaining width Ws may be uniform (constant), and the groove width Wt of the trench 22 may be two or more types.
( Reference example )
Next, a reference example will be described focusing on differences from the first embodiment.

図１３には、本参考例におけるＰＮコラム対を示す。その他の構成については図１と同じなので説明は省略する。
第１〜第３の実施形態ではコラム単位（不純物領域単位）で面密度を変えるようにしたが、本参考例ではコラム内部で縦方向に不純物面密度差をつけている。つまり、半導体装置のアクティブ領域における、コラム対の、縦方向（電流が流れる方向）Ｚでの不純物面密度を場所（深さ）により不均一化している。 FIG. 13 shows a PN column pair in this reference example . Other configurations are the same as those in FIG.
In the first to third embodiments, the surface density is changed in column units (impurity region units), but in this reference example , the impurity surface density difference is given in the vertical direction inside the columns. That is, the impurity surface density in the vertical direction (direction in which current flows) Z of the column pair in the active region of the semiconductor device is made non-uniform depending on the location (depth).

具体的には、Ｎ型不純物領域４の不純物濃度をＮ１の一種類とし、Ｐ型不純物領域５の不純物濃度をＰ１の一種類とし、Ｎ型不純物領域４についての縦方向Ｚでの幅Ｗ４（Ｚ）は下端部が最も広く上側ほど直線的に狭くなり、Ｐ型不純物領域５についての縦方向Ｚでの幅Ｗ５（Ｚ）は下端部が最も狭く上側ほど直線的に広くなっている。   Specifically, the impurity concentration of the N-type impurity region 4 is one type of N1, the impurity concentration of the P-type impurity region 5 is one type of P1, and the width W4 in the vertical direction Z of the N-type impurity region 4 ( Z) is widest at the lower end and linearly narrows toward the upper side, and the width W5 (Z) in the vertical direction Z of the P-type impurity region 5 is linearly wider at the lower end and narrower at the upper side.

このようにして、各Ｎ型不純物領域４の不純物濃度を等しくするとともに各Ｐ型不純物領域５の不純物濃度を等しくし、さらに、Ｎ型不純物領域４についての縦方向での幅Ｗ４およびＰ型不純物領域５についての縦方向での幅Ｗ５を、縦方向において場所（深さ）により異ならせることによって、コラム対の縦方向での不純物面密度を場所により不均一化している。   In this way, the impurity concentration of each N-type impurity region 4 is made equal, the impurity concentration of each P-type impurity region 5 is made equal, and the width W4 and the P-type impurity in the vertical direction of the N-type impurity region 4 are further made. By making the width W5 in the vertical direction of the region 5 different depending on the location (depth) in the vertical direction, the impurity surface density in the vertical direction of the column pair is made non-uniform depending on the location.

これにより、図１４に示すように、トランジスタのオンからオフへの切換時（スイッチングのオフ時）において図中破線で示す空乏層の広がりについて、ＰＮコラム対が完全空乏化するタイミングを電流が流れる方向でずらすことができる。そのため、オンからオフへの切換時における電流の変化率を小さくし電圧の跳ね上がりを抑制することができる。   Accordingly, as shown in FIG. 14, when the transistor is switched from on to off (when switching is off), the current flows at the timing when the PN column pair is fully depleted with respect to the spread of the depletion layer indicated by the broken line in the figure. Can be shifted in the direction. Therefore, it is possible to reduce the rate of change of current at the time of switching from on to off, and to suppress voltage jump.

図１３に代わり、図１５に示すように、Ｎ型不純物領域４の縦方向での幅およびＰ型不純物領域５の縦方向での幅を縦方向において場所（深さ）により異ならせ、かつ、領域４，５についての横方向での幅（図１５においてはＰ型不純物領域５の横方向での幅）も各領域４，５（図１５においては各Ｐ型不純物領域５）で異ならせるようにしてもよい。なお、図１５ではＰ型不純物領域５の横方向での幅を各領域５で異ならせたが、Ｎ型不純物領域４の横方向での幅を各領域４で異ならせても、あるいは、Ｎ型不純物領域４およびＰ型不純物領域５の両方について横方向での幅を両方の各領域４，５で異ならせてもよい。   Instead of FIG. 13, as shown in FIG. 15, the width in the vertical direction of the N-type impurity region 4 and the width in the vertical direction of the P-type impurity region 5 are varied depending on the location (depth) in the vertical direction, and The widths of the regions 4 and 5 in the lateral direction (the width in the lateral direction of the P-type impurity region 5 in FIG. 15) are also made different in the regions 4 and 5 (the P-type impurity regions 5 in FIG. 15). It may be. In FIG. 15, the lateral width of the P-type impurity region 5 is different in each region 5, but the lateral width of the N-type impurity region 4 is different in each region 4, or N The widths in the lateral direction of both the type impurity region 4 and the P type impurity region 5 may be made different in each of the regions 4 and 5.

前記実施形態および参考例は以下のようにしてもよい。
図１等でのシリコンウェハとして高不純物濃度シリコン基板１に低不純物濃度のシリコン層２を積層したエピタキシャルウェハを用いても、バルク基板を用いてもよい。 The embodiment and the reference example may be as follows.
As the silicon wafer in FIG. 1 or the like, an epitaxial wafer in which a silicon layer 2 having a low impurity concentration is stacked on a silicon substrate 1 having a high impurity concentration may be used, or a bulk substrate may be used.

また、ＰＮコラム（Ｎ型不純物領域４とＰ型不純物領域５）の作成方法として、トレンチ形成後にトレンチ側壁からイオン注入して埋め込んでもよい。また、ＰＮコラムの作成方法として、トレンチ形成後にトレンチ内に不純物ドープト材料（例えば酸化物）を埋め込み、熱処理により不純物ドープト材料から不純物をトレンチ側壁側に拡散する方法を採ってもよい。あるいは、ＰＮコラムの作成方法として、トレンチを形成することなく、単にイオン注入と拡散によりコラムを作ってもよい。   Further, as a method of creating the PN column (N-type impurity region 4 and P-type impurity region 5), ions may be implanted from the trench side wall and buried after the trench is formed. In addition, as a method for forming the PN column, a method may be employed in which an impurity doped material (for example, an oxide) is embedded in the trench after the trench is formed, and the impurity is diffused from the impurity doped material to the trench sidewall by heat treatment. Alternatively, as a method for creating the PN column, the column may be simply formed by ion implantation and diffusion without forming a trench.

コラム対の、電流が流れる方向に直交する方向での不純物面密度を場所により不均一化するためのやり方として、広義には、Ｎ型不純物領域４の幅Ｗ４およびＰ型不純物領域５の幅Ｗ５およびＮ型不純物領域４の不純物濃度およびＰ型不純物領域５の不純物濃度の少なくとも１つを、電流が流れる方向に直交する方向において場所により異ならせればよい。   In a broad sense, the width W4 of the N-type impurity region 4 and the width W5 of the P-type impurity region 5 can be broadly defined as a method for making the impurity surface density in the direction perpendicular to the direction of current flow of the column pair different depending on the location. In addition, at least one of the impurity concentration of the N-type impurity region 4 and the impurity concentration of the P-type impurity region 5 may be varied depending on the location in a direction orthogonal to the direction in which the current flows.

プレーナー型のＭＯＳＦＥＴを例に説明したが、コンケーブ型でも、トレンチ型でも同様の効果が得られる。図１６にはトレンチゲート型ＭＯＳＦＥＴの場合の一例を示す。図１６においてＰ型シリコン層３０の表層部にはＮ型ソース領域３１が形成されるとともにＰ型シリコン層３０にはトレンチ３２がソース領域３１およびＰ型シリコン層３０を貫通するように形成され、トレンチ３２内にゲート酸化膜３３を介してゲート電極３４が形成されている。ゲート電極３４はシリコン酸化膜３５にて覆われ、その上にはソース電極３６が形成されている。また、基板１の裏面にはドレイン電極３７が形成されている。   Although a planar type MOSFET has been described as an example, the same effect can be obtained with either a concave type or a trench type. FIG. 16 shows an example of a trench gate type MOSFET. In FIG. 16, an N-type source region 31 is formed in the surface layer portion of the P-type silicon layer 30 and a trench 32 is formed in the P-type silicon layer 30 so as to penetrate the source region 31 and the P-type silicon layer 30. A gate electrode 34 is formed in the trench 32 via a gate oxide film 33. The gate electrode 34 is covered with a silicon oxide film 35, and a source electrode 36 is formed thereon. A drain electrode 37 is formed on the back surface of the substrate 1.

また、横型ＭＯＳＦＥＴに適用してもよい。図１７には横型ＭＯＳＦＥＴの場合の一例を示す。図１７においてＮ型シリコン基板４０の上面での表層部にＰ型チャネル形成領域４１が形成され、そのチャネル形成領域４１内での表層部にＮ型ソース領域４２が形成されている。基板４０の上面でのチャネル形成領域４１が露出する部位にはゲート酸化膜４３を介してゲート電極４４が形成されている。また、Ｎ型シリコン基板４０の上面においてＰ型チャネル形成領域４１とは離間した位置において表層部にＮ＋ドレイン領域４５が形成されている。Ｐ型チャネル形成領域４１とＮ＋ドレイン領域４５とはそれぞれ帯状に形成され、かつ、一定の距離をおいて平行に形成されている。 Further, it may be applied to a lateral MOSFET. FIG. 17 shows an example of a lateral MOSFET. In FIG. 17, a P-type channel formation region 41 is formed in the surface layer portion on the upper surface of the N-type silicon substrate 40, and an N-type source region 42 is formed in the surface layer portion in the channel formation region 41. A gate electrode 44 is formed through a gate oxide film 43 at a portion where the channel formation region 41 is exposed on the upper surface of the substrate 40. An N + drain region 45 is formed in the surface layer portion at a position separated from the P-type channel formation region 41 on the upper surface of the N-type silicon substrate 40. The P-type channel formation region 41 and the N + drain region 45 are each formed in a strip shape, and are formed in parallel at a certain distance.

Ｐ型チャネル形成領域４１とＮ＋ドレイン領域４５との間において、Ｎ型シリコン基板４０の上面での表層部には、横方向（電流が流れる方向）に延びるＮ型不純物領域４６と、同じく横方向（電流が流れる方向）に延びるＰ型不純物領域４７とが隣接して交互に配置されている。 Between the P-type channel formation region 41 and the N + drain region 45, the surface layer portion on the upper surface of the N-type silicon substrate 40 has an N-type impurity region 46 extending in the lateral direction (the direction in which current flows). P-type impurity regions 47 extending in the direction (direction in which current flows) are alternately arranged adjacent to each other.

ここで、例えば、各Ｎ型不純物領域４６の不純物濃度を等しくし、各Ｐ型不純物領域４７の不純物濃度を等しくし、各Ｎ型不純物領域４６の幅Ｗ４６を等しくし、Ｐ型不純物領域４７の幅Ｗ４７を横方向（詳しくは図中のＹ方向）において場所により異ならせることによって、コラム対の横方向（詳しくは図中のＹ方向）での不純物面密度を場所により不均一化する。   Here, for example, the impurity concentration of each N-type impurity region 46 is made equal, the impurity concentration of each P-type impurity region 47 is made equal, the width W46 of each N-type impurity region 46 is made equal, and the P-type impurity region 47 By varying the width W47 depending on the location in the horizontal direction (specifically, the Y direction in the drawing), the impurity surface density in the horizontal direction (specifically, the Y direction in the drawing) of the column pair is made non-uniform depending on the location.

また、ＭＯＳＦＥＴ以外にも、ＩＧＢＴやダイオードに適用してもよい。
これまでの説明では第１導電型がＮ型で、第２導電型がＰ型であったが、これを逆にして第１導電型がＰ型で、第２導電型がＮ型でもよい。 Moreover, you may apply to IGBT and a diode besides MOSFET.
In the above description, the first conductivity type is N type and the second conductivity type is P type. However, the first conductivity type may be P type and the second conductivity type may be N type.

次に、不純物面密度を場所により不均一化するときの不純物面密度の最適化について言及する。
図１８には、不純物面密度と素子耐圧の関係を示す。 Next, the optimization of the impurity surface density when the impurity surface density is made uneven depending on the location will be described.
FIG. 18 shows the relationship between the impurity surface density and the element breakdown voltage.

図１８は、素子構造が異なる構造１，２を用い、構造１，２において不純物面密度を異ならせて耐圧測定を行ったものである（構造１，２として、例えば図４の構造と図６の構造）。より具体的には、例えば図４の構造において例えば濃度Ｎ１，Ｎ２，Ｎ３の三種類となっている所を全て濃度Ｎ１とした半導体装置と全て濃度Ｎ２とした半導体装置と全て濃度Ｎ３とした半導体装置で耐圧測定を行うとともに、例えば図６の構造において例えば幅Ｗ４（小），幅Ｗ４（中），幅Ｗ４（大）の三種類となっている所を全て幅Ｗ４（小）とした半導体装置と全て幅Ｗ４（中）とした半導体装置と全て幅Ｗ４（大）とした半導体装置で耐圧測定を行ったものである。   FIG. 18 shows the result of breakdown voltage measurement using structures 1 and 2 having different element structures and different impurity surface densities in structures 1 and 2 (structures 1 and 2, for example, the structure shown in FIG. Structure). More specifically, for example, in the structure of FIG. 4, for example, a semiconductor device having all the concentrations N1, N2, N3, and a semiconductor device having all the concentrations N2, and a semiconductor having all the concentrations N3. For example, in the structure shown in FIG. 6, for example, in the structure shown in FIG. 6, the width W4 (small), the width W4 (medium), and the width W4 (large) are all width W4 (small). The withstand voltage measurement was performed using the semiconductor device having the entire width W4 (medium) and the semiconductor device having the entire width W4 (large).

図１８において、素子耐圧が最大になる不純物面密度から、正負、即ち、高不純物面密度側と低不純物面密度側のいずれにずれても素子耐圧は低下し、ほぼ左右対称の特性を示す。この傾向は、素子構造を変えても同じである。   In FIG. 18, the element breakdown voltage decreases even if it shifts from the impurity surface density at which the element breakdown voltage is maximized to either positive or negative, that is, either the high impurity plane density side or the low impurity plane density side, and exhibits substantially bilaterally symmetric characteristics. This tendency is the same even if the element structure is changed.

そこで、不純物面密度を二種類設定する場合、耐圧が最大になる不純物面密度を基準として、正負に同じだけずらした、ほぼ耐圧が等しい２点を選定する。具体的には、例えば、図１８において二種類の不純物面密度α１，α２は耐圧が最大になる不純物面密度から正負に同じ量だけずらして設定している。これにより、素子耐圧を局所的に低下させることなくオフ時の電圧の跳ね上がりを低減できる。つまり、単に素子耐圧を場所により低下させると、ブレークダウン時に電流集中を起こし素子破壊に至る可能性があるが、ほぼ耐圧が等しい２点を選定することにより電流集中させることなくブレークダウン時に電流集中を回避して素子破壊を防止することができる。   Therefore, when two types of impurity surface densities are set, two points having substantially the same breakdown voltage, which are shifted by the same positive and negative, are selected with reference to the impurity surface density at which the breakdown voltage is maximized. Specifically, for example, in FIG. 18, the two types of impurity surface densities α1 and α2 are set so as to be shifted from the impurity surface density at which the withstand voltage is maximized by the same amount in the positive and negative directions. Thereby, the jumping of the voltage at the time of OFF can be reduced without reducing the element withstand voltage locally. In other words, if the device breakdown voltage is simply reduced depending on the location, current concentration may occur during breakdown, leading to device destruction. However, by selecting two points with almost the same breakdown voltage, current concentration during breakdown is avoided. Can be avoided to prevent element destruction.

不純物面密度を三種類以上設定する場合は、正負に同じだけずらした２点と、その２点に挟まれた領域より不純物面密度を選定する。具体的には、例えば、図１８において三種類の不純物面密度α１，α２，α３について、不純物面密度α１，α２は耐圧が最大になる不純物面密度から正負に同じだけずらして設定し、不純物面密度α３は不純物面密度α１，α２に挟まれた領域に設定している。不純物面密度α３は不純物面密度α１，α２に挟まれた領域において中心に設定するとよりよい。同様に、図１８において四種類の不純物面密度β１，β２，β３，β４について、不純物面密度β１，β２は耐圧が最大になる不純物面密度から正負に同じだけずらして設定し、不純物面密度β３，β４は不純物面密度β１，β２に挟まれた領域に設定している。不純物面密度β３，β４は不純物面密度β１，β２に挟まれた領域において三等分した不純物面密度となるように設定するとよりよい。同様に、図１８において五種類の不純物面密度α１，α２，α３，α４，α５について、不純物面密度α１，α２は耐圧が最大になる不純物面密度から正負に同じだけずらして設定し、不純物面密度α３，α４，α５は不純物面密度α１，α２に挟まれた領域に設定している。不純物面密度α３，α４，α５は不純物面密度α１，α２に挟まれた領域において四等分した不純物面密度となるように設定するとよりよい。   When three or more types of impurity surface densities are set, the impurity surface density is selected from two points shifted by the same positive and negative values and a region sandwiched between the two points. Specifically, for example, for the three types of impurity surface densities α1, α2, and α3 in FIG. 18, the impurity surface densities α1, α2 are set to be shifted from the impurity surface density at which the withstand voltage is maximized by the same amount as the impurity surface density. The density α3 is set in a region sandwiched between the impurity surface densities α1 and α2. The impurity surface density α3 is better set at the center in the region sandwiched between the impurity surface densities α1 and α2. Similarly, in FIG. 18, for the four types of impurity surface densities β1, β2, β3, and β4, the impurity surface densities β1 and β2 are set to be shifted from the impurity surface density that maximizes the withstand voltage by the same amount, and the impurity surface density β3 , Β4 are set in a region sandwiched between the impurity surface densities β1, β2. The impurity surface densities β3 and β4 are preferably set so as to be an impurity surface density divided into three equal parts in a region sandwiched between the impurity surface densities β1 and β2. Similarly, for the five types of impurity surface densities α1, α2, α3, α4, and α5 in FIG. 18, the impurity surface densities α1 and α2 are set so as to be shifted from the impurity surface density that maximizes the withstand voltage by the same amount. The densities α3, α4, and α5 are set in a region between the impurity surface densities α1 and α2. The impurity surface densities α3, α4, and α5 are preferably set so that the impurity surface density is divided into four equal parts in a region sandwiched between the impurity surface densities α1 and α2.

なお、三種類以上とは、連続的に変化するものも含む。
以上のように、これまでの各実施形態および参考例において、不純物面密度を場所により不均一化すべく、不純物面密度として、二種類とし、かつ、耐圧が最大となる不純物面密度に対し高不純物面密度側と低不純物面密度側に等しいずれ量となる不純物面密度を設定すると、素子耐圧が局所的に低下するのを防止することができる。また、これまでの各実施形態および参考例において、不純物面密度を場所により不均一化すべく、不純物面密度として、三種類以上とし、かつ、耐圧が最大となる不純物面密度に対し高不純物面密度側と低不純物面密度側に等しいずれ量となる不純物面密度を設定するとともに、その間に挟まれた領域に残りの不純物面密度を設定すると、素子耐圧が局所的に低下するのを防止することができる。 The three or more types include those that change continuously.
As described above, in each of the above embodiments and reference examples , in order to make the impurity surface density non-uniform depending on the location, two types of impurity surface densities are used, and the impurity surface density is higher than the impurity surface density at which the breakdown voltage is maximized. If the impurity surface density is set such that the amount of shift is equal between the surface density side and the low impurity surface density side, it is possible to prevent the device breakdown voltage from being locally reduced. Further, in each of the embodiments and reference examples thus far, the impurity surface density is not less than three in order to make the impurity surface density non-uniform depending on the location, and the impurity surface density is higher than the impurity surface density with the maximum withstand voltage. When the impurity surface density is set so that the amount of shift is equal to the low impurity surface density side and the remaining impurity surface density is set in a region sandwiched therebetween, the device breakdown voltage is prevented from being locally reduced. be able to.

第１の実施形態における半導体装置の縦断面図。1 is a longitudinal sectional view of a semiconductor device according to a first embodiment. スーパージャンクション構造部の縦断面図。The longitudinal cross-sectional view of a super junction structure part. スイッチング時の波形図。Waveform diagram during switching. 第２の実施形態における半導体装置の縦断面図。The longitudinal cross-sectional view of the semiconductor device in 2nd Embodiment. スーパージャンクション構造部の縦断面図。The longitudinal cross-sectional view of a super junction structure part. 第３の実施形態における半導体装置の縦断面図。The longitudinal cross-sectional view of the semiconductor device in 3rd Embodiment. スーパージャンクション構造部の縦断面図。The longitudinal cross-sectional view of a super junction structure part. 製造工程を説明するための縦断面図。The longitudinal cross-sectional view for demonstrating a manufacturing process. 製造工程を説明するための縦断面図。The longitudinal cross-sectional view for demonstrating a manufacturing process. 製造工程を説明するための縦断面図。The longitudinal cross-sectional view for demonstrating a manufacturing process. 製造工程を説明するための縦断面図。The longitudinal cross-sectional view for demonstrating a manufacturing process. 別例の半導体装置の縦断面図。The longitudinal cross-sectional view of the semiconductor device of another example. 参考例におけるＰＮコラム対の縦断面図。The longitudinal cross-sectional view of the PN column pair in a reference example . スーパージャンクション構造部の縦断面図。The longitudinal cross-sectional view of a super junction structure part. 図１３に代わるＰＮコラム対の縦断面図。FIG. 14 is a longitudinal sectional view of a PN column pair instead of FIG. 13. 別例の半導体装置の縦断面図。The longitudinal cross-sectional view of the semiconductor device of another example. 別例の半導体装置の斜視図。The perspective view of the semiconductor device of another example. 不純物面密度と素子耐圧の関係図。The relationship diagram of impurity surface density and device breakdown voltage. 比較例における半導体装置の縦断面図。The longitudinal cross-sectional view of the semiconductor device in a comparative example. 比較例におけるスーパージャンクション構造部の縦断面図。The longitudinal cross-sectional view of the super junction structure part in a comparative example. 比較例におけるスーパージャンクション構造部の縦断面図。The longitudinal cross-sectional view of the super junction structure part in a comparative example. 比較例におけるスーパージャンクション構造部の縦断面図。The longitudinal cross-sectional view of the super junction structure part in a comparative example. 比較例におけるスイッチング時の波形図。The wave form figure at the time of switching in a comparative example.

符号の説明Explanation of symbols

１…Ｎ＋シリコン基板、２…シリコン層、３…シリコン層、４…Ｎ型不純物領域、５…Ｐ型不純物領域、２０…Ｎ型シリコンウェハ、２２…トレンチ、２３…Ｐ型エピタキシャル膜。 DESCRIPTION OF SYMBOLS 1 ... N + silicon substrate, 2 ... Silicon layer, 3 ... Silicon layer, 4 ... N-type impurity region, 5 ... P-type impurity region, 20 ... N-type silicon wafer, 22 ... Trench, 23 ... P-type epitaxial film.

Claims (6)

半導体基板において、電流が流れる方向に延びる第１導電型の不純物領域（４）と、同じく電流が流れる方向に延びる第２導電型の不純物領域（５）とが、電流が流れる方向に直交する方向において、隣接して交互に配置され、オン時に前記第１導電型の不純物領域（４）と前記第２導電型の不純物領域（５）からなるコラム対における前記第１導電型の不純物領域（４）がドリフト層となって電流が流れるとともにオフ時に前記第１導電型の不純物領域（４）と第２導電型の不純物領域（５）との界面から空乏層が広がる、スーパージャンクション構造を有する半導体装置であって、
半導体装置のアクティブ領域の全域において、隣り合う第１導電型の不純物領域（４）の幅（Ｗ４）および隣り合う第２導電型の不純物領域（５）の幅（Ｗ５）および隣り合う第１導電型の不純物領域（４）の不純物濃度および隣り合う第２導電型の不純物領域（５）の不純物濃度の少なくとも１つを異ならせた不均一領域をもたせることによって、前記コラム対の、電流が流れる方向に直交する方向での不純物面密度を不均一化したことを特徴とする半導体装置。 In the semiconductor substrate, the first conductivity type impurity region (4) extending in the direction of current flow and the second conductivity type impurity region (5) extending in the same direction of current flow are orthogonal to the direction of current flow. In FIG. 3, the first conductivity type impurity regions (4) in a column pair that are alternately arranged adjacent to each other and are turned on and made up of the first conductivity type impurity regions (4) and the second conductivity type impurity regions (5). ) Becomes a drift layer and a current flows, and a semiconductor having a super junction structure in which a depletion layer spreads from an interface between the first conductivity type impurity region (4) and the second conductivity type impurity region (5) when turned off. A device,
The width (W4) of the adjacent first conductivity type impurity region (4), the width (W5) of the adjacent second conductivity type impurity region (5), and the adjacent first conductivity in the entire active region of the semiconductor device. By providing a non-uniform region in which at least one of the impurity concentration of the type impurity region (4) and the impurity concentration of the adjacent second conductivity type impurity region (5) is different , current flows in the column pair. A semiconductor device characterized in that an impurity surface density in a direction orthogonal to the direction is made non- uniform. 各第１導電型の不純物領域（４）の幅（Ｗ４）を等しくするとともに各第２導電型の不純物領域（５）の幅（Ｗ５）を等しくし、前記不均一領域として、隣り合う第１導電型の不純物領域（４）の不純物濃度および隣り合う第２導電型の不純物領域（５）の不純物濃度を異ならせた領域をもたせることによって、前記コラム対の、電流が流れる方向に直交する方向での不純物面密度を不均一化したことを特徴とする請求項１に記載の半導体装置。 The width (W4) of each impurity region (4) of each first conductivity type is made equal, and the width (W5) of each impurity region (5) of each second conductivity type is made equal, so that the first region adjacent to each other as the non-uniform region . A direction perpendicular to the direction of current flow of the column pair is provided by providing a region in which the impurity concentration of the conductivity type impurity region (4) and the impurity concentration of the adjacent second conductivity type impurity region (5) are different. 2. The semiconductor device according to claim 1, wherein the impurity surface density is uneven . 各第１導電型の不純物領域（４）の幅（Ｗ４）を等しくするとともに各第２導電型の不純物領域（５）の幅（Ｗ５）を等しくし、さらに、各第２導電型の不純物領域（５）の不純物濃度を等しくし、前記不均一領域として、隣り合う第１導電型の不純物領域（４）の不純物濃度を異ならせた領域をもたせることによって、前記コラム対の、電流が流れる方向に直交する方向での不純物面密度を不均一化したことを特徴とする請求項１に記載の半導体装置。 The width (W4) of each impurity region (4) of each first conductivity type is made equal, the width (W5) of each impurity region (5) of each second conductivity type is made equal, and each impurity region of each second conductivity type is further made By making the impurity concentration of (5) equal, and providing the region where the impurity concentration of the adjacent first conductivity type impurity region (4) is different as the non-uniform region , the current flow direction of the column pair The semiconductor device according to claim 1, wherein the impurity surface density in a direction orthogonal to is made non- uniform. 各第１導電型の不純物領域（４）の不純物濃度を等しくするとともに各第２導電型の不純物領域（５）の不純物濃度を等しくし、さらに、各第２導電型の不純物領域（５）の幅（
Ｗ５）を等しくし、前記不均一領域として、隣り合う第１導電型の不純物領域（４）の幅（Ｗ４）を異ならせた領域をもたせることによって、前記コラム対の、電流が流れる方向に直交する方向での不純物面密度を不均一化したことを特徴とする請求項１に記載の半導体装置。 The impurity concentration of each impurity region (4) of the first conductivity type is made equal, the impurity concentration of the impurity region (5) of the second conductivity type is made equal, and the impurity region (5) of each second conductivity type is further made equal. width(
W5) is made equal, and the non-uniform region has a region in which the width (W4) of the adjacent first conductivity type impurity region (4) is different, thereby orthogonally crossing the column pair in the direction of current flow. 2. The semiconductor device according to claim 1, wherein the impurity surface density in the direction of the non- uniformity is made non- uniform. 不純物面密度を場所により不均一化すべく、不純物面密度として、二種類とし、かつ、耐圧が最大となる不純物面密度に対し高不純物面密度側と低不純物面密度側に等しいずれ量となる不純物面密度を設定したことを特徴とする請求項１〜４のいずれか１項に記載の半導体装置。 In order to make the impurity surface density non-uniform depending on the location, there are two types of impurity surface densities, and the amount of deviation is equal between the high impurity surface density side and the low impurity surface density side with respect to the impurity surface density at which the withstand voltage is maximized. the semiconductor device according to any one of claims 1 to 4, characterized in that setting the impurity surface density. 不純物面密度を場所により不均一化すべく、不純物面密度として、三種類以上とし、かつ、耐圧が最大となる不純物面密度に対し高不純物面密度側と低不純物面密度側に等しいずれ量となる不純物面密度を設定するとともに、その間に挟まれた領域に残りの不純物面密度を設定したことを特徴とする請求項１〜４のいずれか１項に記載の半導体装置。 In order to make the impurity surface density non-uniform depending on the location, there are three or more types of impurity surface densities, and the amount of shift equal to the high impurity surface density side and the low impurity surface density side with respect to the impurity surface density at which the withstand voltage is maximized. 5. The semiconductor device according to claim 1 , wherein an impurity surface density is set, and a remaining impurity surface density is set in a region sandwiched therebetween.
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