JP5206259B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device on which a power semiconductor element is mounted.

In a semiconductor device equipped with a power semiconductor element, the power semiconductor element is operated by bonding the electrode of the power semiconductor element to a lead frame that is a wiring line.
Since such a semiconductor device requires a rated current of 1 A or more per channel, high efficiency is required for the arrangement of the electrode pads of the power semiconductor element. For this reason, the vertical power semiconductor element whose energization direction is the vertical direction is mounted on the semiconductor device. A solder material is usually used as a bonding material for bonding the power semiconductor element and the lead frame (see, for example, Patent Document 1).
JP 2007-165690 A

  However, when a stress is repeatedly applied to the solder joint portion of the power semiconductor element by the operation of the power semiconductor element, peeling may occur at the solder joint portion. This causes a problem that the reliability of the electrical connection of the semiconductor device is impaired.

As a method for solving this problem, a method in which an element mounted on a semiconductor device is a lateral power semiconductor element is also conceivable.
However, the lateral power semiconductor element has an ESD (Electoro Static Dicharge) surge withstand of 1/5 or less as compared with a vertical power semiconductor element of the same size. For this reason, in order to obtain the ESD surge withstand capability equivalent to that of the vertical power semiconductor element in the horizontal power semiconductor element, there is a problem that the area must be increased and the semiconductor device cannot be reduced in size.

  The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor device that is highly reliable and can be downsized with respect to electrical connection.

  In order to solve the above-described problems, a die pad, a semiconductor chip in which a vertical element in which a back surface electrode is brought into contact with the die pad via a contact material, and a die pad and a front surface of the semiconductor chip are arranged. And a wiring for electrically connecting the formed electrode, wherein the back electrode and the electrode are electrically connected through an impurity layer formed in the semiconductor chip. .

  According to the above means, a highly reliable and small-sized semiconductor device can be realized with respect to electrical connection.

Hereinafter, a semiconductor device according to the present embodiment will be described in detail with reference to the drawings.
In this embodiment, a surge absorption IC chip (hereinafter referred to as an IC chip) is described as an example of a semiconductor device.

FIG. 1 is a schematic plan view of an essential part of a semiconductor device.
The semiconductor device 1 has a die pad 10d, a metal paste 11 disposed on the die pad 10d, and an IC chip 12 disposed on the metal paste 11. That is, the back side of the IC chip 12 and the die pad 10 d are electrically connected via the metal paste 11. A vertical element is formed on the IC chip 12.

  A plurality of electrode pads 13 and 14 are disposed on the main surface (front surface) of the IC chip 12. Each electrode pad 13 and each lead frame 10L are electrically connected through a bonding wire 15 which is a metal wiring. The electrode pad 14 is electrically connected to a lead frame 10L extending from the die pad 10d through the bonding wire 16. That is, the back surface of the IC chip 12 and the electrode pad 14 are electrically connected through the bonding wire 16.

  Such a semiconductor device 1 incorporates circuits such as a power Zener diode (hereinafter referred to as a diode), an input surge absorption circuit, a noise cut / level shift circuit, and a buffer circuit (described later).

For example, copper (Cu) is used as the material for the die pad 10d and the lead frame 10L.
Moreover, as a metal material contained in the metal paste 11, for example, silver (Ag) is used.

  Moreover, as a material of the electrode pads 13 and 14, for example, aluminum (Al) or copper (Cu) is used. Then, nickel (Ni) / gold (Au) plating may be applied from the lower layer. Or you may make the semiconductor base material (for example, silicon | silicone (Si) etc.) of IC chip 12 expose as an electrode pad, without giving the said plating.

  Moreover, as a material of the main surface (back surface electrode) opposite to the main surface of the IC chip 12 on which the electrode pads 13 and 14 are arranged, for example, aluminum (Al) or copper (Cu) is used. Yes. Then, nickel (Ni) / gold (Au) plating may be applied from the lower layer. Alternatively, a semiconductor substrate (for example, silicon (Si)) of the IC chip 12 may be exposed as an electrode pad.

Moreover, as a material of the bonding wires 15 and 16, for example, gold (Au) is used.
Further, a conductive plate (lead frame) may be used instead of the bonding wire 15.

Further, the number of electrode pads 13 and 14 arranged is not limited to the number shown.
Next, the structure of the semiconductor device 1 will be supplemented using a cross-sectional view. In the drawings shown below, the same members as those in FIG. 1 are denoted by the same reference numerals.

  FIG. 2 is a schematic cross-sectional view of a main part of the semiconductor device. FIG. 2 illustrates the state of the periphery of the electrode pad 14 described above and the periphery of the predetermined electrode pad 13 arranged in a region other than the electrode pad 14.

As shown in the figure, the IC chip 12 uses, for example, a p + type substrate 12s as a base material of the IC chip 12, and a p− epitaxial layer 12ep is formed on the p + type substrate 12s.
An n + layer 12n is formed in the p− epitaxial layer 12ep below the electrode pad 13, and the electrode pad 13 is disposed on the n + layer 12n. That is, a PN junction is formed below the electrode pad 13 and a vertical diode is disposed.

  On the other hand, below the electrode pad 14, a p + layer 12p having the same impurity concentration as that of the p + type substrate 12s is formed in the p− epitaxial layer 12ep, and the electrode pad 14 is disposed on the p + layer 12p. Then, the p + layer 12p in contact with the electrode pad 14 is extended to the p + type substrate 12s, and the p + layer 12p and the p + type substrate 12s are directly conducted.

That is, the back electrode 12 b and the electrode pad 14 are electrically connected through the p + impurity layer formed in the IC chip 12.
Thus, in the IC chip 12, the back surface electrode 12 b of the IC chip 12 is at the same potential as the die pad 10 d through the metal paste 11. Even if the IC chip 12 is peeled off from the die pad 10d, the back electrode 12b of the IC chip 12 is still connected to the lead frame 10L extending from the die pad 10d, the bonding wire 16, the electrode pad 14, and p + in the p-epitaxial layer 12ep. It has the same potential as the die pad 10d via the layer 12p and the p + type substrate 12s.

  According to the inventor's prior investigation, when gold (Au) plating is applied to the surface of the back electrode 12b, if the metal paste 11 is used as a contact material between the back electrode 12b and the die pad 10d, There may be a gap between the back electrode 12b and the die pad 10d.

  However, even in such a case, the back surface electrode 12b passes through the lead frame 10L extending from the die pad 10d, the bonding wire 16, the electrode pad 14, the p + layer 12p in the p− epitaxial layer 12ep, and the p + type substrate 12s. Thus, the back electrode 12b can always be at the same potential as the die pad 10d.

In addition, about the conductivity type of the impurity mixed in the semiconductor substrate of IC chip 12, you may replace said p type and n type.
Next, the configuration of the IC chip 12 will be described using a functional block diagram.

FIG. 3 is a functional block diagram of the semiconductor device. In this figure, a functional block diagram of the one-channel semiconductor device 1 is illustrated.
The IC chip 12 is integrated into one chip by integrating an input surge absorption circuit, a noise cut / level shift circuit, and a buffer circuit. These circuits are constituted by, for example, a complementary metal oxide semiconductor (CMOS) circuit in which a plurality of power MOSFET (metal oxide semiconductor field effect transistor) elements are combined. Each terminal of the IC chip 12 corresponds to one of the electrode pads 13 and 14.

  The VB terminal is connected to, for example, a battery power source. The VOS terminal is connected to a predetermined power supply voltage. That is, the VB terminal and the VOS terminal are power supply terminals. A pull-up / pull-down resistor 20 is connected between the IN terminal and the VR terminal of the IC chip 12. A diode 21 is connected between the IN terminal and GND, and a diode 22 is connected between the VB terminal and GND.

  If such a semiconductor device 1 is used, for example, ESD energy applied to the IN terminal is efficiently absorbed by the diode 21 arranged between the IN terminal and GND. As described above, the diode 21 is disposed below the predetermined electrode pad 13 of the IC chip 12 (see FIG. 2).

  The electrical signal from which the ESD energy has been removed is converted into a predetermined voltage after the noise is removed by a noise cut / level shift circuit. Further, the signal is subjected to filtering such as blocking of high frequency noise by the buffer circuit, and is output to the OUT terminal. Thereby, an electrical signal in which surge is suppressed is obtained from the OUT terminal.

  Thus, according to semiconductor device 1 concerning this embodiment, back electrode 12b of IC chip 12 and die pad 10d are made to contact using metal paste 11 which is a contact material. With such a configuration, even when stress is repeatedly applied to the IC chip 12 by a heating cycle, the stress can be relaxed by the metal paste 11. Thereby, the back surface electrode 12b and the die pad 10d are difficult to peel off.

  Further, even if a gap is formed between the back electrode 12b and the die pad 10d and the back electrode 12b and the die pad 10d are partially separated, the lead frame 10L extending from the die pad 10d is provided on the IC chip 12. And a bonding wire 16, and further, a spare line of an electrode pad 14, a p + layer 12 p, and a p + type substrate 12 s is provided. As a result, the potential of the back electrode 12b is always maintained at the same potential as that of the die pad 10d.

That is, the IC chip 12 has a double conduction path for conducting the back electrode 12b and the die pad 10d.
When an n + type substrate (not shown) is used as the IC chip 12 instead of the p + type substrate 12s, the conductivity type of the impurity layer illustrated in FIG. 2 is reversed. Then, the semiconductor device shown in FIG. 4 can be configured.

FIG. 4 is another functional block diagram of the semiconductor device.
For example, the diodes 21 and 22 of the input surge absorbing circuit are connected as shown in FIG. That is, the diode 21 is connected between the IN terminal and the VB terminal, and the diode 22 is connected between the VB terminal and GND.

As described above, the diodes 21 and 22 are commonly connected to either the VB terminal or the GND depending on the conductivity type of the semiconductor substrate on which the IC chip is formed.
Here, for example, in the configuration shown in FIG. 4, the surge between the IN terminal and GND flows through the path of the IN terminal → diode 21 (forward direction) → VB terminal → diode 22 (reverse direction) → GND, and the surge is absorbed. .

  As described above, surges can be effectively absorbed by inserting diodes at two locations on the IC chip 12 shown in FIG. 3 or FIG. Therefore, the semiconductor device 1 can be stably operated.

  Further, in the semiconductor device according to the present embodiment, the element configuration of the IC chip 12 is vertical, so that the size of the semiconductor device can be reduced as compared with the case where a horizontal power semiconductor element is used. In addition, a semiconductor device having sufficient ESD surge resistance is realized.

For example, FIG. 5 is a diagram for explaining the dependence of the ESD surge resistance on the element area.
Here, the horizontal axis of FIG. 5 shows the element area (mm ² ) formed on the IC chip 12, and the vertical axis shows the ESD surge withstand (V). The scale is displayed logarithmically.

This figure also shows the element area-ESD surge resistance of a vertical element and a horizontal element with a rated voltage of 60 V and a 150 pF-150Ω condition.
As shown in the figure, when the ESD surge withstand is up to about 3 kV, the lateral MOSFET requires about three times the area of the vertical MOSFET to obtain the ESD surge withstand equivalent to that of the vertical MOSFET.

  Further, if the ESD surge withstand exceeds 3 kV, the horizontal MOSFET requires an area about 10 times or more that of the vertical MOSFET in order to obtain the ESD surge withstand equivalent to that of the vertical MOSFET.

On the other hand, the vertical Zener diode has higher resistance with a smaller area than the vertical MOSFET.
For example, up to about 3 kV of ESD surge withstand, a vertical MOSFET requires about 1.5 times the area of a vertical Zener diode to obtain an ESD surge withstand equivalent to that of a vertical Zener diode. Become.

  In addition, if the ESD surge withstand exceeds 3 kV, the vertical MOSFET requires about 6 to 10 times more area than the vertical Zener diode in order to obtain the ESD surge withstand equivalent to that of the vertical Zener diode. Resulting in.

On the other hand, it has been found that in a lateral MOSFET provided with a vertical Zener diode, there is a region where the ESD surge resistance is constant regardless of the element area.
Therefore, as in this embodiment, the configuration of the diode of the IC chip 12 is vertical, so that the semiconductor device can be reduced in size and a semiconductor device having sufficient ESD surge resistance can be realized. To do.

  Thus, according to the present embodiment, a highly reliable and small-sized semiconductor device 1 is realized with respect to electrical connection.

It is a principal part schematic diagram of a semiconductor device. It is a principal part cross-sectional schematic diagram of a semiconductor device. It is a functional block diagram of a semiconductor device. It is another functional block diagram of a semiconductor device. It is a figure explaining the element area dependence of ESD surge tolerance.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10d Die pad 10L Lead frame 11 Metal paste 12 IC chip 12ep p-Epitaxial layer 12s p + type substrate 12n n + layer 12p p + layer 12b Back electrode 13, 14 Electrode pad 15, 16 Bonding wire 20 Pull-up pull-down resistor 21, 22 Diode

Claims (4)

Die pad,
A semiconductor chip in which a vertical element in which a back electrode is brought into contact with the die pad via a contact material;
Wiring that electrically connects the die pad and the electrode disposed on the front surface of the semiconductor chip;
The semiconductor device is characterized in that the back electrode and the electrode are electrically connected through an impurity layer formed in the semiconductor chip.   The semiconductor device according to claim 1, wherein surge absorbing means is provided in the semiconductor chip.   3. The semiconductor device according to claim 2, wherein the surge absorbing means is a vertical diode.   4. The semiconductor device according to claim 3, wherein the diode is provided at least at one place between the input terminal and the power supply terminal, between the input terminal and the ground terminal, and between the power supply terminal and the ground terminal of the semiconductor chip.

Images