JP5201616B2 - Memory device, memory cell, and memory cell array - Google Patents

Description

  The present invention relates to a memory element, a memory cell, and a memory cell array, and in particular, uses a material whose resistance value changes in response to a temperature change, such as a phase change material that stabilizes in a crystalline phase or an amorphous phase at room temperature. The present invention relates to a phase change nonvolatile memory element, a memory cell, and a memory cell array that record information using a difference in resistance value.

Recently, a phase-change nonvolatile memory called PRAM (Phase change RAM) has been attracting attention as a next-generation nonvolatile memory. For PRAM, a phase change material that is stabilized in either a crystalline phase or an amorphous phase at room temperature is used. Examples of the phase change material include chalcogenide-based materials such as GST (Ge—Sb—Te). For example, Ge ₂ Sb ₂ Te ₅ has a melting point of 630 ° C. and a crystallization temperature of 160 ° C. When this material is heated to 600 ° C. or higher and melted, and then rapidly cooled to room temperature, it is stabilized in an amorphous phase. On the other hand, when this material is heated to 160 ° C. or higher and then gradually cooled to room temperature, it is stabilized in the crystalline phase.

  In a chalcogenide-based material, the specific resistance of the amorphous phase is two to four orders of magnitude higher than the specific resistance of the crystalline phase. In PRAM, information is recorded by utilizing the difference in resistance between the amorphous phase and the crystalline phase. Recording (writing) of information in the PRAM is performed by passing a recording current through the phase change material to heat the phase change material and transferring the phase change material to an amorphous phase or a crystalline phase. For example, binary information can be recorded by setting the high-resistance amorphous phase to “1” and the low-resistance crystal phase to “0”. Further, by detecting the amount of current that flows when a predetermined voltage is applied to the phase change material, it is possible to determine whether the phase is an amorphous phase or a crystalline phase and to reproduce (read) the written information.

  Conventionally, from the viewpoint of improving the recording density, various methods of multi-value recording on the PRAM have been studied (for example, see Patent Documents 1 and 2). In these methods, multilevel recording is realized by using an intermediate layer in which a phase change material is partially transformed into an amorphous phase or a crystalline phase. For example, “0” when the entire phase change material is the crystalline phase, “1” when 1/4 of the total volume of the phase change material is transferred to the amorphous phase, and 1 / of the total volume of the phase change material. By setting “2” when 2 is transferred to the amorphous phase and “3” when transferring the entire phase change material to the amorphous phase, multi-value information can be recorded.

WO2005 / 031725 JP 2006-155700 A

  However, in the conventional multi-value recording method, since the volume ratio of each phase varies depending on the size of the phase change material and the number of phase changes, it is difficult to reliably perform multi-value recording.

  The present invention has been made to solve the above problems, and an object of the present invention is to include a novel phase change type nonvolatile memory element capable of reliably performing multi-value recording, and the memory element. A memory cell and a memory cell array are provided.

  In order to achieve the above object, a memory element according to claim 1 includes a pair of electrodes arranged at a predetermined interval, a first switch resistance element that is turned on by heat generation when energized, and a first switch element The first switch resistance element is configured to include a first resistance element formed of a resistor, and has one end connected to one of the pair of electrodes and the other end connected to the other of the pair of electrodes. And a first memory section in which a current path that passes through the first resistance element in series is formed, and a second switch resistance element that is turned on by being heated by the first resistance element that generates heat when energized, And a second resistance element formed of a second resistor, and connected in parallel with the first resistance element, the second switch resistance element and the second resistance element are connected in series. A second current path is formed. Characterized in that it comprises a memory unit.

  The first switch resistance element and the second switch resistance element are preferably formed of a phase change material that changes from one phase of an amorphous phase and a crystal phase to the other phase in response to a temperature change. . When formed of such a phase change material, the first switch resistance element is subjected to heat generation when energized, and the phase change material undergoes a phase transition from an amorphous phase to a crystalline phase, resulting in a decrease in resistance value. And the second switch resistance element is heated by the first resistance element that generates heat when energized, and the phase change material undergoes a phase transition from an amorphous phase to a crystalline phase, resulting in a decrease in resistance value. It becomes a state.

  The memory element includes a third switch resistor element which is heated by the second resistor element that generates heat when energized and is turned on, and a third resistor element formed of a third resistor. And a third memory unit connected in parallel with the second resistance element to form a current path that passes through the third switch resistance element and the third resistance element in series. it can.

  The memory element further includes third to nth (n is an integer of 4 or more) memory units, and the k + 1th (k is an integer of 3 or more, k <n) memory unit generates heat when energized. A k + 1th switch resistive element that is turned on by heating by the kth resistive element and a (k + 1) th resistive element formed of a (k + 1) th resistive element, and in parallel with the kth resistive element A current path that is connected to pass through the k + 1th switch resistance element and the k + 1th resistance element in series may be formed.

  The memory element according to claim 6 is provided between a pair of electrodes arranged at a predetermined interval and between the pair of electrodes so as to be in contact with each of the pair of electrodes, and an amorphous phase according to a temperature change. And a first phase change layer formed of a first phase change material that changes phase from one phase of the crystal phase to the other, and a first resistance layer laminated on the first phase change layer A first memory layer including a first resistor layer formed on a body, and a first memory layer stacked on the first resistor layer and one of an amorphous phase and a crystalline phase according to a temperature change A second phase change layer formed of a second phase change material that changes phase from one phase to the other phase, and a second layer formed on the second phase change layer and formed by a second resistor. And a second memory portion including the resistor layer.

  The first phase change layer, the first resistor layer, the second phase change layer, and the second resistor layer are stacked in a direction parallel to a surface on which the memory element is placed. The first phase change layer, the first resistor layer, the second phase change layer, and the second resistor layer may be perpendicular to a surface on which the memory element is mounted. It may be laminated in any direction.

  The memory element is formed of a third phase change material that is stacked on the second resistor layer and changes in phase from one of an amorphous phase and a crystalline phase to the other in response to a temperature change. A third memory unit comprising: a third phase change layer; and a third resistor layer stacked on the third phase change layer and formed of a third resistor; and Can be included.

  The memory device further includes third to n-th (n is an integer of 4 or more) memory units, and the k + 1-th (k is an integer of 3 or more, k <n) memory unit is the k-th memory unit. A (k + 1) th phase change layer formed of a (k + 1) th phase change material that is laminated on the resistor layer and changes in phase from one of an amorphous phase and a crystalline phase to the other in response to a temperature change; And (k + 1) th resistor layer formed on the (k + 1) th phase change layer and formed of the (k + 1) th resistor.

  In the memory element, a chalcogenide compound is preferable as the phase change material. Further, it is preferable that the resistance value of the memory element is changed to three or more values. For example, the resistance value of the memory element can be changed by changing the magnitude of the applied voltage or the applied current. In addition, a resistance value of the memory element can be changed by applying a pulse voltage or a pulse current and changing a pulse width of the pulse voltage or the pulse current. Alternatively, the resistance value of the memory element can be changed by applying a pulse voltage or a pulse current and changing the magnitude of the pulse voltage or the pulse current.

  A resistor layer provided between the pair of electrodes and in contact with each of the pair of electrodes and formed of a resistor between the pair of electrodes and the first phase change layer; Can be provided.

The memory element according to claim 16 is formed of a first resistor and a pair of electrodes arranged at a predetermined interval, and provided between the pair of electrodes so as to be in contact with each of the pair of electrodes. And a first phase change that is laminated on the first resistor layer and changes in phase from one of an amorphous phase and a crystalline phase to the other in response to a temperature change. A first memory comprising: a first phase change layer formed of a material; and a second resistor layer stacked on the first phase change layer and formed of a second resistor. And a second phase change material that is laminated on the second resistor layer and changes in phase from one of the amorphous phase and the crystalline phase to the other in response to a temperature change. Formed on the second phase change layer and a third resistor. A second memory portion having a third resistance layer, and characterized in that it comprises a.

  A memory cell according to claim 17 includes the memory element according to any one of claims 1 to 16 and a transistor formed on the same substrate as the memory element. It is said.

  A memory cell array according to claim 18 is characterized in that a plurality of memory cells according to claim 17 are arranged on the same substrate.

  According to the present invention, it is possible to provide a novel phase change nonvolatile memory element, memory cell, and memory cell array capable of reliably performing multi-value recording.

  Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings.

(First embodiment)
<Structure of memory element>
FIG. 1 is a diagram showing a structure of a memory element according to the first embodiment of the present invention. 1A is a plan view of the memory element, and FIG. 1B is a cross-sectional view taken along line AA in FIG. The memory element 10 according to the first embodiment of the present invention includes a flat semiconductor substrate 12 made of silicon (Si) or the like. The semiconductor substrate 12 has a rectangular shape in plan view. The main surface of the semiconductor substrate 12 is covered with an insulating film 14 made of silicon oxide (SiO ₂ ) or zinc sulfide (ZnS). A first electrode 16 and a second electrode 18 made of a thin film such as titanium nitride (TiN), polysilicon (Poly-Si), aluminum (Al), and gold (Au) are formed on the insulating film 14. . The first electrode 16 and the second electrode 18 are arranged at a predetermined interval.

  On the insulating film 14, a memory unit 20 for recording information by phase change is formed. The memory unit 20 has a multilayer structure in which a plurality of thin films are stacked. A first phase change layer 22 made of a first phase change material is disposed in the lowermost layer of the memory unit 20. The first phase change layer 22 is provided between the first electrode 16 and the second electrode 18 so as to contact the insulating film 14 and to contact each of the first electrode 16 and the second electrode 18. Yes.

  On the first phase change layer 22, a first resistor layer 24 formed of a first resistor, a second phase change layer 26 formed of a second phase change material, and a second phase change layer 26 A second resistor layer 28 formed of resistors is laminated in this order. The first phase change layer 22 and the first resistor layer 24 correspond to the “first memory portion” of the present invention, and the second phase change layer 26 and the second resistor layer 28 of the present invention are present. Corresponds to the “second memory section”.

  As the first and second phase change materials, phase change materials that are stabilized in either a crystalline phase or an amorphous phase at room temperature are used. As such a phase change material, chalcogenide-based compounds such as Ge—Sb—Te (GST), Sb—Te, In—Ag—Sb—Te, Se—Sb—Te are suitable. In the chalcogenide-based compound, the specific resistance of the amorphous phase is 2 to 4 orders of magnitude higher than the specific resistance of the crystalline phase. For this reason, the bit error rate decreases during reproduction. The first phase change material and the second phase change material may be the same material or different materials.

For example, Ge ₂ Sb ₂ Te ₅ has a melting point of 630 ° C. and a crystallization temperature of 160 ° C. When this material is heated to 600 ° C. or higher and melted, and then rapidly cooled to room temperature, it is stabilized in an amorphous phase. On the other hand, when this material is heated to 160 ° C. or higher and then gradually cooled to room temperature, it is stabilized in the crystalline phase. Therefore, when the first and second phase change materials are stabilized in an “amorphous phase” having a high specific resistance in an initial state and then heated to 160 ° C. or higher and then cooled, a “crystalline phase having a low specific resistance” The phase transitions to "" and stabilizes.

  As the first and second resistors, it is possible to use a resistor whose specific resistance is lower than the resistance in the amorphous phase of the phase change material disposed in the lower layer and higher than the resistance in the crystal phase. As such a resistor, carbon (C), tungsten (W), molybdenum (Mo), titanium nitride (TiN), tungsten nitride (TiW), or the like is preferable.

  A first resistor layer 24 having a resistance value smaller than that of the first phase change layer 22 is adjacent to the first phase change layer 22 initialized with the amorphous phase. The second phase change layer 26 initialized with an amorphous phase is adjacent to a second resistor layer 28 having a smaller resistance value than that of the second phase change layer 26. Here, the resistance value of the phase change layer or the resistor layer is not the specific resistance of the constituent material but the resistance value when the current passes through each layer. That is, when each layer is an individual resistance element, this is the resistance value of each resistance element. By allowing the resistor layer having a small resistance value to be adjacent to the phase change layer, a current easily flows through the resistor layer. The first resistor and the second resistor may be made of the same material or different materials.

  In the present embodiment, the second memory unit (second phase change layer 26 and second resistor) is formed on the first memory unit (first phase change layer 22 and first resistor layer 24). The example in which the layer 28) is stacked has been described, but the third memory unit, the fourth memory unit,. . . A plurality of memory portions such as an nth memory portion can be provided. By providing n memory units, multi-value recording of (n + 1) values can be realized. Note that a memory element having n memory units will be described later.

Although not shown in the present embodiment, the memory unit 20 may be covered with an insulating film made of SiO ₂ , ZnS, or the like. By covering with an insulating film, when the first and second phase change materials are transferred to the amorphous phase, the liquid phase material liquefied by melting (melting) is prevented from scattering from the exposed surface to the outside. can do.

<Method for Manufacturing Memory Element>
A manufacturing method for manufacturing the memory element 10 shown in FIG. 1 will be described. The manufacturing process of the memory element 10 mainly includes a process of manufacturing an electrode section and a process of manufacturing a memory section in which a phase change layer and a resistor layer are stacked.

  An insulating film 14 is formed on the main surface of the semiconductor substrate 12, and a first electrode 16 and a second electrode 18 are formed on the insulating film 14. First, an electrode material such as TiN or Poly-Si is deposited on the insulating film 14 by sputtering. A predetermined electrode pattern is formed of a photoresist on the electrode material by photolithography. The portions of the electrode material other than the electrode pattern are removed by etching to form the first electrode 16 and the second electrode 18 having a predetermined pattern. Then, the photoresist left on the first electrode 16 and the second electrode 18 is peeled off.

  Next, the memory unit 20 is formed using a lift-off process. First, the insulating film 14 on which the first electrode 16 and the second electrode 18 are formed is covered with a resist film for lift-off process. A portion of the resist film where the memory portion 20 is to be formed is removed, and a resist pattern is formed so that the resist film remains around the resist film. A first phase change material, a first resistor, a second phase change material, and a second resistor are deposited in this order on the resist pattern by sputtering to form a multilayer film.

  After forming the multilayer film, the resist film for lift-off process is removed. The multilayer film deposited on the resist film is also removed together with the resist film. Thus, the first phase change layer 22 formed of the first phase change material, the first resistor layer 24 formed of the first resistor, and the second formed of the second phase change material. The memory section 20 is formed by stacking the phase change layer 26 and the second resistor layer 28 formed of the second resistor in this order. Each of the first phase change material and the second phase change material undergoes a phase transition to an amorphous phase in the same manner as the erasing method described later, and the first phase change layer 22 and the second phase change layer 26 are initialized. Is done.

When the memory unit 20 is covered with an insulating film, an insulating material such as SiO ₂ or ZnS is further deposited on the exposed surfaces (upper surface and side surfaces) of the memory unit 20 by sputtering. When n (n is an integer of 2 or more) memory units are provided, the first phase change material, the first resistor,... K (k <n Integer phase change material, kth resistor,... Nth phase change material, and nth resistor are deposited in ascending order to form a multilayer film. The resistance values of the plurality of resistor layers may be the same, but different values are preferable from the viewpoint of heating action. From the relationship of heating, it is preferable to select the resistor (material) so that the resistance value of the resistor layer becomes smaller as going outward (approaching n).

<Recording and playback methods>
A multi-value recording method in the memory element 10 shown in FIG. 1 will be described with reference to FIG.
The first phase change layer 22 and the second phase change layer 26 of the memory unit 20 can be formed of, for example, Ge—Sb—Te (GST). In addition, the first resistor layer 24 and the second resistor layer 28 of the memory unit 20 can be formed of, for example, titanium nitride (TiN).

When the first phase change layer 22 is an amorphous phase, the resistance value is “r ₁ ^a ”, and when the first phase change layer 22 is a crystalline phase, the resistance value is “r ₁ ^c ”. When the second phase change layer 26 is an amorphous phase, the resistance value is “r ₂ ^a ”, and when the second phase change layer 26 is a crystalline phase, the resistance value is “r ₂ ^c ”. The resistance value of the first resistor layer 24 is “R ₁ ”, and the resistance value of the second resistor layer 28 is “R ₂ ”.

For example, in a chalcogenide compound, the specific resistance of the amorphous phase is 2 to 4 orders of magnitude higher than the specific resistance of the crystalline phase. Therefore, as shown in the following formula (1a), the resistance values r ₁ ^a and r ₂ ^a when the phase change layer is an amorphous phase are compared with the resistance values r ₁ ^c and r ₂ ^c when the phase change layer is a crystal phase. And very big. Further, the resistance values R ₁ and R ₂ of the resistor layer are smaller than the resistance values r ₁ ^a and r ₂ ^a when the phase change layer is an amorphous phase as shown in the following formula (1b). It is preferable that the resistance values r ₁ ^c and r ₂ ^c are larger when the layer is in a crystalline phase.

In the case where the phase change layer is a crystalline phase, the ratio of the current flowing through each current path is determined by the magnitude relationship between the resistance values R ₁ and R ₂ of the resistor layer and the resistance values r ₁ ^c and r ₂ ^c of the phase change layer. Changes. For example, if r ₁ ^c or r ₂ ^c >> R ₁ , the current flowing through the first resistor layer 24 increases. If R ₁ >> R ₂ >> r ₁ ^c or r ₂ ^c , the current flowing through the second resistor layer increases.

Further, if ^{_{R 1 or R 2> r 1}} c orr 2 c, the current flowing in accordance with a ratio of _{R 1} / _{R 2,} and the current flowing through the first resistor layer 24 and the second resistance layer The ratio is determined. The ratio of R ₁ / R ₂ is a fixed ratio, and the value hardly changes even when repeated recording is performed. In addition, the higher the resistance values R ₁ and R ₂ , the better the heat generation efficiency of the resistor layer. For this reason, as shown in the above formula (1b), the resistance values R ₁ and R ₂ of the resistor layer are smaller than the resistance values r ₁ ^a and r ₂ ^a when the phase change layer is an amorphous phase. It is preferable that the resistance values r ₁ ^c and r ₂ ^c are larger when the change layer is a crystalline phase.

2A to 2E are conceptual diagrams showing states (a) to (e) of the memory element 10 when each voltage is applied. FIG. 3 is a diagram showing the relationship between the voltage applied to the memory element 10 during information recording and the detected current. The applied voltage, there are four types of read voltage _{V R,} the first write voltage _{V W1,} a second write voltage _{V W2,} and the erase voltage _{V E.} The voltage value increases in the order of read voltage V _R <first write voltage V _W1 <second write voltage V _W2 <erase voltage V _E.

FIG. 2A shows a state (a) in which the memory element 10 is initialized. In the initialization state (a), both the first phase change layer 22 and the second phase change layer 26 are amorphous phases, and the resistance value thereof is r ₁ ^a . First electrode 16 of the memory device 10 in a state (a) and between the second electrode 18, when the read voltage V _R is applied, current is passed through the first phase change layer 22 made of amorphous phase Then, it flows into the first resistor layer 24 having a smaller resistance value and passes through the first phase change layer 22 again. Since the resistance value of the first phase change layer 22 is an amorphous phase is as large as r ₁ ^a, as can be seen from FIG. 3, even if the read voltage V _R is applied, a small current I ₀ only detected.

FIG. 2B shows a state (b) in which the first write voltage V _W1 is applied to the memory element 10. When the first write voltage _VW1 is applied between the first electrode 16 and the second electrode 18 of the memory element 10, a part of the first phase change layer 22 in the current path generates heat and becomes amorphous. It transitions from the phase to the crystalline phase and stabilizes. The portions of the first phase change layer 22 that have transitioned to the crystal phase are referred to as a crystal phase portion 22C ₁ and a crystal phase portion 22C ₂ . The resistance value when the current passes through these crystal phase portions 22C ₁ and 22C ₂ is r ₁ ^c .

Current passes through the crystal phase portions 22C ₁ of the first phase change layer 22, flows into the first resistive element layer 24, again passes through the crystal phase portion 22C ₂ of the first phase change layer 22. Since the resistance values of the crystal phase portions 22C ₁ and 22C ₂ are as small as r ₁ ^c , as can be seen from FIG. 3, when the first write voltage V _W1 is applied, a current I _W1 higher than the current I ₀ is detected. The

FIG. 2C shows the first recording state (c) of the memory element 10. In the first recording state (c), crystal phase portions 22C ₁ and 22C ₂ having a small resistance value with r ₁ ^c are formed in the first phase change layer 22. On the other hand, the second phase change layer 26 remains in an amorphous phase, and its resistance value is as large as r ₂ ^a .

Between with the first electrode 16 of the memory device 10 (c), the second electrode 18, when the read voltage _{V R} is applied, the current is a crystalline phase portion 22C ₁ of the first phase change layer 22 passes, flows into the first resistive element layer 24, again passes through the crystal phase portion 22C ₂ of the first phase change layer 22. As can be seen from FIG. 3, when the read voltage V _R is applied, a high current I ₁ from the current I ₀ is detected.

FIG. 2D shows a state (d) in which the second write voltage V _W2 is applied to the memory element 10. When the second write voltage _VW2 is applied between the first electrode 16 and the second electrode 18 of the memory element 10, the first resistor layer 24 in the current path generates heat, and the first resistance A portion of second phase change layer 26 adjacent to body layer 24 is heated. As it can be seen from FIG. 3, a second write voltage _{V W2} is higher than the read voltage _{V R.} When the second write voltage V _W2 is applied, a current I _W2 higher than the current I ₁ is detected.

FIG. 2E shows a second recording state (e) of the memory element 10. In the second recording state (e), a part of the second phase change layer 26 is heated and transitions from the amorphous phase to the crystalline phase and stabilizes. Crystal phase portions 26C ₁ and 26C ₂ having a small resistance value with r ₂ ^c are formed in the second phase change layer 26. The resistance value when passing through the crystal phase portions 26C ₁ and 26C ₂ is r ₂ ^c .

Between with the first electrode 16 of the memory device 10 of (e) between the second electrode 18, when the read voltage _{V R} is applied, the current is a crystalline phase portion 22C ₁ of the first phase change layer 22 pass. Some of the current passing through the crystalline phase portion 22C ₁ flows into the first resistive element layer 24, again passes through the crystal phase portion 22C ₂ of the first phase change layer 22.

Other current passing through the crystalline phase portion 22C ₁ passes through the crystal phase portions 26C ₁ of the first resistor layer 24 and the second phase change layer 26, flows into the second resistance layer 28, again crystalline phase portion 26C ₂ of the second phase change layer 26, the first resistor layer 24, passes through the crystal phase portion 22C ₂ of the first phase change layer 22. As can be seen from FIG. 3, when the read voltage V _R is applied, a high current I ₂ from the current I ₁ is detected.

  As described above, the first phase change layer 22, the first resistor layer 24, the second phase change layer 26, and the second resistor layer 28 of the memory unit 20 are in the initialized state (a), In each of the first recording state (c) and the second recording state (e), composite resistors having different resistance values are formed. For example, the initialization state (a) is set to “0”, the first recording state (c) is set to “1”, and the second recording state (e) is set to “2”. Can be recorded (written).

Between the first electrode 16 of the memory element and the second electrode 18, by applying a read voltage V _R for detecting a current flowing in the memory unit 20, to reproduce the recorded multi-valued information (read )be able to. For example, a "0" from the detected current I ₀ at the time of applying a read voltage V _R corresponding to the initial state (a), from the detected current I ₁ corresponding to a first recording condition (c) "1 "the, from the detected current I ₂ can be read respectively" 2 "corresponding to the second recording condition (e),.

In the above, as shown in FIGS. 2D and 2E, the first resistor layer 24 in the current path generates heat, and the second phase change layer adjacent to the first resistor layer 24 is used. The example in which part of the layer 26 is heated and the crystal phase portions 26C ₁ and 26C ₂ are formed has been described. However, as shown in FIG. 6A, the first resistor layer 24 generates heat in the state (d). In this case, the “wider portion” of the first phase change layer 22 and the second phase change layer 26 that is in contact with the first resistor layer 24 transitions from the amorphous phase to the crystalline phase and is stabilized. It is also possible to do.

In this case, as shown in FIG. 6B, in the state (e), the first phase change layer 22 has a crystal phase portion 22C formed in a wide range, and the second phase change layer 26 has crystals. The phase portion 26C is formed in a wide range. The resistance value of the crystal phase portion 22C is r ₁ ^c as in the crystal phase portions 22C ₁ and 22C ₂ . The resistance value of the crystal phase portion 26C is r ₂ ^c like the crystal phase portions 26C ₁ and 26C ₂ .

<Change in resistance during recording>
4A to 4C are diagrams showing the combined resistance in each of the initialization state (a), the first recording state (c), and the second recording state (e) of the memory element. As described above, the resistance value when the first phase change layer 22 is an amorphous phase is “r ₁ ^a ”, and the resistance value when it is a crystal phase is “r ₁ ^c ”. When the second phase change layer 26 is an amorphous phase, the resistance value is “r ₂ ^a ”, and when the second phase change layer 26 is a crystalline phase, the resistance value is “r ₂ ^c ”. The resistance value of the first resistor layer 24 is “R ₁ ”, and the resistance value of the second resistor layer 28 is “R ₂ ”. 4A to 4C, a layer or a portion having a resistance value of R will be described as “resistance R”.

As shown in FIG. 4A, in the initialization state (a), the resistor r ₁ ^a , the resistor R ₁ , and the resistor r ₁ ^a are connected in series. Further, a resistor r ₂ ^a , a resistor R ₂ , and a resistor r ₂ ^a are also connected in series. The resistor r ₂ ^a , the resistor R ₂ , and the resistor r ₂ ^a connected in series are connected in parallel with the resistor R ₁ . Here, since the resistance r ₂ ^a has a very high resistance value compared to the resistance R ₁ , no current flows through the path including the resistance r ₂ ^a . Connected resistors r _{1 a} in ^series, only the current path passing through the resistor R _1, and the resistance r ₁ ^a is formed, a small current I ₀ flows when the read voltage V _R is applied. Therefore, the resistance value Ra of the composite resistor in the initialization state (a) is expressed by the following formula (2).

As shown in FIG. 4B, in the first recording state (c), the resistor r ₁ ^c , the resistor R ₁ , and the resistor r ₁ ^c are connected in series. Further, a resistor r ₂ ^a , a resistor R ₂ , and a resistor r ₂ ^a are also connected in series. The resistor r ₂ ^a , the resistor R ₂ , and the resistor r ₂ ^a connected in series are connected in parallel with the resistor R ₁ . The resistance r ₁ ^c is sufficiently smaller than the resistance r ₁ ^a . Further, since the resistance r ₂ ^a has a very high resistance value as compared with the resistance R ₁ , no current flows through the path including the resistance r ₂ ^a . Connected resistors r _{1 c} in ^series, only the current path passing through the resistor R _1, and the resistance r ₁ ^c is formed, when the read voltage V _R is applied to the current I ₁ flows. Therefore, the resistance value Rc of the composite resistance in the first recording state (c) is expressed by the following formula (3).

As shown in FIG. 4C, in the second recording state (e), the resistor r ₁ ^c , the resistor R ₁ , and the resistor r ₁ ^c are connected in series. In addition, a resistor r ₂ ^c , a resistor R ₂ , and a resistor r ₂ ^c are also connected in series. The resistor r ₂ ^c , the resistor R ₂ , and the resistor r ₂ ^c connected in series are connected in parallel with the resistor R ₁ . Here, since the resistance r ₂ ^c is sufficiently smaller than the resistance r ₂ ^a , ^a current also flows through a path including the resistance r ₂ ^c . That is, the resistance R ₁ connected in parallel with a resistor r _{2 ^c,} the resistance R _2, and a current path passing through the resistor r ₂ ^c is further formed, a current flows I ₂ when the read voltage V _R is applied . Therefore, the resistance value Re of the composite resistance in the second recording state (e) is expressed by the following formula (4).

  As described above, the memory element 10 of the present embodiment functions as a variable resistor whose overall resistance value changes digitally. In this example, the three resistance values Ra, Rc, and Re can be taken. As described above, in the memory element 10 according to the present embodiment, a plurality of memory portions are formed, and different resistance values are obtained depending on whether or not the phase change layer of each memory portion has undergone a phase transition from an amorphous phase to a crystalline layer. Accurately realized, multi-value recording is performed using the difference in resistance value. For this reason, compared with the conventional multi-value recording method which performs multi-value recording according to the volume ratio of each phase, the resistance value does not fluctuate and multi-value recording can be performed reliably. That is, a highly reliable memory element can be provided.

<Conceptual diagram of resistance circuit>
FIG. 5 is a circuit diagram showing a state in which the memory element 10 shown in FIG. 1 is connected to a power source. A switch resistance element SW ₁ and a resistance element R ₁ are connected to the power supply 30 in series. Moreover, a switch element SW ₂ and the resistance element R ₂ are connected in series, a switching element SW ₂ connected in series with the resistance element R ₂ are connected in parallel with the resistor element R _1.

The switching elements SW _1, the resistance elements _{R 01} are connected in parallel. The resistance element R ₀₁ is connected to a terminal provided between the switch element SW ₁ and the resistance element R ₁ and a terminal provided between the power supply 30 and the switch element SW ₁ . Further, the switching element SW _2, the resistance element _{R 02} are connected in parallel. Resistive element R ₀₂ is provided between the terminals provided between one end of the switch element SW ₂ and the resistance element R _2, the terminal to which the other end of the switch element SW ₂ is connected to the resistor element R ₁ Connected to other terminals.

The switch element SW ₁ and the resistance element R ₀₁ are the switch resistance element SWR ₁ having both a switch function and a resistance function. The switch resistance element SWR ₁ corresponds to the first phase change layer 22 of the memory unit 20. The switch element SW ₂ and the resistor _{R 02} is a switch resistance element SWR _2. The switch resistance element SWR ₂ corresponds to the second phase change layer 26 of the memory unit 20.

Further, the resistor element R _{1 corresponds} to the first resistor layer 24, and the resistor element R _{2 corresponds} to the first resistor layer 28. Accordingly, the switch resistance element SWR ₁ and the resistance element R ₁ correspond to the “first memory portion” of the present invention, and the switch resistance element SWR ₂ and the resistance element R ₂ correspond to the “second memory portion” of the present invention. To do.

The resistance value of the resistance element R ₀₁ corresponds to the resistance value “2r ₁ ^a ” when the entire first phase change layer 22 is in an amorphous phase. The resistance value of the switch element SW ₁ is the resistance value “2r ₁ ^c ” when a part of the first phase change layer 22 has transitioned to the crystalline phase. The resistance value of the resistance element R ₀₁ is very large compared to the resistance value “2r ₁ ^c ” of the switch element SW ₁ and the resistance value “R ₁ ” of the resistance element R ₁ .

When both the switch element SW ₁ and the switch element SW ₂ are OFF, a current path is formed through the resistor element R ₀₁ and the resistor element R ₁ connected in series. This corresponds to the initialization state (a) described above. The resistance value at this time is Ra represented by the above formula (2).

The first phase change layer 22 (resistive element R ₀₁ ) generates heat by energization. Due to the heat generation of the first phase change layer 22 itself, a part of the first phase change layer 22 changes from an amorphous phase to a crystalline phase. In step a portion of the first phase change layer 22 has been transferred to the crystalline phase from the amorphous phase, the switch element SW ₁ is turned ON. When the switch element SW ₁ is turned ON, no current flows in the resistor value is large resistive element R _01, a current path passing through the switch element SW ₁ connected in series with the resistance element R ₁ is formed. This corresponds to the first recording state (c). The resistance value at this time is Rc represented by the above formula (3).

Further, the resistance value of the resistance element R ₀₂ corresponds to the resistance value “2r ₂ ^a ” when the entire second phase change layer 26 is an amorphous phase. The resistance value of the switch element SW ₂ is the resistance value “2r ₂ ^c ” when a part of the second phase change layer 26 has transitioned to the crystal phase. The resistance value “2r ₂ ^a ” in the case where the second phase change layer 26 as a whole is an amorphous phase is much larger than the resistance value of the resistance element R ₁ .

The first resistor layer 24 (resistive element R ₁ ) generates heat by energization. The second phase change layer 26 is heated by the first resistor layer 24, and a part of the second phase change layer 26 changes from the amorphous phase to the crystalline phase. At the stage where part of the second phase change layer 26 has been transferred to the crystalline phase from the amorphous phase, the switch element SW ₂ is turned ON. When the switch element SW ₁ and the switch element SW ₂ are both turned ON, a current path passing through the switching element SW ₂ connected in series with the resistance element R ₂ is formed. This corresponds to the second recording state (e). The resistance value at this time is Re represented by the above formula (4).

As described above, in the circuit shown in FIG. 5, the memory element 10 connected to the power supply 30 can be changed by turning on and off the switch resistance element SWR ₁ and the switch resistance element SWR ₂ including the phase change material. Acts as a resistor. Therefore, the memory element 10 shown in FIG. 1 can record multi-value information by utilizing the difference between these resistance values.

<Erase method>
7A to 7C are views for explaining an information erasing method in the memory element 10 shown in FIG. FIG. 7A shows a state (f) in which a voltage equal to or higher than the erase voltage Ve is applied to the memory element. In general, a phase change material such as GST is heated to a melting point (usually around 600 ° C.) or more when phase transitioning to an amorphous phase. For this reason, the erase voltage Ve is applied to heat the phase change material.

  As shown in FIG. 7A, a voltage equal to or higher than the erase voltage Ve between the first electrode 16 and the second electrode 18 of the memory element (see FIG. 2E) in the second recording state (e). Is applied, the amount of current flowing through the current path rapidly increases to Ie or more, and the first resistor layer 24 and the second resistor layer 28 generate heat. As a result, as shown in FIG. 7C, the entire first phase change layer 22 and the second phase change layer 26 are transformed to the amorphous phase, stabilized, and initialized (a) (FIG. Return to 2 (A).

  FIG. 7B shows a state (g) in which a voltage equal to or higher than the erase voltage Ve is applied to the memory element. As shown in FIG. 7B, a voltage equal to or higher than the erasing voltage Ve is also applied to the memory element (see FIG. 6B) in the second recording state (e) in which the crystal phase portion is formed in a wide range. Then, the amount of current flowing through the current path rapidly increases to Ie or more, and the first resistor layer 24 and the second resistor layer 28 generate heat. As a result, as shown in FIG. 7C, the entire first phase change layer 22 and the second phase change layer 26 are transformed to the amorphous phase, stabilized, and initialized (a) (FIG. Return to 2 (A).

(Second Embodiment)
FIG. 8 is a diagram showing the structure of a memory element according to the second embodiment of the present invention. 8A is a plan view of the memory element, and FIG. 8B is a cross-sectional view taken along line BB in FIG. The memory element 40 according to the second embodiment of the present invention includes a stepped semiconductor substrate 42 made of Si or the like. The semiconductor substrate 42 includes a flat main substrate portion 42A and a step portion 42B formed one step higher than the main substrate portion 42A. The side surface of the step portion 42B is orthogonal to the surface of the main substrate portion 42A. Therefore, the shape of the semiconductor substrate 12 is a rectangular shape in plan view, but is L-shaped in cross section.

The main surface of the semiconductor substrate 42 is covered with an insulating film 44 made of SiO ₂ , ZnS or the like. That is, the insulating film 44 covers the surface of the main substrate portion 42A, the upper surface of the stepped portion 42B, and the side surface of the stepped portion 42B existing between the surface of the main substrate portion 42A and the upper surface of the stepped portion 42B. A first electrode 46 and a second electrode 48 made of a thin film such as TiN, Poly-Si, Al, or Au are formed on the insulating film 44. The first electrode 46 is disposed on the surface of the main substrate portion 42A, and the second electrode 48 is disposed on the upper surface of the step portion 42B.

  On the insulating film 44, a memory unit 50 for recording information by phase change is formed. The memory unit 50 has a multilayer structure in which a plurality of thin films are stacked. A first phase change layer 52 made of a first phase change material is disposed in the lowermost layer of the memory unit 50. The first phase change layer 52 is provided between the first electrode 46 and the second electrode 48 so as to contact the insulating film 44 and to contact each of the first electrode 46 and the second electrode 48. Yes. That is, the first phase change layer 52 is in contact with the first electrode 46 on the surface of the main substrate portion 42A, and reaches the second electrode 48 on the upper surface of the step portion 42B through the side surface of the step portion 42B. The first electrode 46 and the second electrode 48 are provided.

  On the first phase change layer 52, a first resistor layer 54 formed of a first resistor, a second phase change layer 56 formed of a second phase change material, and a second phase change layer 56 are formed. A second resistor layer 58 formed of resistors is stacked in this order. The memory element 40 is disposed on a plane parallel to the surface of the main board portion 42A. The side surface of the step portion 42B is orthogonal to the surface of the main substrate portion 42A. Accordingly, when the memory unit 50 is viewed as a whole, the first phase change layer 52, the first resistor layer 54, the second phase change layer 56, and the second resistor layer 58 are formed in the stepped portion 42B. On the side surface, they are stacked in a direction (X direction) parallel to the surface on which the memory element is placed.

  In the first embodiment, each layer of the memory unit is stacked in a direction (longitudinal direction) perpendicular to the surface on which the memory element is placed. If this is a “vertical type”, the second embodiment is a “horizontal type” in which each layer of the memory unit is stacked in a direction (lateral direction) parallel to the surface on which the memory element is placed. . The first phase change layer 52 and the first resistor layer 54 correspond to the “first memory portion” of the present invention, and the second phase change layer 56 and the second resistor layer 58 of the present invention. Corresponds to the “second memory section”.

  As the first and second phase change materials, phase change materials that are stabilized in either a crystalline phase or an amorphous phase at room temperature are used. As such a phase change material, a chalcogenide compound such as Ge—Sb—Te (GST), Sb—Te, In—Ag—Sb—Te is preferable as described above. As the first and second resistors, it is possible to use a resistor whose specific resistance is lower than the resistance in the amorphous phase of the phase change material disposed in the lower layer and higher than the resistance in the crystal phase. As such a resistor, C, W, Mo, TiN, TiW and the like are suitable.

  The memory element 40 according to the second embodiment has the same configuration as the memory element 10 according to the first embodiment, except that the memory unit 50 is a horizontal type. The memory element 40 according to the second embodiment can be manufactured in the same manner as the memory element 10 according to the first embodiment.

  Further, multi-value recording can be performed in the same manner as the memory element 10 according to the first embodiment. For example, each of the first phase change layer 52, the first resistor layer 54, the second phase change layer 56, and the second resistor layer 58 is replaced with the first phase change of the first embodiment. The layer 22, the first resistor layer 24, the second phase change layer 26, and the second resistor layer 28 are formed of the same material.

At this time, when the first phase change layer 52 is an amorphous phase, the resistance value is “r ₁ ^a ”, and when the first phase change layer 52 is a crystalline phase, the resistance value is “r ₁ ^c ”. The resistance value when the second phase change layer 56 is an amorphous phase is “r ₂ ^a ”, and the resistance value when the second phase change layer 56 is a crystal phase is “r ₂ ^c ”. The resistance value of the first resistor layer 54 is “R ₁ ”, and the resistance value of the second resistor layer 58 is “R ₂ ”.

In the state in which the memory element 40 is initialized, both the first phase change layer 52 and the second phase change layer 56 are in an amorphous phase, and the resistance value thereof is r ₁ ^a . First electrode 16 of the memory element 40 in the initial state and between the second electrode 18, when the read voltage V _R is applied, a current is passed through the first phase change layer 52 made of amorphous phase Then, it flows into the first resistor layer 54 having a smaller resistance value and passes through the first phase change layer 52 again. Since the resistance value of the first phase change layer 52 is an amorphous phase is as large as r ₁ ^a, even if a read voltage V _R is applied, a small current I ₀ only detected.

  Similarly to the memory element 10 according to the first embodiment, multi-value recording can be performed by changing from an initialized state to a plurality of recording states by applying a voltage. Therefore, the description is omitted here.

  In the memory element 40 according to the present embodiment, a plurality of memory portions are formed, and different resistance values are accurately realized depending on whether or not the phase change layer of each memory portion has changed from an amorphous phase to a crystalline layer. Multi-value recording is performed using the difference in resistance value. For this reason, compared with the conventional multi-value recording method which performs multi-value recording according to the volume ratio of each phase, the resistance value does not fluctuate and multi-value recording can be performed reliably. That is, a highly reliable memory element can be provided.

  Further, since the memory element 40 has the memory unit 50 as a horizontal type, the area per element is reduced, and the memory element 40 can be mounted at a high density.

(Third embodiment)
In the first embodiment, a memory section in which a first resistor layer, a second phase change layer, and a second resistor layer are stacked in this order is formed on the first phase change layer. As described in the example, as shown in FIG. 5, a pair of electrodes, a plurality of switch resistance elements, and a plurality of resistance elements are formed so as to constitute a “circuit that functions as a variable resistance” when connected to a power source. The memory element of the present invention is not limited to the structure shown in FIG.

  For example, the memory unit can have a multi-layer structure in which n partial memory units each including a resistor layer stacked on a phase change layer are sequentially stacked. FIG. 9 is a cross-sectional view of a memory element according to the third embodiment. The same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

The memory element 10A according to the third embodiment includes a memory unit 20A that records information by phase change. The memory unit 20A includes n partial memory units (first memory unit 20 ₁ to n-th memory unit 20 _n ). One partial memory unit has a two-layer structure in which a resistor layer is stacked on a phase change layer. Similar to the first embodiment, the second memory unit (the second phase change layer 26 and the first phase change layer 26 and the first resistor layer 24) is formed on the first memory unit (the first phase change layer 22 and the first resistor layer 24). A second resistor layer 28) is laminated.

For example, when the memory unit 20A includes three partial memory units (the first memory unit 20 ₁ to the third memory unit 20 ₃ ), the memory unit 20A is provided on the second resistor layer 28 of the second memory unit. The third memory portion (third phase change layer and third resistor layer) is laminated to form a memory portion 20A having a multilayer structure.

  In this case, when the second resistor layer generates heat by energization, the third phase change layer is heated by the second resistor layer, and a part of the third phase change layer is changed from the amorphous phase to the crystalline phase. To metastasize. Due to the phase transition, the resistance value of the third phase change layer decreases, and a current flows across the third phase change layer. As a result, a new current path is formed, and the resistance value of the entire memory unit 20A changes. Therefore, by having three partial memory units, it is possible to realize quaternary multi-value recording.

Further, for example, in the case of including n (n is an integer of 4 or more) partial memory units, the third memory units 20 ₃ to 20 n are provided on the second resistor layer 28 of the second memory unit. memory unit 20 _n are sequentially stacked in ascending order of the memory portion 20A of the multilayer structure is formed. The k-th (k is an integer of 3 or more, k <n) memory section 20 _k has a two-layer structure in which a k-th resistor layer is formed on a k-th phase change layer.

  In this case, when the kth resistor layer generates heat by energization, the (k + 1) th phase change layer is heated by the kth resistor layer, and a part of the (k + 1) th phase change layer is amorphous. Transition from phase to crystalline phase. Due to the phase transition, the resistance value of the (k + 1) th phase change layer decreases, and a current flows across the (k + 1) th phase change layer. As a result, a new current path is formed, and the resistance value of the entire memory unit 20A changes. Therefore, by having n partial memory units, multi-value recording of (n + 1) values can be realized.

  The number n of partial memory units is theoretically unlimited and is not limited to 2-4.

FIG. 10 is a circuit diagram showing a state in which the memory element 10A shown in FIG. 9 is connected to a power source. As shown in FIG. 10, this circuit includes n switch resistance elements SWR _{1 to} SWR _n and n resistance elements R _{1 to} R _n . The k-th switch resistance element SWR _k is composed of a switch element SW _k and a resistance element R _0k . The switch element SW _k and the resistance element R _0k are connected in parallel.

Further, the switch element SW _k and the resistance element R _k are connected in series, and the switch element SW _{k + 1} and the resistance element R _{k + 1} are connected in series. The switch element SW _{k + 1} and the resistance element R _{k + 1} connected in series are connected in parallel with the resistance element R _k . A resistance element R _{0 (k + 1)} is connected in parallel to the switch element SW _{k + 1} . The resistance element R _{0 (k + 1)} is between a terminal provided between one end of the switch element SW _{k + 1} and the resistance element R _{k + 1,} and a terminal connected to the other end of the switch element SW _{k + 1} and the resistance element R _k. And a terminal provided on the

The switch resistance element SWR _k corresponds to the phase change layer of the _k-th memory unit 20 _k , and the resistance element R _k corresponds to the resistor layer of the k-th memory unit 20 _k . When the resistance element R _k generates heat due to energization, a part of the phase change layer of the (k + 1) th memory unit 20 _{k + 1} changes from the amorphous phase to the crystal phase, and the switch element SW _{k + 1} is turned on. As a result, a new current path passing through the switch element SW _{k + 1} and the resistance element R _{k + 1} is formed.

Therefore, as described above, in the circuit shown in FIG. 10, the memory element 10A connected to the power supply functions as a variable resistor by turning on and off the _n switch resistance elements SWR _{1 to} SWR _n . In the memory element 10A shown in FIG. 9, multi-value information can be recorded by utilizing the difference between these resistance values.

  In the memory element 10A according to the present embodiment, a plurality of memory portions are formed, and different resistance values are accurately realized depending on whether or not the phase change layer of each memory portion has changed from an amorphous phase to a crystalline layer. Multi-value recording is performed using the difference in resistance value. For this reason, compared with the conventional multi-value recording method which performs multi-value recording according to the volume ratio of each phase, the resistance value does not fluctuate and multi-value recording can be performed reliably. That is, a highly reliable memory element can be provided.

  In the memory element 10A, since the memory unit 20A is composed of n partial memory units, multi-value recording of (n + 1) values can be realized.

(Fourth embodiment)
FIG. 11A is a cross-sectional view illustrating a structure of a memory cell including the memory element 10 illustrated in FIG. By forming a plurality of such memory cells on the same substrate, a memory cell array can be configured.

A memory cell 60 according to the fourth embodiment includes an n-type silicon semiconductor substrate 62. In the vicinity of the surface of the n-type silicon semiconductor substrate 62, a p ⁺ diffusion region 64 and a p ⁺ diffusion region 66 are provided so as to be separated from each other. The p ⁺ diffusion region 64 and the p ⁺ diffusion region 66 are regions where p ⁺ type impurities are diffused by ion implantation or the like. A region between the p ⁺ diffusion region 64 and the p ⁺ diffusion region 66 is a channel region 68 in which carriers move.

p ⁺ on the diffusion region 64, p ⁺ diffusion region 64 and electrically connected to the source 70 is provided. On p ⁺ diffusion region 66, p ⁺ diffusion region 66 and electrically connected to the drain 72 is provided. A gate 76 is provided on the channel region 68 via a gate insulating film 74. The source 70, the drain 72, and the gate 76 are made of a conductive material such as Poly-Si or Al. The gate insulating film 74 is made of an insulating material such as SiO ₂ .

The p ⁺ diffusion region 64, p ⁺ diffusion region 66, channel region 68, source 70, drain 72, gate insulating film 74, and gate 76 described above constitute a p-channel MOSFET (hereinafter referred to as p-MOS) 80 that is a transistor. It is configured.

  In the memory cell 60, the memory element 10 is formed using an n-type silicon semiconductor substrate 62 as a substrate. That is, the insulating film 14 is formed on a part of the n-type silicon semiconductor substrate 62. A first electrode 16 and a second electrode 18 are formed on the insulating film 14. The first electrode 16 and the second electrode 18 are arranged at a predetermined interval. The first electrode 16 extends to the drain 72 and is electrically connected to the drain 72.

  On the insulating film 14, a memory unit 20 for recording information by phase change is formed. The memory unit 20 has a multilayer structure in which a first resistor layer 24, a second phase change layer 26, and a second resistor layer 28 are stacked in this order on a first phase change layer 22. Have. A first phase change layer 22 is disposed in the lowermost layer of the memory unit 20. The first phase change layer 22 is provided between the first electrode 16 and the second electrode 18 so as to contact the insulating film 14 and to contact each of the first electrode 16 and the second electrode 18. Yes.

The memory element 10 and the p-MOS 80 are covered with an insulating film 78. The insulating film 78 is made of an insulating material such as SiO ₂ . A hole 82 is formed in the insulating film 78 so as to penetrate the insulating film 78 and reach the source 70. The hole 82 is filled with a conductive material such as Al to form a contact portion 84 electrically connected to the source 70. Similarly, a hole 86 that reaches the gate 76 through the insulating film 78 is formed, and the hole 86 is filled with a conductive material to form a contact portion 88. In addition, a hole 90 that reaches the second electrode 18 through the insulating film 78 is formed, and the hole 90 is filled with a conductive material to form a contact portion 92.

  In the p-MOS 80, when a negative gate voltage Vt is applied to the gate 76 via the contact portion 88, a current flows between the source 70 and the drain 72 (ON state). On the other hand, in the state where the gate voltage Vt is not applied, no current flows between the source 70 and the drain 72 (OFF state). Accordingly, when a read voltage, a write voltage, an erase voltage, or the like is applied between the contact portion 84 and the contact portion 92, a current flows through the memory element 10 if the p-MOS 80 is in the ON state. On the other hand, if the p-MOS 80 is in the OFF state, no current flows through the memory element 10.

  FIG. 11B is a circuit diagram in the case where the memory cell 60 is represented by a simple circuit. The memory cell 60 includes a p-MOS 80 and a memory element 10 connected in series. The p-MOS 80 has a source side (S) grounded and a drain side (D) connected to one end of the memory element 10. The other end of the memory element 10 is connected to the power supply voltage terminal 94. A read voltage, a write voltage, an erase voltage, and the like are applied from the power supply voltage terminal 94 to the memory cell 60.

  The p-MOS 80 is a switching transistor. If the gate voltage Vt is applied to the gate (G) of the p-MOS 80 and the p-MOS 80 is in the ON state, a current corresponding to the applied voltage (read voltage, write voltage, etc.) flows through the memory element 10, and the memory element The resistance value of 10 changes. By utilizing this difference in resistance value, multi-value information can be recorded in the memory element 10 and reproduced. On the other hand, if the gate voltage Vt is not applied and the p-MOS 80 is in the OFF state, no current flows through the memory element 10.

  The memory cell 60 according to the present embodiment includes the memory element 10 according to the first embodiment. In the memory element 10, a plurality of memory portions are formed, and different resistance values are accurately realized depending on whether or not the phase change layer of each memory portion has changed from an amorphous phase to a crystalline layer. Multi-value recording is performed using. For this reason, compared with the conventional multi-value recording method which performs multi-value recording according to the volume ratio of each phase, the resistance value does not fluctuate and multi-value recording can be performed reliably. That is, a highly reliable memory cell can be provided.

  In addition, since the memory cell 60 includes the p-MOS 80 that is a transistor, the memory element 10 can be switched by on / off control of the p-MOS 80.

(Fifth embodiment)
FIG. 12 is a diagram showing a structure of a memory element according to the fifth embodiment of the present invention. FIG. 12 is a cross-sectional view of a memory element according to the fifth embodiment. In the memory element 10B, a heater resistor layer 96 formed of a resistor is disposed in the lowermost layer of the memory unit 20B, and the first phase change layer 22 is stacked on the resistor layer 96. The structure is the same as that of the memory element according to the first embodiment (see FIG. 1). For this reason, the same code | symbol is attached | subjected to the same component and description is abbreviate | omitted.

  As the resistor constituting the resistor layer 96, a resistor whose specific resistance is lower than the resistance in the amorphous phase of the phase change material disposed in the lower layer and higher than the resistance in the crystal phase can be used. As the resistor, C, W, Mo, TiN, TiW and the like are suitable.

  In the memory device 10 according to the first exemplary embodiment, in the initialized state, the first phase change layer 22 and the second phase change layer 26 are both in an amorphous phase and have a large resistance value. When recording is performed from the initialized state, when a predetermined voltage is applied between the first electrode 16 and the second electrode 18 of the memory element 10, one of the first phase change layers 22 in the current path is recorded. The part generates heat and transitions from the amorphous phase to the crystalline phase and stabilizes.

Current passes through the crystal phase portions 22C ₁ of the first phase change layer 22, flows into the first resistive element layer 24, again passes through the crystal phase portion 22C ₂ of the first phase change layer 22. Since the resistance values of the crystal phase portions 22C ₁ and 22C ₂ are as small as r ₁ ^c , an excessive current may flow through the memory element 10 when a voltage having the same magnitude as the predetermined voltage is applied. The same possibility exists when the second phase change layer 26 transitions from an amorphous phase to a crystalline phase.

  On the other hand, in the memory element 10B according to the fifth embodiment, in the initialization state, the first phase change layer 22 and the second phase change layer 26 are both amorphous phases, and the resistance value is large. . When recording is performed from the initialized state, since the resistance value of the first phase change layer 22 is large, when a predetermined voltage is applied between the first electrode 16 and the second electrode 18 of the memory element 10B. The current does not flow into the first phase change layer 22 but flows into the resistor layer 96. As a result, a part of the resistor layer 96 between the first electrode 16 and the second electrode 18 generates heat locally.

  The first phase change layer 22 laminated on the resistor layer 96 is indirectly heated by the heated resistor layer 96. As a result, a part of the first phase change layer 22 transitions from the amorphous phase to the crystalline phase and is stabilized. The first phase change layer 22 undergoes phase transition when a relatively low voltage is applied. Thus, in the memory element 10B according to the fifth embodiment, the applied voltage when the first phase change layer 22 is transitioned from the amorphous phase to the crystalline phase can be kept low.

  In the memory element 10B according to the present embodiment, as in the first embodiment, a plurality of memory portions are formed, and whether the phase change layer of each memory portion has undergone a phase transition from an amorphous phase to a crystalline layer. Different resistance values are accurately realized depending on whether or not, and multi-value recording is performed by utilizing the difference in resistance values. For this reason, compared with the conventional multi-value recording method which performs multi-value recording according to the volume ratio of each phase, the resistance value does not fluctuate and multi-value recording can be performed reliably. That is, a highly reliable memory element can be provided.

(Modification)
In the above embodiment, the example in which the applied voltage is changed to change the resistance value of the memory element has been described. However, it is sufficient that the thermal energy (power amount) applied to the phase change material can be changed. It is also possible to change the resistance value of the memory element by changing the size of. In addition to applying a pulse voltage or pulse current, the resistance value of the memory element can be changed by changing the “pulse width” or “magnitude” of the pulse voltage or pulse current. Both “pulse width” and “size” may be varied.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the structure of the memory element based on the 1st Embodiment of this invention, (A) is a top view of a memory element, (B) is the sectional view on the AA line of (A). FIG. 2 is a diagram for explaining a multi-value recording method in the memory element shown in FIG. 1, and (A) to (E) are partial cross-sectional views showing states (a) to (e) of the memory element when a voltage is applied. is there. It is a diagram which shows the relationship between the voltage applied to the memory element at the time of information recording, and a detection current. (A)-(C) are figures which show three types of compound resistance of a memory element. FIG. 2 is a circuit diagram illustrating a state in which the memory element illustrated in FIG. 1 is connected to a power source. (A) And (B) is a fragmentary sectional view which shows the other state which may arise with a multi-value recording method. (A)-(C) are the figures for demonstrating the information erasing method in the memory element shown in FIG. It is a figure which shows the structure of the memory element based on the 2nd Embodiment of this invention, (A) is a top view of a memory element, (B) is the BB sectional drawing of (A). It is sectional drawing of the memory element which concerns on 3rd Embodiment. FIG. 10 is a circuit diagram when the memory element shown in FIG. 9 is represented by a circuit. 2A is a partial cross-sectional view showing a structure of a memory cell including the memory element shown in FIG. 1, and FIG. 2B is a circuit diagram when the memory cell of FIG. 1A is represented by a circuit. It is sectional drawing which shows the structure of the memory element based on the 5th Embodiment of this invention.

Explanation of symbols

10 memory element 10A memory element 12 semiconductor substrate 14 insulating film 16 first electrode 18 second electrode 20 memory part 20A memory part 20 _k memory part 22 first phase change layer 22C ₁ crystal phase part 22C ₂ crystal phase part 24 first Resistor layer 26 second phase change layer 26C ₁ crystal phase portion 26C ₂ crystal phase portion 28 second resistor layer 30 power supply 40 memory element 42 semiconductor substrate 42A main substrate portion 42B stepped portion 44 insulating film 46 first electrode 48 Second electrode 50 Memory portion 52 First phase change layer 54 First resistor layer 56 Second phase change layer 58 Second resistor layer 60 Memory cell 62 Silicon semiconductor substrate 64 Diffusion region 66 Diffusion region 68 Channel Region 70 Source 72 Drain 74 Gate insulating film 76 Gate 78 Insulating film 82 Hole 84 Contact portion 86 Hole 88 Contact portion 90 Ho 92 contact portion 94 supply voltage terminal 96 resistor layer
R ₀ resistance element R ₁ resistance element R ₂ resistance element R _k resistance element SW ₁ switch element SW ₂ switch element SW _k switch element SWR ₁ switch resistance element SWR ₂ switch resistance element SWR _k switch resistance element

Claims (18)

A pair of electrodes arranged at a predetermined interval;
A first switch resistance element that is turned on by heat generation during energization and a first resistance element formed of a first resistor, one end of which is connected to one of the pair of electrodes A first memory section having the other end connected to the other of the pair of electrodes and forming a current path passing through the first switch resistance element and the first resistance element in series;
A second switch resistor element that is heated by the first resistor element that generates heat when energized and is turned on; and a second resistor element formed of a second resistor; A second memory unit connected in parallel with a resistance element to form a current path passing in series through the second switch resistance element and the second resistance element;
A memory device comprising:   The first switch resistance element and the second switch resistance element are formed of a phase change material that changes from one phase of an amorphous phase and a crystalline phase to the other phase in response to a temperature change. The memory element according to claim 1. The first switch resistance element is turned on due to heat generation during energization, the phase change material undergoes a phase transition from an amorphous phase to a crystalline phase, and the resistance value is lowered.
The second switch resistance element is heated by the first resistance element that generates heat during energization, and the phase change material undergoes a phase transition from an amorphous phase to a crystalline phase, resulting in a decrease in resistance value and an ON state. The memory element according to claim 2.   A third switch resistor element that is heated by the second resistor element that generates heat when energized and is turned on; and a third resistor element formed of a third resistor; The third memory unit further includes a third memory unit connected in parallel with the resistor element and formed with a current path that passes through the third switch resistor element and the third resistor element in series. The memory element according to any one of? Further includes third to nth (n is an integer of 4 or more) memory units;
The k + 1th (k is an integer of 3 or more, k <n) memory portion is formed of a (k + 1) th switch resistance element that is turned on by heating by the kth resistance element that generates heat during energization, and a (k + 1) th resistance body. A current path that is connected in parallel to the kth resistance element and passes through the k + 1th switch resistance element and the k + 1th resistance element in series is formed. The memory device according to claim 1, wherein the memory device is a memory device. A pair of electrodes arranged at a predetermined interval;
A first phase change material that is provided between the pair of electrodes so as to be in contact with each of the pair of electrodes and changes in phase from one phase of an amorphous phase and a crystalline phase to the other in response to a temperature change. A first memory unit comprising: a first phase change layer formed; and a first resistor layer formed on the first phase change layer and formed of a first resistor;
A second phase change formed of a second phase change material that is laminated on the first resistor layer and changes in phase from one of an amorphous phase and a crystalline phase to the other in response to a temperature change. A second memory unit comprising: a layer; and a second resistor layer formed on the second phase change layer and formed of a second resistor;
A memory device comprising:   The first phase change layer, the first resistor layer, the second phase change layer, and the second resistor layer are stacked in a direction parallel to a surface on which the memory element is placed. The memory device according to claim 6, wherein the memory device is a memory device.   The first phase change layer, the first resistor layer, the second phase change layer, and the second resistor layer are stacked in a direction perpendicular to a surface on which the memory element is placed. The memory device according to claim 6, wherein the memory device is a memory device.   A third phase change formed of a third phase change material that is laminated on the second resistor layer and changes in phase from one of an amorphous phase and a crystalline phase to the other in response to a temperature change And a third memory unit including a layer and a third resistor layer formed on the third phase change layer and formed of a third resistor. The memory element according to claim 6. Further includes third to nth (n is an integer of 4 or more) memory units;
The k + 1th (k is an integer of 3 or more, k <n) memory section is stacked on the kth resistor layer and changes from one phase of the amorphous phase and the crystalline phase to the other phase in accordance with the temperature change. A (k + 1) th phase change layer formed of the (k + 1) th phase change material and a (k + 1) th resistor layer stacked on the (k + 1) th phase change layer and formed of the (k + 1) th resistor. The memory element according to claim 6, further comprising:   The memory element according to claim 2, wherein the phase change material is a chalcogenide compound.   The memory element according to claim 1, wherein a resistance value of the memory element changes to three or more.   The memory device according to claim 12, wherein the resistance value of the memory device is changed by changing a magnitude of an applied voltage or an applied current.   14. The memory element according to claim 12, wherein a resistance value of the memory element is changed by applying a pulse voltage or a pulse current and changing a pulse width of the pulse voltage or the pulse current.   15. The resistance value of the memory element is changed by applying a pulse voltage or a pulse current and changing a magnitude of the pulse voltage or the pulse current. Memory element. A pair of electrodes arranged at a predetermined interval;
A first resistor layer formed between the pair of electrodes so as to be in contact with each of the pair of electrodes and formed of a first resistor, and laminated on the first resistor layer A first phase change layer formed of a first phase change material that changes from one phase of an amorphous phase and a crystalline phase to the other phase in response to a temperature change, and laminated on the first phase change layer And a second resistor layer formed of the second resistor, and a first memory unit,
A second phase change formed of a second phase change material that is laminated on the second resistor layer and changes in phase from one of an amorphous phase and a crystalline phase to the other in response to a temperature change. A second memory unit comprising: a layer; and a third resistor layer formed on the second phase change layer and formed of a third resistor;
A memory device comprising:   A memory cell comprising the memory element according to claim 1 and a transistor formed over the same substrate as the memory element.   A memory cell array in which a plurality of memory cells according to claim 17 are arranged on the same substrate.

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