JP5194693B2 - Semiconductor element module and power conversion device - Google Patents

Semiconductor element module and power conversion device Download PDF

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JP5194693B2
JP5194693B2 JP2007263073A JP2007263073A JP5194693B2 JP 5194693 B2 JP5194693 B2 JP 5194693B2 JP 2007263073 A JP2007263073 A JP 2007263073A JP 2007263073 A JP2007263073 A JP 2007263073A JP 5194693 B2 JP5194693 B2 JP 5194693B2
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壮章 田畑
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この発明は、電圧駆動型半導体素子モジュールと、これを用いた電力変換装置に関する。   The present invention relates to a voltage-driven semiconductor element module and a power conversion device using the same.

図8(a)に、電力変換装置として一般的な3相インバータの例を示す。
ここでは、半導体素子で構成された電力変換装置Convの出力端U,V,Wに、3相コイルとして図示される負荷Mが接続されている。この回路では、半導体素子Qu,Qv,Qw,Qx,Qy,Qzを任意にオン・オフさせることで、直流電源Vdから3相交流電力を得ることができ、負荷Mに任意の交流電力を供給することができる。
FIG. 8A shows an example of a general three-phase inverter as a power conversion device.
Here, a load M illustrated as a three-phase coil is connected to output terminals U, V, and W of a power conversion device Conv formed of semiconductor elements. In this circuit, the semiconductor elements Qu, Qv, Qw, Qx, Qy, and Qz can be arbitrarily turned on and off to obtain three-phase AC power from the DC power supply Vd and supply arbitrary AC power to the load M. can do.

例えば、負荷Mを電動機として、図8(b)のような3相交流電流iu,iv,iwを流すことで、電動機を駆動することができる。図8(c)に、図8(a)の一相分を示す。この一相分に図8(b)のような電流iuが流れた場合、各半導体素子IGBT(絶縁ゲート型バイポーラトランジスタ),FWD(帰還ダイオード)にはそれぞれ図8(d)に示すような、バランスした電流が流れる。なお、図8(a)の場合、直流電源Vdは、3相インバータの直流中間コンデンサCdと直結している。この場合、直流電源Vdの変動により、3相インバータの出力が変動してしまうため、直流電圧変動分を補償した3相インバータの出力制御が必要となる。   For example, using the load M as an electric motor, the electric motor can be driven by flowing a three-phase alternating current iu, iv, iw as shown in FIG. FIG. 8C shows one phase portion of FIG. When a current iu as shown in FIG. 8B flows in this one phase, each semiconductor element IGBT (insulated gate bipolar transistor) and FWD (feedback diode) are respectively shown in FIG. Balanced current flows. In the case of FIG. 8A, the DC power supply Vd is directly connected to the DC intermediate capacitor Cd of the three-phase inverter. In this case, since the output of the three-phase inverter fluctuates due to fluctuations in the DC power supply Vd, output control of the three-phase inverter that compensates for the DC voltage fluctuation is required.

図9に、図8(a)の3相インバータに、一般的な昇圧チョッパ回路Chopを付加した例を示す。これは、直流電源Vdと3相インバータの直流中間コンデンサCdとの間に、図9に示すように半導体素子Qp,QnとリアクトルLcを設け、半導体素子Qp,Qnを交互にオン・オフすることで、直流中間コンデンサCdの電圧Edを直流電源Vdの電圧よりも高く調整できるようにしたものである。例えば直流電源Vdにバッテリを想定した場合、バッテリ電圧の垂下に対しても、昇圧チョッパ回路Chopで3相インバータの直流中間電圧Edを一定にして、3相インバータの出力を安定させることができる。   FIG. 9 shows an example in which a general boost chopper circuit Chop is added to the three-phase inverter of FIG. As shown in FIG. 9, semiconductor elements Qp and Qn and a reactor Lc are provided between the DC power supply Vd and the DC intermediate capacitor Cd of the three-phase inverter, and the semiconductor elements Qp and Qn are alternately turned on and off. Thus, the voltage Ed of the DC intermediate capacitor Cd can be adjusted higher than the voltage of the DC power supply Vd. For example, when a battery is assumed as the DC power supply Vd, the output of the three-phase inverter can be stabilized by making the DC intermediate voltage Ed of the three-phase inverter constant by the boost chopper circuit Chop even when the battery voltage drops.

図10(a)は、負荷Mの中性点と3相インバータConvの直流中間コンデンサCdの一端との間に、直流電源Vdを接続した例であり、例えば特許文献1,2に開示されているものである。
これは、図9のような昇圧チョッパ回路Chopを用いずに、負荷Mのインダクタンスと3相インバータの半導体素子Qu〜Qzを利用して任意にオン・オフすることにより、3相インバータの直流中間コンデンサ電圧Edを、直流電源Vdよりも高い値に設定できるようにしたものである。
FIG. 10A shows an example in which a DC power source Vd is connected between the neutral point of the load M and one end of the DC intermediate capacitor Cd of the three-phase inverter Conv. It is what.
This is because the step-up chopper circuit Chop as shown in FIG. 9 is not used but the on / off of the load M and the semiconductor elements Qu to Qz of the three-phase inverter are arbitrarily turned on and off, so The capacitor voltage Ed can be set to a value higher than the DC power supply Vd.

また、3相交流電流を流し、負荷Mに同時に供給することで、例えば負荷Mを電動機とした場合、直流電源Vdを昇圧して直流中間コンデンサ電圧Edに供給すると同時に、電動機Mを駆動することができる。特に、図9に示した昇圧チョッパ回路Chopを不要にできるため、部品点数の削減、コストダウンに寄与することができる。   In addition, when a three-phase AC current is supplied and supplied to the load M at the same time, for example, when the load M is an electric motor, the DC power source Vd is boosted and supplied to the DC intermediate capacitor voltage Ed and at the same time, the electric motor M is driven. Can do. In particular, since the step-up chopper circuit Chop shown in FIG. 9 can be made unnecessary, it is possible to contribute to reduction of the number of parts and cost reduction.

特許第3219039号明細書Japanese Patent No. 3219039 特許第3223842号明細書Japanese Patent No. 3223842

図10(b)に、図10(a)の回路を用いたときの3相電流波形例を示す。
3相交流電流iu,iv,iwは、負荷Mに供給するための電力相当の電流を直流電源Vdから供給する。ここで、直流電源Vdから出力される電流をidとすると、負荷Mの各相コイルに分配される。一方、負荷Mには3相電流を流して電力を供給するため、図10(b)のように、3相交流電流波形にid /3の直流電流が重畳する。
FIG. 10B shows an example of a three-phase current waveform when the circuit of FIG. 10A is used.
The three-phase AC currents iu, iv, iw are supplied from the DC power source Vd with a current corresponding to the power supplied to the load M. Here, if the current output from the DC power supply Vd is id, it is distributed to each phase coil of the load M. On the other hand, in order to supply power by supplying a three-phase current to the load M, a DC current of id / 3 is superimposed on the three-phase AC current waveform as shown in FIG.

図10(c)に、図10(a)の1相分を示す。図10(b)のような電流が流れると、各IGBT(絶縁ゲート型バイポーラトランジスタ),FWD(帰還ダイオード)には図10(d)のように電流が流れ、図8(d)の一般的な3相インバータと異なり、各半導体素子に流れる電流が異なり、特定の半導体素子の電流責務が厳しくなる。例えば図10(d)の例では、U−FWD,X−IGBTに電流が多く流れ、熱責務が厳しくなり、素子を破壊するおそれがある。   FIG. 10C shows one phase of FIG. When a current as shown in FIG. 10 (b) flows, a current flows through each IGBT (insulated gate bipolar transistor) and FWD (feedback diode) as shown in FIG. 10 (d). Unlike a three-phase inverter, the current flowing through each semiconductor element is different, and the current duty of a specific semiconductor element becomes severe. For example, in the example of FIG. 10 (d), a large amount of current flows through U-FWD and X-IGBT, the heat duty becomes severe, and the device may be destroyed.

したがって、この発明の課題は、運転状況に応じて変化する半導体素子の電流により発生する熱責務を軽減することにある。   Therefore, an object of the present invention is to reduce the thermal duty generated by the current of the semiconductor element that changes according to the operating condition.

このような課題を解決するため、請求項1の発明では、半導体素子からなる電力変換装置の出力端に負荷を接続し、この負荷の中性点と前記電力変換装置の正極または負極間に電源を接続した電力変換システムにおいて、
前記電力変換装置を構成する半導体素子のうち、熱責務の大きい素子が冷却風の風上側となるように、前記冷却風の向きを、運転状況に応じて変えることを特徴とする。
In order to solve such a problem, in the invention of claim 1, a load is connected to the output terminal of the power conversion device made of a semiconductor element, and a power source is connected between the neutral point of the load and the positive electrode or the negative electrode of the power conversion device. In the power conversion system connected to
The direction of the cooling air is changed according to the operating condition so that an element having a large heat duty among the semiconductor elements constituting the power conversion device is located on the upstream side of the cooling air .

請求項の発明では、前記請求項の半導体素子モジュールを用いて電力変換装置を構成することができる。 According to the second aspect of the present invention, a power conversion device can be configured using the semiconductor element module of the first aspect .

この発明によれば、装置の運転状況に応じて冷却方向を変えることにより、効率の良い冷却ができ、半導体素子の熱責務を軽減することが可能となる利点がもたらされる。   According to the present invention, by changing the cooling direction in accordance with the operating state of the apparatus, it is possible to perform efficient cooling and to bring about an advantage that the thermal duty of the semiconductor element can be reduced.

図1はこの発明の実施の形態を説明する説明図である。
図1(a)は、図10(a)のような電力変換システムにおける、電力変換装置の1相分の回路を示し、図1(b)は図1(a)に対応する半導体モジュール構成例を示す。これらの図からも明らかなように、UアームFWDのDuとXアームIGBTのQxは冷却風の風上に配置され、UアームIGBTのQuとXアームFWDのDxは冷却風の風下に配置されている。
FIG. 1 is an explanatory view for explaining an embodiment of the present invention.
FIG. 1A shows a circuit for one phase of a power conversion device in the power conversion system as shown in FIG. 10A, and FIG. 1B shows a semiconductor module configuration example corresponding to FIG. Indicates. As is clear from these figures, the U-arm FWD Du and the X-arm IGBT Qx are located on the cooling wind, and the U-arm IGBT Qu and the X-arm FWD Dx are located on the cooling air lee. ing.

各半導体素子は図1(b)のように、銅パターンP,N,ACとボンディングワイヤで接続され、図1(a)に示す1相分を構成している。これらは絶縁基板IsBの上に配置され、モジュールとしてパッケージングされる。モジュールは冷却体などに設置され、これに風を当てることで、半導体素子を冷却する。   As shown in FIG. 1B, each semiconductor element is connected to the copper patterns P, N, and AC by bonding wires to constitute one phase shown in FIG. These are arranged on the insulating substrate IsB and packaged as a module. The module is installed in a cooling body or the like, and the semiconductor element is cooled by applying air to the module.

図2にIGBTチップの例を示す。IGBTチップはその製造方法から、表面がエミッタ電極Eとなりボンディングワイヤで接続され、裏面がコレクタ電極Cとなり銅パターンに接続される。
また、図3にFWDチップの例を示す。IGBTチップと同様、表面がアノード電極Aとなりボンディングワイヤで接続され、裏面がカソード電極Kとなり銅パターンに接続される。
FIG. 2 shows an example of an IGBT chip. From the manufacturing method of the IGBT chip, the front surface becomes an emitter electrode E and is connected by a bonding wire, and the back surface becomes a collector electrode C and is connected to a copper pattern.
FIG. 3 shows an example of the FWD chip. Similar to the IGBT chip, the front surface becomes an anode electrode A and is connected by a bonding wire, and the back surface becomes a cathode electrode K and is connected to a copper pattern.

図10(a)のような回路では、図4(b)に示すように、UアームFWDとXアームIGBTに電流が多く流れるが、これらを図1(b)のように、冷却風の風上に配置することにより、冷却が強化される。一方、UアームIGBTとXアームFWDは電流が小さく温度上昇も小さいため、UアームFWDとXアームIGBTの温度上昇による冷却風の上昇に対しても、問題なく冷却可能である。   In the circuit as shown in FIG. 10 (a), a large amount of current flows through the U arm FWD and the X arm IGBT as shown in FIG. 4 (b). By placing it above, cooling is enhanced. On the other hand, since the U-arm IGBT and the X-arm FWD have a small current and a small temperature rise, the U-arm IGBT and the X-arm IGBT can be cooled without problems even when the cooling air rises due to the temperature rise of the U-arm FWD and the X-arm IGBT.

図5に、この発明の第1の変形例を示す。これは、各半導体素子IGBTとFWDとを2つずつ2並列接続した点が特徴で、この場合も、電流が多く流れるUアームFWDの2つのDuとXアームIGBTの2つのQxを冷却風の風上に配置するようにしている。その他は図1と同様なので、詳細は省略する。
図6に、この発明の第2の変形例を示す。これは、半導体素子の並列数をn(≧3)にする以外は図1,5の場合と同じである。なお、図6のi,jの値は熱設計に応じて任意に選ばれる。
FIG. 5 shows a first modification of the present invention. This is characterized by the fact that each semiconductor element IGBT and FWD are connected in parallel two by two. In this case, too, two Dus of the U-arm FWD through which a large amount of current flows and two Qx of the X-arm IGBT are cooled. It is arranged upwind. Others are the same as in FIG.
FIG. 6 shows a second modification of the present invention. This is the same as the case of FIGS. 1 and 5 except that the number of parallel semiconductor elements is n (≧ 3). The values of i and j in FIG. 6 are arbitrarily selected according to the thermal design.

図7はこの発明の別の実施の形態を説明する説明図である。
ここでは、図7(b)のように、UアームIGBT のQuとXアームFWDのDxの電流責務が厳しくなっているので、図7(c)のように冷却方向を図1(b)とは逆向きに変更することで、UアームIGBT のQuとXアームFWDのDxに対する冷却を強化させるようにしたものである。なお、UアームFWDとXアームIGBTは電流が小さいため、UアームIGBT のQuとXアームFWDのDxの温度上昇による冷却風の上昇に対しても問題なく冷却可能である。
FIG. 7 is an explanatory diagram for explaining another embodiment of the present invention.
Here, as shown in FIG. 7 (b), the current duty of the U arm IGBT Qu and the X arm FWD Dx is strict, so the cooling direction as shown in FIG. Is changed in the opposite direction to enhance the cooling of U-arm IGBT Qu and X-arm FWD Dx. Since the U arm FWD and the X arm IGBT have a small current, the U arm FWD and the X arm FWD can be cooled without any problem even if the cooling air rises due to the temperature rise of the Qu of the U arm IGBT and the Dx of the X arm FWD.

上記では半導体スイッチング素子として、専らIGBT素子を用いる場合について説明したが、MOSFET(金属酸化膜電界効果トランジスタ)なども同様に使用することができるのは勿論である。   In the above description, the case where an IGBT element is exclusively used as the semiconductor switching element has been described, but it is needless to say that a MOSFET (metal oxide field effect transistor) or the like can be used as well.

この発明の実施の形態を示す構成図Configuration diagram showing an embodiment of the present invention 図1で用いられるIGBT素子の概略図Schematic diagram of the IGBT element used in FIG. 図1で用いられるFWD素子の概略図Schematic diagram of the FWD element used in FIG. 図10(a)の1相分の回路図とその各素子に流れる電流波形図A circuit diagram for one phase of FIG. 10A and a current waveform diagram flowing through each element. 図1の第1変形例を示す構成図The block diagram which shows the 1st modification of FIG. 図1の第2変形例を示す構成図The block diagram which shows the 2nd modification of FIG. この発明の別の実施の形態を示す構成図The block diagram which shows another embodiment of this invention 3相インバータ回路と動作説明図Three-phase inverter circuit and operation explanatory diagram 図8に昇圧チョッパを付加した3相インバータ回路構成図Fig. 8 3-phase inverter circuit configuration with boost chopper added モータ中性点を利用する3相インバータの回路構成図Circuit diagram of a three-phase inverter that uses the motor neutral point

Qu,Qx…IGBT素子、Du,Dx…FWD素子、P,N,AC…銅パターン、IsB…絶縁基板、A,C,E,K…電極、Vd…直流電源、Ed…コンデンサ電圧。

Qu, Qx ... IGBT element, Du, Dx ... FWD element, P, N, AC ... Copper pattern, IsB ... Insulating substrate, A, C, E, K ... Electrode, Vd ... DC power supply, Ed ... Capacitor voltage.

Claims (2)

半導体素子からなる電力変換装置の出力端に負荷を接続し、この負荷の中性点と前記電力変換装置の正極または負極間に電源を接続した電力変換システムにおいて、
前記電力変換装置を構成する半導体素子のうち、熱責務の大きい素子が冷却風の風上側となるように、前記冷却風の向きを、運転状況に応じて変えることを特徴とする半導体素子モジュール。
In a power conversion system in which a load is connected to an output end of a power conversion device made of a semiconductor element, and a power source is connected between a neutral point of the load and a positive electrode or a negative electrode of the power conversion device,
A semiconductor element module , wherein the direction of the cooling air is changed according to the operating condition so that an element having a large heat duty among the semiconductor elements constituting the power conversion device is located on the upstream side of the cooling air .
請求項1に記載の半導体素子モジュールを備えたことを特徴とする電力変換装置。 A power conversion device comprising the semiconductor element module according to claim 1 .
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