JP5192467B2 - Ring oscillator circuit - Google Patents

Description

  The present invention relates to a ring oscillator circuit and a method for designing a ring oscillator circuit.

  Semiconductor devices are becoming finer. Along with miniaturization, semiconductor devices are required to operate at a low voltage and to operate at high speed. However, with miniaturization, operating voltage margins, transistor characteristic variations, and power consumption are becoming problems. In general, when the operating voltage of a transistor included in a semiconductor device is lowered, power consumption is reduced. However, the voltage margin is reduced, and the influence of characteristic variations (power supply voltage variations, manufacturing variations, etc.) increases. Therefore, it is desired to achieve both reduction of power consumption and suppression of the influence of characteristic variation. The semiconductor device may be provided with an oscillation circuit for generating an internal control signal. The oscillation circuit always operates. Therefore, the oscillation circuit is particularly required to reduce power consumption and the influence of characteristic variation.

  A ring oscillator circuit may be used as the oscillation circuit. FIG. 1 is a diagram illustrating an example of a ring oscillator circuit. A ring oscillator circuit 100 shown in FIG. 1 includes a plurality of inverting circuits 101 (inverter circuits). The number of inverting circuits is an odd number. The plurality of inverting circuits are arranged in series between the input terminal IN and the output terminal OUT. The output terminal of the last stage inverting circuit is connected to the input terminal of the first stage inverting circuit. In this ring oscillator circuit, a plurality of inverting circuits operate with the same power supply voltage. In such a ring oscillator circuit, the oscillation frequency depends on the power supply voltages of a plurality of inverting circuits. When the power supply voltage fluctuates, the oscillation frequency may fluctuate.

  As a related technique, there is a voltage controlled oscillation circuit described in Patent Document 1 (Japanese Patent Laid-Open No. 2008-98728). This voltage controlled oscillation circuit includes a ring oscillator having n number of inverting circuits, and (n−k) (k is a natural number smaller than n, which is 1 or more) out of n number of inverting circuits included in the ring oscillator. A first power supply circuit that applies a power supply voltage to the inverting circuit and a power supply voltage to k number of inverting circuits that the first power supply circuit of the n inverting circuits of the ring oscillator circuit does not apply the power supply voltage to. And a second power supply circuit to be applied. According to the present invention, even when the power supply voltage of one power supply circuit fluctuates, the fluctuation of the output clock can be suppressed by preventing the power supply voltage of the other power supply circuit from fluctuating.

JP 2008-98728 A

  However, when a plurality of types of power supply voltages are used in the ring oscillator circuit, there is a problem that the duty ratio in the output signal output from the ring oscillator circuit may deviate from a desired value.

  The ring oscillator circuit according to the present invention includes a plurality of first inversion circuits each operating with a first voltage, and a plurality of second inversion circuits each operating with a second voltage different from the first voltage. It has. The plurality of first inversion circuits and the plurality of second inversion circuits are connected in a ring shape. The plurality of first inverting circuits include a first inverting circuit group configured by two successive stages of the first inverting circuits. The plurality of second inverting circuits include a second inverting circuit group configured by two successive stages of the second inverting circuits.

  The ring oscillator circuit design method according to the present invention includes a step of determining the number of stages of the plurality of inversion circuits for a ring oscillator circuit in which a plurality of inversion circuits are connected in a ring, and generating stage number data; And determining the operating voltage of each of the plurality of inverting circuits to be either the first voltage or the second voltage, and generating operating voltage data indicating the operating voltage of each of the inverting circuits. The step of generating the operating voltage data includes: a first inverting circuit group in which the plurality of inverting circuits are formed by two successive first inverting circuits each operating at a first voltage; A step of determining an operating voltage of each inverting circuit so as to include a second inverting circuit group formed by two successive inverting circuits operating at a second voltage different from the voltage.

  According to the present invention, there are provided a ring oscillator circuit and a ring oscillator circuit design method capable of obtaining a desired duty ratio even when a plurality of types of power supply voltages are used in the ring oscillator circuit.

FIG. 1 is a diagram illustrating an example of a ring oscillator circuit. FIG. 2 is a schematic diagram showing the ring oscillator circuit according to the first embodiment. FIG. 3 is a circuit diagram showing an example of the inverting circuit. FIG. 4 is a graph showing characteristics of the ring oscillator circuit according to the comparative example. FIG. 5 is a graph showing the relationship between the oscillation frequency and the power supply voltage. FIG. 6 is a schematic diagram illustrating a ring oscillator circuit according to a comparative example. FIG. 7 is a simulation result showing the relationship between the duty ratio and the power supply voltage. FIG. 8 is a schematic diagram showing a ring oscillator circuit according to the second embodiment. FIG. 9 is a block diagram showing a ring oscillator circuit design apparatus according to the third embodiment. FIG. 10 is a flowchart showing an operation method of the ring oscillator circuit design apparatus.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 2 is a schematic diagram showing the ring oscillator circuit 1 according to the present embodiment. As shown in FIG. 2, the ring oscillator circuit 1 includes a ring oscillator circuit input terminal IN (hereinafter referred to as an input terminal IN), a ring oscillator circuit output terminal OUT (hereinafter referred to as an output terminal OUT), And a plurality of inversion circuits (4, 5). The plurality of inverting circuits (4, 5) are arranged between the input terminal IN and the output terminal OUT, and are connected in series. The output terminal of the inverting circuit arranged in the final stage is connected to the input terminal of the inverting circuit arranged in the first stage. In other words, the plurality of inversion circuits (4, 5) are connected so as to be annular.

  The plurality of inverting circuits (4, 5) includes a plurality of first inverting circuits 4 and a plurality of second inverting circuits 5. Each of the plurality of first inversion circuits 4 is an inversion circuit in which the first voltage Va is used as the power supply voltage. Each of the plurality of second inverting circuits 5 is an inverting circuit in which the second voltage Vz is used as the power supply voltage. The first voltage Va is different from the second voltage Vz. As the first voltage Va, a standard voltage in a semiconductor device in which the ring oscillator circuit 1 is mounted is used. A voltage lower than the first voltage Va is used as the second voltage Vz.

  FIG. 3 is a circuit diagram showing an example of each inverting circuit (4, 5). As shown in FIG. 3, each inverting circuit includes a P-type MISFET and an N-type MISFET that are connected so as to be complementary. In the following description, the two MISFETs included in the first inversion circuit 4 may be described as a first P-type MISFET and a first N-type MISFET, respectively. In addition, the two MISFETs included in the second inversion circuit 5 may be described as a second P-type MISFET and a second N-type MISFET, respectively.

  Refer to FIG. 2 again. The plurality of inverter circuits (4, 5) are divided into a plurality of first inverter circuit groups 2, a plurality of second inverter circuit groups 3, and an output stage inverter circuit group 6. Each of the plurality of first inversion circuit groups 2 is constituted by two successive first inversion circuits 4. In each first inverting circuit group 2, the output terminal of one first inverting circuit 4 is connected to the input terminal of the other first inverting circuit 4. Similarly, each of the plurality of second inverting circuit groups 3 is constituted by two successive second inverting circuits 5. In each second inverting circuit group 3, the output terminal of one second inverting circuit 5 is connected to the input terminal of the other second inverting circuit 5. The plurality of first inverting circuit groups 2 and the plurality of second inverting circuit groups are arranged alternately. The output stage inverting circuit group 6 includes three stages of first inverting circuits 4. The output stage inversion circuit group 6 is arranged so that its output end is connected to the ring oscillator circuit output end OUT. The first-stage inverting circuit is the first inverting circuit 4.

  As described above, the power consumption can be reduced by using a plurality of types of power supply voltages (first voltage Va and second voltage Vz). In addition, the influence of the characteristic variation (such as MISFET manufacturing variation) on the oscillation frequency can be reduced. Further, the first inverting circuit group 2 and the second inverting circuit group 3 are arranged alternately so that the duty ratio in the output signal output from the output terminal OUT is set to a desired value (50%). It becomes possible to approach. These points will be described in detail below.

  First, the point that the power consumption is reduced and the influence of the characteristic variation are reduced will be described in detail.

  First, for comparison with the present embodiment, the characteristics of the ring oscillator circuit shown in FIG. That is, the characteristics of the ring oscillator circuit in which all of the plurality of inverting circuits operate with the same power supply voltage will be described.

  FIG. 4 is a graph illustrating the characteristics of the ring oscillator circuit according to the first comparative example. In FIG. 4, the horizontal axis represents the power supply voltage Vdd supplied to each inverting circuit. The vertical axis represents the oscillation frequency of the ring oscillator circuit. FIG. 4 shows the characteristics when the number N of the inverting circuits included in the ring oscillator circuit is 19, when the number N is 35, and when the number N is 51. The characteristics shown in FIG. 4 are results obtained by simulation.

  As shown in FIG. 4, when the power supply voltage is low, the oscillation frequency is also low. In general, as the power supply voltage is lowered, the ratio of the linear operation region to the operation region of the MISFET included in each inverting circuit increases. For this reason, the oscillation frequency greatly decreases as the power supply voltage decreases. Further, the oscillation frequency becomes lower as the number of stages of the inverting circuit is larger.

Specifically, the oscillation frequency f can be approximated by the following equation 1.
(Formula 1); f∝1 / (2 * n * τ)
In Equation 1, τ represents a delay time per stage of the inverting circuit. n indicates the number of stages of the inverting circuit.

  In order to reduce power consumption, it is conceivable to reduce the number of stages of inverting circuits. Here, referring to Equation 1, it can be seen that the oscillation frequency f increases if the number n of the inverting circuits is reduced. That is, in order to obtain a high oscillation frequency, the number of stages of the inverting circuit may be reduced. Thereby, power consumption can also be reduced. Further, if the number n of inverting circuits is reduced, it is advantageous in terms of layout area required for the inverting circuit. However, when the number of stages is small, the influence of variations in the characteristics of the inverting circuits on the oscillation frequency tends to increase. Further, when it is desired to obtain a low oscillation frequency, it is difficult to reduce the number n of inverting circuits. In order to obtain a low oscillation frequency, it is conceivable to reduce the capability of the MISFET (reduce the size of the MISFET). However, if the size of the MISFET is reduced, the influence of the characteristic variation increases. Referring to Equation 1, it can be seen that if the delay time τ is reduced (the capability of the MISFET is increased), the oscillation frequency is increased.

  In order to reduce power consumption, it is conceivable to use a voltage lower than a standard voltage (a power supply voltage that is typically used in a semiconductor device including a ring oscillator circuit) as the power supply voltage of each inverting circuit. However, if the power supply voltage is lowered, the oscillation frequency is also lowered. The relationship between the oscillation frequency and the power supply voltage will be described below.

The drain currents of the P-type MISFET and N-type MISFET included in each inverting circuit are expressed as Idp and Idn, respectively. Further, the power supply voltage of each inverting circuit is expressed as Va. In this case, the delay time τ of each inverting circuit is approximated by the following equation 2.
(Formula 2); τ∝1 / [1/2 × (Idp + Idn)]
In addition, Idp and Idn are approximated by the following expression 3.
(Formula 3); Idp, Idnｄ (Va−Vt) ^α
In Equation 3, Vt represents the threshold voltage of the MISFET. α is a coefficient. The value of α in Equation 3 is different between PMISFET and NMISFET.

From Equations 1 to 3, the relationship between the oscillation frequency f and the power supply voltage Va of each inverting circuit is approximated by Equation 4 below.
(Formula 4); f∝Va ^β
In Equation 4, the coefficient β is a value that depends on the size ratio between the P-type MISFET and the NMISFET in each inverting circuit, the device structure (the capability of the unit-size MISFET considering the threshold voltage and the like), and the like. In the characteristics shown in FIG. 4, β is about 2.9.

  As shown in Equation 4, the oscillation frequency depends on the power supply voltage. Therefore, it can be seen that if the power supply voltage is lowered to reduce power consumption, the oscillation frequency is lowered. Here, if the power supply voltage is lowered, the operation margin is reduced, and the oscillation frequency may be easily affected by characteristic variations (MISFET manufacturing variations, voltage variations, etc.).

  As described above with reference to FIG. 4 and Formulas 1 to 4, in order to reduce power consumption, it is conceivable to reduce the number of stages of the inverting circuit and to set the power supply voltage low. However, it is understood that the influence of characteristic variation becomes large by reducing the number of stages and the power supply voltage.

  On the other hand, in the ring oscillator circuit 1 according to the present embodiment, the second voltage Vz lower than the standard voltage Va (first voltage) is used as the power supply voltage of the second inverting circuit. Thereby, power consumption is reduced. Also, power consumption is reduced from the viewpoint of the number of stages of inverting circuits.

  FIG. 5 is a graph showing the relationship between the oscillation frequency and the power supply voltage in the ring oscillator circuit 1 according to the present embodiment. In FIG. 5, the horizontal axis represents the value of the second voltage Vz. The vertical axis represents the oscillation frequency. The relationship shown in FIG. 5 shows the result of simulation. FIG. 5 shows simulation results for the case where the number of stages of the inverting circuit is 19, the number of stages is 35, and the number of stages is 51. The first voltage Va is a constant value (1.2V).

  Comparing the simulation results shown in FIG. 5 and FIG. 4, when the number of stages is the same, the ring oscillator circuit in the present embodiment has a lower oscillation frequency. For example, in the simulation result of the present embodiment shown in FIG. 5, when the number of stages is 35 and the second voltage Vz is 1.0 V, the oscillation frequency is 1700 MHz. On the other hand, in the simulation result of Comparative Example 1 shown in FIG. 4, when the number of stages is 35 and the power supply voltage is the standard voltage (1.2 V), the oscillation frequency is 1950 MHz. That is, if the number of stages is the same, it can be seen that the oscillation frequency is lower in this embodiment. In the ring oscillator circuit according to the present embodiment, in order to obtain the same oscillation frequency of 1950 MHz as in Comparative Example 1, it is understood that the number of stages of the inverting circuit may be set to about 29 (1995 MHz). That is, in the present embodiment, the number of inverting circuits can be reduced from 35 (Comparative Example 1) to 29. Thereby, the effect of reducing the number of stages of 29 / 35≈82% is obtained, and the current consumption is also reduced from the viewpoint of reducing the number of stages.

  Further, in the present embodiment, the influence of the characteristic variation that is concerned by lowering the power supply voltage can be reduced by providing the first inverting circuit to which the first voltage is supplied as the power supply voltage. . That is, in this embodiment, since plural types of voltages (two types in this embodiment) are used as the power supply voltage, it is possible to achieve both reduction in power consumption and reduction in influence due to characteristic variation. .

  Subsequently, the point that the duty ratio can be brought close to a desired value in the present embodiment will be described in detail. The ring oscillator circuit is often used as a clock signal source. The duty ratio of the clock signal is preferably about 50%. Therefore, in the present embodiment, a case will be described in which the target value of the duty ratio of the output signal of the ring oscillator circuit is 50%.

  For comparison with the present embodiment, a ring oscillator circuit according to Comparative Example 2 will be described. As an example of the case where two types of power supply voltages are used, a ring oscillator circuit in which the first inverting circuit 4 and the second inverting circuit 5 are alternately arranged can be considered. Therefore, as Comparative Example 2, a ring oscillator circuit in which the first inverting circuit 4 and the second inverting circuit 5 are alternately arranged will be described. FIG. 6 is a schematic diagram illustrating a ring oscillator circuit according to the second comparative example. In Comparative Example 2 shown in FIG. 6, the first-stage and final-stage inverting circuits are the first inverting circuits 4. In the ring oscillator circuit shown in Comparative Example 2, it is difficult to obtain a value near 50% as the duty ratio.

  FIG. 7 is a simulation result showing the relationship between the duty ratio and the power supply voltage. In FIG. 7, simulation results are shown for each of the present embodiment, the modified example of the present embodiment, Comparative Example 1, Comparative Example 2, and Comparative Example 3. The modification is a ring oscillator circuit in which the positions of the first inversion circuit 4 and the second inversion circuit 5 in the present embodiment are switched. That is, in the modification, the first-stage inverting circuit is the second inverting circuit 5, and the output-stage inverting circuit group 6 is formed by the three-stage second inverting circuit 5. Comparative Example 3 shows a ring oscillator circuit in which the arrangement of the first inverting circuit 4 and the second inverting circuit 5 in the comparative example 2 is switched. That is, in Comparative Example 3, the first-stage and final-stage inverting circuits are the second inverting circuits.

  Usually, in the inverting circuit, if the driving capabilities of the P-type MISFET and the N-type MISFET are substantially equal, an oscillation waveform having a duty ratio of about 50% can be obtained. Therefore, in the ring oscillator circuit shown in Comparative Example 1 in FIG. 7, a duty ratio of approximately 50% is obtained. On the other hand, in Comparative Examples 2 and 3, as the second voltage is made lower than the first voltage (1.2 V), the duty ratio is far from 50%. On the other hand, in the present embodiment and the modification of the present embodiment, a value closer to 50% than the comparative examples 2 and 3 is obtained as the duty ratio.

  In Comparative Examples 2 and 3, the first inversion circuit 4 and the second inversion circuit 5 are alternately arranged. Therefore, in the path from the first stage to the last stage, a signal having the same logic level is input to only one of the first inversion circuit 4 and the second inversion circuit 5. For example, in the comparative example 2 (see FIG. 6), consider a case where the input terminal of the first inversion circuit 4 at the first stage changes from the low level to the high level. In this case, the outputs of all the first inverting circuits 4 change from the high level to the low level, and the outputs of all the second inverting circuits 5 change from the low level to the high level. Since the second inverting circuit 5 having a lower power supply voltage takes longer to change, the transition time from the low level to the high level is longer than the transition time from the high level to the low level. As a result, in the output signal, the high level time is shorter than the low level time, and the duty ratio is far from 50%.

  On the other hand, in this embodiment and this modification, both the change from the high level to the low level and the change from the low level to the high level occur in both the first inversion circuit 4 and the second inversion circuit 5. Occur. Therefore, the difference between the low level time and the high level time is kept equal, and the duty ratio is brought close to 50%.

  As described above, according to the present embodiment, by using a plurality of types of power supply voltages, it is possible to achieve both a reduction in power consumption and a reduction in the influence of characteristic variations on the oscillation frequency. In addition, since the first inverting circuit group 2 and the second inverting circuit group 3 are alternately arranged, the duty ratio can be made closer to a desired value (50%).

  In the present embodiment, an inverting circuit that operates at a second voltage lower than the standard voltage is used as the second inverting circuit 5. Therefore, depending on the difference between the gate voltage and the source voltage of the P-type MISFET, there is a possibility that the P-type MISFET that should be turned off is not turned off. For example, it is assumed that the standard voltage is Vdd and the second voltage is VddL (Vdd> VddL). The threshold voltage of the P-type MISFET is assumed to be Vtp. In this case, the second voltage VddL is determined such that “Vdd−VddL <| Vtp |” is satisfied. However, if VddL is too small, the P-type MISFET may not be turned off and the leakage current may increase. When actually applied to a product, VddL is determined in consideration of the power consumption specifications of the product. However, the present invention can be applied even when the above equation is not satisfied.

  In the present embodiment, the case where the output stage inverting circuit group 6 is constituted by three stages of inverting circuits has been described. However, the number of inverting circuits included in the output stage inverting circuit group 6 may be one.

(Second Embodiment)
Next, the second embodiment will be described. FIG. 8 is a schematic diagram showing the ring oscillator circuit 1 according to the present embodiment. This embodiment differs from the first embodiment in that a voltage higher than the first voltage Va (standard voltage) is used as the power supply voltage (second voltage) used for the second inverting circuit 5. Yes. Since other points can be the same as those in the first embodiment, a detailed description thereof will be omitted.

  In the present embodiment, the structures of the MISFETs (first P-type MISFET and first N-type MISFET) included in the first inversion circuit 4 are the same as the MISFETs (second P-type MISFET and second N-type MISFET) included in the second inversion circuit 5, respectively. ) The structure is different. Specifically, at least one of the thickness of the gate insulating film and the channel length of the MISFET is different between the first inversion circuit 4 and the second inversion circuit 5.

  A semiconductor device on which the ring oscillator circuit 1 is mounted may be designed to operate with two or more kinds of voltages. In such a semiconductor device, a plurality of types of MISFETs may be mounted corresponding to a plurality of power supply voltages. When the ring oscillator circuit 1 is mounted on such a semiconductor device, even if the MISFET structure is different between the first inversion circuit 4 and the second inversion circuit 5, no special manufacturing process is required. .

  In the ring oscillator circuit 1 shown in FIG. 8, the first-stage and final-stage inverting circuits are the first inverting circuits 4. However, the second inversion circuit 5 may be used as the first-stage and final-stage inversion circuits as necessary.

  According to this embodiment, the same operational effects as those of the first embodiment can be achieved. In addition, since a voltage higher than the standard voltage is used as the second voltage, the oscillation frequency can be increased.

(Third embodiment)
Subsequently, a third embodiment will be described. In the present embodiment, a ring oscillator circuit design apparatus and a ring oscillator circuit design method for designing the ring oscillator circuit described in the above-described embodiments will be described.

  FIG. 9 is a block diagram showing the ring oscillator circuit design apparatus 10 according to the present embodiment. As illustrated in FIG. 9, the ring oscillator circuit design device 10 includes a stage number determination unit 12, an operating voltage determination unit 13, a stage number adjustment unit 14, and a determination unit 15. The ring oscillator circuit design device 10 is realized by a computer. Specifically, this is realized by a CPU executing a ring oscillator circuit design program stored in advance in a storage medium such as a ROM (Read Only Memory). The ring oscillator circuit design device 10 is connected to a storage device 11 exemplified by a hard disk. The storage device 11 stores in advance information indicating a target frequency (target frequency range), a standard voltage, a target duty ratio, a target current consumption, and the like as design data.

  FIG. 10 is a flowchart showing an operation method of the ring oscillator circuit design apparatus 10.

Step S1; Determination of Stage Number First, the stage number determination unit 12 acquires design data from the storage device 11. The stage number determination unit 12 determines the number of stages of the inverting circuit included in the ring oscillator circuit based on the design data. At this time, the stage number determination unit 12 assumes that the power supply voltages of all the inverting circuits are the standard voltage Va (first voltage). Then, the number of stages is determined so that the oscillation frequency becomes the target frequency. The oscillation frequency of the ring oscillator circuit is obtained by simulation. In determining the number of stages, the stage number determination unit 12 may reflect a parameter indicating manufacturing variation of the MISFET, a parameter indicating power consumption, and the like. The stage number determination unit 12 generates stage number data indicating the determined number of stages.

Step S2: Determination of Operating Voltage Subsequently, the operating voltage determination unit 13 determines the operating voltage (power supply voltage) of each inverter circuit for the ring oscillator circuit including the inverter circuit having the number of stages indicated in the stage number data. Specifically, it is determined whether the power supply voltage of each inverting circuit is the first voltage Va or the second voltage Vz. That is, it is determined whether the first inverting circuit 4 or the second inverting circuit 5 is used as each inverting circuit. At this time, the operating voltage determination unit 13 forms a first inversion circuit group 2 in which the two stages of the first inversion circuits 4 are continuous and a second inversion circuit group 3 in which the two stages of the second inversion circuits are continuous. The operating voltage of each inverting circuit is determined. Here, a specific numerical value of the second voltage Vz can be determined by simulating the oscillation frequency when the operating voltages of all the inverting circuits are set to Vz.

  The operating voltage determination unit 13 generates operating voltage data indicating the relationship between each inverting circuit and the operating voltage.

Step S3: Adjustment of the number of stages Subsequently, the stage number adjustment unit 14 adjusts the number of stages of the inverting circuit based on the operating voltage data and the stage number data. The stage number adjustment unit 14 adjusts the number of stages so that the oscillation frequency becomes the target frequency. The stage number adjusting unit 14 generates adjusted data indicating the adjusted stage number and whether each inverting circuit is a first inverting circuit or a second inverting circuit.

Step S4; Determination Subsequently, the determination unit 15 determines whether there is no problem with the characteristics of the ring oscillator circuit indicated by the adjusted data based on the adjusted data. For example, the determination unit 15 calculates the influence of the oscillation frequency, duty ratio, current consumption, characteristic variation, and the like as characteristics by simulation calculation or the like. Then, the calculation result of these characteristics is compared with a preset target value (value stored in the storage device 11) to determine whether there is no problem.

  For example, it is determined whether or not the oscillation frequency is within a target frequency (range of fx1 to fx2). Further, it is determined whether or not the duty ratio is within a target range (when used as a clock signal source, around 50%). Further, it is determined whether or not the current consumption is equal to or less than the target current consumption. In addition, by performing simulation taking into account variations in threshold voltage and gate length in MISFETs, the lower limit value of the number of inverting circuits and the effect of variations in characteristics are such that the effects of variations in characteristics are sufficiently reduced. A lower limit value of the second voltage and the like that are sufficiently small are required. Based on the obtained lower limit value of the number of stages and the lower limit value of the second voltage, the influence degree of the characteristic variation is determined.

  If there is no problem, the adjusted data is output as data indicating the designed ring oscillator circuit, and the process ends. On the other hand, if there is a problem, the process of the next step S5 is performed.

Step S5: Change of the second voltage If it is determined in step S4 that there is a problem, the operating voltage determination unit 13 is notified of this. The operating voltage determination unit 13 changes the value of the second voltage Vz to another value. And the process after step S2 is repeated again.

  The ring oscillator circuit according to the above-described embodiment is designed by the processes in steps S1 to S5.

Next, the operation when adjusting the number of stages (the operation in step S3) will be described in detail. In step S3, the stage number adjustment unit 14 determines whether the number of stages of the inverting circuit is applicable to Case A or Case B below.
Case A: Number of stages k = 2n + 1 (n is an integer greater than or equal to 3) and n is an odd number Case B: Number of stages k = 2n + 1 (n is an integer greater than 3) and n is an even number

  In case A, either the number of stages of the first inverting circuit or the number of stages of the second inverting circuit is increased by three. Accordingly, the number of stages of the inverting circuit having the larger number of stages is reduced by two. Alternatively, the number of stages of the inverting circuit with the smaller number of stages is increased by two.

  In case B, one of the first inverting circuit and the second inverting circuit is increased by one stage. When adjusting the number of stages so that the oscillation frequency is increased, the number of stages of the inverting circuit having the smaller number of stages is reduced by two. Conversely, when adjusting the number of stages so that the oscillation frequency is lowered, the inverting circuit having the larger number of stages is increased by two stages.

  In both cases A and B, the oscillation frequency is compared with the target frequency after the number of stages is adjusted. If further adjustment is required, the determination of whether the case is A or B and the increase / decrease in the number of steps are repeated.

  For specific description, the ring oscillator circuit shown in FIG. 2 will be described. That is, it is assumed that the ring oscillator circuit indicated by the adjusted data is the ring oscillator circuit shown in FIG. The oscillation frequency of the ring oscillator circuit is assumed to be lower than the target frequency. In this case, in order to increase the oscillation frequency, the number of stages of the inverting circuit is reduced. Here, in the ring oscillator circuit shown in FIG. 2, the number of stages of the first inverting circuit 4 is larger than the number of stages of the second inverting circuit 5. Accordingly, the number of stages of the first inverting circuit 4 is reduced by two stages. Specifically, the first inversion circuit at the last stage (k-th stage) and one stage before the last stage (k-1 stage) is deleted. Conversely, when the oscillation frequency is higher than the target frequency, a two-stage second inversion circuit is inserted between the k-th stage first inversion circuit and the (k−1) -th stage first inversion circuit. .

  Subsequently, the operation in the step of changing the value of the second voltage Vz (step S5) will be described in detail. For example, if it is determined in step S4 that the power consumption is higher than the target value, it is conceivable to change the value of the second voltage Vz to a smaller value in step S5. However, if the value of the second voltage Vz is decreased, the oscillation frequency is also decreased. As a result, in order to adjust the oscillation frequency to the target frequency, the number of stages of the inverting circuit may be increased in the subsequent step S3. For example, in the case of the ring oscillator circuit shown in FIG. 2, the first inverting circuit having two stages, ie, the final stage (k stage) and the k-1 stage (the k-1 stage and k-2 stage may be used). May be deleted. On the other hand, when the value of the second voltage Vz is changed to a large value, the oscillation frequency increases. As a result, in the next step S3, the number of inverting circuits may be reduced. That is, when the value of the second voltage Vz is greatly changed in step S5, it may be necessary to adjust the number of inverting circuits. Therefore, in step S5, it is desirable to keep the change width of the second voltage Vz to the minimum necessary so that it is not necessary to greatly change the number of stages of the inverting circuit.

  The present invention has been described with reference to the first to third embodiments. These embodiments are not independent from each other, and can be used in combination within a consistent range.

DESCRIPTION OF SYMBOLS 1: Ring oscillator circuit 2: First inversion circuit group 3: Second inversion circuit group 4: First inversion circuit 5: Second inversion circuit 6: Output stage inversion circuit group 10: Ring oscillator circuit design device 11: Memory device 12 : Stage number determination unit 13: Operating voltage determination unit 14: Stage number adjustment unit 15: Determination unit

Claims (1)

A plurality of first inverting circuits each operating with a first voltage;
A plurality of second inverting circuits each operating with a second voltage different from the first voltage;
Comprising
The plurality of first inversion circuits and the plurality of second inversion circuits are connected in a ring shape,
The plurality of first inversion circuits include a first inversion circuit group configured by two successive stages of the first inversion circuits,
The plurality of second inverting circuits include a second inverting circuit group including a second inverting circuit group constituted by two successive stages of the second inverting circuits.

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