JP2010074721A - Delay circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a delay circuit capable of suppressing a delay amount from being varied based on variation in the threshold voltage of a transistor for each product. <P>SOLUTION: Capacitive elements M5-M8 are connected to output terminals of inverter buffers 11-14, respectively. A Vt dependent voltage generation unit applies a voltage corresponding to a threshold voltage Vtn of an MOS transistor included in the unit 2 itself to a substrate of MOS transistors that the capacitive elements M5-M8 include. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a delay circuit using an inverter buffer.

  In the conventional delay circuit, a plurality of inverter buffers having transistors are connected in series with each other. In addition, a capacitive element for adjusting the delay amount of the delay circuit is connected to each output terminal of each inverter buffer. The higher the capacitance of the capacitive element, the greater the delay amount of the delay circuit.

  It is desired that the delay amount of the delay circuit is constant. However, since a power supply voltage is used as a driving voltage for driving the transistors of the delay circuit, if the power supply voltage fluctuates, the operation state of the transistors of the delay circuit fluctuates, and the delay amount of the delay circuit fluctuates. .

  Patent Document 1 describes a delay circuit capable of suppressing a variation in delay amount based on a variation in power supply voltage. Note that the gate capacitance of the transistor is used as the capacitance of the capacitor.

  In this delay circuit, a constant voltage that suppresses fluctuations in the power supply voltage is generated. The constant voltage is used as a driving voltage for the transistor of the delay circuit.

As a result, it is possible to suppress fluctuations in the operation state of the transistor based on fluctuations in the power supply voltage, and thus it is possible to suppress fluctuations in the delay amount based on fluctuations in the power supply voltage.
JP-A-11-168362

  However, the delay circuit described in Patent Document 1 has a problem in that variations in the amount of delay based on variations in threshold voltages of transistors and temperature characteristics of transistors due to manufacturing processes and the like cannot be suppressed.

  The delay circuit according to the present invention includes a plurality of inverter buffers connected in series with each other, and each of the plurality of inverter buffers has a one-to-one correspondence with a gate connected to the output terminal of the inverter buffer. A plurality of capacitive elements having a first transistor; and a voltage generator having a second transistor and applying a voltage corresponding to a threshold voltage of the second transistor to the substrate of the first transistor.

  The delay circuit according to the present invention corresponds to each of a plurality of inverter buffers connected in series with each other and the plurality of inverter buffers, and is connected to an output terminal of the corresponding inverter buffer and has a gate capacitance of the transistor. A plurality of capacitive elements used, and each substrate of the plurality of capacitive elements is biased with a voltage having a threshold voltage dependency of a transistor with respect to an operating voltage applied to the plurality of inverter buffers.

  According to the present invention, since the substrate voltage of the capacitive element is changed according to the threshold voltage of the transistor, it is possible to change the capacitance of the capacitive element according to the threshold voltage, and the threshold voltage of the transistor for each product. It is possible to suppress the variation in the delay amount based on the variation of the.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing the configuration of the delay circuit according to the first embodiment of the present invention. In FIG. 1, the delay circuit includes a delay unit 1 and a Vt dependent voltage generation unit 2.

  The delay unit 1 includes an input terminal IN, an output terminal OUT, inverter buffers 11 to 14, and capacitive elements M5 to M8. Note that the number of inverter buffers is only four in FIG. The number of capacitive elements is the same as the number of inverter buffers.

  Each of the inverter buffers 11 to 14 is connected in series with each other. The input terminal of the first-stage inverter buffer 11 is connected to the input terminal IN, and the output terminal of the last-stage inverter buffer 14 is connected to the output terminal OUT.

  Each of inverter buffers 11 to 14 includes a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) 1a and an N-channel MOS transistor (hereinafter referred to as an NMOS transistor) 1b.

  The source of the PMOS transistor 1a is connected to the power supply terminal VCC. The source of the NMOS transistor 1b is connected to the ground potential terminal GND.

  The gates of the PMOS transistor 1a and the NMOS transistor 1b are shared and serve as the input terminal of the inverter buffer. The drains of the PMOS transistor 1a and the NMOS transistor 1b are shared and serve as an output terminal of the inverter buffer.

  Capacitance elements M5 to M8 correspond to each of inverter buffers 11 to 14 on a one-to-one basis. The capacitive elements M5 to M8 are connected to the output terminals of the inverter buffers corresponding to the capacitive elements M5 to M8.

  Capacitance elements M5 to M8 are MOS elements each having a MOS transistor and utilizing the gate capacitance of the MOS transistor. Specifically, in capacitive elements M5 to M8, the gate of its own MOS transistor is connected to the output terminal of the inverter buffer corresponding to itself. The source, drain and substrate of the MOS transistor are connected in common.

  Thereby, the capacitive elements M5 to M8 can be used as capacitive elements utilizing the gate capacitance of the MOS transistor. Capacitance elements M5 and M6 have PMOS transistors, and MOS transistors M7 and M8 have NMOS transistors.

  The capacitive elements M5 to M8 are associated with the inverter buffers 11 to 14 so that the capacitive elements having the PMOS transistors and the capacitive elements having the NMOS transistors are alternately connected to the output terminals of the inverter buffers 11 to 14. It is done. More specifically, the capacitive element M5 is connected to the output terminal of the inverter buffer 11, the capacitive element M6 is connected to the output terminal of the inverter buffer 12, and the capacitive element M7 is connected to the output terminal of the inverter buffer 13. The capacitive element M8 is connected to the output terminal of the inverter buffer 14.

  By configuring the delay unit 1 in this way, the delay unit 1 delays the data input to the input terminal IN and outputs it from the output terminal OUT.

  The Vt dependent voltage generator 2 has a plurality of MOS transistors. In the present embodiment, it is assumed that there are four or more MOS transistors included in the Vt-dependent voltage generator 2. In FIG. 1, four MOS transistors M1 to M4 among the plurality of MOS transistors are shown.

  Since the threshold voltage of the transistor varies from product to product depending on the manufacturing process or the like, the MOS transistor included in the Vt dependent voltage generator 2 and the MOS transistor included in the delay unit 1 in the same product have the same threshold voltage. Have.

  Each of the MOS transistors included in the Vt-dependent voltage generator 2 is interposed between the power supply terminal VCC and the ground potential terminal GND. Each of the MOS transistors is diode-connected. Further, each of the MOS transistors is connected in series with each other. The MOS transistor M1 is the foremost MOS transistor, and its drain and gate are connected to the power supply terminal VCC. The MOS transistor M4 is the MOS transistor at the last stage, and its source is connected to the ground potential terminal GND.

  A terminal voltage of an output terminal of a predetermined MOS transistor among the MOS transistors included in the Vt dependent voltage generation unit 2 is applied as a substrate voltage IVCC to the substrates of the MOS transistors of the capacitive elements M5 to M8.

  The predetermined MOS transistor is different for each channel of the MOS transistor of the capacitive element. That is, the predetermined MOS transistors are different between the capacitive elements M5 and M6 and the capacitive elements M7 and M8.

  Since each of the MOS transistors included in the Vt-dependent voltage generator 2 is diode-connected and connected in series with each other, the voltage between the respective terminals of the MOS transistor becomes equal to the threshold voltage Vtn of the MOS transistor. . Therefore, when the number of stages from the first stage MOS transistor M1 to the predetermined MOS transistor is M, the substrate voltage IVCC becomes IVCC = VCC−M × Vtn.

  For this reason, the Vt dependent voltage generator 2 applies a voltage corresponding to the threshold voltage Vtn to the substrates of the capacitive elements M5 to M8 as the substrate voltage IVCC. More specifically, the higher the threshold voltage Vtn, the lower the Vt-dependent voltage generator 2 applies a lower voltage to the substrates of the capacitive elements M5 to M8 as the substrate voltage IVCC.

  Therefore, the substrates of the capacitive elements M5 to M8 are biased with a voltage having the threshold voltage dependency of the MOS transistor with respect to the operating voltage to the inverter buffers 11 to 14.

  Note that the number M of stages for determining the substrate voltage IVCC is appropriately set according to the characteristics of the MOS transistor.

  Next, the effect will be described.

  According to the present embodiment, the capacitive elements M5 to M8 are connected to the output terminals of the inverter buffers 11 to 14, respectively. The Vt-dependent voltage generator 2 applies a voltage corresponding to the threshold voltage Vtn of the MOS transistor it has to the substrate of the MOS transistors included in the capacitive elements M5 to M8.

  In this case, since the substrate voltage IVCC of the capacitive elements M5 to M8 is changed according to the threshold voltage Vtn of the MOS transistor, the gate capacitances of the capacitive elements M5 to M8 can be changed according to the threshold voltage Vtn. . Therefore, the delay amount of the delay unit 1 having the capacitive elements M5 to M8 and the inverter buffers 11 to 14 can be changed according to the threshold voltage Vtn. Therefore, it is possible to suppress the variation in the delay amount based on the variation in the threshold voltage of the transistor for each product.

  In the present embodiment, the substrates of the capacitive elements M5 to M8 are biased with a voltage having the threshold voltage dependency of the MOS transistor with respect to the operating voltages of the inverter buffers 11 to 14.

  In this case, since the substrate voltage IVCC of the capacitive elements M5 to M8 is changed according to the threshold voltage Vtn of the MOS transistor, the gate capacitances of the capacitive elements M5 to M8 can be changed according to the threshold voltage Vtn. . Therefore, the delay amount of the delay unit 1 having the capacitive elements M5 to M8 and the inverter buffers 11 to 14 can be changed according to the threshold voltage Vtn. Therefore, it is possible to suppress the variation in the delay amount based on the variation in the threshold voltage of the transistor for each product.

  In the present embodiment, the Vt-dependent voltage generator 2 applies a lower voltage to the substrates of the transistors of the capacitive elements M5 to M8 as the substrate voltage IVCC as the threshold voltage Vtn is higher.

  In this case, when the threshold voltage Vtn at which the delay operation of the delay unit 1 is delayed is high, the substrate voltage IVCC is low, so that the gate capacitances of the capacitive elements M5 to M8 can be reduced. It becomes possible to speed up the delay operation. In addition, when the threshold voltage Vtn at which the delay operation of the delay unit 1 is accelerated is low, the substrate voltage IVCC increases, so that the gate capacitances of the capacitive elements M5 to M8 can be increased. As a result, the delay of the delay unit 1 It becomes possible to slow down the operation.

  Therefore, it is possible to more appropriately suppress the variation in the delay amount based on the variation in the threshold voltage of the transistor for each product.

  In the present embodiment, the MOS transistor included in the Vt-dependent voltage generator 2 is diode-connected between the power supply terminal VCC and the ground potential terminal GND. The Vt dependent voltage generator 2 applies the terminal voltage of the output terminal of the MOS transistor to the substrates of the capacitive elements M5 to M8.

  In this case, it is possible to easily apply a voltage that decreases as the threshold voltage Vtn increases to the substrates of the capacitive elements M5 to M8.

  In the present embodiment, the Vt-dependent voltage generator 2 has a plurality of MOS transistors, and these MOS transistors are connected in series with each other. The Vt-dependent voltage generator 2 applies the terminal voltage of the output terminal of a predetermined MOS transistor among the MOS transistors to the substrate of the transistors of the capacitive elements M5 to M8.

  In this case, by appropriately setting the number M of stages from the first-stage MOS transistor M1 to the predetermined MOS transistor, a voltage suitable for the characteristics of the MOS transistor can be applied to the substrates of the capacitive elements M5 to M8.

  As described above, the delay circuit according to the present embodiment has a one-to-one correspondence with each of the plurality of inverter buffers (11 to 14) and the plurality of inverter buffers (11 to 14) connected in series, and the gates thereof are A plurality of capacitive elements (M5 to M8) connected to the corresponding output terminal of the inverter buffer and a voltage corresponding to the threshold voltage (Vtn) of the second transistors (M1 to M4) are set to the first transistors (M1 to M4). And a voltage generator (2) to be applied to the substrate.

  The delay circuit corresponds to each of the plurality of inverter buffers (11 to 14) connected in series and the plurality of inverter buffers (11 to 14), and is connected to the output terminal of the corresponding inverter buffer. And a plurality of capacitive elements (M1 to M4) using gate capacitances of the transistors, and the respective substrates of the plurality of capacitive elements (M1 to M4) are connected to the plurality of inverter buffers (11 to 14). The operation voltage is biased with a voltage having a dependency on the threshold voltage of the transistor.

  Moreover, it is comprised so that a voltage generation part (2) may apply a low voltage to the board | substrate of a 1st transistor (M1-M4), so that the threshold voltage (Vtn) of a 2nd transistor (M1-M4) is high.

  Further, the second transistors (M1 to M4) are diode-connected between the power supply terminal (VCC) and the ground potential terminal (GND), and the voltage generator (2) is an output terminal of the second transistors (M1 to M4). Is applied to the substrate of the first transistor (M5 to M8).

  And there are a plurality of second transistors (M1 to M4), these second transistors (M1 to M) are connected in series with each other, and the voltage generator (2) is the second transistor (M1 to M4). The terminal voltage of the output terminal of the predetermined second transistor is configured to be applied to the substrate of the first transistor (M5 to M8).

  Next, a second embodiment will be described.

  In the present embodiment, a delay circuit capable of suppressing the variation of the delay amount based on the temperature characteristic of the transistor in addition to the suppression of the variation of the delay amount based on the variation of the threshold voltage of the transistor for each product will be described.

  FIG. 2 is a circuit diagram showing the configuration of the delay circuit of the present embodiment. In the following, description will be given mainly of the configuration and functions different from those described in FIG. In addition, the same code | symbol is attached | subjected to what has the same function as FIG.

  In FIG. 2, the terminal voltage of the output terminal of the MOS transistor M4 is applied to the substrates of the MOS transistors M7 and M8 which are NMOS transistors.

  In addition to the configuration shown in FIG. 1, the Vt-dependent voltage generator 2 has at least one of MOS transistors M9 and M10. The terminal voltage of the output terminal of the MOS transistor M4 is applied to the substrates of the MOS transistors M7 and M8, which are NMOS transistors. The MOS transistor M9 is an NMOS transistor, and the MOS transistor M10 is a PMOS transistor.

  MOS transistors M9 and M10 are interposed between MOS transistor M4 and ground potential terminal GND. The MOS transistors M9 and M10 are always off.

  In FIG. 2, the gate and source of the MOS transistor M9 are shared and connected to the ground potential terminal GND, and the drain of the MOS transistor M9 is connected to the source of the MOS transistor M4. The gate of the MOS transistor M10 is connected to the power supply terminal VCC. The source of the MOS transistor M10 is connected to the source of the MOS transistor M4. The drain of the MOS transistor M10 is connected to the MOS transistor ground potential terminal GND.

  As a result, in the Vt dependent voltage generator 2, no current flows from the power supply terminal VCC to the ground potential terminal GND except for the leak current generated in the MOS transistors M9 and M10.

  Therefore, when the leakage voltage due to this leakage current is Vl, the substrate voltage IVCC applied to the capacitive elements M5 to M8 is IVCC = VCC−M × Vtn−Vl.

  The higher the temperature of the delay circuit, the larger the leakage current and the larger the leakage voltage Vl. That is, the leakage voltage Vl depends on the temperature of the delay circuit. Therefore, the Vt dependent voltage generator 2 applies a voltage corresponding to the temperature to the substrates of the capacitive elements M5 to M8 as the substrate voltage IVCC.

  Next, the effect will be described.

  In the present embodiment, the Vt-dependent voltage generator 2 includes a MOS transistor that is always off and is interposed between the MOS transistors M1 to M4 and the ground potential terminal GND.

  In this case, a voltage corresponding to the temperature can be applied to the substrates of the capacitive elements M5 to M8.

  Specifically, since the threshold voltage Vtn decreases as the temperature increases, the value of VCC-M × Vtn increases. However, since the leak voltage Vl increases as the temperature increases, the substrate voltage IVCC is determined by the MOS transistor M9 and It is relatively low compared to the case without M10. Therefore, it is possible to suppress the delay of the delay operation of the delay circuit due to the increase in temperature.

  Further, since the threshold voltage Vtn increases as the temperature decreases, the value of VCC-M × Vtn decreases. However, the leakage voltage Vl decreases as the temperature decreases, so that the substrate voltage IVCC does not include the MOS transistors M9 and M10. It is relatively higher than the case. Therefore, it is possible to suppress the progress of the delay operation of the delay circuit due to the temperature becoming lower.

  Therefore, it is possible to suppress a variation in the delay amount based on the temperature characteristics of the transistor.

  As described above, the voltage generator (2) of the delay circuit according to the present embodiment includes the always-off transistors (M9 and M10) interposed between the second transistors (M1 to M4) and the ground potential terminal (GND). Configured.

  Next, a third embodiment will be described.

  FIG. 3 is a circuit diagram showing the configuration of the delay circuit of the present embodiment. In the following, description will be given mainly of the configuration and functions different from those described in FIGS. In addition, the same code | symbol is attached | subjected to what has the same function as FIG. 1 and FIG.

  The MOS transistors included in the Vt-dependent voltage generation unit 2 are all NMOS transistors in FIGS. 1 and 2, but include NMOS transistors and PMOS transistors in FIG.

  More specifically, in the Vt-dependent voltage generator 2, an NMOS transistor is connected in series from the power supply terminal VCC, and a PMOS transistor is connected in series from the output terminal of the last NMOS transistor.

  In FIG. 2, MOS transistors M1 and M2 are NMOS transistors, and MOS transistors M3 and M4 are PMOS transistors.

  Next, the effect will be described.

  In the present embodiment, the MOS transistor included in the Vt dependent voltage generator 2 includes an NMOS transistor and a PMOS transistor.

  In this case, depending on the manufacturing process, the threshold voltage variation of the transistor for each product occurs in one of the NMOS transistor and the PMOS transistor or in both the NMOS transistor and the PMOS transistor. It becomes possible to suppress the variation in the delay amount based on the variation in the threshold voltage.

  As described above, the MOS transistors (M1 to M4) included in the voltage generator (2) of the delay circuit according to the present embodiment include the NMOS transistors (M1 and M2) and the PMOS transistors (M3 and M4).

  In each embodiment described above, the illustrated configuration is merely an example, and the present invention is not limited to the configuration.

  For example, all the MOS transistors included in the Vt-dependent voltage generator 2 may be PMOS transistors.

  The capacitive elements M5 to M8 may be all PMOS transistors or all NMOS transistors.

  Further, although the power supply voltage VCC is used as the power supply potential of the inverter buffers 11 to 14 and the Vt dependent voltage generation unit 2, for example, the fluctuation of the power supply voltage VCC generated by the invention described in Patent Document 1 is suppressed. A constant voltage may be used.

1 is a circuit diagram showing a configuration of a delay circuit according to a first embodiment of the present invention. It is the circuit diagram which showed the structure of the delay circuit of 2nd embodiment of this invention. It is the circuit diagram which showed the structure of the delay circuit of 3rd embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Delay part 1a P channel MOS transistor 1b N channel MOS transistor 2 tv dependence voltage generation part 11-14 Inverter buffer M1-M4, M9, M10 MOS transistor M5-M8 Capacitance element

Claims (7)

A plurality of inverter buffers connected in series with each other;
A plurality of capacitive elements each having a first transistor connected to each of the plurality of inverter buffers on a one-to-one basis and having a gate connected to an output terminal of the inverter buffer corresponding to itself;
A delay circuit including a second transistor, and a voltage generator configured to apply a voltage corresponding to a threshold voltage of the second transistor to the substrate of the first transistor. The delay circuit according to claim 1,
The voltage generator is a delay circuit that applies a lower voltage to the substrate as the threshold voltage is higher. The delay circuit according to claim 2,
The second transistor is diode-connected between a power supply terminal and a ground potential terminal,
The voltage generator is a delay circuit that applies a terminal voltage of an output terminal of the second transistor to the substrate. The delay circuit according to claim 3, wherein
There are a plurality of the second transistors, and each of the plurality of second transistors is connected in series with each other,
The voltage generation unit is a delay circuit that applies a terminal voltage of an output terminal of a predetermined second transistor of the plurality of second transistors to the substrate. The delay circuit according to claim 4, wherein
The plurality of second transistors include a delay circuit including an N-channel transistor and a P-channel transistor. The delay circuit according to any one of claims 3 to 5,
The voltage generating unit further includes a third transistor that is always off and is interposed between the second transistor and the ground potential terminal. A plurality of inverter buffers connected in series with each other;
Corresponding to each of the plurality of inverter buffers, having a plurality of capacitive elements connected to the output terminals of the corresponding inverter buffers and utilizing the gate capacitance of the transistors,
A delay circuit, wherein each substrate of the plurality of capacitive elements is biased with a voltage having a threshold voltage dependency of a transistor with respect to an operating voltage applied to the plurality of inverter buffers.

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