JP5181959B2 - DC power supply and semiconductor integrated circuit for power control - Google Patents

Description

  The present invention relates to a DC power supply device and a power supply control semiconductor integrated circuit that forms the DC power supply device, and more particularly to a technique that is effective when used for a DC-DC converter such as a series regulator that forms a power supply device that outputs a plurality of DC voltages.

  In an electronic system such as a personal computer, a plurality of boards such as a main board (motherboard) and sub boards (child boards and grandchild boards) are mounted, and a plurality of LSIs such as a main LSI and sub LSI are mounted on each board. ing. In such a system, the system may malfunction if the startup order of LSIs is not specified when the power is turned on.

Conventionally, in a DC power supply device having two regulators, two regulators are connected in series, and a delay detection circuit for detecting a rise delay of the output of the preceding regulator is provided, and the output of this delay detection circuit is used as a start signal An invention has been proposed in which a subsequent regulator is activated (for example, Patent Document 1).
Japanese Patent Laid-Open No. 2004-266953

  Although the DC power supply device of the above-mentioned prior application has an advantage that the sequence control for starting up a plurality of regulators in order can be surely performed, the start-up order is fixed and the subsequent-stage regulator is raised until the output of the previous-stage regulator rises In other words, it is not possible to start up the regulator in the subsequent stage (expected start-up) before the output of the regulator in the previous stage rises.

  In addition, depending on the system, it may be better not only to start up LSIs but also to turn off LSI power supplies in a predetermined order when stopped. However, since the DC power supply device of the prior invention does not have a function for setting the order of shutdown, there is a problem that user convenience is poor.

  The present invention has been made paying attention to the problems as described above. The purpose of the present invention is to enable start-up of the output of each regulator in an arbitrary order in a DC power supply device having a plurality of regulators. There is to do.

  Another object of the present invention is to make it possible to raise the output of a subsequent regulator before the output of the former regulator rises in a DC power supply device having a plurality of regulators.

  Still another object of the present invention is to enable a DC power supply device including a plurality of regulators to drop the output of each regulator in a desired order when the system is stopped.

In order to achieve the above object, according to the present invention, in a DC power supply device including a plurality of regulators each formed as a semiconductor integrated circuit, a resistor is connected to a first external terminal that connects a capacitor to each of the plurality of regulators. Providing a second external terminal and a delay control circuit including a constant current source capable of forming a time constant circuit together with the capacitor and the resistor, the capacitor is charged by the constant current source of the delay control circuit the adjustable rise timing of the output voltage, respectively in accordance with the potential, the fall timing of the output voltage according to the potential of the charge charged in the capacitor drops by being discharged through the resistor individually adjustable It is composed.

  According to the above-described means, the output of each regulator can be raised in an arbitrary order, and the output of the subsequent-stage regulator can be raised before the output of the previous-stage regulator rises. Further, the output of each regulator can be lowered in a desired order when the system is stopped.

Preferably, a current control transistor connected between the input terminal and the output terminal, a control circuit for driving and controlling the current control transistor, a first external terminal for connecting an external capacitor, and an external connection A delay control circuit including a second external terminal to which a resistor is connected, a constant current source having a determination means for determining a potential of an internal node that forms a time constant circuit together with the capacitor and the resistor and changes in accordance with the time constant; The operation start timing of the control circuit by the output of the determination means can be adjusted according to the potential generated by charging the capacitor by the constant current source of the delay control circuit, and the capacitor the control times by the output of said determination means in accordance with the potential of the electric charge charged in the drops by being discharged through the resistor Operation timing of the stop constitutes a semiconductor integrated circuit power supply controller to be adjustable in.

  By using a plurality of power supply control semiconductor integrated circuits having the above-described configuration and changing the capacitance value and the resistance value of the external capacitor connected to the external terminal of each semiconductor integrated circuit, these elements, the delay control circuit, It is possible to realize a DC power supply device that can raise the output of each regulator in an arbitrary order according to the time constant determined by, and can lower the output of each regulator in a desired order when the system is stopped. .

  Further, preferably, a switch element connected between the output terminal and a ground point is provided, and an output timing of the delay control circuit is determined according to a resistance value of the resistor, and the switch is determined by an output of the determination means. The output voltage falls when the element is turned on. As a result, the output of each regulator can be quickly lowered in a desired order.

  Here, an error amplifier that outputs a voltage corresponding to a potential difference between a voltage obtained by dividing the output voltage and a predetermined reference voltage and controls the current control transistor based on the output voltage is provided. The bias of the error amplifier is controlled.

Further, in a power supply control semiconductor integrated circuit in which a plurality of regulator circuits are formed on a single semiconductor chip, a plurality of output terminals corresponding to each of the plurality of regulator circuits are connected to a first external capacitor. A constant current source having a terminal, a second external terminal for connecting an external resistor, a time constant circuit together with the capacitor and the resistor, and a determination means for determining a potential of an internal node that changes in accordance with the time constant A delay control circuit including the delay control circuit, and the rising timing of the output voltage of any one of the plurality of regulator circuits can be adjusted in accordance with a potential generated by charging the capacitor by the constant current source of the delay control circuit. is, the potential of the electric charge charged in the capacitor drops by being discharged through the resistor Accordingly, the falling timing of the output voltage of any one of the plurality of regulator circuits is adjustable, and the regulator circuit other than any one of the regulator circuits outputs after a predetermined delay time from the rising of the output voltage of the regulator circuit. The power supply control semiconductor integrated circuit is configured such that the voltage rises and the output voltage falls after a predetermined delay time from the fall of the output voltage of the regulator circuit.

  Thereby, a plurality of DC output voltages can be obtained with one semiconductor integrated circuit, and the outputs of the plurality of regulators can be raised in a predetermined order, and the outputs of the plurality of regulators can be lowered in a predetermined order. A DC power supply that can be realized can be realized.

  According to the present invention, in a DC power supply device including a plurality of regulators, the output of each regulator can be raised in an arbitrary order. Further, it becomes possible to start raising the output of the subsequent-stage regulator before the output of the preceding-stage regulator rises. Further, the output of each regulator can be lowered in a desired order when the system is stopped.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.
Example 1
FIG. 1 shows a first embodiment of a DC power supply apparatus to which the present invention is applied. This embodiment is a combination of regulators with one output, and a DC power supply device using two series regulators will be described as an example, but it can also be applied to a DC power supply device using three or more series regulators. . Although not particularly limited, the elements constituting the circuit in the range surrounded by the alternate long and short dash lines 10A and 10B in FIG. 1 are each formed on one semiconductor chip, and each is a semiconductor integrated circuit (regulator). IC).

  The two regulator ICs 10A and 10B have the same configuration, and are different only in the capacitance value and the resistance value of the external capacitor, so the configuration will be described only for one regulator IC 10A. In the regulator IC 10A, C1 is an external smoothing capacitor connected to the voltage input terminal IN to stabilize the input voltage Vin, and C2 is an external smoothing capacitor connected to the output terminal OUT to stabilize the output voltage Vout. It is.

  The regulator IC 10A in this embodiment includes an LDO (low saturation series regulator) 11 connected between the voltage input terminal IN and the output terminal OUT, and a resistor connected in series between the output terminal OUT and the ground point. R0, a switch SW0, and a delay control circuit 12 that controls activation of the LDO 11 based on an on / off control signal CE input to the external terminal CNT.

  The regulator IC 10A has an external terminal PC to which an external capacitor Cd for setting the rising delay time in the delay control circuit 12 is connected, and an external terminal for setting the falling delay time in the delay control circuit 12. And an external terminal PR to which the resistor Rd is connected.

  Although not particularly limited, as shown in FIG. 2, the LDO 11 is connected between the input terminal IN and the output terminal OUT and controls a current flowing from the input terminal IN to the output terminal OUT. Q1, an open collector transistor Q2 for controlling the base voltage of Q1, and a control voltage via the transistor Q2 according to the potential difference between the feedback voltage VFB obtained by dividing the output voltage Vout by resistors R1 and R2 and the reference voltage Vref An error amplifier AMP for controlling the transistor Q1 is provided.

  In addition, a bias circuit BIAS for applying a bias to the error amplifier AMP is provided. The bias circuit BIAS starts biasing the error amplifier AMP when the control signal ST from the delay control circuit 12 changes to a high level, and the control signal ST Is changed to the low level, the driving of the control transistor Q1 is stopped by turning off the bias.

  Further, although not particularly limited, a comparator CMP for detecting an abnormality such as an input overvoltage state or a rise in chip temperature is provided, and provided between the base of the transistor Q2 and the ground point at the output of the comparator CMP. By turning on the transistor Q3, the control transistor Q1 can be turned off by turning off the transistor Q2.

  FIG. 3 shows a configuration example of the delay control circuit 12. The delay control circuit 12 includes a constant current source CS, a switch SW1 connected between the constant current source CS and the external terminal PC, and a switch SW2 connected between the external terminal PC and the external terminal PR. And an inverter INV3 as level determination means having an input terminal connected to a connection node Nd1 between the switch SW1 and the capacitor Cd, an inverter INV4 that inverts the output of the inverter INV3, and generates the control signal ST.

  The switch SW2 is complementarily turned on and off by the output of the inverter INV1 that inverts the input signal CE of the external terminal CNT, and the switch SW1 is complementarily turned on and off by the output of the inverter INV2 that inverts the output of the inverter INV1.

  When the switch SW1 is turned on, the capacitor Cd is charged by the constant current source CS, the potential Vcd of the node Nd1 gradually rises as shown in FIG. 4, and when the logical threshold value of the inverter INV3 is reached, the output of the inverter INV3 is When the control signal ST, which is the output of the inverter INV4, changes to the low level, the bias circuit BIAS is activated and the error amplifier AMP is activated. As a result, the output voltage Vout starts to rise.

  When the switch SW1 is turned off, SW2 is turned on, and the charge of the capacitor Cd is discharged via the resistor Rd, and the potential Vcd of the node Nd1 gradually decreases as shown in FIG. When the potential Vcd reaches the logic threshold value of the inverter INV3, the output of the inverter INV3 changes to a high level, whereby the switch SW0 is turned on and the output voltage Vout is lowered. At this time, the control signal ST, which is the output of the inverter INV4, changes to a low level, whereby the bias supply from the bias circuit BIAS to the error amplifier AMP is cut off, the operation of the error amplifier is stopped, and the control transistor Q1 is turned off. The

  In the DC power supply device of the embodiment of FIG. 1, the output of each regulator rises as shown by t1 and t2 in FIG. 4 by making the capacitance values of the capacitors Cd connected to the external terminals PC of the regulator ICs 10A and 10B different. You can change the timing. Also, by making the resistance values of the resistors Rd connected to the external terminals PR of the regulator ICs 10A and 10B different, the falling timing of the output of each regulator can be changed as shown by t3 and t4 in FIG.

Note that the delay control circuit of FIG. 3 shows the principle, and it goes without saying that the actual circuit may be a more complicated circuit rather than such a simple circuit.
(Example 2)
FIG. 5 shows a second embodiment of a DC power supply apparatus to which the present invention is applied. This embodiment is intended for a multi-output regulator. As an example, a DC power supply apparatus using a regulator IC having two outputs will be described. However, a DC power supply apparatus using a regulator IC having three or more outputs is described. It can also be applied to. In FIG. 5, the elements constituting the circuit in the range surrounded by the alternate long and short dash line 10 are formed on one semiconductor chip and configured as a regulator IC.

  The regulator IC 10 in this embodiment includes two LDOs (regulator circuits) 11a and 11b connected between a voltage input terminal IN and an output terminal OUT, two output terminals OUT1 and OUT2, an output terminal OUT1, and a ground point. A resistor Ra and a switch SWa connected in series with each other, and a resistor Rb and a switch SWb connected in series between the output terminal OUT2 and a ground point.

  The regulator IC 10 has an external terminal PC to which an external capacitor Cd for setting the rising delay time of the LDO 11a and LDO 11b by the delay control circuit 12 is connected, and the falling delay of the LDO 11a and LDO 11b by the delay control circuit 12. An external terminal PR to which an external resistor Rd for setting time is connected is provided.

  In the regulator IC of FIG. 5, a circuit having a configuration similar to that shown in FIG. 3 can be used as the delay control circuit 12. The difference from the circuit of FIG. 3 is that in this embodiment, a circuit that detects the rising of the output of the first LDO 11a and an AND gate that takes the logical sum of the output of the circuit and the outputs of the inverters INV3 and INV4 are provided. The configuration is such that the control signal ST2 of the LDO 11b and the control signal of the switch SWa are generated.

  Instead of providing a rise detection circuit and an AND gate, a delay circuit for delaying the outputs of the inverters INV3 and INV4 by a predetermined time Δt to generate the control signal ST2 of the LDO 11b and the control signal of the switch SWa may be provided. Good. As this delay circuit, for example, a circuit using a delay time of a logic gate by connecting a plurality of inverters in series, or a circuit using a time constant circuit having the same configuration as the circuit of FIG.

  In the DC power supply device of the embodiment of FIG. 5, the rising timing and the rising timing of each regulator cannot be freely set unlike the DC power supply device of the embodiment of FIG. 1, but as shown in FIG. The rising timing and falling timing of the regulator that rises to can be changed by adjusting the capacitance value of the capacitor Cd connected to the external terminal PC and the resistance value of the resistor Rd connected to the external terminal PR.

  Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment. For example, in the above embodiment, the built-in regulator is a series regulator (step-down regulator). However, the present invention can also be applied to a step-up switching regulator.

  In the above embodiment, the resistor R0 and the switch SW0 are provided between the output terminal and the ground point in the chip in order to accelerate the fall of the output of the regulator. However, the resistor R0 and the switch SW0 are external to the chip. And a signal for controlling it may be output from the regulator IC. Alternatively, the resistor R0 and the switch SW0 may be omitted, and the LDO may be turned off so that the output voltage Vout naturally falls with the current flowing through the load.

  Furthermore, in the second embodiment, the regulator IC in which two LDOs are built in is shown in the order in which the output rises in advance. However, the order in which the regulator ICs in which three or more LDOs are built in is raised. You may comprise so that it can change.

  In the above description, the example in which the present invention is applied to a series regulator IC has been described. However, the present invention is not limited to the present invention, and a secondary battery charge control circuit, a DC-DC converter, a WLED, as well as a plurality of LDOs. (White light emitting diode) Widely used for a multi-function power supply control IC such as a power management IC equipped with a plurality of power supply system circuits such as a driver circuit.

It is a circuit block diagram which shows 1st Embodiment of the series regulator IC to which this invention is applied. FIG. 2 is a circuit configuration diagram showing a configuration example of an LDO built in the series regulator IC of FIG. 1. FIG. 2 is a circuit configuration diagram showing a configuration example of a delay control circuit built in the series regulator IC of FIG. 1. It is a time chart which shows the operation timing of the direct-current power supply device using the series regulator IC of FIG. It is a circuit block diagram which shows 2nd Embodiment of the series regulator IC to which this invention is applied. It is a time chart which shows the operation timing of the direct-current power supply device using the series regulator IC of FIG.

Explanation of symbols

10 Series Regulator IC
11 LDO (Low Saturation Series Regulator)
12 Delay control circuit AMP Error amplifier BIAS Bias circuit CMP Anomaly detection comparator Q1 Current control transistor Cd External capacitor for rising adjustment Rd External resistor for falling adjustment SW0 Switch element for output voltage falling CE ON / OFF control signal

Claims (6)

A DC power supply device including a plurality of regulators each formed as a semiconductor integrated circuit,
A first external terminal for connecting a capacitor to each of the plurality of regulators; a second external terminal for connecting a resistor; and a delay control circuit including a constant current source capable of forming a time constant circuit together with the capacitor and the resistor. Prepared ,
The rising timing of the output voltage can be adjusted according to the potential generated by charging the capacitor by the constant current source of the delay control circuit, and the charge charged in the capacitor is discharged via the resistor. The DC power supply device is characterized in that the falling timing of the output voltage can be adjusted in accordance with the potential that drops. A current control transistor connected between the input terminal and the output terminal;
A control circuit for driving and controlling the current control transistor;
A first external terminal for connecting an external capacitor;
A second external terminal for connecting an external resistor;
A delay control circuit including a constant current source having a determination unit configured to determine a potential of an internal node which forms a time constant circuit together with the capacitor and the resistor and changes according to the time constant;
The operation start timing of the control circuit by the output of the determination means can be adjusted according to the potential generated by charging the capacitor by the constant current source of the delay control circuit ,
The operation stop timing of the control circuit by the output of the determination means can be adjusted in accordance with the potential that drops when the charge charged in the capacitor is discharged through the resistor. A semiconductor integrated circuit for power control.   A switch element connected between the output terminal and a ground point is provided, and the output voltage falls when the switch element is turned on by an output of the determination means. Item 3. The semiconductor integrated circuit for power supply control according to Item 2.   The control circuit includes an error amplifier that outputs a voltage corresponding to a potential difference between a voltage obtained by dividing the output voltage and a predetermined reference voltage, and controls the current control transistor based on the output voltage. 4. The semiconductor integrated circuit for power control according to claim 2, wherein the bias of the error amplifier is controlled by an output. A power supply control semiconductor integrated circuit in which a plurality of regulator circuits are formed on one semiconductor chip,
A plurality of output terminals corresponding to each of the plurality of regulator circuits, a first external terminal for connecting an external capacitor, a second external terminal for connecting an external resistor, a time constant circuit together with the capacitor and the resistor A delay control circuit including a constant current source having a determination unit configured to determine a potential of an internal node that is configured and changes according to a time constant;
The rising timing of the output voltage of any one of the plurality of regulator circuits can be adjusted according to the potential generated when the capacitor is charged by the constant current source of the delay control circuit, and the capacitor is charged . The falling timing of the output voltage of any one of the plurality of regulator circuits can be adjusted in accordance with the potential that drops due to the electric charge being discharged through the resistor ,
In any one of the regulator circuits, the output voltage rises after a predetermined delay time from the rise of the output voltage of the regulator circuit, and the output voltage falls after a predetermined delay time from the fall of the output voltage of the regulator circuit. A semiconductor integrated circuit for power control, which is configured as described above.   A plurality of switches respectively connected between the plurality of output terminals and a ground point are provided, and when a control signal indicating operation stop is input, the plurality of switches are sequentially turned on by an output of the determination unit. The power supply control semiconductor integrated circuit according to claim 5, wherein the output voltage is configured to sequentially fall.

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