JP5062188B2 - POWER CIRCUIT, ELECTRONIC DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND POWER CIRCUIT CONTROL METHOD - Google Patents

Description

The present invention relates to a power supply circuit, an electronic device, a semiconductor integrated circuit device, and a control method for the power supply circuit.
Semiconductor devices (LSIs) are being increased in speed and integration. In addition, the voltage of semiconductor devices has been reduced with the demand for lower power consumption. An electronic device is configured by combining various semiconductor devices, and a power source having a voltage corresponding to the configuration of each device is supplied to the semiconductor devices. The operation of the semiconductor device may become unstable depending on the order of the supplied power. For this reason, adjusting the timing which produces | generates among several power supplies is desired.

  Conventionally, semiconductor devices (LSIs) have been increased in speed and integration. In addition, the voltage of semiconductor devices has been reduced with the demand for lower power consumption. An electronic device is configured by combining various semiconductor devices, and a power source having a voltage corresponding to the configuration of each device is supplied to the semiconductor devices. The operation of the semiconductor device may become unstable depending on the order of the supplied power. For this reason, power supply circuits that control the order of supplying a plurality of power supplies having different voltages have been proposed (see, for example, Patent Document 1, Patent Document 2, and Patent Document 3).

Also in the inside of one semiconductor device, the operation may become unstable due to the order of supplying a plurality of different voltages as described above. For example, an ASIC (Application Specific Integrated Circuit) as a semiconductor device includes an input / output circuit (I / O circuit, Interface section) operating at a standard voltage (a voltage common to a connected device) and a voltage lower than the standard voltage. And an internal circuit (Core section) that operates in Then, it is necessary to supply power to the input / output circuit section after supplying power to the internal circuit. By supplying power in this order, generation of an error signal in the input / output circuit section is prevented. FIG. 13 is a circuit diagram of the power supply circuit 10 that supplies power in this way .

  The power supply circuit 10 includes a conversion circuit (DC-DC converter unit) 12 that supplies a first voltage V1 obtained by stepping down the input voltage Vin and a second voltage V2 equal to the input voltage Vin to the semiconductor circuit 11. . The semiconductor circuit 11 includes an internal circuit 11a that operates with the first voltage V1 and an input / output circuit 11b that operates with the second voltage V2. The conversion circuit 12 uses the output signal of the PWM control circuit 23 that compares the output signal of the oscillator 21 and the output signal of the comparator 22 that compares the first voltage V1 and the reference voltage Vr1 to the first transistor T1 and the second transistor. On / off control of T2 is performed to generate a first voltage V1 obtained by stepping down the input voltage Vin. The power supply circuit 10 includes a switch circuit 13 and a switch control circuit (SW control unit) 14 that controls the switch circuit 13. The switch control circuit 14 includes a comparator 25 that compares the first voltage V1 and the reference voltage Vr2, and the output signal of the comparator 25 constitutes the switch circuit 13 and controls on / off of the transistor TS that functions as a switch. . With this configuration, the power supply circuit 10 turns on the transistor TS when the first voltage V1 becomes higher than the reference voltage Vr2, and outputs a second voltage V2 that is substantially equal to the input voltage Vin.

  Incidentally, the electronic device includes a plurality of semiconductor integrated circuits 31 as shown in FIG. Each semiconductor integrated circuit 31 includes an internal circuit and an input / output circuit as described above. Each semiconductor device malfunctions when the power supply voltage supplied to the internal circuit fluctuates, and therefore requires a highly accurate voltage (a voltage very close to a required value), and thus includes a power supply circuit 10.

JP-A-8-95652 JP 11-143559 A JP 2004-129333 A

  However, since the power supply circuit 10 of each semiconductor integrated circuit 31 has variations in the timing of supplying power, the input / output circuit 11b that transmits signals between the semiconductor integrated circuits 31 causes latch-up as shown in FIG. There was a problem that through current flowed. This problem also occurs between circuits in one semiconductor device, for example, in an internal circuit and an input / output circuit.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a power supply circuit, an electronic apparatus, a semiconductor integrated circuit device, and a control method for the power supply circuit that can control the order of turning on a plurality of power supplies. Is to provide.

In order to achieve the above object, according to the first aspect of the present invention , the converter includes a switch circuit for outputting the input voltage as the second DC voltage, and the conversion circuit has a capacitance value of the connected soft start capacitor. The input voltage is converted into the first DC voltage by pulse width modulation based on the difference voltage between the low-potential-side voltage and the first DC voltage among the soft start signal and the reference voltage that change with the time constant determined in (1). The switch control circuit controls the resistance value of the switch circuit according to the voltage of the soft start signal, and controls the second DC voltage in proportion to the voltage of the soft start signal. Therefore, when a plurality of power supply circuits are provided, the first DC voltage and the second DC voltage can be increased simultaneously in each power supply circuit. A through current can be prevented from flowing between the circuit to which the first DC voltage is supplied and the circuit to which the second DC voltage is supplied, and the second DC voltage is supplied. It is possible to prevent a through current from flowing between the input / output circuits.

According to the invention described in claim 2 , the electronic apparatus includes a plurality of power supply circuits described in claim 1 , and the same soft start signal is input to each power supply circuit. Therefore, the first DC voltage and the second DC voltage can be increased simultaneously in the plurality of power supply circuits. A through current can be prevented from flowing between the circuit to which the first DC voltage is supplied and the circuit to which the second DC voltage is supplied, and the second DC voltage is supplied. It is possible to prevent a through current from flowing between the input / output circuits.

According to the invention described in claim 3, the semiconductor integrated circuit device includes a power supply circuit according to claim 1, and a semiconductor circuit in which the first and second DC voltage generated by the power supply circuit is supplied Provided. Therefore, it is possible to prevent a through current from flowing between a circuit that is provided in the semiconductor circuit and operates with the first DC voltage, and a circuit that operates with the second DC voltage.

According to the fourth aspect of the present invention, the power supply circuit includes a conversion circuit that converts the input voltage into the first DC voltage, a switch circuit that outputs the input voltage as the second DC voltage, and a switch circuit. A switch control circuit for controlling on / off of the switch. The conversion circuit has a pulse width based on a difference voltage between a soft start signal that changes with a time constant determined by a capacitance value of a connected soft start capacitor and a reference voltage and a low-potential-side voltage and a first DC voltage. A first DC voltage is generated by the modulation. Switch control circuit controls the resistance value of the switching circuit in accordance with the voltage of the soft-start signal, controls the second DC voltage in proportion to the voltage of the soft-start signal. Therefore, when a plurality of power supply circuits are provided, the first DC voltage and the second DC voltage can be increased simultaneously in each power supply circuit. A through current can be prevented from flowing between the circuit to which the first DC voltage is supplied and the circuit to which the second DC voltage is supplied, and the second DC voltage is supplied. It is possible to prevent a through current from flowing between the input / output circuits.

  As described above, according to the present invention, it is possible to provide a power supply circuit, an electronic device, a semiconductor integrated circuit device, and a power supply circuit control method capable of controlling the order of turning on a plurality of power supplies.

1 is a block diagram of a semiconductor integrated circuit device according to a first embodiment. The block diagram of an electronic device. The wave form diagram which shows the operation | movement of a DC-DC converter. The block diagram of the semiconductor integrated circuit device of a second embodiment. The wave form diagram which shows the operation | movement of a DC-DC converter. The block diagram of the semiconductor integrated circuit device of a third embodiment. The block diagram of an electronic device. The wave form diagram which shows the operation | movement of a DC-DC converter. The block diagram of the semiconductor integrated circuit device provided with another DC-DC converter. The block diagram of the semiconductor integrated circuit device provided with another DC-DC converter. The block diagram of the semiconductor integrated circuit device provided with another DC-DC converter. The block diagram of the semiconductor integrated circuit device provided with another DC-DC converter. 1 is a block diagram of a conventional semiconductor integrated circuit device. The block diagram of the conventional electronic device. 1 is a partial circuit diagram of a semiconductor integrated circuit device.

(First embodiment)
Hereinafter, a first embodiment embodying the present invention will be described with reference to FIGS. FIG. 1 is a schematic block diagram of a semiconductor integrated circuit device (hereinafter simply referred to as a semiconductor device) 40.

  The semiconductor device 40 includes a semiconductor circuit 41 and a power supply circuit 42 (DC-DC converter) that supplies a plurality of operation power supplies to the semiconductor circuit 41. These circuits 41 and 42 are formed on one chip. . The semiconductor circuit 41 includes a plurality of circuits that operate with different power supply voltages. As a plurality of circuits, FIG. 1 shows an internal circuit (Core Logic) 41a and an input / output circuit (Interface Logic) 41b. The internal circuit 41a operates at the first voltage, and the input / output circuit 41b operates at the second voltage.

  The power supply circuit 42 generates a power supply having a necessary voltage in the semiconductor circuit 41 based on the input voltage Vin. In the present embodiment, the power supply circuit 42 is a DC-DC converter, generates a first voltage V1 as a first DC voltage having a value obtained by stepping down the input voltage Vin, and a value substantially equal to the input voltage Vin. The second voltage V2 is output as a second DC voltage.

The power supply circuit 42 includes a conversion circuit 43, a switch circuit 44, and a switch control circuit (SW control unit) 45.
The conversion circuit 43 converts the input voltage Vin that is direct current into a first voltage V1 that is direct current. The switch circuit 44 receives the input voltage Vin and is connected to the semiconductor circuit 41. The switch control circuit 45 receives the first voltage V1 and the notification signal ST. The switch control circuit 45 performs on / off control of the switch circuit 44 based on the first voltage V1 and the notification signal ST. When the switch circuit 44 is turned on (closed), the input voltage Vin is output to the semiconductor circuit 41 as the second voltage V2.

  The conversion circuit 43 includes an error amplification circuit 51, a reference power supply e1, an oscillator 52, a PWM control circuit 53, a first transistor T1, and a second transistor T2. The conversion circuit 43 controls the first and second transistors T2 based on a pulse width modulated signal based on the difference voltage between the first voltage V1 and the reference voltage Vr1 of the reference power supply e1, and generates the first voltage V1.

  In the error amplifier circuit 51, the reference voltage Vr1 is input from the reference power source e1 to the non-inverting input terminal, and the first voltage V1 is input to the inverting input terminal. The error amplifying circuit 51 outputs a signal S1 obtained by amplifying the difference voltage between the reference voltage Vr1 and the first voltage V1. The oscillator 52 is a triangular wave oscillator and outputs a triangular wave signal OSC1 having a predetermined frequency. The PWM control circuit 53 compares the voltage of the output signal S1 of the error amplification circuit 51 and the triangular wave signal OSC1, and generates a first control signal SG1 and a second control signal SG2 having a pulse width corresponding to the comparison result.

  The first transistor T1 is a P-channel MOS transistor in the present embodiment, and the input voltage Vin is applied to the source, the drain is connected to the second transistor T2, and the first control signal SG1 is applied to the gate. The second transistor T2 is an N-channel MOS transistor in this embodiment, the source is connected to a low-potential power supply (ground GND in this embodiment), the drain is connected to the first transistor T1, and the second control signal SG2 is connected to the gate. Is applied. The first terminal of the choke coil L1 is connected to a node to which the first transistor T1 and the second transistor T2 are connected, and the second terminal of the coil L1 is connected to the semiconductor circuit 41. The second terminal of the coil L1 is connected to the ground GND via the smoothing capacitor C1.

  The first transistor T1 and the second transistor T2 are turned on and off approximately complementarily by the first control signal SG1 and the second control signal SG2. The first voltage V1 obtained by stepping down the input voltage Vin is supplied to the semiconductor circuit 41 by turning on and off the transistors T1 and T2. The first voltage V1 is determined by the on / off ratio of the transistors T1 and T2 according to the comparison result between the signal S1 (amplified signal of the difference voltage between the first voltage V1 and the reference voltage Vr1) and the triangular wave signal OSC1. That is, the conversion circuit 43 feeds back the detection result of the first voltage V1 and controls the pulse widths of the first control signal SG1 and the second control signal SG2 output from the PWM control circuit 53 (PWM control). The first voltage V1 is controlled by controlling the ratio (on / off ratio) of the on-time and off-time of the transistor T1.

  In the present embodiment, the switch circuit 44 is configured by a P-channel MOS transistor TS. The transistor TS has an input voltage Vin applied to a first terminal (for example, a source terminal), and a second terminal (for example, a drain terminal) that is a semiconductor circuit. The control terminal (gate terminal) is connected to the switch control circuit 45.

  The switch control circuit 45 includes reference power supplies e11 and e12, comparators 61 and 62, and a transistor T11. The first comparator 61 is a voltage comparator. The first voltage V1 is input to the inverting input terminal, the first reference voltage Vr11 is input from the first reference power supply e11 to the non-inverting input terminal, and the output terminal is connected to the transistor T11. It is connected. In the first reference power supply e11, the first reference voltage Vr11 is set lower than the first voltage V1. The first comparator 61 compares the first voltage V1 with the first reference voltage Vr11, and outputs an H level or L level signal S11 according to the comparison result.

  The transistor T11 is an N-channel MOS transistor in this embodiment, and has a source connected to a low potential power supply (ground GND), a drain connected to the external terminal P1, and a gate applied with a signal S11. Therefore, the switch control circuit 45 outputs the notification signal ST corresponding to the state of the transistor T11 from the external terminal P1. The state of the transistor T11 (ON or OFF) indicates the comparison result of the first comparator 61, that is, the level relationship between the first voltage V1 and the first reference voltage Vr11, that is, the first voltage V1 is equal to the first reference voltage Vr11. Corresponds to whether or not. Therefore, by appropriately setting the first reference voltage Vr11, it is possible to output the notification signal ST indicating whether or not the first voltage V1 has substantially reached a predetermined voltage.

  Conversely, it can be considered that the notification signal ST is input to the switch control circuit 45 via the external terminal P1. This notification signal ST is applied to the inverting input terminal of the second comparator 62. The drain of the transistor T11 is connected to the inverting input terminal of the second comparator 62. Therefore, a voltage corresponding to the on / off state of the transistor T11 and the voltage of the notification signal ST is applied to the inverting input terminal of the second comparator 62. That is, the inverting input terminal of the second comparator 62 is at the ground GND level when the transistor T11 is on, and is at the level of the notification signal ST when the transistor T11 is off.

  In the second comparator 62, the second reference voltage Vr12 is input from the second reference power source e12 to the non-inverting input terminal. In the second reference power source e12, the second reference voltage Vr12 is set lower than the input voltage Vin. The second comparator 62 compares the voltage level of the inverting input terminal with the second reference voltage Vr12, and outputs an H level or L level signal S12 according to the comparison result. This signal S12 is applied to the gate of the transistor TS constituting the switch circuit 44.

  In FIG. 1, the external terminal P1 is connected to the first terminal of the resistor R1, and the input voltage Vin is applied to the second terminal of the resistor R1. Accordingly, in the connection state of FIG. 1, the resistor R1 pulls up the external terminal P1 to the input voltage Vin level.

  In the switch control circuit 45 configured as described above, the first comparator 61 outputs an H level signal S11 when the first voltage V1 is lower than the first reference voltage Vr11. T11 turns on. Therefore, since the level of the inverting input terminal is lower than the second reference voltage Vr12, the second comparator 62 outputs the H level signal S12, and the switch circuit 44 is turned off (opened) by the signal S12.

  As another example, when the first voltage V1 is higher than the first reference voltage Vr11, the first comparator 61 outputs a signal S11 of L level, and the transistor T11 is turned off by the signal S11. For this reason, the notification signal ST is input to the second comparator 62. For this reason, the second comparator 62 outputs a signal S12 corresponding to the comparison result between the level of the notification signal ST and the second reference voltage Vr12, and the switch circuit 44 is turned on (closed) or turned off (opened) by the signal. .

  Accordingly, the switch control circuit 45 controls the switch circuit 44 to be turned off when the first voltage V1 is lower than the first reference voltage Vr11, and the level of the notification signal ST (external) when the first voltage V1 is higher than the first reference voltage Vr11. The switch circuit 44 is controlled to be turned on or off according to the level of the terminal P1.

  As shown in FIG. 2, the electronic device 70 includes a plurality of (two in FIG. 2) semiconductor devices together with the semiconductor device 40 shown in FIG. 1 (referred to as a first semiconductor device 40a to be distinguished from other semiconductor devices). (Second and third semiconductor devices) 40b and 40c are provided. Similar to the first semiconductor device 40a, the second semiconductor device 40b and the third semiconductor device 40c include semiconductor circuits (not shown) that operate at the first voltage V1b and the second voltage V2. The semiconductor circuits of the respective semiconductor devices 40a, 40b, and 40c are connected to each other through an input / output circuit so as to be able to exchange signals.

  The second semiconductor device 40b and the third semiconductor device 40c include a power circuit (not shown) configured similarly to the power circuit 42 of the first semiconductor device 40a, and the external terminals P1 of the power circuits are connected to each other. Has been. Accordingly, the resistor R1 pulls up the external terminal P1 of each semiconductor device 40a, 40b, 40c.

  In the semiconductor devices 40a, 40b, and 40c connected as described above, the timing for outputting the second voltage V2 varies. This variation is caused by the speed at which the first voltage V1 increases. For example, in each of the semiconductor devices 40a, 40b, and 40c, the first voltage V1 is set to voltages V1a, V1b, and V1c, and the second voltage V2 is set to voltages V2a, V2b, and V2c, respectively. As shown in FIG. 3, the first voltage V1a, V1b, and V1c are increased at the fastest rate of the first voltage V1b in the second semiconductor device 40, and the first voltage V1a in the first semiconductor device 40 is the highest. Is the slowest.

  Under the above conditions, the power supply circuit 42 of each of the semiconductor devices 40a, 40b, and 40c turns on the transistor T11 when the first voltages V1a, V1b, and V1c are lower than the reference voltage Vr11 to connect the external terminal P1 to the ground GND. To level. That is, between the semiconductor devices 40a, 40b, and 40c, the power supply circuit 42 outputs the L level notification signal ST from the external terminal P1 when the first voltages V1a, V1b, and V1c are lower than the reference voltage Vr11. It becomes equivalent. Then, in at least one of the plurality of semiconductor devices 40a, 40b, and 40c, when the first voltages V1a, V1b, and V1c are lower than the reference voltage Vr11, the notification signal ST becomes L level. Therefore, as shown in FIG. 3, when the first voltage V1a of the first semiconductor device 40 that rises the latest becomes higher than the reference voltage Vr11, the notification signal ST becomes H level.

  Then, the power supply circuit 42 of each of the semiconductor devices 40a, 40b, 40c controls the switch circuit 44 to be turned on in response to the H level notification signal ST. For this reason, the timing at which the second voltage V2 is output in each of the semiconductor devices 40a, 40b, and 40c is substantially the same. For this reason, since the timing at which the second voltage V2 is supplied to the input / output circuit 41b is substantially the same between the semiconductor devices 40a, 40b, and 40c, no latch-up occurs in the input / output circuit 41b.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The switch control circuit 45 performs on / off control of the transistor TS of the switch circuit 44 based on the comparison result obtained by comparing the first voltage V1 and the reference voltage Vr11 and the input notification signal ST. Accordingly, the second voltage V2 can be output after the first voltage V1 becomes higher than the reference voltage Vr11 and the preparation of another device is completed by the notification signal ST, and the order of the plurality of voltages V1 and V2 is controlled. can do. Then, it is possible to prevent a through current from flowing between the internal circuit 41a supplied with the first voltage V1 and the input / output circuit 41b supplied with the second voltage V2.

  (2) The switch control circuit 45 outputs a signal corresponding to the comparison result obtained by comparing the first voltage V1 and the reference voltage Vr11. Therefore, when a plurality of power supply circuits 42 are provided, the first voltage V1 is set to the reference voltage Vr11 in all the power supply circuits 42 by connecting the power supply circuits 42 so as to receive the output signal as the notification signal ST. The second voltage V2 can be output after the preparation of the other device is completed by the notification signal ST, and the order of the plurality of voltages V1 and V2 can be controlled. Then, it is possible to prevent a through current from flowing between the input / output circuits 41b to which the second voltage V2 is supplied.

(Second embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.
For convenience of explanation, the same components as those in the first embodiment are denoted by the same reference numerals, and a part of the explanation is omitted.

FIG. 4 is a block circuit diagram of a semiconductor integrated circuit device (semiconductor device) 80 in the present embodiment.
The semiconductor device 80 includes a semiconductor circuit 41 and a power supply circuit 81 (DC-DC converter) that supplies a plurality of operation power supplies to the semiconductor circuit 41. These circuits 41 and 81 are formed on one chip. .

The power supply circuit 81 includes a conversion circuit 43, a switch circuit 44, and a switch control circuit (SW control unit) 82.
The switch control circuit 82 includes a voltage dividing circuit 83, an error amplifier 84, a transistor T21, and a resistor R13.

  The voltage dividing circuit 83 is composed of a plurality of (two in this embodiment) resistors R11 and R12 connected in series. The first terminal of the first resistor R11 is connected to the output side terminal (the second terminal of the transistor TS) of the switch circuit 44, the second terminal of the first resistor R11 is connected to the first terminal of the second resistor R12, A second terminal of the two resistor R12 is connected to the ground GND. A node between the first resistor R11 and the second resistor R12 is connected to the inverting input terminal of the error amplifier 84. Accordingly, the voltage dividing circuit 83 generates a voltage V21 obtained by dividing the second voltage V2 in accordance with the resistance value ratio between the first resistor R11 and the second resistor R12.

  In the error amplifier 84, the voltage generated by the voltage dividing circuit 83 is input to the inverting input terminal, the first voltage V1 is input to the non-inverting input terminal, and the output terminal is connected to the transistor T21. The error amplifier 84 outputs a signal S21 obtained by amplifying the difference voltage between the first voltage V1 and the divided voltage V21.

  In this embodiment, the transistor T21 is a P-channel MOS transistor, the source is connected to the first terminal of the resistor R13, the drain is connected to the low potential power supply (ground GND), and the signal S21 is applied to the gate. The input voltage Vin is applied to the second terminal of the resistor R13. A node between the transistor T21 and the resistor R21 is connected to the gate of the transistor TS constituting the switch circuit 44.

  In the power supply circuit 81 configured as described above, in the error amplifier 84, when the divided voltage V21 is lower than the first voltage V1, the on-resistance value of the transistor T21 is reduced by the output signal S21 of the error amplifier 84. For this reason, the voltage of the signal S22 applied to the gate of the transistor TS constituting the switch circuit 44 is lowered, and the on-resistance value of the transistor TS is reduced. Therefore, the second voltage V2 increases according to the on-resistance value of the transistor TS.

  As the second voltage V2 increases, the divided voltage V21 increases and approaches the first voltage V1, that is, when the differential voltage approaches 0, the voltage of the signal S21 output from the error amplifier 84 decreases, and the transistor T21 is turned on. The resistance value increases. For this reason, the voltage of the signal S22 applied to the gate of the transistor TS constituting the switch circuit 44 is increased, and the on-resistance value of the transistor TS is increased. Accordingly, the second voltage V2 is lowered.

  The first voltage V1 gradually rises from the power-on in accordance with the operation of the conversion circuit 43. Accordingly, since the voltage at the non-inverting input terminal of the error amplifier 84 increases, the second voltage V2 increases accordingly. That is, as shown in FIG. 5, the power supply circuit 81 operates as a linear regulator that increases the second voltage V2 in proportion to the increase in the first voltage V1. Then, when the first voltage V1 is stabilized at a constant voltage, the switch control circuit 82 stabilizes the second voltage V2 output from the switch circuit 44 with respect to the voltage at the non-inverting input terminal of the error amplifier 84 at a constant voltage. To do.

  The power supply circuit 81 configured as described above prevents a through current generated in the internal circuit 41 a in the semiconductor circuit 41. That is, the internal circuit 41a and the input / output circuit 41b have different operating power supplies, the first voltage V1 that is the operating power supply is supplied to the internal circuit 41a, and the second voltage V2 that is the operating power supply is not supplied to the input / output circuit 41b. In this case, in the internal circuit 41a, the voltage of the input gate that receives a signal from the input / output circuit 41b becomes unstable, and a through current flows. On the other hand, the power supply circuit 81 of the present embodiment increases the second voltage V2 supplied to the input / output circuit 41b in proportion to the increase of the first voltage V1 supplied to the internal circuit 41a. Therefore, the voltage of the input gate that receives a signal from the input / output circuit 41b in the internal circuit is stabilized, and a through current is prevented.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The power supply circuit 81 increases the second voltage V2 supplied to the input / output circuit 41b in proportion to the increase of the first voltage V1 supplied to the internal circuit 41a. Therefore, the voltage of the input gate that receives a signal from the input / output circuit 41b in the internal circuit is stabilized, and a through current can be prevented.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS.
For the convenience of explanation, the same components as those in the first and second embodiments are denoted by the same reference numerals, and a part of the explanation is omitted.

FIG. 6 is a block circuit diagram of a semiconductor integrated circuit device (semiconductor device) 90 in the present embodiment.
The semiconductor device 90 includes a semiconductor circuit 41 and a power supply circuit 91 (DC-DC converter) that supplies a plurality of operating power supplies to the semiconductor circuit 41. These circuits 41 and 91 are formed on one chip. .

The power supply circuit 91 includes a conversion circuit 92, a switch circuit 44, and a switch control circuit (SW control unit) 82.
The conversion circuit 92 includes an error amplifier 93, a reference power supply e1, a PWM control circuit 53, an oscillator 52, a first transistor T1, and a second transistor T2. A soft start signal SS is input to the conversion circuit 92. The conversion circuit 92 includes first and second transistors T2 based on a pulse width-modulated signal based on a difference voltage between the low-potential side voltage of the reference voltage Vr1 and the soft start signal SS of the reference power source e1 and the first voltage V1. To generate the first voltage V1.

  The error amplifier 93 has two non-inverting input terminals and outputs a signal S31 obtained by amplifying the difference voltage between the lower voltage input to both non-inverting input terminals and the voltage input to the inverting input terminals. In the present embodiment, in the error amplifier 93, the reference voltage Vr1 is input from the reference power source e1 to the first non-inverting input terminal, the second non-inverting input terminal is connected to the external terminal P2, and the first inverting input terminal is the first. The voltage V1 is input. A capacitor C2 is connected between the external terminal P2 and the ground GND. A constant current circuit 94 is connected to the external terminal. Therefore, a soft start signal SS having a voltage across the capacitor C2 that increases in potential with charging by the constant current circuit 94 is input to the second non-inverting input terminal of the error amplifier 93. Accordingly, the error amplifier 93 outputs a signal S31 obtained by amplifying the difference voltage between the lower voltage of the reference voltage Vr1 and the soft start signal SS and the first voltage V1.

  In the conversion circuit 92 configured as described above, when the power is turned on (when the power supply circuit 91 is activated), the capacitor C2 connected to the external terminal P2 is discharged, so that the potential of the soft start signal SS is zero volts (0V). ). Therefore, the conversion circuit 92 outputs the first voltage V1 of 0V. The potential of the soft start signal SS gradually rises from 0 V due to charging by the current I1 supplied by the constant current circuit 94 built in the power supply circuit 91. While the voltage of the soft start signal SS is lower than the reference voltage Vr11, the conversion circuit 92 controls the transistors T1 and T2 according to the difference voltage between the voltage of the soft start signal SS and the first voltage V1. Accordingly, since the voltage of the soft start signal SS gradually increases, the conversion circuit 92 gradually increases the first voltage V1 according to the potential of the soft start signal SS. When the potential of the soft start signal SS becomes higher than the reference voltage Vr11, the conversion circuit 92 controls the transistors T1 and T2 according to the difference voltage between the reference voltage Vr11 and the first voltage V1. Therefore, the conversion circuit 92 operates to control the output voltage (first voltage V1) with the reference voltage Vr11 and to maintain the first voltage V1 at a constant voltage.

  As shown in FIG. 7, the electronic device 100 includes a plurality of (two in FIG. 2) semiconductor devices 90 shown in FIG. 6 (hereinafter referred to as the first semiconductor device 90a in order to be distinguished from other semiconductor devices). Semiconductor devices (second and third semiconductor devices) 90b and 90c are provided. Similar to the first semiconductor device 90a, the second semiconductor device 90b includes a semiconductor circuit (not shown) that operates at the first voltage V1b and the second voltage V2, and the third semiconductor device 90c includes the first semiconductor device 90a. Similarly to the above, a semiconductor circuit (not shown) that operates at the first voltage V1c and the second voltage V2 is provided. In the present embodiment, the values of the first voltages required by the internal circuits 41a of the semiconductor devices 90a, 90b, and 90c are different, and these are V1a, V1b, and V1c. The semiconductor circuit 41 of each of the semiconductor devices 90a, 90b, and 90c is connected so as to be able to exchange signals via the input / output circuit 41b. The second semiconductor device 90b and the third semiconductor device 90c include a power supply circuit (not shown) configured similarly to the power supply circuit 91 of the first semiconductor device 90a, and the external terminals P2 of each power supply circuit are connected to each other. Yes. Therefore, a soft start signal SS having a potential corresponding to the charge of the capacitor C2 connected to the external terminal P2 is input to each semiconductor device 90a, 90b, 90c. Therefore, as shown in FIG. 8, the power supply circuit 91 of each of the semiconductor devices 90a, 90b, and 90c raises the second voltage V2 simultaneously with the first voltages V1, V1b, and V1c, and the first voltages V1, V1b, As the voltage V1c increases, the second voltage V2 is increased proportionally.

  The power supply circuit 91 configured as described above increases the second voltage V2 supplied to the input / output circuit 41b in proportion to the increase of the first voltage V1 supplied to the internal circuit 41a. Therefore, the voltage of the input gate that receives a signal from the input / output circuit 41b in the internal circuit is stabilized, and a through current is prevented. In the electronic device 100, the power supply circuit 91 of the plurality of semiconductor devices 90a, 90b, and 90c has the first voltage V1 based on the soft start signal SS having a potential corresponding to the charge of the capacitor C2 connected to the external terminal P2. (, V1b, V1c) is increased. Accordingly, the second voltage V2 generated in each of the semiconductor devices 90a, 90b, and 90c increases simultaneously. For this reason, since the timing at which the second voltage V2 is supplied to the input / output circuit 41b matches between the semiconductor devices 90a, 90b, and 90c, no latch-up occurs in the input / output circuit 41b.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The power supply circuit 91 increases the second voltage V2 supplied to the input / output circuit 41b in proportion to the increase of the first voltage V1 supplied to the internal circuit 41a. Accordingly, since the voltage of the input gate that receives the signal from the input / output circuit 41b in the internal circuit is stabilized, a through current can be prevented. In the electronic device 100, the power supply circuit 91 of the plurality of semiconductor devices 90a, 90b, and 90c has the first voltage V1 based on the soft start signal SS having a potential corresponding to the charge of the capacitor C2 connected to the external terminal P2. (, V1b, V1c) is increased. Accordingly, the second voltage V2 generated in each of the semiconductor devices 90a, 90b, and 90c increases at the same time, and the timing at which the second voltage V2 is supplied to the input / output circuit 41b is coincident between the semiconductor devices 90a, 90b, and 90c. Therefore, the occurrence of latch-up in the input / output circuit 41b can be prevented.

In addition, you may implement each said embodiment in the following aspects.
In the third embodiment, the first voltage V1 is input to the error amplifier 93 of the switch control circuit 82. However, as shown in FIG. 9, a soft start signal SS may be input. Even in this configuration, it is possible to obtain the same effect as in the above embodiment.

  In each of the above embodiments, the step-down power supply circuit that outputs the first voltage V1 obtained by stepping down the input voltage Vin and the second voltage V2 that is substantially the same value as the input voltage Vin is embodied. The voltage V1 and the second voltage V2 may be changed as appropriate.

  For example, the semiconductor integrated circuit device 110 shown in FIG. The semiconductor integrated circuit device 119 includes a power supply circuit 111 that outputs a first voltage V1 obtained by boosting the input voltage Vin. The power supply circuit 111 connects the other end of the coil L2 to which the input voltage Vin is applied to one end to a node between the transistors T1 and T2 of the conversion circuit 112, and boosts the input voltage Vin from the source of the first transistor T1. 1 voltage V1 is output.

  Further, the semiconductor integrated circuit device 120 shown in FIG. The semiconductor integrated circuit device 120 includes a power supply circuit 121 that generates a negative voltage. In the conversion circuit 122 of the power supply circuit 121, the source of the second transistor T2 is connected to the semiconductor circuit 41, and the negative reference voltage Vr31 is input to the non-inverting input terminal of the error amplifier 93. The power supply circuit 91 configured in this way outputs a negative second voltage V2 from the source of the second transistor T2.

  Further, the present invention may be embodied in the semiconductor integrated circuit device 130 shown in FIG. The semiconductor integrated circuit device 130 includes a semiconductor circuit 131 and a power supply circuit 132, and the semiconductor circuit 131 includes an internal circuit 131a that operates with a plurality of first power supplies Va and Vb. The power supply circuit 132 generates a boosted voltage and a negative voltage. The conversion circuit 133 of the power supply circuit 132 includes first and second transistors T1 and T2 connected in series, and third and fourth transistors T3 and T4 connected in series. The first transistor T1 is a P-channel MOS transistor, the source is connected to the semiconductor circuit 131, the drain is connected to the drain of the second transistor T2, and the gate is connected to the PWM control circuit 134. The operation of the PWM control circuit 134 is the same as that of the PWM control circuit 53 described above. The second transistor T2 is an N-channel MOS transistor, the source is connected to the ground GND, the drain is connected to the first transistor T1, and the gate is connected to the PWM control circuit 134. A smoothing capacitor C1 is connected between the source of the first transistor T1 and the ground GND.

  The third transistor T3 is a P-channel MOS transistor, the input voltage Vin is applied to the source, the drain is connected to the fourth transistor T4, and the gate is connected to the PWM control circuit 134. The fourth transistor T4 is an N-channel MOS transistor, the source is connected to the semiconductor circuit 41, the drain is connected to the third transistor T3, and the gate is connected to the PWM control circuit 134. A smoothing capacitor C11 is connected between the source of the fourth transistor T4 and the ground GND.

  A choke coil L1 is connected between a node N1 between the first transistor T1 and the second transistor T2 and a node N2 between the third transistor T3 and the fourth transistor T4.

  The power supply circuit 132 generates voltages Va and Vb as first voltages obtained by converting the input voltage Vin. That is, the power supply circuit 132 supplies the voltage Va obtained by boosting the input voltage Vin by the first and second transistors T1 and T2 from the source of the first transistor T1 to the internal circuit 131a of the semiconductor circuit 131. The negative voltage Vb is supplied from the source of the fourth transistor T4 to the internal circuit 131a of the semiconductor circuit 131 by the transistors T3 and T4.

  By connecting the choke coil L1 as described above, an increase in the occupied area of the power supply circuit 132 can be suppressed as compared with the case where the boost choke coil and the negative voltage choke coil are separately provided.

  In each of the above embodiments, the semiconductor circuit and the power supply circuit are formed on one chip, that is, the semiconductor integrated circuit device is configured by one chip, but this device is configured by a plurality of chips, The chip may be accommodated in one package. Alternatively, the semiconductor circuit and the power supply circuit may be configured by different chips or packages, and these chips or packages may be mounted on a printed circuit board to configure a semiconductor integrated circuit device. When the power supply circuit is formed on the chip, the choke coil L1 and the smoothing capacitor C1 may be elements connected to the outside of the chip. In this case, elements formed on the chip (for example, a plurality of elements surrounded by a solid line in FIG. 1) constitute a control circuit of the DC-DC converter. The control circuit may be constituted by elements other than the first and second transistors T1 and T2.

The technical idea that can be grasped from each of the above embodiments will be described below.
(Appendix 1)
A power supply circuit that generates a plurality of voltages supplied to a load from an input voltage,
A conversion circuit for converting the input voltage into a first DC voltage;
A switch circuit for outputting the input voltage as a second DC voltage;
A switch control circuit that controls the switch circuit based on a comparison result of comparing the first DC voltage with a reference voltage and an input notification signal;
A power supply circuit comprising:
(Appendix 2)
The power supply circuit according to claim 1, wherein a signal corresponding to a comparison result obtained by comparing the first DC voltage with a reference voltage is output.
(Appendix 3)
A power supply circuit that generates a plurality of voltages supplied to a load from an input voltage,
A conversion circuit for converting the input voltage into a first DC voltage;
A switch circuit for outputting the input voltage as a second DC voltage;
A switch control circuit that controls a resistance value of the switch circuit according to the first DC voltage, and controls the second DC voltage in proportion to the first DC voltage;
A power supply circuit comprising:
(Appendix 4)
A power supply circuit that generates a plurality of voltages supplied to a load from an input voltage,
The pulse width modulation based on the difference voltage between the soft-start signal that changes with the time constant determined by the capacitance value of the connected soft-start capacitor and the reference voltage and the low-voltage side voltage and the first DC voltage A conversion circuit for converting an input voltage into a first DC voltage;
A switch circuit for outputting the input voltage as a second DC voltage;
The resistance value of the switch circuit is controlled in accordance with the first DC voltage or the voltage of the soft start signal, and the second DC voltage is proportional to the voltage of the first DC voltage or the soft start signal. A switch control circuit to control;
A power supply circuit comprising:
(Appendix 5)
An electronic apparatus comprising a plurality of power supply circuits according to appendix 1 or appendix 2, wherein the same notification signal is input to each power supply circuit.
(Appendix 6)
An electronic apparatus comprising a plurality of power supply circuits according to appendix 4, wherein the same soft start signal is input to each power supply circuit.
(Appendix 7)
A semiconductor integrated circuit comprising: the power supply circuit according to any one of appendices 1 to 4; and a semiconductor circuit to which the first and second DC voltages generated by the power supply circuit are supplied. Circuit device.
(Appendix 8)
A method for controlling a power supply circuit that generates a plurality of voltages to be supplied to a load from an input voltage,
A conversion circuit for converting the input voltage into a first DC voltage;
A switch circuit for outputting the input voltage as a second DC voltage;
A switch control circuit for controlling on / off of the switch circuit,
The switch control circuit includes:
A control method for a power supply circuit, comprising: controlling the switch circuit based on a comparison result obtained by comparing the first DC voltage with a reference voltage and an input notification signal.
(Appendix 9)
A method for controlling a power supply circuit that generates a plurality of voltages to be supplied to a load from an input voltage,
A conversion circuit for converting the input voltage into a first DC voltage;
A switch circuit for outputting the input voltage as a second DC voltage;
A switch control circuit for controlling on / off of the switch circuit;
With
The switch control circuit controls a resistance value of the switch circuit according to the first DC voltage, and controls the second DC voltage in proportion to the first DC voltage. A method for controlling the power supply circuit.
(Appendix 10)
A method for controlling a power supply circuit that generates a plurality of voltages to be supplied to a load from an input voltage,
A conversion circuit for converting the input voltage into a first DC voltage;
A switch circuit for outputting the input voltage as a second DC voltage;
A switch control circuit for controlling on / off of the switch circuit;
With
The conversion circuit is based on a voltage difference between a soft-start signal that changes with a time constant determined by a capacitance value of a connected soft-start capacitor and a low-potential voltage of a reference voltage and the first DC voltage. Generating the first DC voltage by pulse width modulation;
The switch control circuit controls a resistance value of the switch circuit according to the first DC voltage or the voltage of the soft start signal, and is proportional to the voltage of the first DC voltage or the soft start signal. A control method for a power supply circuit, wherein the second DC voltage is controlled.
(Appendix 11)
The power supply circuit according to any one of appendices 1 to 4, wherein the conversion circuit is a step-down DC-DC converter that steps down the input voltage to generate the first DC voltage. .
(Appendix 12)
5. The power supply circuit according to claim 1, wherein the conversion circuit is a step-up DC-DC converter that boosts the input voltage to generate the first DC voltage. .
(Appendix 13)
The conversion circuit is a negative voltage type DC-DC converter that generates the negative first DC voltage based on the input voltage. Power supply circuit.
(Appendix 14)
The conversion circuit is a DC-DC converter that generates a boosted voltage obtained by boosting the input voltage and a negative voltage generated based on the input voltage as the first DC voltage. 4. The power supply circuit according to claim 1.
(Appendix 15)
Each of the semiconductor integrated circuit devices includes a plurality of semiconductor integrated circuit devices each including the power supply circuit according to appendix 1 or appendix 2 and a semiconductor circuit to which the first and second DC voltages generated by the power supply circuit are supplied. The same notification signal is input to the power supply circuit of the electronic device.
(Appendix 16)
A power supply circuit of each semiconductor integrated circuit device, comprising a plurality of semiconductor integrated circuit devices each including the power supply circuit according to appendix 4 and a semiconductor circuit to which the first and second DC voltages generated by the power supply circuit are supplied The same soft start signal is input to the electronic device.

40 Semiconductor Integrated Circuit Device 41 Semiconductor Circuit 41a Internal Circuit 41b Input / Output Circuit 43 Conversion Circuit 44 Switch Circuit 45 Switch Control Circuit ST Notification Signal SS Soft Start Signal V1 First Voltage V2 Second Voltage Vr11 Reference Voltage

Claims (4)

A power supply circuit that generates a plurality of voltages supplied to a load from an input voltage,
The input is performed by pulse width modulation based on a difference voltage between a soft start signal changing with a time constant determined by a capacitance value of a connected soft start capacitor and a reference voltage and a low-potential side voltage and a first DC voltage. a converting circuit for converting a voltage to the first DC voltage,
A switch circuit for outputting the input voltage as a second DC voltage;
A switch control circuit for the controlling the resistance value of the switching circuit and in proportion to the voltage before Symbol soft start signal controlling said second DC voltage according to the voltage of the previous SL soft start signal,
A power supply circuit comprising: An electronic apparatus comprising a plurality of power supply circuits according to claim 1 , wherein the same soft start signal is input to each power supply circuit. A power supply circuit according to claim 1, the semiconductor integrated circuit device characterized by first and second DC voltage generated by the power supply circuit and a semiconductor circuit is supplied. A method for controlling a power supply circuit that generates a plurality of voltages to be supplied to a load from an input voltage,
A conversion circuit for converting the input voltage into a first DC voltage;
A switch circuit for outputting the input voltage as a second DC voltage;
A switch control circuit for controlling on / off of the switch circuit;
With
The conversion circuit is based on a voltage difference between a soft-start signal that changes with a time constant determined by a capacitance value of a connected soft-start capacitor and a low-potential voltage of a reference voltage and the first DC voltage. Generating the first DC voltage by pulse width modulation;
It said switch control circuit controls the resistance value of the switching circuit in accordance with the voltage before Symbol soft start signal, it has to control the second DC voltage in proportion to the voltage before Symbol soft start signal A method for controlling a power supply circuit.

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