JP5177976B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including an element having a layer containing an organic compound over a flexible substrate and a manufacturing method thereof.

  Semiconductor devices are required to be manufactured at low cost, and in recent years, devices such as transistors, memories, solar cells, and the like using layers containing organic compounds in control circuits, memory circuits, and the like have been actively developed. (For example, patent document 1).

  Various applications using semiconductor devices having elements such as transistors, memories, solar cells and the like using layers containing such organic compounds are expected, and a flexible plastic film pursuing miniaturization and weight reduction. Attempts have been made to use.

  Since the heat resistance of plastic films is low, the maximum temperature of the process must be lowered. For this reason, a semiconductor device using a plastic film is manufactured using a vapor deposition method or a sputtering method using a metal mask.

  In addition, since plastic films have low heat resistance, as a result, it is impossible to form a transistor having better electrical characteristics than when formed on a glass substrate.

Therefore, a technique has been proposed in which a fine element formed on a glass substrate using a photolithography process is peeled off from the substrate and attached to another base material such as a plastic film (see Patent Document 2).
JP 2004-47791 A JP 2003-174153 A

  However, when a semiconductor device is manufactured using a vapor deposition method or a sputtering method using a metal mask, an alignment process for aligning the metal mask is necessary. For this reason, there is a problem that the yield of the product is lowered due to the alignment defect.

  In addition, when a semiconductor device is manufactured using a vapor deposition method or a sputtering method using a metal mask, element design is performed in consideration of misalignment. For this reason, it is difficult to manufacture a transistor, a memory, a solar cell, and the like having a fine structure, and it is difficult to reduce the size, weight, and performance of the semiconductor device.

  Furthermore, when peeling an element having a layer containing an organic compound using a peeling process as shown in Patent Document 2, specifically, a peeling layer 102 is formed on a substrate 101 as shown in FIG. An inorganic insulating layer 103 is formed over the separation layer 102, a first electrode layer 104 is formed over the inorganic insulating layer 103, a layer 105 containing an organic compound is formed over the first electrode layer 104, and organic In the case where the second electrode layer 106 is formed over the layer 105 including a compound and the element 151 including the layer including an organic compound and the layer 157 including the element 151 are separated, the layer 105 including the organic compound and the second layer There is a problem of peeling between the electrode layers 106.

  This is because the adhesive force between the layer 105 containing an organic compound and the second electrode layer 106 is low. Specifically, the layer 105 containing an organic compound functions as an organic semiconductor, and thus is formed using a material having a carrier transporting property. A material having carrier transportability generally does not have a polar substituent such as an imide group, a cyano group, or a hydroxyl group. As a result, the adhesion between the layer 105 containing an organic compound and the second electrode layer 106 becomes very small, and the layer 105 containing the organic compound is peeled off between the second electrode layer 106 in the peeling step. End up.

  As a result, it is difficult to manufacture a semiconductor device in which an element including a layer containing an organic compound is provided over a plastic film with a high yield.

  In view of the above problems, an object of the present invention is to manufacture a semiconductor device in which an element including a layer containing an organic compound is provided over a flexible substrate with high yield.

The gist of the present invention is to form, on a substrate having a release layer, a region having low adhesion when the substrate is viewed from above and a region having high adhesion so as to surround the outer edge thereof. Further, in the cross section of the region having low adhesion, for example, the layer containing the organic compound having no polar substituent such as imide group, cyano group and hydroxyl group is in contact with the inorganic compound layer, and the cross section of the region having high adhesion , A plurality of inorganic compound layers are in contact with each other. The region 503 with high adhesion may surround the outer edge of the region 502 with low adhesion as shown in FIG. 13A as an example. Further, as shown in FIG. 13B as an example, the region 503 with high adhesion may be formed discontinuously so as to surround the outer edge of the region 502 with low adhesion. Further, as shown in FIG. 13C as an example, a rectangular region 503 with high adhesion may be formed so as to correspond to each side of the region 502 with low adhesion. Note that the region with high adhesion can have various shapes such as a rectangular shape, a circular shape, an elliptical shape, and a curved shape.

  In addition, in the present invention, after forming an element formation layer in which a region 502 with low adhesion and a region 503 with high adhesion are formed so as to surround an outer edge of the region 502 on a substrate having a peeling layer 501, the substrate and the element formation are performed. The gist is to separate the layers in a release layer and attach them to a flexible substrate.

  Note that the region having low adhesion is typically a region where the layer containing the organic compound and the second electrode layer are in contact with each other, and the region having high adhesion is typically the second electrode layer and the inorganic compound. The area where the layers touch. In addition, the region having high adhesion is typically a region where the second electrode layer and the conductive layer are in contact with each other.

  Further, according to one embodiment of the present invention, a release layer is formed over a substrate, an inorganic compound layer, a first conductive layer, and a layer containing an organic compound are formed over the release layer, and the layer containing the organic compound and the inorganic compound A second conductive layer in contact with the layer is formed to form an element formation layer, and a first flexible substrate is attached to the second conductive layer, and then the substrate and the element formation layer are separated from each other in the separation layer. A method for manufacturing a semiconductor device is characterized in that separation is performed.

  Another embodiment of the present invention is a semiconductor device including a flexible substrate, an inorganic compound layer, a layer containing an organic compound, a layer containing an organic compound, and a conductive layer in contact with the inorganic compound layer. It is characterized by that.

  Note that the inorganic compound layer is an insulator layer or a conductive layer. A metal layer may be used instead of the inorganic compound layer. The inorganic compound layer may function as an interlayer insulating layer or a connection layer.

  The layer containing an organic compound and the conductive layer in contact with the layer containing an organic compound form part of a memory element or a light-emitting element.

  Moreover, this invention includes the following.

  In one embodiment of the present invention, a release layer is formed over a substrate, an inorganic compound layer, a first conductive layer, and a layer containing an organic compound are formed over the release layer, and the layer containing the organic compound and the inorganic compound layer are formed. A second conductive layer is formed to form an element formation layer, and a first flexible substrate is attached to the second conductive layer, and then the substrate and the element formation layer are separated in a separation layer. This is a method for manufacturing a semiconductor device.

  In one embodiment of the present invention, after forming a release layer over a substrate, an inorganic insulating layer is formed over the release layer, a first electrode layer is formed over the inorganic insulating layer, the first electrode layer, and the inorganic layer A layer containing an organic compound is formed over part of the insulator layer, a second electrode layer in contact with the layer containing the organic compound and the inorganic insulator layer is formed to form an element formation layer, and the second electrode layer A method for manufacturing a semiconductor device is characterized in that after a first flexible substrate is attached to the substrate, the substrate and the element formation layer are separated in a release layer.

  According to one embodiment of the present invention, after forming a release layer over a substrate, an insulating layer is formed over the release layer, a first electrode layer is formed over the insulating layer, and an inorganic portion covering the end portion of the first electrode layer Forming an insulating layer, forming a layer containing an organic compound in a part of the inorganic insulating layer and an exposed portion of the first electrode layer, and a second electrode layer in contact with the layer containing the organic compound and the inorganic insulating layer; Forming a device forming layer, attaching a first flexible substrate over the second electrode layer, and then separating the substrate and the device forming layer in a release layer It is a manufacturing method of an apparatus.

  In one embodiment of the present invention, after forming a release layer over a substrate, an inorganic insulating layer is formed over the release layer, a first electrode layer is formed over the inorganic insulating layer, and over the first electrode layer An organic insulating layer is formed, the organic insulating layer is selectively etched to expose a part of the first electrode layer and a part of the inorganic insulating layer, and a part of the organic insulating layer and the first A layer containing an organic compound is formed on the exposed portion of the electrode layer, a second electrode layer in contact with the layer containing the organic compound and the inorganic insulating layer is formed to form an element forming layer, and the second electrode layer is formed on the second electrode layer A method for manufacturing a semiconductor device is characterized in that after a first flexible substrate is attached, the substrate and the element formation layer are separated in a release layer.

  In one embodiment of the present invention, after a separation layer is formed over a substrate, an insulating layer is formed over the separation layer, a first electrode layer and a conductive layer are formed over the insulating layer, and the first electrode layer and the conductive layer are formed. An organic insulating layer is formed thereon, the organic insulating layer is selectively etched to expose a part of the first electrode layer and a part of the conductive layer, and a part of the organic insulating layer and the first A layer containing an organic compound is formed on the exposed portion of the electrode layer, a second electrode layer in contact with the layer containing the organic compound and the conductive layer is formed to form an element formation layer, and the first electrode layer is formed on the second electrode layer. A method for manufacturing a semiconductor device is characterized in that after bonding a flexible substrate, the insulating layer is peeled off from the substrate at the peeling layer.

  Note that after the element formation layer and the separation layer are separated, a second flexible substrate may be attached to the element formation layer.

  According to one embodiment of the present invention, an inorganic insulating layer formed over a first flexible substrate, a first electrode layer formed over the inorganic insulating layer, a part of the inorganic insulating layer, and A layer containing an organic compound formed on the first electrode layer, a second electrode layer in contact with the layer containing the organic compound and the inorganic insulating layer, and a second possible layer formed on the second electrode layer. A semiconductor device including a flexible substrate.

  According to one embodiment of the present invention, an insulating layer formed over a first flexible substrate, a first electrode layer formed over the insulating layer, and an inorganic insulating layer covering an end portion of the first electrode layer A physical layer, a part of the inorganic insulating layer and a layer containing an organic compound formed on the first electrode layer, a layer containing the organic compound, a second electrode layer in contact with the inorganic insulating layer, a second And a second flexible substrate formed on the electrode layer.

  According to one embodiment of the present invention, an insulating layer formed over a first flexible substrate, a first electrode layer and a conductive layer formed over the insulating layer, and the first electrode layer and the conductive layer An organic insulating layer covering the edge; a layer containing an organic compound formed on the organic insulating layer and the first electrode layer; a second electrode layer in contact with the organic compound layer and the conductive layer; And a second flexible substrate formed on the second electrode layer.

  Note that the first electrode layer, the layer containing an organic compound, and the second electrode layer are part of a memory element, a light-emitting element, a photoelectric conversion element, a solar cell, or a transistor.

  In the present invention, since the adhesion between the inorganic compound layer and the conductive layer is higher than the adhesion between the layer containing the organic compound and the conductive layer, it is difficult to peel off at the interface between the inorganic compound layer and the conductive layer in the peeling step. . For this reason, it is possible to prevent peeling at the interface between the conductive layer and the layer containing an organic compound by forming a region having low adhesion as viewed from above and a region having high adhesion so as to surround the outer edge thereof. . In addition, an element including a layer containing an organic compound formed over a substrate, typically a memory element, a light-emitting element, a photoelectric conversion element, a solar cell, or a layer including a transistor can be peeled with high yield. Furthermore, a semiconductor device in which an element including a layer containing an organic compound is provided over a flexible substrate can be manufactured with high yield.

  In addition, the semiconductor device of the present invention has many regions where the inorganic compound layer and the conductive layer are in contact with the inorganic compound layer and the conductive layer sandwiching the layer containing the organic compound and the organic insulating layer. For this reason, the region where the layer containing an organic compound or the organic insulating layer is exposed to the outside air is reduced, and moisture, oxygen, or the like is less likely to enter these regions, so that deterioration of the semiconductor device can be reduced.

In addition, since a semiconductor device in which an element including a layer containing an organic compound is provided over a flexible substrate can be obtained, a lightweight and thin semiconductor device can be obtained.

Embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

(Embodiment 1)
In this embodiment, a method for peeling an element including an organic compound layer provided between a pair of electrodes and an element formation layer including the element with high yield will be described with reference to FIGS.

  As shown in FIG. 1A, a separation layer 102 is formed over a substrate 101, and an inorganic insulating layer 103 is formed over the separation layer 102. Next, the first electrode layer 104 is formed over the inorganic insulating layer, and the layer 105 containing an organic compound is formed over the first electrode layer 104 and the inorganic insulating layer 103. In FIG. 1A, a region 100 is a region where the inorganic insulating layer 103 is exposed. Note that the layer 105 containing an organic compound is formed in a shape having an opening with a metal mask so that a part of the inorganic insulating layer 103 is exposed from the opening. Alternatively, after the layer 105 containing an organic compound is formed over the surfaces of the first electrode layer 104 and the inorganic insulating layer 103, part of the layer is etched to expose part of the inorganic insulating layer 103.

  As the substrate 101, a glass substrate, a quartz substrate, a metal substrate or a stainless steel substrate with an insulating layer formed on one surface, a heat-resistant plastic substrate that can withstand the processing temperature in this step, or the like is used. Since there is no restriction on the size and shape of the substrate 101 listed above, for example, if a substrate having a side of 1 meter or more and a rectangular shape is used, the productivity is remarkably improved. Can do. This advantage is a great advantage compared to the case of using a circular silicon substrate.

The release layer 102 is formed of tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), sputtering, plasma CVD, coating, printing, or the like. Selected from cobalt (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), and silicon (Si) A single layer is formed by stacking a plurality of layers, each of which is made of the above-described element, an alloy material containing the element as a main component, or a compound material containing the element as a main component. The crystal structure of the layer containing silicon may be any of amorphous, microcrystalline, and polycrystalline. Here, the coating method is a method of forming a film by discharging a solution onto an object to be processed, and includes, for example, a spin coating method and a droplet discharging method. The droplet discharge method is a method of forming a pattern with a predetermined shape by discharging a droplet of a composition containing fine particles from a minute hole.

In the case where the separation layer 102 has a single-layer structure, a layer containing tungsten, molybdenum, or a mixture of tungsten and molybdenum is preferably formed. Alternatively, a layer containing tungsten oxide or oxynitride, a layer containing molybdenum oxide or oxynitride, or a layer containing an oxide or oxynitride of a mixture of tungsten and molybdenum is formed. Note that the mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum.

In the case where the separation layer 102 has a stacked structure, it is preferable that a layer containing tungsten, molybdenum, or a mixture of tungsten and molybdenum be formed as a first layer, and oxidation of tungsten, molybdenum, or a mixture of tungsten and molybdenum be formed as a second layer. A layer comprising a nitride of tungsten, molybdenum, or a mixture of tungsten and molybdenum, oxynitride of tungsten, molybdenum, or a mixture of tungsten and molybdenum, or a nitride oxide of tungsten, molybdenum, or a mixture of tungsten and molybdenum Form.

In the case where a layered structure of a layer containing tungsten and a layer containing an oxide of tungsten is formed as the separation layer 102, a layer containing tungsten is formed, and an insulating layer formed using an oxide is formed thereover. The fact that a layer containing an oxide of tungsten is formed at the interface between the layer containing tungsten and the insulating layer may be utilized. Further, the layer containing tungsten oxide may be formed by performing thermal oxidation treatment, oxygen plasma treatment, treatment with a strong oxidizing power such as ozone water, or the like on the surface of the layer containing tungsten. This also applies to the case where a layer containing tungsten nitride, oxynitride, and nitride oxide is formed. After forming a layer containing tungsten, a silicon nitride layer, a silicon oxynitride layer, or a nitrided oxide layer is formed thereon. A silicon layer may be formed.

The oxide of tungsten is represented by WOx. x is in the range of 2 to 3, and when x is 2 (WO ₂ ), x is 2.5 (W ₂ O ₅ ), x is 2.75 (W ₄ O ₁₁ ), There are cases where x is 3 (WO ₃ ).

Further, according to the above process, the peeling layer 102 is formed so as to be in contact with the substrate 101, but the present invention is not limited to this process. An insulating layer serving as a base may be formed so as to be in contact with the substrate 101, and the peeling layer 102 may be provided so as to be in contact with the insulating layer.

The inorganic insulating layer 103 is formed as a single layer or a multilayer using an inorganic compound by a sputtering method, a plasma CVD method, a coating method, a printing method, or the like. As a typical example of the inorganic compound, silicon oxide or silicon nitride can be given. Typical examples of silicon oxide include silicon oxide, silicon oxynitride, silicon nitride oxide, and the like. Typical examples of silicon nitride include silicon nitride, silicon oxynitride, silicon nitride oxide, and the like.

Furthermore, the inorganic insulating layer 103 may have a stacked structure. For example, the layers may be stacked using an inorganic compound, and typically, silicon oxide, silicon nitride oxide, and silicon oxynitride may be stacked.

The first electrode layer 104 is formed of a single layer or a multilayer structure made of a highly conductive metal, alloy, compound, or the like using a sputtering method, a plasma CVD method, a coating method, a printing method, an electrolytic plating method, an electroless plating method, or the like. Can be used. Typically, a metal, an alloy, a conductive compound, or a mixture thereof having a large work function (specifically, 4.0 eV or more), or a metal, an alloy having a small work function (specifically, 3.8 eV or less). , Conductive compounds, and mixtures thereof can be used.

As typical examples of metals, alloys, and conductive compounds having a high work function (specifically, 4.0 eV or more), indium tin oxide (hereinafter referred to as ITO), silicon-containing indium tin oxide, 2 Examples thereof include indium oxide containing -20 atomic% of zinc oxide (ZnO). Also, titanium (Ti), gold (Au), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu ), Palladium (Pd), or a nitride of a metal material (eg, titanium nitride (TiN), tungsten nitride (WN), molybdenum nitride (MoN)), or the like can also be used.

Typical examples of metals, alloys, and conductive compounds having a small work function (specifically, 3.8 eV or less) include metals belonging to Group 1 or 2 of the periodic table of elements, that is, lithium (Li) or cesium (Cs). Alkali metals such as magnesium (Mg), calcium (Ca), strontium (Sr), aluminum (Al) and alloys containing any of these (MgAg, AlLi), europium (Er), And rare earth metals such as ytterbium (Yb) and alloys containing these.

Note that in the case where an electrode for injecting holes into the layer containing an organic compound, that is, an anode is used for the first electrode layer 104 or the second electrode layer 106, a material having a high work function is preferably used. . Conversely, when using an electrode for injecting electrons into the layer containing an organic compound, that is, a cathode, it is preferable to use a material having a small work function.

  The layer 105 containing an organic compound can be formed by an evaporation method, an electron beam evaporation method, a coating method, or the like. In the case where the layer 105 including an organic compound is formed using the above manufacturing method, the layer 105 including an organic compound is formed in a shape having a region 100 where a part of the inorganic insulating layer 103 is exposed. Further, after a layer 105 containing an organic compound is formed on the surfaces of the inorganic insulating layer 103 and the first electrode layer 104, a region 100 exposing a part of the inorganic insulating layer 103 is formed by selective etching. May be.

Here, after a titanium film with a thickness of 50 to 200 nm is formed by a sputtering method, the first electrode layer 104 is formed by etching into a desired shape by a photolithography method. Next, a layer containing an organic compound formed of NPB is formed by a vapor deposition method.

Next, as illustrated in FIG. 1B, the second electrode layer 106 is formed over the inorganic insulating layer 103 and the layer 105 containing an organic compound. As a result, the region 110 in which the second electrode layer 106 is in contact with the inorganic insulating layer 103 can be formed. In addition, the element 151 including a layer containing an organic compound can be formed using the first electrode layer 104, the layer 105 containing an organic compound, and the second electrode layer 106. The second electrode layer 106 can be formed by an evaporation method, a sputtering method, a CVD method, a printing method, a coating method, or the like. Note that in the case where a material with a high work function is used for the first electrode layer 104, a material with a low work function is preferably used for the second electrode layer 106. In the case where a material with a low work function is used for the first electrode layer 104, a material with a high work function is preferably used for the second electrode layer 106.

Here, aluminum is vapor-deposited by an evaporation method to form the second electrode layer 106.

Note that here, a stack from the inorganic insulating layer 103 to the second electrode layer 106 is referred to as an element formation layer 152.

Here, a more specific structure of the element 151 having a layer containing an organic compound is described below with reference to FIGS. Note that 205 in FIG. 6A corresponds to 105 in FIG. 1, 205 and 201 in FIG. 6B correspond to 105, and 205 and 202 in FIG. 6C correspond to 105 in FIG. 6 corresponds to 105 in FIG. 1D, and 205, 245, and 244 in FIG. 6E correspond to 105 in FIG.

As shown in FIG. 6A, a layer 205 containing an organic compound is formed so that the crystal state, conductivity, and shape are changed by the voltage applied to the first electrode layer 104 and the second electrode layer 106. Thus, the element 151 including a layer containing an organic compound functions as a memory element. Note that the layer 205 including an organic compound may be provided as a single layer or a plurality of layers formed using different organic compounds may be stacked.

The thickness of the layer 205 containing an organic compound is preferably such that the electrical resistance of the memory element changes due to voltage application to the first electrode layer 104 and the second electrode layer 106. A typical film thickness of the layer 105 containing an organic compound is 5 nm to 100 nm, preferably 10 nm to 60 nm, and more preferably 5 to 30 nm.

The layer 205 containing an organic compound can be formed using an organic compound having a hole-transport property or an organic compound having an electron-transport property.

Examples of the hole-transporting organic compound include phthalocyanine (abbreviation: H ₂ Pc), copper phthalocyanine (abbreviation: CuPc), vanadyl phthalocyanine (abbreviation: VOPc), and 4,4 ′, 4 ″ -tris ( N, N-diphenylamino) triphenylamine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenylamino] triphenylamine (abbreviation: MTDATA), 1,3,5-tris [N, N-di (m-tolyl) amino] benzene (abbreviation: m-MTDAB), N, N′-diphenyl-N, N′-bis (3-methylphenyl) -1 , 1′-biphenyl-4,4′-diamine (abbreviation: TPD), 4,4′-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (abbreviation: NPB), 4,4′- Screw {N- [4- (M-Tolyl) amino] phenyl-N-phenylamino} biphenyl (abbreviation: DNTPD), 4,4′-bis [N- (4-biphenylyl) -N-phenylamino] biphenyl (abbreviation: BBPB), 4, Examples thereof include, but are not limited to, 4 ′, 4 ″ -tri (N-carbazolyl) triphenylamine (abbreviation: TCTA). Among the compounds described above, aromatic amine compounds typified by TDATA, MTDATA, m-MTDAB, TPD, DNTPD, BBPB, TCTA, and the like are easy to generate holes and are a group of compounds suitable as organic compounds. . The substances described here are mainly substances having a hole mobility of 10 ⁻⁶ cm ² / Vs or higher.

As the organic compound having an electron transporting property, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [h ] -Quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc. Can be used. In addition, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) A material such as a metal complex having an oxazole-based or thiazole-based ligand such as ₂ ) can also be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used. The substances mentioned here are mainly substances having an electron mobility of 10 ⁻⁶ cm ² / Vs or higher.

  6B, an insulating layer 201 may be formed between the first electrode layer 104 and the layer 205 containing an organic compound in the memory element.

The insulating layer 201 is a layer that injects holes or electrons from the first electrode layer or the second electrode layer into the layer containing an organic compound by a tunnel effect. The insulating layer 201 is formed to have a thickness with which a charge can be injected into the layer 205 containing an organic compound by a tunnel effect at a predetermined voltage. A typical thickness of the insulating layer 201 is an insulating layer having a thickness of 1 nm to 4 nm, preferably 1 nm to 2 nm. Since the insulating layer 201 is extremely thin with a thickness of 1 nm to 4 nm, a tunnel effect is generated in the insulating layer 201, and charge injection into the layer 205 containing an organic compound is increased. Therefore, when the thickness of the insulating layer 201 is greater than 4 nm, the tunnel effect in the insulating layer 201 does not occur, charge injection into the layer 205 containing an organic compound becomes difficult, and the applied voltage at the time of writing to the memory element increases. To do. In addition, the thickness of the insulating layer 201 is as thin as 1 nm to 4 nm, so that throughput is improved.

The insulating layer 201 is formed using a thermally and chemically stable inorganic compound or organic compound.

Representative examples of the inorganic compound forming the insulating layer 201 include Li ₂ O, Na ₂ O, K ₂ O, Rb ₂ O, BeO, MgO, CaO, SrO, BaO, Sc ₂ O ₃ , ZrO ₂ , and HfO _2. RfO ₂ , TaO ₂ , TcO ₂ , MnO ₂ , Fe ₂ O ₃ , CoO, PdO, Ag ₂ O, Al ₂ O ₃ , Ga ₂ O ₃ , Bi ₂ O _3, etc. Things.

Further, representative examples of the inorganic compound that forms the insulating layer 201 include LiF, NaF, KF, CsF, BeF ₂ , MgF ₂ , CaF ₂ , SrF ₂ , BaF ₂ , AlF ₃ , AgF, and MnF _3. Insulating fluorides, LiCl, NaCl, KCl, CsCl, BeCl ₂ , CaCl ₂ , BaCl ₂ , AlCl ₃ , SnCl ₄ , AgCl, ZnCl ₂ , TiCl ₄ , TiCl ₃ , ZrCl ₄ , FeCl ₃ , PdCl ₂ , SbCl ₃ , SbCl ₂ , SrCl ₂ , TlCl ₃ , CuCl, CuCl ₂ , MnCl ₂ , RuCl _{2, and} other insulating chlorides, KBr, CsBr, AgBr, BaBr ₂ , LiBr, etc. bromides having an insulating _{property, NaI, KI, BaI 2,} TlI 3, Ag Include iodides having _{TiI 4, CaI 2, SiI 4} , insulating typified by CsI or the like.

As typical examples of the inorganic compound that forms the insulating layer 201, Li ₂ CO ₃ , K ₂ CO ₃ , Na ₂ CO ₃ , MgCO ₃ , CaCO ₃ , SrCO ₃ , BaCO ₃ , MnCO ₃ , FeCO ₃ , CoCO ₃ , NiCO ₃ , CuCO ₃ , Ag ₂ CO ₃ , ZnCO _3, etc., insulating carbonates, Li ₂ SO ₄ , K ₂ SO ₄ , Na ₂ SO ₄ , MgSO ₄ , CaSO ₄ , SrSO ₄ , BaSO ₄ , Ti ₂ (SO ₄ ) ₃ , Zr (SO ₄ ) ₂ , MnSO ₄ , FeSO ₄ , Fe ₂ (SO ₄ ) ₃ , CoSO ₄ , Co ₂ (SO ₄ ) ₃ , NiSO ₄ , CuSO ₄ , Ag ₂ SO ₄ , ZnSO ₄ , Al ₂ (SO ₄ ) ₃ , In ₂ (SO ₄ ) ₃ , SnSO ₄ , Sn (SO ₄ ) ₂ , Sb ₂ (SO ₄ ) ₃ , Bi ₂ (SO ₄ ) _{3 and the} like, insulating sulfates such as LiNO ₃ , KNO ₃ , NaNO ₃ , Mg (NO ₃ ) ₂ , Ca (NO ₃ ) ₂ , Sr ( NO ₃ ) ₂ , Ba (NO ₃ ) ₂ , Ti (NO ₃ ) ₄ , Zr (NO ₃ ) ₄ , Mn (NO ₃ ) ₂ , Fe (NO ₃ ) ₂ , Fe (NO ₃ ) ₃ , Co (NO ₃ ) ₂ , Ni (NO ₃ ) ₂ , Cu (NO ₃ ) ₂ , AgNO ₃ , Zn (NO ₃ ) ₂ , Al (NO ₃ ) ₃ , In (NO ₃ ) ₃ , Sn (NO ₃ ) _2, etc. Examples thereof include nitrides having insulation properties typified by nitrates having typical insulation properties, AlN, SiN, and the like. In addition, the composition of these inorganic compounds does not need to be a strict integer ratio, and may deviate.

Note that in the case where the insulating layer 201 is formed using an inorganic compound, the thickness of the insulating layer is preferably greater than or equal to 1 nm and less than or equal to 2 nm. When the thickness of the insulating layer is 3 nm or more, the applied voltage at the time of writing increases.

Typical examples of the organic compound that forms the insulating layer 201 include polyimide, acrylic, polyamide, benzocyclobutene, polyester, novolac resin, melamine resin, phenol resin, epoxy resin, silicon resin, furan resin, diallyl phthalate resin, and the like. Organic resin to be used.

As a method for forming the insulating layer 201, an evaporation method, an electron beam evaporation method, a sputtering method, a CVD method, or the like can be used. A spin coating method, a sol-gel method, a printing method, a droplet discharge method, or the like can be used.

  Alternatively, as illustrated in FIG. 6C, a continuous insulating layer 202 having unevenness may be used. However, the thickness of the convex portion of the insulating layer is 1 nm to 4 nm, preferably 2 nm to 4 nm, and the thickness of the concave portion is 0.1 nm to less than 2 nm, preferably 1 nm to less than 2 nm.

  6D, a discontinuous insulating layer 203 dispersed over the first electrode layer 104 may be used. The discontinuous insulating layer 203 may have an island shape, a stripe shape, a mesh shape, or the like.

  Furthermore, insulating particles may be provided instead of the insulating layers 201 to 203. Insulating particles at this time preferably have a particle size of 0.1 nm to 4 nm, more preferably 1 nm to 4 nm.

  Furthermore, the insulating layers 201 to 203 or the insulating particles may be provided between the layer 205 containing an organic compound and the second electrode layer 106.

  An insulating layer having a thickness of 4 nm or less, preferably 2 nm or less is provided between the first electrode layer 104 and the layer 205 containing an organic compound, or between the layer 205 containing an organic compound and the second electrode layer 106. Thus, since a tunnel current flows through the insulating layer, variation in applied voltage and current value at the time of writing to the memory element can be reduced. An insulating layer having a thickness of 4 nm or less, preferably 2 nm or less is provided between the first electrode layer 104 and the layer 205 containing an organic compound or between the layer 205 containing an organic compound and the second electrode layer 106. By providing the charge injection property due to the tunnel effect, the thickness of the layer 205 containing an organic compound can be increased, and a short circuit in an initial state can be prevented. As a result, the reliability of the memory device and the semiconductor device can be improved.

Further, as a structure different from the above structure, an element having a rectifying action is provided between the first electrode layer 104 and the layer 205 containing an organic compound or between the second electrode layer 106 and the layer 205 containing an organic compound. (FIG. 6E). The element having a rectifying action is typically a Schottky diode, a diode having a PN junction, a diode having a PIN junction, or a transistor in which a gate electrode and a drain electrode are connected. Of course, other configurations of diodes may be used. Here, a case where a PN junction diode 211 including semiconductor layers 244 and 245 is provided between the first electrode layer 104 and the layer 205 containing an organic compound is shown. One of the semiconductor layers 244 and 245 is an N-type semiconductor and the other is a P-type semiconductor. By providing an element having a rectifying action in this manner, the selectivity of the memory cell can be improved and the operation margin for reading and writing can be improved.

In addition, by forming the layer 105 containing an organic compound as a layer having a light emitting function, the element 151 having a layer containing an organic compound functions as a light emitting element. In this case, the layer 105 containing an organic compound is formed using a light-emitting organic compound.

Examples of the light-emitting organic compound include 9,10-di (2-naphthyl) anthracene (abbreviation: DNA) and 2-tert-butyl-9,10-di (2-naphthyl) anthracene (abbreviation: t-BuDNA). ), 4,4′-bis (2,2-diphenylvinyl) biphenyl (abbreviation: DPVBi), coumarin 30, coumarin 6, coumarin 545, coumarin 545T, perylene, rubrene, periflanthene, 2,5,8,11-tetra (Tert-butyl) perylene (abbreviation: TBP), 9,10-diphenylanthracene (abbreviation: DPA), 5,12-diphenyltetracene, 4- (dicyanomethylene) -2-methyl-6- [p- (dimethylamino) ) Styryl] -4H-pyran (abbreviation: DCM1), 4- (dicyanomethylene) -2-methyl-6- [2- Loridin-9-yl) ethenyl] -4H-pyran (abbreviation: DCM2), 4- (dicyanomethylene) -2,6-bis [p- (dimethylamino) styryl] -4H-pyran (abbreviation: BisDCM) and the like. Can be mentioned. In addition, bis [2- (4 ′, 6′-difluorophenyl) pyridinato-N, C ² ] (picolinato) iridium (abbreviation: FIrpic), bis {2- [3 ′, 5′-bis (trifluoromethyl) Phenyl] pyridinato-N, C ² } (picolinato) iridium (abbreviation: Ir (CF ₃ ppy) ₂ (pic)), Tris (2-phenylpyridinato-N, C ² ) iridium (abbreviation: Ir (ppy)) _3), (acetylacetonato) bis (2-phenylpyridinato--N, ^{C 2)} iridium (abbreviation: _Ir (ppy) 2 (acac)), (acetylacetonato) bis [2- (2'-thienyl ) pyridinato -N, ^{C 3]} iridium _{(abbreviation: Ir (thp) 2 (acac} )), ( acetylacetonato) bis (2-phenylquinolinato--N, ^{C 2)} Illizi Beam _{(abbreviation: Ir (pq) 2 (acac} )), ( acetylacetonato) bis [2- (2'-benzothienyl) pyridinato -N, ^{C 3]} iridium (abbreviation: _Ir (btp) 2 (acac)) A compound capable of emitting phosphorescence such as can also be used.

  7A corresponds to 105 in FIG. 1, and the multilayers represented by 173, 176, and 177 in FIG. 7B correspond to 105 in FIG. As shown in FIG. 7A, a hole injection layer 171 formed of a hole injection material, a hole transport layer 172 formed of a hole transport material, and light emission on the first electrode layer 104. A light emitting layer 173 formed of a conductive organic compound, an electron transport layer 174 formed of an electron transporting material, an electron injection layer 175 formed of an electron injecting material, and the second electrode layer 106 are stacked. An element 151 functioning as a light-emitting element may be formed.

Here, as the hole transporting material, the hole transporting materials listed in the layer 205 containing an organic compound in FIG. 6A can be used as appropriate.

As the hole-injecting material, a phthalocyanine-based compound is effective, and phthalocyanine (abbreviation: H ₂ Pc), copper phthalocyanine (abbreviation: CuPc), vanadyl phthalocyanine (abbreviation: VOPc), or the like can be used. In addition, there is a material obtained by chemically doping a conductive polymer compound, and polyethylenedioxythiophene (abbreviation: PEDOT) or polyaniline (abbreviation: PAni) doped with polystyrene sulfonic acid (abbreviation: PSS) can also be used. . Also effective are inorganic semiconductor thin films such as molybdenum oxide (MoO _x ), vanadium oxide (VO _x ), nickel oxide (NiO _x ), and ultra-thin films of inorganic insulators such as aluminum oxide (Al ₂ O ₃ ). . In addition, 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA), N, N'-bis (3-methylphenyl) -N, N'-diphenyl-1,1'-biphenyl-4,4'-diamine (Abbreviation: TPD), aromatic amine compounds such as 4,4′-bis {N- [4- (N, N-di-m-tolylamino) phenyl] -N-phenylamino} biphenyl (abbreviation: DNTPD) Can also be used. Furthermore, a substance showing acceptability to these aromatic amine compounds may be added. Specifically, 2,3,5,6-tetrafluoro-7,7,8,8 which is an acceptor for VOPc. - tetracyanoquinodimethane _{(abbreviation:} F 4 -TCNQ) obtained by adding or may be used after addition of MoO _x is an acceptor to NPB.

Here, as the electron-transporting material, the electron-transporting materials listed in the layer 205 containing an organic compound in FIG. 6A can be used as appropriate.

Examples of the electron injection material include alkali metal halides such as LiF and CsF, alkaline earth halides such as CaF ₂ , and alkali metal oxides such as Li ₂ O in addition to the electron transport materials described above. Insulator ultrathin films are often used. Alkali metal complexes such as lithium acetylacetonate (abbreviation: Li (acac)) and 8-quinolinolato-lithium (abbreviation: Liq) are also effective. Furthermore, the material which mixed the electron transport material mentioned above and metals with small work functions, such as Mg, Li, and Cs by co-evaporation etc. can also be used.

In addition, as shown in FIG. 7B, the first electrode layer 104, a hole transport layer 176 formed of an organic compound and an inorganic compound having an electron accepting property with respect to the organic compound, a light emitting layer 173, an organic compound Alternatively, the element 151 functioning as a light-emitting element may be formed by stacking the electron transport layer 177 formed of an inorganic compound having an electron donating property with respect to the organic compound and the second electrode layer 106.

The hole transport layer 176 formed of an organic compound and an inorganic compound having an electron accepting property with respect to the organic compound is formed using the above-described hole transporting organic compound as appropriate as the organic compound. The inorganic compound may be anything as long as it can easily receive electrons from the organic compound, and various metal oxides or metal nitrides can be used. Such transition metal oxides are preferable because they easily exhibit electron accepting properties. Specific examples include titanium oxide, zirconium oxide, vanadium oxide, molybdenum oxide, tungsten oxide, rhenium oxide, ruthenium oxide, and zinc oxide. Among the metal oxides described above, any of the transition metal oxides in Groups 4 to 8 of the periodic table has a high electron accepting property and is a preferred group. Vanadium oxide, molybdenum oxide, tungsten oxide, and rhenium oxide are particularly preferable because they can be vacuum-deposited and are easy to handle.

The electron transport layer 177 formed of an organic compound and an inorganic compound having an electron donating property with respect to the organic compound is formed using the above-described electron transport organic compound as appropriate as the organic compound. The inorganic compound may be anything as long as it easily gives an electron to the organic compound, and various metal oxides or metal nitrides can be used. Alkali metal oxides, alkaline earth metal oxides can be used. Rare earth metal oxides, alkali metal nitrides, alkaline earth metal nitrides, and rare earth metal nitrides are preferred because they easily exhibit electron donating properties. Specific examples include lithium oxide, strontium oxide, barium oxide, erbium oxide, lithium nitride, magnesium nitride, calcium nitride, yttrium nitride, and lanthanum nitride. In particular, lithium oxide, barium oxide, lithium nitride, magnesium nitride, and calcium nitride are preferable because they can be vacuum-deposited and are easy to handle.

An electron transport layer or a hole transport layer formed of an organic compound and an inorganic compound has excellent electron injection / transport characteristics. Therefore, both the first electrode layer 104 and the second electrode layer 106 are almost limited in work function. Various materials can be used without being subjected to this. In addition, the driving voltage can be reduced.

In addition, by forming the layer 105 containing an organic compound as a layer that generates a photocurrent, the element 151 having a layer containing an organic compound functions as a photoelectric conversion element or a solar cell. In this case, the layer 105 containing an organic compound is formed to be a bonding layer of the charge generation layer and the charge reception layer.

  The stack of 161 and 162 in FIG. 8A corresponds to 105 in FIG. 1, the stack of 161 and 163 in FIG. 8B corresponds to 105 in FIG. 1, and 162 in FIG. The stacking of 164 corresponds to 105 in FIG. 1, and the stacking of 163 and 164 in FIG. 8D corresponds to 105 in FIG. As shown in FIG. 8A, the photoelectric conversion element and the solar cell are formed by sequentially providing a first electrode layer 104, a charge generation layer 161, a charge receiving layer 162, and a second electrode layer 106. It is a laminated structure.

  The first electrode layer 104 or the second electrode layer 106 is formed using a light-transmitting conductive material. The charge generation layer 161 and the charge reception layer 162 may be formed by appropriately selecting the organic compound having a hole transport property and the organic compound having an electron transport property, respectively. As the electron-transporting organic compound, a perylene derivative, a naphthalene derivative, a quinone, methyl viologen, fullerene, an organometallic compound containing ruthenium, platinum, titanium, or the like may be used. Here, the charge generation layer 161 is formed using a compound having a hole-transport property, and the charge-accepting layer 162 is formed using a compound having an electron-transport property.

In addition, as illustrated in FIG. 8B, an electron transport layer 163 formed using an organic compound having an electron transporting property and an inorganic compound having an electron donating property with respect to the organic compound is used instead of the charge-accepting layer 162. May be formed. The electron-transport layer 163 is formed by appropriately selecting an electron-transport organic compound shown in FIG. 7B and an electron-transport layer 177 formed of an inorganic compound having an electron-donating property with respect to the organic compound. be able to.

Further, as shown in FIG. 8C, instead of the charge generation layer 161, an electron generation layer 164 formed of an organic compound having a hole transporting property and an inorganic compound having an electron accepting property with respect to the organic compound is provided. May be used. The electron-generating layer 164 is formed by appropriately selecting a compound shown in the hole-transporting layer 176 formed of an electron-transporting organic compound shown in FIG. 7B and an inorganic compound having an electron-accepting property with respect to the organic compound. can do.

Further, as shown in FIG. 8D, an electron generation layer 164 formed of an organic compound having a hole transporting property and an inorganic compound having an electron accepting property with respect to the organic compound is used instead of the charge generation layer 161. Instead of the charge-accepting layer 162, an electron-transporting layer 163 formed of an organic compound having an electron-transporting property and an inorganic compound having an electron-donating property for the organic compound may be formed.

  By forming a layer containing an organic compound so as to become a bonded charge generation layer and charge reception layer, electrons and holes generated in the charge generation layer are converted into electron carriers and hole carriers that become photocurrents. Is possible. As a result, a solar cell and a photoelectric conversion device that can convert light energy into electrical energy can be manufactured.

In addition, when the charge generation layer or the charge reception layer is formed using an organic compound and an inorganic compound, generation efficiency of electrons and holes can be improved. As a result, a photoelectric conversion element and a solar cell with high energy conversion efficiency can be realized.

Alternatively, as the element 151 including a layer containing an organic compound, a thin film transistor (referred to as an organic semiconductor transistor) in which an active region is formed using a layer containing an organic compound may be formed.

Here, the structure of the organic semiconductor transistor will be described with reference to FIGS. FIG. 9A illustrates an example in which a staggered organic semiconductor transistor is applied. A separation layer 102 and an inorganic insulating layer 103 are provided over a substrate 101, and an organic semiconductor transistor is provided as an element 151 including a layer containing an organic compound over the inorganic insulating layer 103. In the organic semiconductor transistor, a gate electrode 1402, an insulating layer 1403 functioning as a gate insulating film, a semiconductor layer 1404 overlapping with the insulating layer 1403 functioning as a gate electrode and a gate insulating film, and a wiring 1405 connected to the semiconductor layer 1404 are formed. Yes. Note that the semiconductor layer 1404 is in contact with the wiring 1405 and the insulating layer 1403 functioning as a gate insulating film.

The gate electrode 1402 can be formed using a material and a method similar to those of the first electrode layer 104. Alternatively, the gate electrode 1402 can be formed by drying and baking using a droplet discharge method. Alternatively, the gate electrode 1402 can be formed by printing a paste containing fine particles over the inorganic insulating layer 103 by a printing method, followed by drying and baking. As typical examples of the fine particles, fine particles mainly containing any of gold, copper, an alloy of gold and silver, an alloy of gold and copper, an alloy of silver and copper, and an alloy of gold, silver, and copper may be used. Further, fine particles mainly containing a conductive oxide such as indium tin oxide (ITO) may be used.

The insulating layer 1403 functioning as a gate insulating film can be formed using a material and a method similar to those of the inorganic insulating layer 103. Alternatively, an organic compound can be used.

Examples of the material of the semiconductor layer 1404 of the organic semiconductor transistor include polycyclic aromatic compounds, conjugated double bond compounds, phthalocyanines, and charge transfer complexes. For example, anthracene, tetracene, pentacene, 6T (hexathiophene), TCNQ (tetracyanoquinodimethane), PTCDA (perylene carboxylic acid anhydride), NTCDA (naphthalene carboxylic acid anhydride) and the like can be used. Examples of the material for the semiconductor layer 1404 of the organic semiconductor transistor include π-conjugated polymers such as organic polymer compounds, carbon nanotubes, polyvinyl pyridine, and phthalocyanine metal complexes. In particular, when a polyacetylene, polyaniline, polypyrrole, polythienylene, polythiophene derivative, poly (3 alkylthiophene), polyparaphenylene derivative or polyparaphenylene vinylene derivative is used, which is a π-conjugated polymer whose skeleton is composed of conjugated double bonds preferable.

  As a method for forming the semiconductor layer 1404 of the organic semiconductor transistor, a method capable of forming a film with a uniform thickness over the substrate may be used. The thickness is 1 nm to 1000 nm, preferably 10 nm to 100 nm. As a specific method, an evaporation method, an electron beam evaporation method, or the like can be used.

As shown in FIG. 9B, a gate electrode 1402, an insulating layer 1403 functioning as a gate insulating film, a wiring 1405, and a semiconductor layer 1404 overlapping with the insulating layer functioning as the gate electrode and the gate insulating film are formed. May be. The wiring 1405 is in contact with the insulating layer functioning as a gate insulating film and the semiconductor layer 1404.

Next, as illustrated in FIG. 1C, the insulating layer 107 is formed over the second electrode layer 106. Next, the substrate 108 is attached to the surface of the insulating layer 107.

  The insulating layer 107 is preferably formed by applying a composition using a coating method, followed by drying and heating. Such an insulating layer 107 is preferably an insulating layer with less surface unevenness because it is provided as a protective layer in a subsequent peeling step. Such an insulating layer can be formed by a coating method. Alternatively, the insulating layer 107 may be formed by polishing a surface by a CMP method after being formed by a thin film formation method such as a CVD method or a sputtering method. The insulating layer 107 formed using the coating method is acrylic resin, polyimide resin, melamine resin, polyester resin, polycarbonate resin, phenol resin, epoxy resin, polyacetal, polyether, polyurethane, polyamide (nylon), furan resin, diallyl Organic compounds such as phthalate resins, inorganic siloxane polymers containing Si-O-Si bonds, or alkylsiloxane polymers among compounds consisting of silicon, oxygen, and hydrogen formed from siloxane polymer materials typified by silica glass , Alkyl silsesquioxane polymer, hydrogenated silsesquioxane polymer, organic siloxax in which hydrogen bonded to silicon represented by hydrogenated alkyl silsesquioxane polymer is substituted with an organic group such as methyl or phenyl It is formed of a polymer. The insulating layer formed by forming the insulating film by the above-described thin film forming method and then polishing the surface by the CMP method is formed of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like.

  As the substrate 108, a flexible substrate is preferably used, and a thin and light substrate is preferable. Typically, PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PES (polyethersulfone), polypropylene, polypropylene sulfide, polycarbonate, polyetherimide, polyphenylene sulfide, polyphenylene oxide, polysulfone, polyphthalamide, etc. A substrate can be used. Also, paper made of a fibrous material, a laminated film of a base film (polyester, polyamide, inorganic vapor deposition film, paper, etc.) and an adhesive organic resin film (acrylic organic resin, epoxy organic resin, etc.) are used. You can also In the case of using the substrate, although not illustrated, an adhesive layer is provided between the insulating layer 107 and the substrate 108, and the insulating layer 107 and the substrate 108 are attached to each other.

  Further, as the substrate 108, a film having a bonding layer on which the object to be processed and a lamination process are performed by thermocompression bonding (a laminate film (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, or the like)) may be used. . Laminate film is an adhesive layer provided on the surface of the base film, or a layer provided on the outermost layer (not an adhesive layer) is melted by heat treatment, and bonded by pressure to the workpiece. It is possible to glue the film. In this case, it is not necessary to separately provide an adhesive layer between the insulating layer 107 and the substrate 108.

  Here, the insulating layer 107 is formed using an epoxy resin by applying a composition by a coating method, followed by drying and baking. Next, a laminate film is thermocompression bonded to the surface of the insulating layer 107, and the substrate 108 is attached to the insulating layer 107.

  Next, as illustrated in FIG. 1D, the separation between the separation layer 102 and the inorganic insulating layer 103 is separated. Here, the inorganic insulating layer 103 and the second electrode layer 106 are in contact with each other. Since the adhesiveness between the inorganic insulating layer 103 and the second electrode layer 106 is high, peeling at the interface between the layer 105 containing an organic compound and the second electrode layer 106 is difficult in the peeling step, and the peeling layer 102 and the inorganic insulating layer The material layer 103 peels off.

Note that in this embodiment, a peeling layer and an insulating layer are formed between the substrate and the element formation layer, a metal oxide film is provided between the peeling layer and the insulating layer, and the metal oxide film is weakened by crystallization. Although the method of physically peeling the element formation layer is used, the present invention is not limited to this. (1) A method in which an amorphous silicon film containing hydrogen is provided between a substrate and an element formation layer, and the substrate is separated by releasing hydrogen gas of the amorphous silicon film by laser light irradiation. A peeling layer and an insulating layer are formed between the element formation layers, a metal oxide film is provided between the peeling layer and the insulating layer, the metal oxide film is weakened by crystallization, and a part of the peeling layer is made into a solution or NF ₃ , A method of physically peeling off a weakened metal oxide film after etching with a halogen fluoride gas such as BrF ₃ or ClF ₃ , and (3) mechanically removing only the substrate on which the element formation layer is formed. A method of removing or removing by etching with a solution or halogen fluoride gas such as NF ₃ , BrF ₃ , ClF ₃ , (4) a metal layer and a metal as a peeling layer between a substrate having high heat resistance and a layer having a transistor An oxide layer is provided and the gold The metal oxide layer is weakened by crystallization, and a part of the metal layer is removed by etching with a solution or halogen fluoride gas such as NF ₃ , BrF ₃ , ClF ₃ , and then the metal oxide layer is physically damaged. For example, a method of peeling off can be used as appropriate.

    Next, as illustrated in FIG. 1E, a substrate 109 is attached to the surface of the inorganic insulating layer 103. As the substrate 109, a substrate similar to the substrate 108 can be used as appropriate. Here, the substrate 109 is attached to the inorganic insulating layer 103 by thermocompression bonding of the laminate film.

  Through the above steps, an element including a layer containing an organic compound can be provided over a flexible substrate with high yield by using a separation step.

(Embodiment 2)
In this embodiment mode, a method for peeling an element formation layer different from that in Embodiment Mode 1 will be described with reference to FIGS. The present embodiment is different from the first embodiment in that an insulating layer (partition wall) that covers the end portion of the first electrode layer is provided.

  As shown in FIG. 2A, as in Embodiment Mode 1, the separation layer 102 is formed over the substrate 101, the inorganic insulating layer 103 is formed over the separation layer 102, and the first insulating layer 103 is formed over the inorganic insulating layer 103. One electrode layer 104 is formed.

  Next, an insulating layer (partition wall) 111 that covers an end portion of the first electrode layer 104 is formed. In this embodiment, the insulating layer 111 is formed using an inorganic insulator such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum nitride by a thin film formation method such as a CVD method or a sputtering method. Here, after the insulating film is formed using a thin film formation method, the insulating film 111 is selectively etched so that a part of the first electrode layer 104 is exposed, whereby the insulating layer 111 is formed.

  Note that the insulating layer 111 is preferably etched so that the cross-sectional shape has an inclination angle of 30 ° to 75 °, preferably 35 ° to 60 °. By having such an inclination angle, it is possible to increase the cross-sectional coverage of a layer containing an organic compound to be formed later, prevent disconnection, and improve the yield.

  Next, a layer 112 containing an organic compound is formed on the exposed surfaces of the insulating layer 111 and the first electrode layer 104 as in Embodiment 1. Note that the layer 112 containing an organic compound is formed so that part of the insulating layer 111 is exposed. That is, the exposed portion 114 of the insulating layer 111 is formed.

  Next, as illustrated in FIG. 2B, the second electrode layer 113 is formed in the layer 112 containing an organic compound and the exposed portion 114 of the insulating layer 111 in the same manner as in Embodiment Mode 1. As a result, a region 115 where the second electrode layer 113 is in contact with the insulating layer 111 can be formed. In the region 115 where the second electrode layer 113 is in contact with the insulating layer 111, the adhesion between the insulating layer 111 and the second electrode layer 113 is high, and thus the layer 112 containing the organic compound and the second electrode layer in the separation step It is difficult to peel off at the interface 113, and peeling can be performed with the peeling layer 102 and the inorganic insulating layer 103.

Note that here, a stack from the inorganic insulating layer 103 to the second electrode layer 113 is referred to as an element formation layer 153.

Hereinafter, the formation of the insulating layer 107 illustrated in FIG. 2C, the bonding of the substrate 108, the peeling step illustrated in FIG. 2D, and the bonding of the substrate 109 illustrated in FIG. Since it is the same as that, it abbreviate | omits here.

  Through the above steps, an element including a layer containing an organic compound can be provided over a flexible substrate with high yield by using a separation step.

(Embodiment 3)
In this embodiment mode, a method for peeling an element formation layer different from that in Embodiment Mode 1 will be described with reference to FIGS. This embodiment is different from Embodiment 2 in that an insulating layer (partition wall) that covers an end portion of the first electrode layer is formed of an organic compound.

  As shown in FIG. 3A, as in Embodiment Mode 1, the separation layer 102 is formed over the substrate 101, the inorganic insulating layer 103 is formed over the separation layer 102, and the first insulating layer 103 is formed over the inorganic insulating layer 103. One electrode layer 104 is formed.

  Next, an insulating layer (partition wall) 121 that covers an end portion of the first electrode layer 104 is formed. In this embodiment mode, the insulating layer 121 is formed using an acrylic resin, polyimide resin, melamine resin, polyester resin, polycarbonate resin, phenol resin, epoxy resin, polyacetal, polyether, polyurethane, polyamide (nylon), furan resin, diallyl phthalate resin. The film is formed by using a non-photosensitive organic compound such as a coating method, a printing method, or a droplet discharge method. Note that the organic compound forming the insulating layer 121 has a polar substituent such as an imide group, a cyano group, or a hydroxyl group. In the case where the insulating layer 121 is formed by a coating method, the composition is discharged, dried and baked to form an insulating film, and then the insulating film is selectively etched using a resist mask formed by a photolithography process. Then, the insulating film 121 is formed by removing the insulating film so as to expose part of the first electrode layer 104 and part of the inorganic insulating layer 103. In the case where the insulating layer 121 is formed using a printing method or a droplet discharge method, the composition is applied so as to cover an end portion of the first electrode layer 104 and to expose a part of the inorganic insulating layer 103. The insulating layer 121 is formed by drying and baking.

  Here, after an insulating film is formed by a coating method, a part of the insulating film is removed by dry etching so that a part of the first electrode layer 104 and a part of the inorganic insulating layer 103 are exposed. Thus, the insulating layer 121 is formed. That is, the insulating layer 121 is formed so as to form the exposed portion 120 of the inorganic insulating layer 103.

  Note that the insulating layer 121 is preferably etched so that the cross-sectional shape thereof has an inclination angle of 30 ° to 75 °, preferably 35 ° to 60 °, like the insulating layer 111 described in Embodiment 2.

  Next, a layer 122 containing an organic compound is formed over the exposed surfaces of the insulating layer 121 and the first electrode layer 104 as in Embodiment 1.

  Next, as illustrated in FIG. 3B, the second electrode layer 123 is formed on the exposed portion 120 of the layer 122 containing an organic compound, the insulating layer 121, and the inorganic insulating layer 103 in the same manner as in Embodiment Mode 1. Form. As a result, a region 124 where the second electrode layer 123 is in contact with the inorganic insulating layer 103 can be formed. In the region 124 where the second electrode layer 123 is in contact with the inorganic insulator layer 103, the adhesiveness between the inorganic insulator layer 103 and the second electrode layer 123 is high. It is difficult to peel off at the interface with the two electrode layers 123, and peeling can be performed with the peeling layer 102 and the inorganic insulating layer 103.

Note that here, a stack from the inorganic insulating layer 103 to the second electrode layer 123 is referred to as an element formation layer 154.

  Hereinafter, the formation of the insulating layer 107 illustrated in FIG. 3C, the bonding of the substrate 108, the peeling step illustrated in FIG. 3D, and the bonding of the substrate 109 illustrated in FIG. Since it is the same as that, it abbreviate | omits here.

  Through the above steps, an element including a layer containing an organic compound can be provided over a flexible substrate with high yield by using a separation step.

(Embodiment 4)
In this embodiment mode, a method for peeling an element formation layer having a structure different from those in Embodiment Modes 1 to 3 will be described with reference to FIGS. The present embodiment is different from Embodiment 3 in that an insulating layer (partition wall) that covers the end portion of the first electrode layer is formed of a photosensitive organic compound.

  As shown in FIG. 4A, the separation layer 102 is formed over the substrate 101 as in Embodiment Mode 1, the inorganic insulating layer 103 is formed over the separation layer 102, and the first insulating layer 103 is formed over the inorganic insulating layer 103. One electrode layer 104 is formed.

  Next, an insulating layer (partition wall) 131 that covers an end portion of the first electrode layer 104 is formed. In this embodiment mode, the insulating layer 131 is formed using a positive or negative photosensitive material such as acrylic, polyimide, styrene, vinyl chloride, diazo resin, azide compound, novolac resin, or polyvinyl cinnamate. A sensitizer may be added to the photosensitive material. The insulating layer 131 is formed by a coating method, a printing method, or a droplet discharge method. In the case where the insulating layer 131 is formed by a coating method, a composition is discharged, dried and baked to form an insulating film, and then a part of the first electrode layer 104 and a part of the inorganic insulating layer 103 The insulating film is exposed and developed so as to expose the film, and a part of the insulating film is removed, followed by baking to form the insulating layer 131. The insulating layer 131 formed by exposing and developing a photosensitive organic compound becomes an insulating layer having a curvature at the upper end. For this reason, it is possible to prevent disconnection of a layer including an organic compound formed later, and to improve yield.

  Here, a composition containing photosensitive acrylic is applied using a coating method, and after drying to form an insulating film formed of acrylic, the insulating film is exposed, developed by a photolithography process, baked after being developed, The insulating layer 131 is formed so that a part of the first electrode layer 104 and a part of the inorganic insulating layer 103 are exposed. That is, the exposed portion 130 of the inorganic insulating layer 103 is formed.

  Note that the insulating layer 131 is preferably etched so that the cross-sectional shape thereof has an inclination angle of 30 ° to 75 °, preferably 35 ° to 60 °, like the insulating layer 111 described in Embodiment 2.

  Next, a layer 132 containing an organic compound is formed on the exposed surfaces of the insulating layer 131 and the first electrode layer 104 as in Embodiment 1.

  Next, as illustrated in FIG. 4B, the second electrode layer 133 is formed on the exposed portion of the layer 132 containing an organic compound, the insulating layer 131, and the inorganic insulating layer 103 as in Embodiment 1. To do. As a result, a region 134 in which the second electrode layer 133 is in contact with the inorganic insulating layer 103 can be formed. In the region 134 where the second electrode layer 133 is in contact with the inorganic insulator layer 103, the adhesion between the inorganic insulator layer 103 and the second electrode layer 133 is high, and thus the layer 132 containing the organic compound and the first layer in the peeling step It is difficult to peel off at the interface between the two electrode layers 133, and the peeling can be performed with the peeling layer 102 and the inorganic insulating layer 103.

Note that here, a stack from the inorganic insulating layer 103 to the second electrode layer 133 is referred to as an element formation layer 155.

  Hereinafter, the formation of the insulating layer 107 illustrated in FIG. 4C, the bonding of the substrate 108, the peeling step illustrated in FIG. 4D, and the bonding of the substrate 109 illustrated in FIG. Since it is the same as that, it abbreviate | omits here.

  Through the above steps, an element including a layer containing an organic compound can be provided over a flexible substrate with high yield by using a separation step.

(Embodiment 5)
In this embodiment, a method for peeling an element formation layer having a structure different from those in Embodiments 1 to 4 will be described with reference to FIGS. This embodiment is different from Embodiment 2 or 3 in that the second electrode layer is in contact with a conductive layer formed in the same manner as the first electrode layer.

  As shown in FIG. 5A, as in Embodiment Mode 1, a separation layer 102 is formed over a substrate 101, an inorganic insulating layer 103 is formed over the separation layer 102, and a conductive layer is formed over the inorganic insulating layer 103. After the layer is formed, the conductive layer is selectively etched using a resist mask formed by a photolithography process, so that the first electrode layer 104 and the conductive layer 181 are formed.

  Next, as in Embodiment 2, an insulating layer 121 that covers an end portion of the first electrode layer 104 is formed. Next, a layer 122 containing an organic compound is formed over the exposed surfaces of the insulating layer 121 and the first electrode layer 104 as in Embodiment 1. Note that the layer 122 containing an organic compound is formed so that part of the conductive layer 181 is exposed. Note that the exposed portion of the conductive layer 181 is denoted by 182.

  Next, as illustrated in FIG. 5B, the second electrode layer 123 is formed in a manner similar to Embodiment 1 so as to be in contact with the layer 122 containing an organic compound and the exposed portion 182 of the first conductive layer 181. To do. As a result, a region 184 where the second electrode layer 123 is in contact with the conductive layer 181 can be formed. In the region 184 where the second electrode layer 123 is in contact with the conductive layer 181, since the adhesion between the conductive layer 181 and the second electrode layer 123 is high, the layer 122 containing the organic compound and the second electrode layer in the peeling step It is difficult to peel off at the interface of 123, and peeling can be performed with the peeling layer 102 and the inorganic insulating layer 103.

Note that here, a stack from the inorganic insulating layer 103 to the second electrode layer 123 is referred to as an element formation layer 156.

  Hereinafter, the formation of the insulating layer 107 illustrated in FIG. 5C, the bonding of the substrate 108, the peeling step illustrated in FIG. 5D, and the bonding of the substrate 109 illustrated in FIG. Since it is the same as that, it abbreviate | omits here.

  Through the above steps, an element including a layer containing an organic compound can be provided over a flexible substrate with high yield by using a separation step.

In this embodiment, a semiconductor device having a memory element as an element having a layer containing an organic compound, typically a memory device will be described.

  FIG. 10A shows a configuration example of the semiconductor device shown in this embodiment. The memory cell array 22 includes a memory cell 300 arranged in a matrix, decoders 23 and 24, a selector 25, and a read / write circuit. 26. Note that the structure of the memory circuit 16 shown here is just an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a write circuit may be provided in the bit line driver circuit.

The decoders 23 and 24, the selector 25, the read / write circuit 26, the interface, and the like can be formed over the substrate using thin film transistors similarly to the memory element. Further, it may be externally attached as an IC chip.

  The memory cell 300 includes a first conductive layer connected to the bit line Bx (1 ≦ x ≦ m), a second conductive layer connected to the word line Wy (1 ≦ y ≦ n), A layer containing an organic compound in contact with the conductive layer. The layer containing an organic compound is provided as a single layer or a stacked layer between the first conductive layer and the second conductive layer.

  An example of a top surface structure and a cross-sectional structure of the memory cell array 22 is shown in FIG. 11A shows a top structure of the memory cell array 22, and the cross-sectional structure between A and B and the cross-sectional structure between C and D in FIG. 11A are shown in FIGS. Corresponding to (C). Note that in FIG. 11A, a region surrounded by a broken line 314 is a region where the first organic insulating layer 306 and the second organic insulating layer 310 are formed. The substrates 332 and 334 and the organic insulator layers 306, 310 and 331 are omitted.

Bit lines 304a to 304g and second electrode layers 312a to 312g are formed in the memory cell array 22, and memory cells are formed at the intersections of the bit lines and the word lines. The conductive element, the layer containing an organic compound, and the second word line (second electrode layer) form a memory element. Hereinafter, the memory cell 300a formed at the intersection of the bit line 304e and the second electrode layer 312d and the memory cell 300b formed at the intersection of the bit line 304d and the second electrode layer 312a will be described (FIG. 11A). reference).

The memory cell 300a includes a memory element 305a (see FIG. 11B). The memory element 305 a includes, over the substrate 334, a first electrode layer 307 connected to the bit line 304 e extending in the first direction, a layer 311 containing an organic compound that covers the first electrode layer 307, And a second electrode layer 312d extending in a second direction perpendicular to the direction. In addition, a region 313 where the insulating layer 303 and the second electrode layer 312d are in contact with each other is formed in the periphery of the memory cell array. Note that the distance between the first electrode layer 307 and the second electrode layer 312d is kept constant in the layer 311 containing an organic compound before data writing. Here, an insulating layer functioning as a protective film may be provided so as to cover the second electrode layer 312d.

In addition, as illustrated in FIG. 11C, the memory cell 300b includes a memory element 305b. The memory element 305b includes a first electrode layer 324 connected to the bit line extending in the first direction, a layer 311 containing an organic compound that covers the first electrode layer 324, and a second layer perpendicular to the first direction. And a second electrode layer 312a extending in the direction. In addition, regions 325 and 326 where the insulating layer 303 and the second electrode layer 312a are in contact with each other are formed in the periphery of the memory cell array.

In addition, an insulating layer 331 for reducing surface unevenness is formed over the second electrode layers 312a to 312g, and a substrate 332 is attached to the insulating layer 331. Here, a plastic film is used as the substrate 332.

  Note that in FIG. 11B, an example in which the layer 311 containing an organic compound is formed over a plurality of first electrode layers is shown; however, the layer 311 containing an organic compound is selectively used only in each memory cell. May be provided. In this case, it can be formed by a vapor deposition method using a metal mask. In addition, the use efficiency of the material can be improved by selectively providing a layer containing an organic compound by discharging and baking an organic compound using a droplet discharge method or the like.

  The materials and formation methods of the bit lines 304a to 304g, the first electrode layers 307 and 324, and the second electrode layers 312a to 312g are the same as those of the first electrode and the second electrode described in Embodiment Mode 1. And any of the formation methods.

  The layer 311 containing an organic compound can be provided using a material and a formation method similar to those of the layer 105 containing an organic compound described in Embodiment Mode 1.

  Further, as the substrates 332 and 334, a flexible substrate, a laminate film, a paper made of a fibrous material, or the like shown in the substrates 108 and 109 shown in Embodiment Mode 1 is used, so that the semiconductor device can be made small and thin. It is possible to reduce the weight.

Next, a method for manufacturing a passive matrix semiconductor device is described with reference to FIGS.

  FIG. 12A is a cross-sectional view of a memory cell array of a passive matrix semiconductor device. Note that peripheral circuits such as a bit line driving circuit, a word line driving circuit, and an interface are omitted.

  As shown in FIG. 12A, a separation layer 302 with a thickness of 30 nm is formed over a substrate 301, and an insulating layer 303 is formed over the separation layer 302. Here, a tungsten layer having a thickness of 30 nm is formed as the separation layer 302 by a sputtering method, and a 100-nm silicon oxide layer, a 50-nm silicon nitride oxide layer, and a 100-nm silicon oxynitride layer are formed by a CVD method as the insulating layer 303. To do. Next, after a 66 nm amorphous silicon film is formed over the insulating layer 303 by a CVD method, heat treatment is performed at 500 ° C. for 1 hour and at 550 ° C. for 4 hours to crystallize the amorphous silicon film. And a metal oxide, here, a tungsten oxide layer is formed at the interface between the peeling layer 302 and the insulating layer 303. Note that formation of a metal oxide at the interface between the separation layer 302 and the insulating layer 303 facilitates separation in a subsequent separation step.

  Next, after removing the crystalline silicon film, bit lines 304e to 304g are formed. Here, a resist mask formed by a photolithography process after a 60 nm titanium layer, a 40 nm titanium nitride layer, a 300 nm aluminum layer, a 60 nm titanium layer, and a 40 nm titanium nitride layer are stacked by a sputtering method is used. The bit lines 304e to 304g are formed by selective etching. Here, the bit lines 304e to 304g are preferably formed using aluminum of a low resistance material.

  Next, a first organic insulator layer 306 is formed over the bit lines 304e to 304g. Here, polyimide is applied, exposed, and developed to expose part of the insulating layer 303 and the bit lines 304e to 304g, and then baked at 300 ° C. for 30 minutes to form the first organic insulating layer 306.

  Next, first electrode layers 307 to 309 are formed on the first organic insulating layer 306 and the exposed portions of the bit lines 304e to 304g. After a titanium film with a thickness of 100 nm is formed by a sputtering method, the first electrode layers 307 to 309 are formed by selective etching using a resist mask formed by a photolithography process. Here, it is preferable to improve the uniformity of the film thickness distribution of the first electrode layer.

  Next, the second organic insulating layer 310 is formed over the first insulating layer and the first electrode layers 307 to 309. Here, the second organic insulating layer 310 is formed using photosensitive polyimide in the same manner as the first organic insulating layer. Even if irregularities are formed on the surfaces of the bit lines 304e to 304g by heating, the organic layers are formed on the first electrode layers 307 to 309 connected to the bit lines 304e to 304g through the second organic insulator layer 310. A layer containing the compound can be formed. Even if the thickness of the layer containing an organic compound is small, it is possible to reduce the involvement of irregularities on the surfaces of the bit lines 304e to 304g, so that a short circuit of the memory element before writing can be prevented.

  Next, a layer 311 containing an organic compound is formed over the first electrode layers 307 to 309 and the second organic insulator layer 310. Here, as the layer 311 containing an organic compound, NPB having a thickness of 10 nm is deposited using a metal mask.

  Next, the second electrode layer 312 d is formed over the layer 311 containing an organic compound and the insulating layer 303.

Here, the second electrode layer 312d is formed so that a region 313 where the insulating layer 303 and the second electrode layer 312d are in contact with each other is formed. In the region where the insulating layer 303 and the second electrode layer 312d are in contact with each other, the adhesiveness between the insulating layer 303 and the second electrode layer 312d is high, so that the separation layer and the insulating layer can be separated with high yield in a subsequent separation step. Is possible.

  Next, after an insulating layer 331 is formed over the second electrode layer 312d, a substrate 332 having an adhesive layer is attached to the insulating layer 331. Here, the insulating layer 331 is formed using an epoxy resin.

Next, after a substrate having an adhesive layer is attached to the surface of the substrate 301, the substrate 332 is bonded to the insulating layer 331 by heating at 120 to 150 degrees to plasticize the adhesive layer of the substrate 332.

  Next, the substrate 301 is placed on the surface of the flat portion, and a roller (not shown) having an adhesive layer is pressure-bonded to the surface of the substrate 332, so that the release layer 302 and the insulating layer 303 are formed as shown in FIG. Peel at the interface.

  Next, as shown in FIG. 12C, a substrate 334 having an adhesive layer on the surface of the insulating layer 303, here a plastic film is attached, and heated to 120 to 150 degrees to plasticize the adhesive layer of the substrate 334. Then, the substrate 334 is bonded to the surface of the insulating layer 303.

  Through the above steps, a passive matrix semiconductor device provided over a plastic film can be manufactured. In this embodiment, any of Embodiment Modes 1 to 5 can be applied.

Next, an operation when data is written to the memory element will be described. here. A case where data is written by electrical action, typically, application of voltage is described (see FIG. 10A). Writing is performed by changing the electrical characteristics of the memory cell. The initial state of the memory cell (the state where no electrical action is applied) is data “0”, and the state where the electrical characteristic is changed is “1”. To do.

When data “1” is written in the memory cell 300, first, the memory cell 300 is selected by the decoders 23 and 24 and the selector 25. Specifically, the decoder 24 applies a predetermined voltage V2 to the word line W3 connected to the memory cell 300. Further, the bit line B 3 connected to the memory cell 300 is connected to the read / write circuit 26 by the decoder 23 and the selector 25. Then, the write voltage V1 is output from the read / write circuit 26 to the bit line B3. Thus, the voltage Vw = V1−V2 is applied between the first electrode layer and the second electrode layer constituting the memory cell 300. By appropriately selecting the voltage Vw, the layer containing the organic compound provided between the electrode layers is changed physically or electrically, and data “1” is written. Specifically, when a read operation voltage is applied, the electrical resistance between the first electrode layer and the second electrode layer in the data “1” state is the first electrode in the data “0” state. The layer containing the organic compound may be physically or electrically changed so as to be significantly smaller than the electric resistance between the layer and the second electrode layer. The voltage Vw is set to 5 to 15 V or -15 to -5 V, for example, appropriately selected from the range of (V1, V2) = (0 V, 5 to 15 V), or (3 to 5 V, -12 to -2 V). it can.

Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. For example, unselected word lines and unselected bit lines may be set in a floating state. In addition, the first electrode layer and the second electrode layer constituting the memory cell need to be correlated so as to satisfy characteristics that can ensure selectivity, such as diode characteristics.

On the other hand, when data “0” is written in the memory cell 300, it is not necessary to apply an electrical action to the memory cell 300. In the circuit operation, for example, as in the case of writing “1”, the memory cell 300 is selected by the decoders 23 and 24 and the selector 25, but the output potential from the read / write circuit 26 to the bit line B3 is selected. The potential of the word line W3 or the potential of the unselected word line is set to the same level as that of the first electrode layer and the second electrode layer constituting the memory cell 300 so that the electrical characteristics of the memory cell 300 are not changed. A voltage (for example, −5 to 5 V) may be applied.

Next, an operation for reading data from the memory element will be described (see FIGS. 10A to 10C). In reading data, the electrical characteristics between the first electrode layer and the second electrode layer constituting the memory cell are different between the memory cell having data “0” and the memory cell having data “1”. Use it. For example, the effective electrical resistance between the first conductive layer and the second conductive layer constituting the memory cell having data “0” (hereinafter simply referred to as the electrical resistance of the memory cell) is R0 at the read voltage. A method of reading data by using the difference in electric resistance when the electric resistance of the memory cell having data “1” is R1 in the read voltage will be described. Note that R1 <R0. As the configuration of the reading / writing circuit, for example, a circuit 26 using a resistance element 46 and a differential amplifier 47 shown in FIG. 10B can be considered. The resistance element 46 has a resistance value Rr, and R1 <Rr <R0. A transistor 48 may be used instead of the resistance element 46, and a clocked inverter 49 may be used instead of the differential amplifier (FIG. 10C). The clocked inverter 49 receives a signal φ or an inverted signal φ that is “High” when reading and “Low” when not reading. Of course, the circuit configuration is not limited to FIGS. 10B and 10C.

When reading data from the memory cell 300, first, the memory cell 300 is selected by the decoders 23 and 24 and the selector 25. Specifically, the decoder 24 applies a predetermined voltage Vy to the word line Wy connected to the memory cell 300. Further, the bit line Bx connected to the memory cell 300 is connected to the terminal P of the read / write circuit 26 by the decoder 23 and the selector 25. As a result, the potential Vp of the terminal P becomes a value determined by resistance division between the resistance element 46 (resistance value Rr) and the memory cell 300 (resistance value R0 or R1). Therefore, when the memory cell 300 has data “0”, Vp0 = Vy + (V0−Vy) × R0 / (R0 + Rr). When the memory cell 300 has data “1”, Vp1 = Vy + (V0−Vy) × R1 / (R1 + Rr). As a result, in FIG. 10B, Vref is selected to be between Vp0 and Vp1, and in FIG. 10C, the changing point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, the output potential Vout is Low / High (or High / Low) according to the data “0” / “1”, and reading can be performed.

For example, the differential amplifier is operated at Vdd = 3V, and Vy = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9, when the memory cell data is “0”, Vp0 = 2.7 V and Vout is “High”, and the memory cell data is “1”. Vp1 = 0.3V and Vout is “Low”. Thus, the memory cell can be read.

According to said method, the state of the electrical resistance of the layer containing an organic compound is read by the voltage value using the difference in resistance value and resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference.

Note that when a voltage is applied to the first electrode layer and the second electrode layer of the memory element, it is preferable to connect a resistor in series with the memory element. The resistance preferably has a resistance value of 5% or less of the memory element. As a result, it is possible to prevent an excessive current from flowing in the short-circuited memory element, and it is possible to prevent element destruction caused by the excessive current.

  Further, a thin film transistor (TFT) may be provided over the inorganic insulating layer 103, and the memory cell 300 or the memory cell array 22 may be provided thereover, or a semiconductor substrate such as Si or an SOI substrate may be used instead of the insulating substrate. Alternatively, a field effect transistor (FET) may be formed on the substrate, and the memory cell 300 or the memory cell array 22 may be provided thereon.

By using the present invention, it is possible to perform peeling at the interface of the peeling layer without peeling at the layer containing the organic compound of the memory element. Therefore, the layer having the memory element formed over the heat resistant substrate can be peeled and provided over the flexible substrate. In addition, since the semiconductor device having the memory element of this embodiment can write (add) data other than at the time of manufacturing the chip and cannot rewrite data, it can prevent forgery due to rewriting. In addition, since the semiconductor device of the present invention includes a memory element having a simple structure in which a layer containing an organic compound is sandwiched between a pair of conductive layers, an inexpensive semiconductor device can be provided.

In this embodiment, a method for manufacturing a semiconductor device having an organic thin film transistor as an element having a layer containing an organic compound will be described.

  As shown in FIG. 14A, a separation layer 302 with a thickness of 30 nm is formed over a substrate 301 as in Example 1, and an insulating layer 303 is formed over the separation layer 302. Next, an amorphous silicon film is formed over the insulating layer 303 and heated to form a crystalline silicon film, and a metal oxide layer is formed at the interface between the separation layer 302 and the insulating layer 303. By forming a metal oxide layer at the interface between the separation layer 302 and the insulating layer 303, separation can be easily performed in a subsequent separation step. Thereafter, the crystalline silicon film is removed. Next, the first electrode layer 351 and the conductive layer 352 are formed over the insulating layer 303. Here, after an aluminum layer is formed by a sputtering method, the aluminum layer is selectively etched using a resist mask formed by a photolithography process, so that the first electrode layer 351 and the conductive layer 352 are formed. Note that the first electrode layer 351 functions as a gate electrode. In addition, the first electrode layer 351 and the conductive layer 352 are not connected.

Next, the insulating layer 353 is formed over the first electrode layer 351 and the conductive layer 352. Here, the insulating layer 353 is formed using polyimide. Note that the insulating layer 353 is formed so as to expose part of the conductive layer 352. In FIG. 14A, reference numeral 355 denotes an exposed insulating layer 353. The insulating layer 353 functions as a gate insulating layer.

Next, a layer 354 containing an organic compound is formed over the overlapping portion of the first electrode layer 351 and the insulating layer 353 by an evaporation method. Here, pentacene is deposited using a metal mask to form the layer 354 containing an organic compound.

Next, as illustrated in FIG. 14B, the second electrode layer 356 is formed over the exposed portion 355 of the conductive layer 352, the insulating layer 353, and the layer 354 containing an organic compound. Here, the second electrode layer 356 is formed using gold by an evaporation method. At this time, a region 358 where the conductive layer 352 and the second electrode layer 356 are in contact with each other is formed. The region 358 in which the conductive layer 352 and the second electrode layer 356 are in contact with each other has high adhesion, so that the separation layer 302 is not separated between the layer 354 containing an organic compound and the second electrode layer 356 in a subsequent separation step. In addition, the insulating layer 303 can be peeled off. The second electrode layer 356 functions as a source electrode (source wiring) and a drain electrode (drain wiring). Next, the protective layer 357 is formed over the insulating layer 353, the layer 354 containing an organic compound, and the second electrode layer 356.

  Hereinafter, the formation of the insulating layer 331 illustrated in FIG. 14C, the bonding of the substrate 332, the peeling step illustrated in FIG. 14D, and the bonding of the substrate 334 illustrated in FIG. Since it is similar, it abbreviate | omits here.

In this embodiment, any of Embodiment Modes 1 to 5 can be applied.

In this example, a method for manufacturing a semiconductor device having an organic solar battery as an element having a layer containing an organic compound will be described.

  As shown in FIG. 15A, a separation layer 302 with a thickness of 30 nm is formed over a substrate 301 as in Example 1, and an insulating layer 303 is formed over the separation layer 302.

Next, an amorphous silicon film is formed over the insulating layer 303 and heated to form a crystalline silicon film, and a metal oxide layer is formed at the interface between the separation layer 302 and the insulating layer 303. Thereafter, the crystalline silicon film is removed. Next, the first electrode layer 341 is formed over the insulating layer 303. Here, after the ITO film is formed by a sputtering method, the ITO film is selectively etched using a resist mask formed by a photolithography process, so that the first electrode layer 341 is formed.

Next, the insulating layer 342 is formed over the first electrode layer 341. Here, the insulating layer 342 is formed using polyimide. Note that the insulating layer 342 is formed so as to expose part of the electrode layer 341. In FIG. 15A, reference numeral 344 denotes an exposed insulating layer 303.

Next, a layer 343 containing an organic compound is formed over part of the first electrode layer 341 and the insulating layer 342 by an evaporation method using a metal mask. Here, the layer 343 including an organic compound is formed by stacking a first layer having a hole-transporting organic compound and an inorganic compound and a second layer having an electron-transporting organic compound. The first layer having a hole-transporting organic compound and an inorganic compound is formed by co-evaporating molybdenum trioxide MoO ₃ and aromatic amine NPB at a molar ratio of 1: 1. The second layer having an electron-transporting organic compound is formed by vapor deposition of fullerene (C60).

Next, as illustrated in FIG. 15B, the second electrode layer 345 is formed over the exposed portion 344 of the insulating layer 303, the insulating layer 342, and the layer 343 containing an organic compound. Here, the second electrode layer 345 is formed using aluminum by an evaporation method. At this time, a region 346 where the insulating layer 303 and the second electrode layer 345 are in contact with each other is formed. The region 346 where the insulating layer 303 and the second electrode layer 345 are in contact with each other has high adhesion, so that the separation layer is not separated between the layer 343 containing an organic compound and the second electrode layer 345 in a subsequent separation step. It can be peeled off by 302 and the insulating layer 303.

  Hereinafter, the formation of the insulating layer 331 illustrated in FIG. 15C, the bonding of the substrate 332, the peeling process illustrated in FIG. 15D, and the bonding of the substrate 334 illustrated in FIG. Since it is the same, it abbreviate | omits here.

In this embodiment, any of Embodiment Modes 1 to 5 can be applied.

The solar cell of the present embodiment is used as a battery, various lighting equipment, lighting equipment, various lighting equipment for home use, outdoor light, street light, unmanned public equipment, personal computer, game machine, navigation system, portable audio equipment, handy AV equipment. It can be provided in cameras such as digital cameras, film cameras, and instant cameras, and watches such as calculators, watches, and wall clocks. When the battery is provided on the wristwatch, the design can be improved by providing it under the dial.

Here, the structure of the semiconductor device of the present invention will be described with reference to FIG. As shown in FIG. 16A, the semiconductor device 20 of the present invention has a function of communicating data without contact, and includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, and other circuits. A control circuit 14 for controlling, an interface circuit 15, a memory circuit 16, a bus 17, and an antenna 18 are included.

Further, as shown in FIG. 16B, the semiconductor device 20 of the present invention has a function of communicating data without contact, and includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, and the like. In addition to the control circuit 14, the interface circuit 15, the storage circuit 16, the bus 17, and the antenna 18, the central processing unit 51 may be included.

Further, as shown in FIG. 16C, the semiconductor device 20 of the present invention has a function of communicating data without contact, and includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, and the like. In addition to the control circuit 14 that controls the circuit, the interface circuit 15, the storage circuit 16, the bus 17, the antenna 18, and the central processing unit 51, a detection unit 52 including a detection element 53 and a detection control circuit 54 may be included.

The semiconductor device of this embodiment includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, a control circuit 14 for controlling other circuits, an interface circuit 15, a storage circuit 16, a bus 17, an antenna 18, a central processing unit. In addition to the unit 51, the detection unit 53 including the detection element 53, the detection control circuit 54, and the like can be configured to form a small and multifunctional semiconductor device.

  The power supply circuit 11 is a circuit that generates various power supplies to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. Further, the power supply circuit 11 may include one or more selected from the solar cells described in Embodiments 1 to 5. The clock generation circuit 12 is a circuit that generates various clock signals to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The data demodulation / modulation circuit 13 has a function of demodulating / modulating data communicated with the reader / writer 19. The control circuit 14 has a function of controlling the memory circuit 16. The antenna 18 has a function of transmitting / receiving electromagnetic waves or radio waves. The reader / writer 19 controls communication and control with the semiconductor device and processing related to the data. The semiconductor device is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and hardware dedicated to cryptographic processing are added.

  The memory circuit 16 includes one or a plurality selected from the memory elements described in Embodiments 1 to 5. Since a memory element having a layer containing an organic compound can simultaneously realize downsizing, thinning, and large capacity, by providing the memory circuit 16 with a memory element having a layer containing an organic compound, A reduction in size and weight can be achieved.

The detection unit 52 can detect temperature, pressure, flow rate, light, magnetism, sound wave, acceleration, humidity, gas component, liquid component, and other characteristics by physical or chemical means. The detection unit 52 includes a detection element 53 that detects a physical quantity or chemical quantity, and a detection control circuit 54 that converts the physical quantity or chemical quantity detected by the detection element 53 into an appropriate signal such as an electrical signal. Yes. The detection element 53 can be formed of a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, a diode, or the like. One or more selected from the photoelectric conversion elements shown in the fifth embodiment. A plurality of detection units 52 may be provided. In this case, a plurality of physical quantities or chemical quantities can be detected simultaneously.

The physical quantity here refers to temperature, pressure, flow rate, light, magnetism, sound wave, acceleration, humidity, etc., and the chemical quantity refers to chemical substances such as gas components such as gas and liquid components such as ions. Point to. In addition, the chemical amount includes organic compounds such as specific biological substances (for example, blood glucose level contained in blood) contained in blood, sweat, urine and the like. In particular, when a chemical amount is to be detected, a specific substance is inevitably selectively detected. Therefore, a substance that selectively reacts with a substance to be detected is provided in the detection element 53 in advance. . For example, when detecting a biological substance, it is preferable that an enzyme, an antibody molecule, a microbial cell, or the like that selectively reacts with the biological substance to be detected by the detection element 53 is fixed to a polymer or the like.

  According to the present invention, a semiconductor device functioning as a wireless chip can be formed. Applications of wireless chips are wide-ranging. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 17A), packaging containers (wrapping paper and Bottle, etc., see FIG. 17C), recording medium (DVD software, video tape, etc., see FIG. 17B), vehicles (bicycle, etc., see FIG. 17D), personal items (bags, glasses, etc.) ), Used for goods such as foods, plants, animals, human bodies, clothing, daily necessities, electronic devices, etc. and goods such as luggage tags (see FIGS. 17E and 17F). be able to. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like.

The semiconductor device 20 of the present invention is fixed to an article by being mounted on a printed board, pasted on a surface, or embedded. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin, and is fixed to each article. Since the semiconductor device 20 of the present invention realizes a small size, a thin shape, and a light weight, the design of the article itself is not impaired even after being fixed to the article. In addition, by providing the semiconductor device 20 of the present invention on bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and if this authentication function is utilized, forgery can be prevented. Can do. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

  In this example, a manufacturing process of a semiconductor device having a light-emitting element will be described.

  As shown in FIG. 18A, a separation layer 302 with a thickness of 30 nm is formed over a substrate 301 as in Example 1, and an insulating layer 303 is formed over the separation layer 302. Next, an amorphous silicon film is formed over the insulating layer 303 and heated to form a crystalline silicon film, and a metal oxide layer is formed at the interface between the separation layer 302 and the insulating layer 303. Thereafter, the crystalline silicon film is removed. Next, the first electrode layer 361 is formed over the insulating layer 303. Here, an ITO film is formed by a sputtering method, and then the ITO film is selectively etched using a resist mask formed by a photolithography process, so that the first electrode layer 361 is formed.

Next, the insulating layer 362 is formed over the first electrode layer 361. Here, the insulating layer 362 is formed using photosensitive polyimide. Note that the insulating layer 362 is formed so as to expose part of the electrode layer 361. In FIG. 18A, reference numeral 364 denotes an exposed region of the insulating layer 303.

Next, a layer 363 containing an organic compound is formed over part of the first electrode layer 361 and the insulating layer 362 by an evaporation method using a metal mask. Here, the layer 363 containing an organic compound is formed using an organic compound having a light-emitting property. The layer 363 containing an organic compound is formed using a red light-emitting organic compound, a blue light-emitting organic compound, and a green light-emitting organic compound, respectively, so that a red light-emitting pixel and a blue light-emitting organic compound are used. Pixels and green light-emitting pixels are formed.

Here, as a layer containing a red light-emitting organic compound, DNTPD is 50 nm, NPB is 10 nm, bis [2,3-bis (4-fluorophenyl) quinoxalinato] iridium (acetylacetonate) (abbreviation: Ir (Fdpq ) ₂ (acac)) is added to 30 nm, Alq ₃ to 60 nm, and LiF to 1 nm.

Further, a layer containing a green light-emitting organic compound is formed by stacking DNTPD at 50 nm, NPB at 10 nm, coumarin 545T (C545T) -added Alq ₃ at 40 nm, Alq ₃ at 60 nm, and LiF at 1 nm. .

In addition, as a layer containing a blue light-emitting organic compound, DNTPD is 50 nm, NPB is 10 nm, 2,5,8,11-tetra (tert-butyl) perylene (abbreviation: TBP) is added, and 9- [ 4- (N-carbazolyl)] phenyl-10-phenylanthracene (abbreviation: CzPA) is formed by stacking 30 nm, Alq ₃ by 60 nm, and LiF by 1 nm.

Further, a white light-emitting pixel may be formed using a white light-emitting organic compound. By providing white light-emitting pixels, power consumption can be reduced.

Next, as illustrated in FIG. 18B, a second electrode layer 365 is formed over the layer 363 containing an organic compound, the insulating layer 362, and the insulating layer 303. Here, an Al film having a thickness of 200 nm is formed by an evaporation method. At this time, a region 366 in contact with the insulating layer 303 formed of an inorganic compound and the second electrode layer 365 is formed. The region 366 where the insulating layer 303 and the second electrode layer 365 are in contact with each other has high adhesion, so that the separation layer 302 is not separated between the layer 363 containing an organic compound and the second electrode layer 365 in a subsequent separation step. In addition, the insulating layer 303 can be peeled off.

  Next, as illustrated in FIG. 18C, a protective layer 367 is formed over the second electrode layer 365. The protective layer is for preventing moisture, oxygen, and the like from entering the light-emitting element and the insulating layer 362. The protective layer 367 is formed using a thin film formation method such as a plasma CVD method or a sputtering method, and contains silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxynitride, or aluminum oxide, diamond-like carbon (DLC), and nitrogen. It is preferable to use carbon (CN) or another insulating material.

  Hereinafter, the formation of the insulating layer 331 illustrated in FIG. 18C, the bonding of the substrate 332, the peeling step illustrated in FIG. 18D, and the bonding of the substrate 334 illustrated in FIG. Since it is similar, it abbreviate | omits here.

  Through the above steps, a semiconductor device having a passive matrix light-emitting element provided over a plastic film can be manufactured.

In this embodiment, any of Embodiment Modes 1 to 5 can be applied.

  Next, an example in which an FPC and a driving IC for driving are mounted on the EL display panel shown in Embodiment 5 will be described. Here, a chip-like driving circuit formed of TFTs is referred to as a driving IC.

The structure shown in FIG. 19 is an example in which a COG method suitable for a small size (for example, a diagonal of 1.5 inches) with a narrow frame is adopted.

In FIG. 19, a driving IC 1011 is mounted on a substrate 1010, and an FPC 1019 is mounted on a terminal portion 1018 arranged at the tip of the driving IC. A plurality of driver ICs 1011 to be mounted are preferably formed on a rectangular substrate having a side of 300 mm to 1000 mm from the viewpoint of improving productivity. That is, a plurality of circuit patterns having a drive circuit portion and an input / output terminal as one unit are formed on a substrate, and finally, the drive ICs may be taken out by dividing them. The length of the long side of the driving IC may be formed in a rectangular shape having a long side of 15 to 80 mm and a short side of 1 to 6 mm in consideration of the length of one side of the pixel portion and the pixel pitch.

The advantage of the external dimensions of the driving IC over the IC chip is the length of the long side. When a driving IC formed with a long side of 15 to 80 mm is used, the number of chips to be mounted is smaller than when an IC chip is used. This can be reduced and the manufacturing yield can be improved. In addition, when a driving IC is formed over a glass substrate, the shape of the substrate used as a base is not limited, and thus productivity is hardly impaired. This is a great advantage compared with the case where the IC chip is taken out from the circular silicon wafer.

Alternatively, a TAB method may be employed. In that case, a plurality of tapes may be attached and a driving IC may be mounted on the tapes. As in the case of the COG method, a single drive IC may be mounted on a single tape. In this case, a metal piece or the like for fixing the drive IC may be attached together due to strength problems. .

In addition, a connection region 1017 provided between the pixel portion 1012 and the driver IC 1011 is provided in order to contact the second electrode layer of the light-emitting element with a lower wiring.

Further, the sealing substrate 1014 is fixed to the substrate 1010 with a sealing material 1015 surrounding the pixel portion 1012 and a filling material surrounded by the sealing material.

Note that an IC chip formed of a Si chip may be used instead of the driving IC.

  As described above, the present invention is implemented, that is, various electronic devices can be completed using the structure of the light-emitting element of Example 5.

Next, one mode of an electronic device in which the semiconductor device of the present invention is mounted will be described with reference to the drawings. The electronic device illustrated here is a mobile phone, which includes housings 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705 (see FIG. 20). The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted on the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 2703, and the semiconductor device 2710 of the present invention can be used as one of them. The plurality of semiconductor devices mounted on the printed wiring board 2703 have any one function of a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

The panel 2701 is connected to the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel region 2709 included in the panel 2701 is arranged so as to be visible from an opening window provided in the housing 2700. A semiconductor device as described in Embodiments 5 and 6 can be used for the panel 2701.

As described above, the semiconductor device of the present invention is characterized in that it is small, thin, and lightweight, and the limited space inside the housings 2700 and 2706 of the electronic device can be effectively used due to the above characteristics. .

Note that the housings 2700 and 2706 are examples of the appearance of a mobile phone, and the electronic device according to the present embodiment can be transformed into various modes depending on the function and application.

FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. FIG. 11 is a cross-sectional view illustrating a structure of a memory element that can be applied to the present invention. FIG. 10 is a cross-sectional view illustrating a structure of a light-emitting element applicable to the present invention. It is sectional drawing explaining the structure of the photoelectric conversion element applicable to this invention. It is sectional drawing explaining the structure of the organic thin-film transistor applicable to this invention. It is a figure explaining the semiconductor device of the present invention. 4A and 4B are a top view and a cross-sectional view illustrating a semiconductor device of the invention. FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. It is a top view illustrating a semiconductor device of the present invention. FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. It is a figure explaining the semiconductor device of the present invention. It is a figure explaining the usage pattern of the semiconductor device of this invention. FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. It is a top view illustrating a semiconductor device of the present invention. It is an expanded view explaining the semiconductor device of this invention. It is sectional drawing explaining the conventional semiconductor device.

Claims (5)

Forming a release layer on the substrate,
Forming an inorganic insulator layer on the release layer;
Forming a first electrode layer on the inorganic insulator layer;
Forming a layer containing an organic compound on part of the first electrode layer and the inorganic insulating layer;
Forming a layer containing the organic compound and a second electrode layer in contact with the inorganic insulating layer;
A first flexible substrate is bonded onto the second electrode layer,
Separating the substrate and the element formation layer composed of the inorganic insulating layer, the first electrode layer, the layer containing the organic compound, and the second electrode layer in the release layer, A method for manufacturing a semiconductor device. Forming a release layer on the substrate,
Forming an inorganic insulator layer on the release layer;
Forming a first electrode layer on the inorganic insulator layer;
Forming an organic insulator layer on the first electrode layer;
Selectively etching the organic insulator layer to expose a portion of the first electrode layer and a portion of the inorganic insulator layer;
Forming a layer containing an organic compound in a part of the organic insulator layer and an exposed portion of the first electrode layer;
Forming a layer containing the organic compound and a second electrode layer in contact with the inorganic insulating layer;
A first flexible substrate is bonded onto the second electrode layer,
In the peeling layer, the substrate, the inorganic insulating layer, the first electrode layer, the organic insulating layer, the layer containing the organic compound, and the element forming layer including the second electrode layer A method for manufacturing a semiconductor device, wherein the semiconductor device is separated. Forming a release layer on the substrate,
Forming an inorganic insulator layer on the release layer;
Forming a first electrode layer and a conductive layer on the inorganic insulator layer;
Forming an organic insulator layer on the first electrode layer and the conductive layer;
Selectively etching the organic insulator layer to expose a portion of the first electrode layer and a portion of the conductive layer;
Forming a layer containing an organic compound in a part of the organic insulator layer and an exposed portion of the first electrode layer;
Forming a layer containing the organic compound and a second electrode layer in contact with the conductive layer;
A first flexible substrate is bonded onto the second electrode layer,
An element forming layer including the substrate, the inorganic insulating layer, the first electrode layer, the conductive layer, the organic insulating layer, the layer containing the organic compound, and the second electrode layer; A method for manufacturing a semiconductor device, wherein separation is performed in the release layer. In any one of Claims 1 thru | or 3 ,
The first electrode layer, the layer containing an organic compound, and the second electrode layer are part of a memory element, a light-emitting element, a photoelectric conversion element, a solar cell, or a transistor. A method for manufacturing a semiconductor device. In any one of Claims 1 thru | or 4 ,
After separating the substrate and the element formation layer, a method for manufacturing a semiconductor device, wherein a second flexible substrate is bonded to the element formation layer.

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