JP5177856B2 - Clock transfer circuit - Google Patents

Description

  The present invention relates to a clock transfer circuit, and more particularly to a clock transfer circuit that outputs data input in synchronization with a clock in synchronization with a clock having a different period in digital signal transmission.

  FIG. 8 shows a conventional clock transfer circuit of this type (see, for example, Patent Document 1). By monitoring a frame pulse signal synchronized with each of writing and reading, a configuration for avoiding writing and reading by the same memory is adopted.

  In FIG. 8, a two-port RAM section 50 having a plurality of address areas corresponding to frames and capable of reading and writing independently, and input data 200 to the two-port RAM section 50 based on a write frame signal 202 and a write clock 205. A write address generation unit 51 for generating an address for writing, a read address generation unit 52 for generating an address for reading the output data 201 from the two-port RAM unit 50 based on the read frame signal 206 and the read clock 210, A read control unit 53 that arbitrates a read operation by a read control signal 209 is provided.

  The write address generation unit 51 generates an upper write address 204 indicating the address area of the 2-port RAM unit 50 and a lower write address 204 indicating an address corresponding to the time slot of the input data 200. The input data 200 can be written to the address corresponding to the lower write address 203 in the address area corresponding to 50 upper write addresses 204.

  The read control unit 53 monitors the upper write address 204, and for each read control signal 209 input from the read address generation unit 52 immediately before the read frame signal 206, the upper read address 208 that does not overlap with the upper write address 204. Can be generated.

  Read address generator 52 generates lower read address 207 indicating the address corresponding to the time slot of output data 201 and read control signal 209, and lower read address in the frame area corresponding to upper read address 208 of the 2-port RAM unit. The output data 201 can be read from the address corresponding to 207. In this way, changes in the phases of the write clock 205 and the read clock 210 can be absorbed.

  Further, the write address counter and the read address counter are reset at power-on, for example, the write address is formed based on the count value of the write address counter, and the read address is formed based on the count value of the read address counter. A clock transfer circuit is known in which a write address and a read address are sufficiently separated from each other by supplying to a dual port memory so that a malfunction such as a read overtaking a write is avoided (see, for example, Patent Document 2). ).

  Furthermore, when data synchronized with a certain basic clock is converted into data synchronized with a different clock, by adopting a Gray code or the like, the memory counter always has 1 bit constituting the counter according to the conversion of the count value. There has been disclosed a data conversion technique in which malfunction is prevented by using a counter that changes only without being affected by variations in hardware propagation delay time (see, for example, Patent Document 3).

JP 2004-140619 (4th page, FIG. 1) JP-A-8-274585 (pages 4-6, FIG. 1) JP 10-242949 (2nd page, Fig. 2)

  However, in the clock transfer circuit described in Patent Document 1 described above, even if the phases of the write clock 205 and the read clock 210 change, the write address for avoiding the conflict between the write and the read Since the distance of the read address is secured depending on the upper address given from the outside, there is a first problem that the intended purpose may not be achieved if there is a change in the external situation.

  Further, the second problem is that since the read frame pulse is input from the outside in synchronization with the read clock, the read frame pulse is externally frequency-synchronized with the input clock (the phase may not be synchronized). There is a second problem that a circuit to be generated is required.

  In the clock transfer circuit described in Patent Document 2, the write address counter and the read address counter are initialized only at the time of power-on, and thereafter, the count value of the write address counter and the read address counter Since the write address and the read address are generated on the basis of the count value, there is a problem that even if there is a change in input data or circuit elements, it is not possible to cope with it, which may cause a malfunction.

  Further, in the frequency conversion device described in Patent Document 3, in the case of a binary counter, a clock may be input simultaneously with a change in count value due to variations in gate delay time, and the change is 2 bits or more. In order to prevent a count value that deviates from the count-up order from being taken in, a gray code or the like is employed, and the writing and reading are not adjusted.

  Therefore, an object of the present invention is to avoid the address conflict between writing and reading in the 2-port RAM section regardless of whether the input data is a frame configuration or a packet configuration, so that even if there is a change in input data or circuit elements, It is an object of the present invention to provide a clock transfer circuit capable of transfer.

The clock phase changing circuit of the present invention is a clock changing circuit for outputting data inputted in synchronization with a clock in synchronization with a clock having a different period, a two-port RAM capable of writing and reading independently, A write address generation unit for sequentially generating a write address to the 2-port RAM for data input in synchronization with the input clock, and a read address generation for sequentially generating a read address for the 2-port RAM in synchronization with the read clock. has a part, constantly monitors the approach of the write address and the read address, the address initialization detection unit for initializing such a write address and a read address when a predetermined difference is a difference exceeding a predetermined difference It is characterized by that.

  Specifically, the address initialization detection unit (7 in FIG. 1) includes a gray code encoding unit (4 in FIG. 1) that converts the write address into a gray code, and the gray code encoded write address. A gray code decoding unit (5 in FIG. 1) that retimes with a read clock and converts it to a binary code, a binary coded write address value, and a read address value with the read address retimed with a read clock When the difference is within a predetermined value, the write address generation unit and the address comparison unit (6 in FIG. 1) for outputting an address initialization signal to the read address generation unit.

The address initialization is performed so that the value of the write address and the value of the read address of the 2-port RAM are different from each other by half the depth of the address of the 2-port RAM.

  In addition, the clock transfer circuit of the present invention generates a write clock PLL (9 in FIG. 7) that establishes synchronization by a reference clock and generates a write clock, and generates the read clock by establishing synchronization by a reference clock. A PLL that monitors the read clock PLL (10 in FIG. 7) and outputs an address initialization signal to the write address generator (2 in FIG. 1) and the read address generator (3 in FIG. 1) when synchronization is simultaneously established. You may make it add a status detection part (11 of FIG. 7) to the said structure.

  The clock transfer circuit according to the present invention constantly monitors the approach between the write address value and the read address value, and initializes the write address and the read address so as to be at an appropriate distance when a predetermined distance is reached. Regardless of the configuration of the input data, the address is initialized only by the change in the phase difference between the write clock and the read clock, and the conflict between the write address and the read address is automatically prevented. Even if it exists, it has the effect that the state where a bit error continues to generate | occur | produce in data can be prevented.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

[Description of configuration]
FIG. 1 is a block diagram showing a configuration of a clock transfer circuit according to a first embodiment of the present invention. In FIG. 1, the clock transfer circuit is composed of a 2-port RAM 1, a write address generation unit 2, a read address generation unit 3, a Gray code encoding unit 4, a Gray code decoding unit 5, and an address comparison unit 6.

  This clock transfer circuit reads the input data 100 from the write clock 104 by writing the input data 100 to the 2-port RAM 1 and reading the output data 101 from the 2-port RAM 1 in synchronization with the read clock 105. Transfer to 105 clocks.

  The two-port RAM 1 can perform writing and reading at the same time, but there must be no malfunction such as reading overtaking writing. To that end, the write address 102 and the read address 103 need to be kept at an appropriate distance. In this embodiment, the address initialization detection unit 7 takes charge of this, and when the difference between the write address 102 and the read address 103 is within ± 1, the write address generation unit 2 and the read address generation unit 3 are initialized.

  The 2-port RAM 1 can perform writing and reading independently of each other. Writing to the 2-port RAM 1 is performed by sequentially writing the input data 100 in response to the write clock 104 to the address specified by the write address 102 output from the write address generator 2. Reading is performed by sequentially reading the output data 101 in response to the read clock 105 from the address specified by the read address 103 output from the read address generator 3.

  The write address generation unit 2 is initialized to ‘0’ (decimal) by the system initialization and the address initialization signal 106 output from the address comparison unit 6. When the initialization control is not received, a write address 102 incremented by +1 by the write clock 104 is generated and output.

  Read address generator 3 is initialized to half the depth of 2-port RAM 1 ('4' if the depth is 8 bits) at system startup and by address initialization signal 106 output from address comparator 6. The When the initialization control is not received, a read address 103 incremented by +1 by the read clock 105 is generated and output.

  The gray code encoding unit 4 encodes the write address 102 into a gray code, and outputs a write address (after gray code encoding) 107. In this case, since the write address 102 is increment data, the adjacent data of the write address (after Gray code encoding) 107 has a feature that only one bit changes.

The gray code decoding unit 5 re-times the write address (after gray code encoding) 107 once with the read clock 105 to decode the gray code, and outputs the write address (after gray code decoding) 108. When retiming with the read clock 105, the write clock 104 and the read 105 clock approach each other due to fluctuations in the transmission path, etc., and the write address (gray) one clock before the write address (after gray code encoding) 107 to be read It is possible to read 107 after code encoding.

The address comparison unit 6 compares the write address (after gray code decoding) 108 with a signal obtained by retiming the read address 103 by 1 bit (this signal 103 ′ is an internal signal of the address comparison unit 6), and the values match or The initialization signal 106 is asserted when ± 1. Thereby, the conflict between the write address 102 and the read address 103 can be avoided.
[Description of operation]
Next, the operation of the clock transfer circuit will be described with reference to FIGS.

FIG. 2 is a timing chart showing the operation of the Gray code decoding unit 5 when the depth of the 2-port RAM 1 is 8 bits. The gray code decoding unit 5 performs retiming on the read clock 105 after the write address (after gray code encoding) 107 inputted in synchronization with the write clock 104, and then decodes the gray code to write address 108 (after Gray code decoding) is obtained. At this time, due to the feature of the Gray code that adjacent values always change by only 1 bit , even if the phase of the read clock 105 is not fixed with respect to the write clock 104, a value to be retimed or Retime previous value.

  In FIG. 2 to FIG. 6, the switching time of the write address (after gray code encoding) 107 and the rising time of the read clock 105 are deviated visually. The timing is approached and retiming is performed at the timing. Therefore, the value of the write address 107 (after Gray code encoding) to be retimed cannot be determined as described above.

  3 to 6 are timing charts divided into four cases according to the slow relationship between the write clock 104 and the read clock 105 and the value to be timed.

  FIG. 3 is a timing chart when the write clock 104 is faster than the read clock 105 due to fluctuations in the transmission path or the like, and when the previous value is read by the Gray code decoding unit 5. Until the time T1, the difference between the value of the write address (after gray code decoding) 108 and the value of the read address (after retiming) 103 'exceeds ± 1. However, at time T1, the value of the write address (after gray code decoding) 108 is “010”, the value of the read address (after retiming) 103 is “011”, and the difference is within ± 1. Therefore, the address initialization signal 106 is asserted at time T2.

  When the address initialization signal 106 is asserted, the write address generation unit 2 is asynchronously initialized and the value of the write address 102 becomes '000', and the read address generation unit 3 is similarly asynchronously initialized and read. The value of the address 103 is “100”. From time T2 to time T3 when one cycle of the read clock 105 elapses, the value of the previous cycle is taken over, so the value of the write address (after Gray code decoding) 108 and the read address (after retiming) 103 ′ The difference between the values is within ± 1.

  However, at time T3, an initialization effect appears, and the value of the write address (after Gray code decoding) 108 is ‘000’, and the value of the read address (after retiming) 103 is ‘100’. Thus, since the difference exceeds ± 1, the address initialization signal 106 is disabled at time T4, and the operation can be continued for the time being without initialization. The output data 101 until initialization is discarded, and the output data 101 after time T2 is validated.

  FIG. 4 is a timing chart when the original value is read by the gray code decoding unit 5 in the case where the write clock 104 is faster than the read 105 clock due to fluctuations in the transmission path. Until the time T1, the difference between the value of the write address (after gray code decoding) 108 and the value of the read address (after retiming) 103 'exceeds ± 1. However, at time T1, the value of the write address (after Gray code encoding) 103 'is' 000 ', the value of the read address (after retiming) 103' is '001', and the difference is within ± 1. Therefore, the address initialization signal 106 is asserted at time T2.

  When the address initialization signal 106 is asserted, the write address generation unit 2 is asynchronously initialized and the value of the write address 102 becomes “000”, and the read address generation unit 3 is similarly asynchronously initialized and read. The value of the address 103 is “100”. From time T2 to time T3 when one cycle of the read clock 105 elapses, the value of the previous cycle is taken over, so the value of the write address (after Gray code decoding) 108 and the read address (after retiming) 103 ′ The difference between the values is within ± 1.

  However, at time T3, an initialization effect appears, and the value of the write address (after Gray code decoding) 108 is ‘000’, and the value of the read address (after retiming) 103 is ‘100’. Thus, since the difference exceeds ± 1, the address initialization signal 106 is disabled at time T4, and the operation can be continued for the time being without initialization. The output data 101 until initialization is discarded, and the output data 101 after time T2 is validated.

  FIG. 5 is a timing chart in the case where the write clock 104 becomes slower than the read clock 105 due to fluctuations in the transmission path and the like, and the previous value is read by the Gray code decoding unit 5. Until the time T1, the difference between the value of the write address (after gray code decoding) 108 and the value of the read address (after retiming) 103 'exceeds ± 1. However, at time T1, the value of the write address (after Gray code encoding) 108 is “111”, the value of the read address (after retiming) 103 is “110”, and the difference between the values is within ± 1. Therefore, the address initialization signal 106 is asserted at time T2.

  When the address initialization signal 106 is asserted, the write address generation unit 2 is asynchronously initialized and the value of the write address 102 becomes “000”, and the read address generation unit 3 is similarly asynchronously initialized and read. The value of the address 103 is “100”. From time T2 to time T3 when one cycle of the read clock 105 elapses, the value of the previous cycle is taken over, so the value of the write address (after Gray code decoding) 108 and the read address (after retiming) 103 ′ The difference between the values is within ± 1.

  However, at time T3, the value of the write address (after Gray code decoding) 108 is' 001 ', the value of the read address (after retiming) 103' is' 100 ', and the difference exceeds ± 1, so the address The initialization signal 106 is disabled at time T4 and can continue to operate for the time being without initialization. The output data 101 until initialization is discarded, and the output data 101 after time T2 is validated.

  FIG. 6 is a timing chart when the original value is read by the Gray code decoding unit 5 in the case where the write clock 104 becomes slower than the read clock 105 due to fluctuations in the transmission path or the like. Until the time T1, the difference between the value of the write address (after gray code decoding) 108 and the value of the read address (after retiming) 103 'exceeds ± 1. However, at time T1, the value of the write address (after Gray code encoding) 108 is '010', the value of the read address (after retiming) 103 is '001', and the difference between the values is within ± 1 Therefore, the address initialization signal 106 is asserted at time T2.

  When the address initialization signal 106 is asserted, the write address generation unit 2 is initialized asynchronously and the value of the write address becomes “000”, and the read address generation unit 3 is similarly asynchronously initialized and read address The value of becomes “100”. From time T2 to time T3 when one cycle of the read clock 105 elapses, the value of the previous cycle is taken over, so the value of the write address (after Gray code decoding) 108 and the read address (after retiming) 103 ′ The difference between the values is within ± 1.

  However, at time T3, the effect of initialization appears, and the value of the write address (after Gray code decoding) 108 becomes ‘000’, and the value of the read address (after retiming) 103 ‘100’. Thus, since the difference exceeds ± 1, the address initialization signal 106 is disabled at time T4, and the operation can be continued for the time being without initialization. The output data 101 until initialization is discarded, and the output data 101 after time T2 is validated.

  As described above in detail, according to the present invention, the approach of the write address 102 and the read address 103 of the 2-port RAM 1 is monitored, and when it is within a predetermined distance, the address initialization signal 106 is generated to generate the write address. By initializing the generation unit 2 and the read address generation unit 3 in a timely manner, the conflict between the write address 102 and the read address 103 can be prevented, and the possibility of continuously generating errors in the transmission path can be automatically avoided.

  FIG. 7 is a block diagram showing the configuration of the clock transfer circuit according to the second embodiment of the present invention. In this clock transfer circuit, the PLL status detector 11 is added to the clock transfer circuit (FIG. 1) described above so that the address initialization signal 112 can be supplied from here. For the description, a data generation unit 8, a write clock generation PLL 9, and a read clock generation PLL 10 are displayed.

  The write clock 104 is generated by the write clock generation PLL 9 and the read clock 105 is generated by the read clock generation PLL 10. The write clock generation PLL 9 and the read clock generation PLL 10 are configured to establish synchronization by a reference clock 109 input from the outside. The data generator 8 outputs input data 100 synchronized with the write clock 104.

  However, when the write clock generation PLL 9 and the read clock generation PLL 10 transition from the asynchronous state to the synchronous state, synchronization with the reference clock 109 is not always established at the same time. Therefore, the difference between the write address 102 and the read address 103 of the 2-port RAM 1 does not always become a stable state at half the depth of the 2-port RAM 1 (difference 4 when the depth is 8 bits). Therefore, here, a configuration is adopted in which the PLL status detection unit 11 is added.

  The PLL status detection unit 11 includes a write clock generation PLL lock / unlock signal 110 indicating the synchronous / asynchronous state of the write clock generation PLL 9 and a read clock generation PLL lock / unlock indicating the synchronous / asynchronous state of the read clock generation unit 10. The lock signal 111 is monitored, and when both PLLs are synchronized, the address initialization signal (PLL synchronization) 112 is asserted and supplied to the write address generation unit 2 and the read address generation unit 3 initialize.

  As described above, the initialization of the write address generation unit 2 and the read address generation unit 3 is performed after frequency synchronization is established between the write clock 102 and the read clock 103, so that the depth of the 2-port RAM 1 is increased. Half is stable. The subsequent operation with respect to a change in frequency due to fluctuations in the write clock 102 is the same as described in the first embodiment.

The block diagram which shows the structure of Example 1 of the clock transfer circuit of this invention. Timing chart showing the operation of the Gray code decoding unit 5 in the clock transfer circuit of the present invention First timing chart of clock transfer circuit of the present invention Second timing chart of clock transfer circuit of the present invention Third timing chart of clock transfer circuit of the present invention Fourth timing chart of clock transfer circuit of the present invention The block diagram which shows the structure of Example 2 of the clock transfer circuit of this invention Block diagram showing one reno configuration of a conventional clock transfer circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 2 port RAM part 2 Write address generation part 3 Read address generation part 4 Gray code encoding part 5 Gray code decoding part 6 Address comparison part 7 Address initialization detection part 8 Data generation part 9 Write clock generation part 10 Read clock generation Part 11 PLL status detection part

Claims (3)

In a clock transfer circuit that outputs data input in synchronization with a clock in synchronization with a clock of a different period,
2-port RAM that can be written and read independently;
A write address generator for sequentially generating a write address of the input data to the 2-port RAM in synchronization with a write clock;
A read address generator for sequentially generating read addresses of the two-port RAM in synchronization with a read clock;
An address initialization detector that constantly monitors the approach between the write address and the read address, and initializes the write address and the read address to be a difference exceeding the predetermined difference when a predetermined difference is reached. Yes, and
The address initialization detection unit
A gray code encoding unit for converting the write address into a gray code;
Retiming the gray code encoded write address with the read clock
And a Gray code decoding part that converts it into a binary code,
The binary coded write address value and the read address are converted to the read clock.
Compared with the read address value retimed by the clock, the difference is within a predetermined value.
Output an address initialization signal to the write address generator and the read address generator
A clock phase change circuit comprising an address comparison unit. The address initialization claims, characterized in that the values of the read address of the write address of the dual port RAM is performed so that the difference was separated by half the depth of the address of the two-port RAM The clock phase change circuit according to Item 1 . A write clock PLL that establishes synchronization with a reference clock and generates the write clock, and a read clock PLL that establishes synchronization with the reference clock and generates the read clock
3. A PLL status detector for outputting an address initialization signal to the write address generator and the read address generator when the synchronization is established at the same time is added. The clock phase changing circuit described.

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