JP5172932B2 - Multilayer chip capacitor - Google Patents

Description

  The present invention relates to a multilayer chip capacitor, and more particularly, to a multilayer chip capacitor that maintains a suitable equivalent series resistance (ESR) while reducing an equivalent series inductance (ESL; Equivalent Serial Inductance).

  Multilayer chip capacitors are widely used as capacitive components for high-frequency circuits. The multilayer chip capacitor can be particularly useful for a decoupling capacitor disposed in a power supply circuit of a semiconductor integrated circuit (LSI). In order to stabilize the power supply circuit, the multilayer chip capacitor must have a lower ESL value. These needs are further increased due to the trend toward higher frequencies and higher currents in electronic devices. The safety of the power supply circuit depends not only on the ESL of the multilayer chip capacitor but also on the ESR. When the ESR becomes a minimum value, the safety of the power supply circuit is weakened, and the voltage fluctuates rapidly when resonance occurs. Therefore, it is preferable to maintain a suitable value for ESR.

  In order to reduce ESL, Patent Document 1 proposes a method in which the leads of the first internal electrode and the second internal electrode having different polarities are arranged in an interdigitated arrangement adjacent to each other. ing. FIG. 1A is an exploded perspective view showing a structure of an internal electrode of a conventional multilayer chip capacitor, and FIG. 1B is a perspective view showing an outer shape of the multilayer chip capacitor of FIG. 1A.

  Referring to FIG. 1a, an internal electrode 14 is formed on the dielectric layers 11a and 11b. The capacitor body 20 is formed by repeatedly laminating the dielectric layers 11a and 11b alternately. The internal electrode 14 is divided into a first internal electrode 12 and a second internal electrode 13 having different polarities. The 1st internal electrode 12 and the 2nd internal electrode 13 comprise one block, and this block is laminated | stacked repeatedly continuously. Each internal electrode 12, 13 is connected to an external electrode (30; 31, 32) via leads 16, 17 (see FIG. 1b). The leads 16 of the first internal electrode 12 are arranged in an array in which fingers are combined adjacent to the leads 17 of the second internal electrode 13. Since the polarities of the voltages supplied to the adjacent leads are different, the magnetic flux generated by the high frequency current flowing from the external electrode is canceled between the adjacent leads, thereby reducing the ESL.

  Each internal electrode (12 or 13) has four leads (16 or 17). Since the resistances generated in the four leads are connected in parallel with each other, the resistance of the entire capacitor becomes very low. As a result, the ESR of the capacitor becomes too small. If the ESR is too small, it is difficult to satisfy the target impedance and the power supply circuit becomes unstable.

In order to prevent the ESR from becoming too small, Patent Document 2 proposes a method of using only one lead for one internal electrode. However, according to Patent Document 2, the direction of the current flowing in the internal electrodes adjacent vertically (in the stacking direction) is the same in some internal electrodes. Thereby, the magnetic flux cannot be canceled between the partially adjacent internal electrodes. As a result, ESL may increase.
US Pat. No. 5,880,925 US Pat. No. 6,441,459

  The present invention is to solve the above-mentioned problems, and its purpose is not only to maintain an ESR value suitable for preventing instability of a power supply circuit, but also to provide a laminate having a reduced ESL. A type chip capacitor is provided.

  In order to achieve the above technical problem, the multilayer chip capacitor according to the first aspect of the present invention includes a capacitor body formed by laminating a plurality of dielectric layers, and the dielectric layer in the capacitor body. A plurality of internal electrode layers each including at least one electrode plate disposed separately from each other and disposed on the same plane, each having only one or two leads extending toward the outer surface of the capacitor body; A plurality of external electrodes formed on the outer surface of the capacitor main body and electrically connected to the electrode plate via the leads, and arranged continuously in a vertical direction (stacking direction) via a dielectric layer. The internal electrode layer forms one block, and the blocks are repeatedly laminated, and each of the electrode plates is formed on one surface of the outer surface of the capacitor body. Each lead has one lead to be drawn out, and the lead drawn to one surface of the capacitor body is arranged in a zigzag shape along the stacking direction of the blocks, and the leads of the electrode plates having different polarities adjacent to each other in the vertical direction Are always adjacent to each other in the horizontal direction perpendicular to the stacking direction.

  According to an embodiment of the present invention, the multilayer chip capacitor may include at least six external electrodes.

  According to an embodiment of the present invention, the multilayer chip capacitor is an 8-terminal capacitor. In this case, the six internal electrode layers continuously arranged on the upper and lower sides form one block, and the blocks can be repeatedly laminated.

  In the 8-terminal capacitor including the block, the first to fourth external electrodes may be sequentially arranged on the outer surface of the capacitor body in this order. In the one block, first to sixth electrode plates each having one lead drawn to the one surface of the capacitor main body can be sequentially stacked in this order. The leads of the first to fourth electrode plates are arranged to connect to the first to fourth external electrodes, respectively, and the leads of the fifth electrode plate are arranged to connect to the third external electrode. The lead of the sixth electrode plate can be disposed so as to be connected to the second external electrode. With such a lead arrangement, the leads drawn to one surface of the capacitor body are arranged in a zigzag shape along the stacking direction.

  According to another embodiment of the present invention, the multilayer chip capacitor may be a 10-terminal capacitor. In this case, the eight internal electrode layers continuously arranged on the upper and lower sides form one block, and the blocks can be repeatedly laminated.

  In the 10-terminal capacitor including the block, first to fifth external electrodes may be sequentially disposed on one surface of the capacitor body. In the one block, first to eighth electrode plates each having one lead drawn to the one surface of the capacitor body can be sequentially stacked. The leads of the first to fifth electrode plates are arranged to be connected to the first to fifth external electrodes, respectively, and the leads of the sixth electrode plate are arranged to be connected to the fourth external electrode. The leads of the seventh electrode plate may be arranged to connect to the third external electrode, and the leads of the eighth electrode plate may be arranged to connect to the second external electrode. With such a lead arrangement, the leads drawn to one surface of the capacitor body are arranged in a zigzag shape along the stacking direction.

  According to the embodiment of the present invention, upper and lower adjacent leads connected to the same external electrode can be arranged so as to extend in different directions while forming a certain angle. Preferably, the adjacent leads connected to the same external electrode are extended in different directions while forming an angle of 45 to 135 degrees with each other.

  According to an embodiment of the present invention, each of the internal electrode layers is divided into a plurality of electrode plates on the same plane by dividing slots, and each of the electrode plates has a lead that provides a connection to the external electrode. Can be made. In this case, each of the electrode plates can have only one lead.

  Each of the internal electrode layers may be divided into a plurality of, for example, two electrode plates on the same plane by dividing slots. The two electrode plates on the same plane may have different polarities. In contrast, the two electrode plates on the same plane may have the same polarity.

  According to an embodiment of the present invention, the divided slots are arranged extending in parallel with the longitudinal direction of the capacitor body.

  According to another embodiment of the present invention, the dividing slot of the internal electrode layer may extend in the diagonal direction of the capacitor body. In this case, the divided slots of the internal electrode layers adjacent to each other in the vertical direction can be arranged extending in different diagonal directions.

  According to still another embodiment of the present invention, the divided slots of the internal electrode layers adjacent to each other in the vertical direction can be arranged to be orthogonal to each other. For example, an internal electrode layer in which divided slots extending parallel to the longitudinal direction of the capacitor body and an internal electrode place in which divided slots extending perpendicular to the longitudinal direction of the capacitor body are arranged alternately in the stacking direction. Can be placed.

  The plurality of electrode plates on the same plane may have the same area. As another method, the plurality of electrode plates on the same plane may have different areas. In this case, the internal electrode layers adjacent in the vertical direction can be arranged so that the in-plane positions of the divided slots are different from each other. Unlike this, the in-plane positions of the divided slots of the internal electrode layers vertically adjacent to each other can be arranged to be the same.

  According to an embodiment of the present invention, each of the electrode plates may be formed with a non-divided slot extending from one side of the electrode plate to the center so as to change a current flow in the electrode plate. it can. The divided slot and the non-divided slot may be extended parallel to each other in the longitudinal direction of the capacitor body. Preferably, the in-plane positions of the electrode plates in the non-divided slots of the electrode plates adjacent in the vertical direction are made to coincide with each other. As described above, when the in-plane positions of the non-divided slots adjacent in the vertical direction coincide with each other, the capacity loss due to the non-divided slots can be reduced. Preferably, currents flow in directions opposite to each other in adjacent regions of two electrode plates on the same plane. Preferably, currents flow in opposite directions to the upper and lower adjacent electrode plates.

  According to an embodiment of the present invention, in each of the blocks, at least one internal electrode layer is divided into a plurality of electrode plates on the same plane by dividing slots, and each of the electrode plates is connected to the external electrode. It can have leads that provide a connection.

  Each of the divided internal electrode layer electrode plates may have as few as one lead providing a connection to the external electrode. The divided slot can be extended in the longitudinal direction of the multilayer chip capacitor body.

  The multilayer chip capacitor may be an 8-terminal capacitor. In this case, each of the blocks is composed of six internal electrode layers arranged continuously in the vertical direction. In each of the blocks, three of the six internal electrode layers are divided into two by the divided slots. It can be divided into two electrode plates.

  In the 8-terminal capacitor, each of the blocks can be constituted by first to sixth internal electrode layers that are sequentially arranged. Each of the first, third and fifth internal electrode layers may be divided into two electrode plates by dividing slots, and each of the divided internal electrode layer electrode plates may have only one lead. Further, each of the second, fourth and sixth internal electrode layers can have two leads without being divided.

  According to an embodiment of the present invention, each of the internal electrode layers is composed of a single electrode plate that is not divided, and each of the electrode plates may have a lead that provides a connection to the external electrode. .

  In this case, each of the electrode plates has two leads drawn on opposite side surfaces of the capacitor body, and the leads drawn on one side surface of the both side surfaces are arranged in a zigzag shape along the stacking direction. Can be done.

  The multilayer chip capacitor may be an 8-terminal capacitor. In this case, the first to sixth internal electrode layers continuously arranged on the upper and lower sides form one block, and the blocks can be repeatedly laminated.

  In the 8-terminal capacitor, first to fourth external electrodes may be sequentially disposed on one surface outside the capacitor body. In addition, the first to sixth internal electrode layers may have first to sixth leads led to one surface of the capacitor body. The first to fourth leads may be arranged to be connected to the first to fourth external electrodes, respectively. The fifth lead may be disposed so as to be connected to the third external electrode, and the sixth lead may be disposed so as to be connected to the second external electrode.

  The multilayer chip capacitor can be a 10-terminal capacitor. In this case, the first to eighth internal electrode layers continuously arranged on the upper and lower sides form one block, and the blocks can be repeatedly laminated.

  In the 10-terminal capacitor, first to fifth external electrodes are sequentially disposed on one surface of the capacitor body. The first to eighth internal electrode layers may have first to eighth leads led out to one surface of the capacitor body. The first to fifth leads may be disposed so as to be connected to the first to fifth external electrodes, respectively. The sixth lead is arranged to connect to the fourth external electrode, the seventh lead is arranged to connect to the third external electrode, and the eighth lead is connected to the second external electrode. Can be arranged.

The multilayer chip capacitor according to the second embodiment of the present invention includes a capacitor body formed by laminating a plurality of dielectric layers, and the capacitor body separated from each other by the dielectric layers in the capacitor body. A plurality of internal electrode layers each having only one or two leads extending toward the outer surface of the capacitor body, and formed on the outer surface of the capacitor body via the leads. Including a plurality of external electrodes electrically connected to the electrode plate, a plurality of internal electrode layers continuously arranged in the upper and lower sides form one block, the blocks are repeatedly stacked, and adjacent to each other in the vertical direction Leads of electrode plates having different polarities are always arranged adjacent to each other in the horizontal direction.

  According to the embodiment of the present invention, the multilayer chip capacitor may be an 8-terminal capacitor. In this case, each of the blocks can be composed of first to eighth internal electrode layers arranged sequentially. Each of the fourth and eighth internal electrode layers may have two leads extending on both side surfaces of the capacitor body. Each of the first and third internal electrode layers and the fifth and seventh internal electrode layers may have only one lead.

  In the 8-terminal capacitor, the fourth internal electrode layer has a first lead extending to one side surface of the capacitor and a second lead extending to the other side surface facing the one side surface, and an eighth internal electrode layer Can have a third lead extending to the one side and a fourth lead extending to the other side. The first lead is disposed to be adjacent to the lead of the third internal electrode layer in the horizontal direction, and the second lead is disposed to be adjacent to the lead of the fifth internal electrode layer in the horizontal direction. Can do. The third lead is disposed to be adjacent to the lead of the first internal electrode layer of the adjacent block in the horizontal direction, and the fourth lead is adjacent to the lead of the seventh internal electrode layer in the horizontal direction. Can be placed.

  According to an embodiment of the present invention, the fourth internal electrode layer can be divided into one electrode plate having the first lead and another electrode plate having the second lead by dividing slots. The eighth internal electrode layer may be divided into one electrode plate having the third lead and another electrode plate having the fourth lead by dividing slots. The first to third internal electrode layers and the fifth to seventh internal electrode layers can have only one lead without being divided.

  According to another embodiment of the present invention, each of the internal electrode layers is composed of one electrode plate that is not divided, and each of the electrode plates may have a lead that provides a connection to the external electrode.

  According to embodiments of the present invention, each internal electrode layer has only one or two leads. This can prevent the ESR from becoming excessively small. Moreover, the leads of the electrode plates of different polarities adjacent to each other in the upper and lower directions are always arranged adjacent to each other in the horizontal direction. Thereby, the increase factor of ESL can be suppressed.

  In the present specification, “divided slot” refers to a slit portion that physically separates internal electrode layers, and “non-divided slot” refers to a slit portion that does not physically separate internal electrode layers.

  According to the present invention, the ESR of the capacitor is prevented from becoming excessively small, and the ESL is further reduced. As a result, the safety of the power supply circuit is improved, the target impedance is satisfied, and the power network can be stably designed. Moreover, the ESR can be easily controlled by adjusting the length of the non-divided slot.

It is a disassembled perspective view which shows the internal electrode structure of the conventional multilayer chip capacitor. FIG. 1B is a perspective view showing an outer shape of the multilayer chip capacitor of FIG. It is a top view which shows the internal electrode structure of the multilayer chip capacitor by one Embodiment of this invention. FIG. 3 is a plan view (a) and a side view (b) for explaining the lead arrangement of FIG. 2. It is a top view which shows the internal electrode structure of the multilayer chip capacitor by other embodiment of this invention. It is a side view which shows arrangement | positioning of the lead withdraw | derived to one surface of a capacitor main body in the multilayer chip capacitor by embodiment (a) and conventional example (b) of this invention. FIG. 6 is a plan view showing an internal electrode structure of a multilayer chip capacitor according to still another embodiment of the present invention. It is the elements on larger scale which show a part of internal electrode shape of FIG. 1 is a plan view showing an internal electrode structure of a multilayer chip capacitor according to embodiments of the present invention. 1 is a plan view showing an internal electrode structure of a multilayer chip capacitor according to embodiments of the present invention. 1 is a plan view showing an internal electrode structure of a multilayer chip capacitor according to embodiments of the present invention. 1 is a plan view showing an internal electrode structure of a multilayer chip capacitor according to embodiments of the present invention. 1 is a plan view showing an internal electrode structure of a multilayer chip capacitor according to embodiments of the present invention. 1 is a plan view showing an internal electrode structure of a multilayer chip capacitor according to embodiments of the present invention. 1 is a plan view showing an internal electrode structure of a multilayer chip capacitor according to embodiments of the present invention. 1 is a plan view showing an internal electrode structure of a multilayer chip capacitor according to embodiments of the present invention. 1 is a plan view showing an internal electrode structure of a multilayer chip capacitor according to embodiments of the present invention. It is the elements on larger scale which show a part of internal electrode shape of FIG. It is a perspective view which shows the external shape of the 8-terminal multilayer chip capacitor by embodiment of this invention. 1 is a plan view showing an internal electrode structure of a multilayer chip capacitor according to an embodiment of the present invention. 1 is a plan view showing an internal electrode structure of a multilayer chip capacitor according to an embodiment of the present invention. FIG. 21 is a side view showing an arrangement of leads drawn out to one surface of a capacitor body in the multilayer chip capacitor of FIG. FIG. 21 is a plan view showing an internal electrode structure of a multilayer chip capacitor according to a modification of FIG. 20. It is a perspective view which shows the external shape of the 10 terminal multilayer chip capacitor by embodiment of this invention. It is a top view which shows the internal electrode structure of the multilayer chip capacitor by other embodiment of this invention. It is a top view which shows the internal electrode structure of the multilayer chip capacitor by other embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments of the present invention can be modified in various different forms, and the scope of the present invention is not limited to the embodiments described below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Accordingly, the shape and size of elements and the like in the drawings can be exaggerated for a clearer description, and the elements denoted by the same reference numerals in the drawings are the same elements.

  2 to 17 show the internal electrode structure of the multilayer chip capacitor according to the embodiments of the present invention. A capacitor using the internal electrode structure of FIGS. 2 to 17 corresponds to an 8-terminal capacitor (eight external electrodes), and the outline of such an 8-terminal capacitor is shown in FIG.

  First, referring to FIG. 18, the capacitor 100 includes a capacitor main body 120 and eight external electrodes 131, 132, 133, 134, 135, 136, 137, 138 formed on the outer surface of the main body 120. The capacitor body 120 is formed by laminating a plurality of dielectric layers. In the capacitor body 120, a plurality of internal electrode layers are arranged separated by the dielectric layer. External electrodes having different polarities are alternately arranged on each of two opposing side surfaces of the main body 120. Examples of the internal structure of the 8-terminal capacitor 100 are shown in FIGS.

  Referring to FIG. 2, six internal electrode layers 1010, 1020, 1030, 1040, 1050, and 1060 formed on the dielectric layer 1000 are sequentially stacked to form one block. That is, the six internal electrode layers 1010 to 1060 are sequentially arranged (see the dashed line arrow in FIG. 2) to form a basic unit (block) of a periodic laminated structure. By repeatedly laminating these blocks, a capacitor body (see reference numeral 120 in FIG. 18) is formed. In FIG. 2, six continuous internal electrode layers 1010, 1020, 1030, 1040, 1050, and 1060 starting from the internal electrode layer 1010 are set as one block (dotted line). I can decide. For example, six consecutive internal electrode layers 1020, 1030, 1040, 1050, 1060, 1010 starting from the internal electrode layer 1020 can be set in one block. Regardless of which internal electrode layer is used as a starting point, a block is composed of six consecutive internal electrode layers.

  Each internal electrode layer 1010, 1020, 1030, 1040, 1050, 1060 is divided into two electrode plates (1011, 1012, 1021 and 1022, 1031 and 1022, 1041 and 1042, 1051 and 1052) on the same plane by dividing slots. , 1061 and 1062). As illustrated, the two electrode plates 1011, 1012 to 1061 and 1062 set on the same plane, that is, in the same internal electrode layer, have different polarities from each other. For example, the electrode plate 1011 has a positive (+) polarity, and the electrode plate 1012 has a negative (−) polarity. The dividing slot crosses the central portion of the internal electrode layer in parallel with the longitudinal direction (L) of the capacitor (that is, perpendicular to the width direction (W)), so that the two electrode plates on the same plane have substantially the same area. Have For example, the internal electrode layer 1010 is divided into two electrode plates 1011 and 1012 having the same area as each other by divided slots arranged extending in parallel with the longitudinal direction (L). Electrode plates of different polarities that are opposed to each other in the direction in which the internal electrode layers 1010 to 1060 are stacked (that is, arranged so as to be vertically adjacent to each other with the dielectric layer in between) Constitutes one capacitor element.

  As shown in FIG. 2, each electrode plate 1011, 1012, 1021, 1022, 1031, 1032, 1041, 1042, 1051, 1052, 1061, 1062 has one lead 1011a, 1012a, 1021a, 1022a, 1031a, 1032a, 1041a, 1042a, 1051a, 1052a, 1061a, 1062a. The leads 1011a to 1062a provide connection of the electrode plate to external electrodes (see the external electrodes 131 to 138 shown in FIG. 18), and electrically connect the internal electrode layers 1010 to 1060 to the external electrodes 131 to 138.

  Thus, each internal electrode layer is divided into two electrode plates, and each electrode plate has only one lead, thereby effectively preventing the phenomenon that the ESR of the capacitor is excessively lowered. Can do. That is, by dividing the internal electrode layer into two electrode plates, the area of the current path is relatively reduced, and the resistance value of the current flowing through the internal electrode layer is increased. Further, since each electrode plate has only one lead, it is possible to prevent a rapid drop in resistance that occurs when a large number of leads are connected in parallel. As a result, the capacitor can maintain an appropriate ESR, and instability of the power supply circuit due to an excessively low ESR can be prevented.

  Also, the leads (for example, the leads 1011a and 1021a) of the electrode plates (for example, the electrode plates 1011 and 1021) of different polarities adjacent to each other vertically (that is, in the stacking direction of the internal electrode layers 1010 to 1060) are always in the horizontal direction. It arrange | positions so that it may mutually adjoin in (direction perpendicular | vertical with respect to the lamination direction). That is, the leads of the electrode frets having different polarities adjacent to each other are always connected to the external electrodes arranged adjacent to each other. For example, the lead 1011a and the lead 1021a are arranged so as to be connected to the external electrode 131 and the external electrode 132, which are arranged adjacent to each other and have different polarities.

  By arranging the leads having different polarities so as to be adjacent to each other in the vertical and horizontal directions, currents in different directions (especially currents in the opposite directions) flow through the adjacent leads. It becomes like this. As a result, the magnetic fluxes generated by the currents cancel each other, the parasitic inductance is reduced, and the ESL of the capacitor is further reduced. That is, the safety of the power supply circuit is further improved by maintaining the appropriate ESR value and further reducing the ESL.

  FIG. 3 is a plan view (a) and a side view (b) for explaining the arrangement of the leads and the like in FIG. The side view of FIG. 3B corresponds to the side view as viewed toward the side surface (a) of FIG. Referring to FIG. 3, it can be seen that the leads 1011a, 1021a, 1031a, 1041a, 1051a, and 1061a drawn to one surface (A) of the capacitor body are arranged in a zigzag shape along the stacking direction (in particular, FIG. 3). (See dotted line in (b)).

  More specifically, first to fourth external electrodes 131 to 134 are arranged in this order on one surface (A) of the capacitor body in this order in a direction perpendicular to the stacking direction (in FIG. 3A, sequentially from left to right). Is arranged). Further, in each block, first to sixth electrode plates 1011, 1021, 1031, 1041, 1051, and 1061 are sequentially stacked, each having one lead to be drawn out to the one surface (A). (See FIG. 2). As shown in FIG. 3, the leads 1011a, 1021a, 1031a, and 1041a of the first to fourth electrode plates 1011, 1021, 1031, and 1041 are connected to the first to fourth external electrodes 131, 132, 133, and 134, respectively. Placed in. The lead 1051a of the fifth electrode plate 1051 is disposed so as to connect to the third external electrode 133. The lead 1061 a of the sixth electrode plate 1061 is disposed so as to be connected to the second external electrode 132. By repeating such lead arrangement for each block, leads and the like drawn out on one surface of the capacitor body are arranged in a zigzag shape along the stacking direction. It can be seen that leads and the like drawn out to the surface facing the one surface (A) are similarly arranged in a zigzag manner (see FIG. 2).

  The zigzag arrangement of the leads 1011a to 1061a described above provides an advantage of reducing mutual inductance between leads of the same polarity adjacent in the vertical direction (stacking direction). As shown in FIG. 3B, the average distance between the vertically adjacent leads connected to the same external electrode is larger than the thickness of the two dielectric layers. For example, the distance between the leads 1011a that are connected to the external electrode 131 and vertically adjacent via the dielectric layer 1000 corresponds to the thickness (D) of the dielectric layer 1000 for approximately six layers. Here, “adjacent leads” is a set of leads having the shortest distance in the stacking direction among a plurality of different leads connected to the same external electrode. When the distance between leads of the same polarity adjacent in the vertical direction is increased in this way, strong mutual inductance due to magnetic coupling between them is reduced or suppressed. This further reduces the ESL of the capacitor.

  FIG. 4 illustrates an internal electrode structure according to another embodiment of the present invention. The embodiment shown in FIG. 4 differs from the embodiment of FIG. 2 described above in that two electrode plates on the same plane have the same polarity.

  Referring to FIG. 4, six internal electrode layers 1110 to 1160 formed on the dielectric layer 1001 are sequentially stacked to form one block. This block is repeatedly laminated to form a capacitor body (see capacitor body 120 shown in FIG. 18).

  Each internal electrode layer 1110, 1120, 1130, 1140, 1150, 1160 formed on the dielectric layer 1001 is divided into two electrode plates (for example, electrode plates 1111 and 1112) on the same plane by dividing slots. Is done. The electrode plates (for example, electrode plates 1111 and 1121) of different polarities facing each other constitute one capacitor element (capacitive element). Each electrode plate has only one lead 1111a to 1162a. The leads 1111a to 1162a provide connection of the electrode plate to the external electrodes (see the external electrodes 131 to 138 shown in FIG. 18), and electrically connect the internal electrode layers 1110 to 1160 to the external electrodes 131 to 138. Also in this embodiment, leads (for example, leads 1111a, 1121a, 1131a, 1141a, 1151a, and 1161a) drawn out on one surface of the capacitor body are arranged in a zigzag shape along the stacking direction (see FIG. 5A).

  5A shows the arrangement of leads drawn to one surface of the capacitor body in the capacitor of FIG. 4, and FIG. 5B shows the arrangement of leads drawn to one surface of the capacitor body in the multilayer chip capacitor according to the conventional example. .

  4 and 5A, first to fourth external electrodes 131 to 134 are sequentially disposed on one surface of the capacitor main body 120. The first to sixth internal electrode layers 1110, 1120, 1130, 1140, 1150, and 1160 have first to sixth leads 1111a, 1121a, 1131a, 1141a, 1151a, and 1161a, respectively, which are drawn out to one surface of the main body (that is, Each internal electrode layer has one lead that is drawn out to one surface of the capacitor). The first to fourth leads 1111a, 1121a, 1131a, and 1141a are disposed to be connected to the first to fourth external electrodes 131, 132, 133, and 134, respectively. The fifth lead 1151a is disposed so as to be connected to the third external electrode 133, and the sixth lead 1161a is disposed so as to be connected to the second external electrode 132. By repeating such a lead arrangement structure, the leads 1111a to 1161a drawn to one surface of the main body are arranged in a zigzag shape along the stacking direction (see the dotted line in FIG. 5A).

  The zigzag arrangement of the leads 1111a to 1161a described above provides an advantage of reducing the mutual inductance between the leads of the same polarity adjacent to each other in the vertical direction. As shown in FIG. 5A, the average distance between the vertically adjacent leads connected to the same external electrode is larger than the thickness of the two dielectric layers. For example, the distance between the vertically adjacent leads 1111a connected to the external electrode 131 corresponds to the thickness (D) of approximately six dielectric layers. Thus, when the distance between leads of the same polarity adjacent vertically is increased, the strong mutual inductance due to magnetic coupling between them is reduced or suppressed. This further reduces the ESL of the capacitor.

  On the other hand, the conventional capacitor does not have the zigzag arrangement of leads described above. Therefore, in the conventional capacitor (see FIGS. 1a and 1b), as shown in FIG. 5 (b), the average distance between the vertically adjacent leads connected to the same external electrode is relatively short. For example, the distance between the upper and lower adjacent leads 16 connected to the external electrode 31 is only the thickness (d) of the dielectric layer for only two layers. Therefore, the ESL is relatively large compared to the present embodiment due to the strong mutual inductance between leads of the same polarity.

  According to the present embodiment, each internal electrode layer is divided into two electrode plates and each electrode plate has only one lead, so that the ESR of the capacitor becomes excessively low, and the power supply thereby Instability of the circuit can be effectively prevented.

  In addition, the leads (for example, the leads 1111a and 1121a) of the electrode plates (for example, the electrode plates 1111 and 1121) of different polarities adjacent to each other are always adjacent to each other in the horizontal direction (direction perpendicular to the stacking direction). Placed in. Accordingly, currents in different directions (especially currents in opposite directions) flow through the adjacent leads (for example, 1111a and 1121a), and the magnetic fluxes cancel each other. That is, the safety of the power supply circuit can be improved by maintaining the appropriate ESR value and reducing the ESL. Furthermore, the effect of reducing ESL is further increased by the zigzag arrangement of the leads described above.

  FIG. 6 illustrates an internal electrode structure according to still another embodiment of the present invention. The embodiment shown in FIG. 6 has two vertically adjacent leads connected to the same external electrode (eg, leads 1211a and 1271a, leads 1221a and 1261a, leads 1231a and 1251a, leads 1232a and 1252a, etc.) Are extending in different directions while forming an angle. “An angle formed by two leads” refers to an angle formed by a line obtained by projecting each lead on a plane perpendicular to the stacking direction. Also in this embodiment, two electrode plates (for example, electrode plates 1211 and 1212) on the same plane have the same polarity as in the embodiment of FIG.

  Referring to FIG. 6, twelve internal electrode layers 1210, 1220, 1230, 1240, 1250, 1260, 1270, 1280, 1290, 1300, 1310, and 1320 formed on the dielectric layer 1002 are sequentially stacked. Form a block. By repeatedly stacking these blocks, a capacitor body (see capacitor body 120 shown in FIG. 18) is formed.

  Each internal electrode layer 1210, 1220, 1230, 1240, 1250, 1260, 1270, 1280, 1290, 1300, 1310, 1320 formed on the dielectric layer 1002 is two electrode plates that are on the same plane by dividing slots. (Eg, electrode plates 1211 and 1212). The electrode plates having different polarities facing each other (for example, electrode plates 1211 and 1221) constitute one capacitor element. Each electrode plate has only one lead 1211a to 1322a. The leads 1211a to 1322a provide connection of the electrode plate to the external electrodes (see the external electrodes 131 to 138 shown in FIG. 18), and electrically connect the internal electrode layers 1210 to 1320 to the external electrodes 131 to 138.

  In particular, in this embodiment, adjacent leads (for example, leads 1211a and 1271a, leads 1221a and 1261a, leads 1231a and 1251a, leads 1232a and 1252a, etc.) connected to the same external electrode are stacked. Stretched at an angle to each other. Such a feature is also clearly shown in the partially enlarged view of FIG. As shown in FIG. 7, the vertically adjacent leads 1211a and 1271a connected to the external electrode 131 extend in different directions while forming an angle (α). Preferably, an angle (α) formed by adjacent leads connected to the same external electrode is 45 to 135 degrees.

  In this way, when the vertically adjacent leads (for example, the leads 1211a and 1271a) connected to the same external electrode extend in different directions while forming an angle, the currents flowing through the adjacent leads are in different directions. It begins to flow. Therefore, an effect of minimizing the phenomenon that magnetic flux is reinforced between the adjacent leads is obtained, and strong mutual inductance is not generated in adjacent leads connected to the same external electrode. Eventually, the ESL of the capacitor is further reduced.

  In this embodiment, too, each internal electrode layer is divided into two electrode plates and each electrode plate has only one lead, and thus the ESR of the capacitor becomes excessive. It is possible to prevent the phenomenon of lowering and the instability of the power supply circuit due to this phenomenon.

  Further, the leads (for example, the leads 1211a and 1221a) of the electrode plates having different polarities (for example, the electrode plates 1211 and 1221) adjacent to each other in the vertical direction are always disposed adjacent to each other in the horizontal direction. Therefore, currents in different directions flow through the adjacent leads (for example, the leads 1211a and 1221a), and the magnetic fluxes cancel each other. Eventually, with the maintenance of a suitable ESR value, the reduced ESL will improve the safety of the power supply circuit.

  FIG. 8 shows an internal electrode structure according to still another embodiment of the present invention. In the embodiment shown in FIG. 8, two electrode plates on the same plane have different areas. In particular, the in-plane positions of the divided slots of the internal electrode layers adjacent in the vertical direction (stacking direction) are different from each other. For example, the division slot of the internal electrode layer 1410 is located near the lower side of the rectangular dielectric layer 1004 in the drawing, whereas the division slot of the internal electrode layer 1420 is the upper side of the dielectric layer 1004 in the drawing. Located nearby. Further, the division slot of the internal electrode layer 1430 adjacent to the internal electrode layer 1420 is located near the lower side of the dielectric layer 1004 in the drawing. In this manner, the internal electrode layers are stacked, so that the positions of the divided slots of the internal electrode layers that are vertically adjacent to each other through the dielectric layer 1004 are different from each other.

  As described above, by arranging the vertically adjacent divided slots at different positions in the internal electrode layer, it is possible to greatly suppress the delamination phenomenon that may occur at the time of manufacturing the capacitor. The delamination phenomenon acts as a factor that adversely affects the reliability of the capacitor.

  Except for the position of the dividing slot described above, the embodiment shown in FIG. 8 is the same as the embodiment shown in FIG. Thus, in the embodiment of FIG. 8, each internal electrode layer is divided into two electrode plates (eg, electrode plates 1411 and 1412) and each electrode plate has only one lead, thereby allowing The phenomenon that the ESR becomes excessively low and the instability of the power supply circuit due to this phenomenon can be effectively prevented.

  In addition, since the leads of the electrode plates with different polarities adjacent to each other are always arranged adjacent to each other in the horizontal direction, an increase in ESL can be suppressed. Similar to the embodiment of FIG. 4, the leads drawn to one surface of the capacitor body are arranged in a zigzag shape. In FIG. 8, reference numeral 1004 indicates a dielectric layer, reference numerals 1410 to 1460 indicate internal electrode layers, and reference numerals 1411a to 1462a indicate leads.

  FIG. 9 shows an internal electrode structure of a multilayer chip capacitor according to still another embodiment of the present invention. In the embodiment of FIG. 9, some internal electrode layers in one block are not divided by dividing slots. That is, there is at least one internal electrode layer (for example, internal electrode layer 1520) that is not divided in one block.

  Referring to FIG. 9, six internal electrode layers each formed on a dielectric layer 1005 form one block, and three internal electrode layers are divided into two electrode plates by dividing slots. Has been. The internal electrode structure in FIG. 9 is the same as the internal electrode structure in FIG. 4 except that the three internal electrode layers 1520, 1540, and 1560 are not divided in one block.

  Specifically, the first to sixth internal electrode layers 1510 to 1560 are sequentially arranged to form one block. The first internal electrode layer 1510, the third internal electrode layer 1530, and the fifth internal electrode layer 1550 are each divided into two electrode plates (for example, electrode plates 1511 and 1512) by a division slot. Each of the electrode plates has only one lead 1511a, 1512a, 1531a, 1532a, 1551a, 1552a. The second, fourth, and sixth internal electrode layers 1520, 1540, and 1560 are each composed of one electrode plate that is not divided. Each of the second internal electrode layer 1520, the fourth internal electrode layer 1540, and the sixth internal electrode layer 1560 has two leads (leads 1521a and 1522a, leads 1541a and 1542a, and leads 1561a and 1562a).

  As described above, the internal electrode layers 1510, 1530, and 1550 divided by the divided slots and the internal electrode layers 1520, 1540, and 1560 that are not divided are alternately arranged, so that the pressurizing and firing steps in the manufacturing process are performed. Thus, it is possible to ensure the uniformity of the applied pressure and prevent the delamination phenomenon.

  According to this embodiment, at least one electrode layer (here, three electrode layers) is divided into two electrode plates by a dividing slot in one block composed of six electrode layers, and each of the divided internal electrode layers is divided. The electrode plate has only one lead. The undivided internal electrode layers 1520, 1540, 1560 each have only two leads. Accordingly, the ESR of the capacitor can have a generally suitable value without having an excessively small value.

  Further, as shown in FIG. 9, leads of different polarities adjacent to each other (for example, 1511a and 1521a) are always arranged adjacent to each other in the horizontal direction. In addition, the leads drawn out on one surface of the capacitor body are arranged in a zigzag shape along the stacking direction. Therefore, even in the case of the present embodiment, an increase factor of ESL can be suppressed.

  FIG. 10 shows an internal electrode structure of a multilayer chip capacitor according to still another embodiment of the present invention. The embodiment of FIG. 10 is the same as the embodiment of FIG. 4 except for the extending direction of the divided slots that divide the internal electrode layer.

  Referring to FIG. 10, the divided slots of the internal electrode layers 1710 to 1760 on the dielectric layer 1007 respectively extend in the diagonal direction of the rectangular dielectric layer 1007. In addition, the divided slots of the internal electrode layers adjacent to each other vertically extend in different diagonal directions. Therefore, when the internal electrode layers are laminated, the positions of the divided slots in the internal electrode layers adjacent to each other in the vertical direction are different from each other.

  In this way, by changing the diagonal direction in which the upper and lower divided slots extend, the uniformity of the applied pressure can be ensured in the pressurization stage. Thereby, the delamination phenomenon inside the capacitor can be prevented.

  Also in this embodiment, each internal electrode layer (for example, internal electrode layer 1710) is divided into two electrode plates (for example, electrode plates 1711 and 1712), and each of the electrode plates (for example, electrode plate 1711) is slightly By having one lead (eg, lead 1711a), a suitable ESR can be maintained. In addition, the ESL reduction effect can be obtained because the leads having different polarities adjacent to each other are always adjacent to each other in the horizontal direction. In addition, the leads drawn out over the capacitor body are arranged in a zigzag shape. Reference numerals 1712a to 1762a denote leads.

  FIG. 11 shows an internal electrode structure of a multilayer chip capacitor according to still another embodiment of the present invention. In the embodiment of FIG. 11, two coplanar electrode plates (for example, electrode plates 1811 and 1812) having the same polarity as each other have different areas as well as in-plane positions of the divided slots in the internal electrode layer. That is, it differs from the embodiment of FIGS. 4 and 8 in that the in-plane position in the dielectric layer 1008 is the same. That is, each internal electrode layer (for example, internal electrode layer 1810) is divided into two electrode plates (for example, electrode plates 1811 and 1812) on the same plane having different areas by dividing slots having the same in-plane position. Has been.

  By dividing each internal electrode layer into different areas having the same polarity by dividing slots having the same in-plane position in this way, there is almost no change in the overall capacitance when compared with the capacitor of FIG. Although not, ESL can be smaller. Also in this embodiment, the appropriate ESR maintenance and ESL reduction effects described with reference to FIG. 4 can be obtained. In FIG. 11, reference numeral 1008 denotes a dielectric layer, reference numerals 1810 to 1860 denote internal electrode layers, and reference numerals 1811a to 1862a denote leads.

  12 to 17 are plan views showing an internal electrode structure of an 8-terminal multilayer chip capacitor according to another embodiment of the present invention. The capacitors shown in FIGS. 12 to 17 have, for example, the outer shape shown in FIG.

  The embodiment of FIG. 12 is the same as the embodiment of FIG. 4 except that the directions in which the divided slots of the internal electrode layers adjacent in the vertical direction are orthogonal to each other. Accordingly, each internal electrode layer 3010-3060 formed on the dielectric layer 3001 is divided into two electrode plates (electrode plates 3011 and 3012, electrode plates 3021 and 3022, etc.) on the same plane by dividing slots. The Each electrode plate (electrode plates 3011, 3012, 3021, 3022, etc.) has only one lead 3011a, 3012a..., 3061a, 3062a.

  As shown in FIG. 12, the divided slots of the internal electrode layers (for example, internal electrode layers 3010 and 3020) that are vertically adjacent to each other are arranged so as to be orthogonal to each other. In particular, a dividing slot extending in parallel with the longitudinal direction (for example, a dividing slot of the internal electrode layer 3010) and a dividing slot extending in a direction perpendicular to the longitudinal direction (for example, a dividing slot of the internal electrode layer 3020) are (Along the stacking direction) In this way, by arranging the divided slots whose extending directions are perpendicular to each other alternately along the stacking direction, the delamination phenomenon that occurs during the manufacture of the capacitor can be greatly suppressed.

  The embodiment of FIG. 13 is the same as the embodiment of FIG. 2 described above except that non-divided slots are formed in each electrode plate. Referring to FIG. 13, each electrode plate (electrode plates 4011, 4012,..., 4061, 4062) is formed with a non-divided slot extending from one side surface of each electrode plate to the center side. In particular, the non-divided slot extends in parallel with the longitudinal direction (L) in the same manner as the divided slot. This undivided slot serves to change the current flow in the electrode plate.

  The above-described non-divided slot lengthens the current path in the electrode plate (eg, electrode plate 4011). This increases the resistance of the current flowing through the electrode plate. Therefore, the non-divided slot serves to prevent the ESR of the capacitor from becoming excessively low. In addition, the ESR can be appropriately controlled by adjusting the length of the non-divided slot. This facilitates the satisfaction of the target impedance and the stable design of the power distribution network.

  Referring to FIG. 13, currents in opposite directions flow in two adjacent electrode plates (for example, electrode plates 4011 and 4012) in mutually adjacent regions (that is, in the vicinity of the divided slots) (see FIG. 13). See arrow). This makes it possible to obtain a magnetic flux canceling effect in the vicinity of the divided slots. Such a magnetic flux canceling effect becomes a factor of reducing the ESL of the capacitor.

  In addition, currents in opposite directions flow through electrode plates adjacent to each other in the vertical direction (for example, electrode plates 4011 and 4021). Thereby, the effect of magnetic flux cancellation can be obtained even between the electrode plates adjacent in the vertical direction. Eventually, the ESL of the capacitor is further reduced, and the safety of the power supply circuit is further improved.

  According to the present embodiment, the in-plane positions on the electrode plates of the non-divided slots of the electrode plates (for example, electrode plates 4011 and 4021) adjacent to each other in the vertical direction coincide with each other. In other words, the non-divided slots adjacent to each other in the upper and lower directions overlap each other. As described above, the non-divided slots adjacent to each other in the vertical direction overlap each other, whereby the loss of capacitance due to the non-divided slots can be minimized. In FIG. 13, reference numeral 4000 denotes a dielectric layer, reference numerals 4010 to 4060 denote internal electrodes, and reference numerals 4011a to 4062a denote leads.

  The embodiment of FIG. 14 is the same as the embodiment of FIG. 4 described above except that non-divided slots are formed in each electrode plate. That is, the electrode plate (electrode plates 4111, 4112, 4121, etc.) is formed with a non-divided slot extending from one side surface of each electrode plate to the center side. Also in this embodiment, the non-divided slot extends in the longitudinal direction (L) like the divided slot to change the current flow in the electrode plate. Therefore, the embodiment (appropriate control of ESR and reduction of ESL) described with reference to FIG. 13 can be obtained also in the embodiment of FIG.

  Also in this embodiment, the in-plane positions of the electrode plates in the non-divided slots of the electrode plates (for example, the electrode plates 4111 and 4121) adjacent to each other in the vertical direction coincide with each other. Therefore, the loss of capacitance due to the non-divided slot can be suppressed. In FIG. 14, reference numeral 4001 indicates a dielectric layer, reference numerals 4110 to 4160 indicate internal electrodes, and reference numerals 4111a to 4162a indicate leads.

  FIG. 15 is a plan view showing an internal electrode structure of an 8-terminal multilayer chip capacitor according to still another embodiment of the present invention. In the embodiment of FIG. 15, each internal electrode layer consists of one undivided electrode plate. The internal electrode structure in FIG. 15 corresponds to a structure in which two electrode plates (for example, electrode plates 1111 and 1112 in FIG. 4) divided on the same plane in the internal electrode structure in FIG. 4 are integrally connected.

  Referring to FIG. 15, the first to sixth internal electrode layers 1110 ′, 1120 ′, 11130 ′, 1140 ′, 1150 ′, and 1160 ′ formed on the dielectric layer 1001 form one block. Each of the internal electrode layers 1110 ′ to 1160 ′ is formed of an undivided single structure, that is, one electrode plate, and each of the electrode plates is extended to two opposite side surfaces of the capacitor body. Two leads (leads 1111a and 1112a, leads 1121a and 1122a, leads 1131a and 1132a, leads 1141a and 1142a, leads 1151a and 1152a, leads 1161a and 1162a). One lead drawn on each side). The leads 1111a to 1162a provide connection of the electrode plate to the external electrodes (see the external electrodes 131 to 138 shown in FIG. 18), and electrically connect the internal electrode layers 1110 ′ to 1160 ′ to the external electrodes 131 to 138. To do.

  According to this embodiment, each internal electrode layer 1110 ′ to 1160 ′ has only two leads (leads 1111a and 1112a, leads 1121a and 1122a, leads 1131a and 1132a, leads 1141a and 1142a, leads 1151a and 1152a, leads 1161a, 1162a), the capacitor ESR can be set to an appropriate value without excessively small value.

  Further, since each internal electrode layer is composed of one electrode plate (undivided integral), there are few steps (or thickness differences) in the manufacturing process, and the adverse effects due to the steps are reduced. This embodiment shows a higher capacitance value than the embodiment with split slots, since there is no capacitance reduction due to split slots. Also in this embodiment, the leads (for example, the leads 1111a and 1121a) of electrode plates of different polarities adjacent to each other in the vertical direction are always arranged adjacent to each other in the horizontal direction. Therefore, it is possible to suppress the ESL increase factor. Similar to the embodiment of FIG. 4, in this embodiment, leads (for example, leads 1111a, 1121a, 1131a, 1141a, 1151a, 1161a) drawn out on one surface of the capacitor body are arranged in a zigzag shape along the stacking direction. .

  FIG. 16 is a plan view showing the internal electrode structure of the multilayer chip capacitor (8 terminals) according to the modification of FIG. In the embodiment of FIG. 16, the vertically adjacent leads (for example, leads 1211a and 1271a, leads 1221a and 1261a, leads 1231a and 1251a, leads 1232a and 1252a, etc.) connected to the same external electrode form a corner. While stretching in different directions. The internal electrode structure in FIG. 16 corresponds to a structure in which two electrode plates (for example, electrode plates 1211 and 1212 in FIG. 6) divided on the same plane in the internal electrode structure in FIG. 6 are integrally connected.

  Referring to FIG. 16, twelve internal electrode layers 1210 ′ to 1320 ′ formed on the dielectric layer 1002 are sequentially stacked to form one block. By repeatedly stacking these blocks, a capacitor body (see capacitor body 120 shown in FIG. 18) is formed. Each of the internal electrode layers 1210 ′ to 1320 ′ is composed of one electrode plate (a single electrode plate that is not divided), and each of the electrode plates has two leads (extracted on opposite side surfaces of the capacitor body) ( Leads 1211a and 1212a to leads 1321a and 1322a). The leads 1211a to 1322a provide connection of the electrode plate to external electrodes (see the external electrodes 131 to 138 shown in FIG. 18).

  Since each internal electrode layer 1210 ′ to 1320 ′ has only two leads, it is possible to prevent the phenomenon that the ESR of the capacitor becomes excessively low and the instability of the power supply circuit due to this phenomenon. In addition, since the leads (for example, the leads 1211a and 1221a) of the electrode plates having different polarities adjacent to each other are always arranged adjacent to each other in the horizontal direction, an increase factor of ESL can be suppressed. Since each of the internal electrode layers 1210 ′ to 1320 ′ is composed of one electrode plate that is not divided, there is little generation of a step in the manufacturing process, and an adverse effect due to the step is reduced. Since there is no reduction in capacitance due to the dividing slot, this embodiment shows a higher capacitance value than the embodiment with the dividing slot. Also in this embodiment, leads (for example, leads 1211a, 1221a, 1231a, 1241a, 1251a, 1261a, 1271a, 1281a, 1291a, 1301a, 1311a, and 1321a) drawn to one surface of the capacitor body are zigzag along the stacking direction. Placed in.

  In particular, in the present embodiment, adjacent leads (for example, leads 1211a and 1271a, leads 1221a and 1261a, leads 1231a and 1251a, leads 1232a and 1252a, etc.) connected to the same external electrode extend while forming an angle. ing. Such a feature is clearly shown in the partially enlarged view of FIG. As shown in FIG. 17, the leads 1211a and 1271a adjacent to the top and bottom (stacking direction) connected to the external electrode 131 extend in different directions while forming a predetermined angle (α). Preferably, this angle (α) is between 45 and 135 degrees.

  When leads 1211a and 1271a adjacent to each other connected to the same external electrode extend in different directions while forming an angle (α), currents flow in different directions through the adjacent leads 1211a and 1271a. Therefore, an effect of suppressing the phenomenon that the magnetic flux is reinforced between the adjacent leads 1211a and 1271a is obtained, and generation of strong mutual inductance is prevented between adjacent leads connected to the same external electrode. Eventually, the ESL of the capacitor is further reduced.

  19 to 22 show an internal electrode structure of a 10-terminal multilayer chip capacitor according to an embodiment of the present invention. The outline of such a 10-terminal capacitor is shown in FIG. Referring to FIG. 23, the capacitor 200 includes ten external electrodes 231 to 240 formed on the outer surface of the capacitor body 220. External electrodes having different polarities are alternately arranged on the outer surface of the capacitor body 220.

  Referring to FIG. 19, the eight internal electrode layers 2010 to 2080 formed on the dielectric layer 2000 are sequentially stacked to form one block. A capacitor body (see capacitor body 220 in FIG. 23) is configured by repeatedly stacking these blocks. Each of the internal electrode layers 2010 to 2080 is divided into two electrode plates (for example, electrode plates 2011 and 2012) on the same plane by dividing slots. Two electrode plates (for example, electrode plates 2011 and 012) on the same plane have different polarities. Two electrode plates (for example, electrode plates 2011 and 2021) opposed to each other through the dielectric layer 2000 constitute one capacitor element.

  As shown in FIG. 19, each electrode plate (eg, electrode plate 2011) has only one lead (eg, lead 2011a). Leads 2011a-2082a provide connection of the electrode plate to external electrodes (see external electrodes 231-240 shown in FIG. 23), and electrically connect internal electrode layers 2010-2080 to external electrodes 231-240. Also in this embodiment, leads (for example, leads 2011a, 2021a, 2031a, 2041a, 2051a, 2061a, 2071a, and 2081a) drawn to one surface of the capacitor body are arranged in a zigzag shape along the stacking direction. Specifically, the first to fifth leads 2011a, 2021a, 2031a, 2041a, and 2051a are disposed to connect to the first to fifth external electrodes 231, 232, 233, 234, and 235, respectively, and the sixth lead 2061a. Is arranged to connect to the fourth external electrode 234, the seventh lead 2071a is arranged to connect to the third external electrode 233, and the eighth lead 2081a is arranged to connect to the second external electrode 232. .

  According to the present embodiment, each internal electrode layer is divided into two electrode plates and each electrode plate has only one lead, so that the ESR of the capacitor is maintained at an appropriate value. As a result, instability of the power supply circuit due to excessively low ESR can be prevented.

  In addition, the leads (for example, the leads 2011a and 2021a) of the electrode plates (for example, the electrode plates 2011 and 2021) that are adjacent to each other in the upper and lower sides are always arranged adjacent to each other in the horizontal direction. That is, the leads of the electrode plates with different polarities adjacent to each other are always connected to the external electrodes adjacent in the horizontal direction. For example, the lead 2011a and the lead 2021a are respectively connected to the external electrode 231 and the external electrode 232 that are adjacent to each other. Therefore, the ESL increase factor of the capacitor can be suppressed. In addition, the leads drawn out on one surface of the capacitor body are arranged in a zigzag shape along the stacking direction. Eventually, along with maintaining the suitable ESR value, the further reduced ESL further improves the stability of the power supply circuit.

  FIG. 20 shows an internal electrode structure of a 10-terminal capacitor according to another embodiment. The embodiment of FIG. 20 is distinguished from the above-described embodiment of FIG. 19 in that two electrode plates on the same plane have the same polarity.

  Referring to FIG. 20, each internal electrode layer 2110 to 2180 formed on the dielectric layer 2001 is divided into two electrode plates (for example, electrode plates 2111 and 2112) on the same plane by dividing slots. Yes. Each electrode plate (eg, electrode plate 2111) has only one lead (eg, lead 2111a). Leads 2111a to 2182a provide connection of the electrode plate to external electrodes (see external electrodes 231 to 240 shown in FIG. 23), and electrically connect internal electrode layers 2110 to 2180 to external electrodes 231 to 240.

  FIG. 21 is a side view showing the arrangement of leads drawn to one surface in the capacitor of FIG. As shown in FIG. 21, leads (for example, leads 2111a, 2121a, 2131a, 2141a, 2151a, 2161a, 2171a, and 2181a) drawn to one surface of the capacitor body are arranged in a zigzag shape along the stacking direction (FIG. 21). See dotted line). Therefore, as described above, the mutual inductance between the leads connected to the same external electrode is suppressed, so that the ESL can be further reduced. According to this embodiment, similarly to the embodiment of FIG. 19, a low ESR value can be obtained together with a suitable ESR value. In FIG. 21, the reference symbol D ′ indicates the distance between the leads 2181a.

  FIG. 22 shows an internal electrode structure of a 10-terminal multilayer chip capacitor according to still another embodiment. In the embodiment of FIG. 22, each internal electrode layer consists of one electrode plate that is not divided. The internal electrode structure in FIG. 22 corresponds to a structure in which two planar electrode plates (for example, electrode plates 2111 and 2112 in FIG. 20) are integrally connected in the internal electrode structure in FIG.

  Referring to FIG. 22, eight internal electrode layers 2110 ′, 2120 ′, 21130 ′, 2140 ′, 2150 ′, 2160 ′, 2170 ′, and 2180 ′ formed on the dielectric layer 2001 respectively constitute one block. To do. Each of the internal electrode layers 2110 ′ to 2180 ′ is composed of one non-divided electrode plate, and each of the electrode plates has two leads (leads 2111a and 2112a to 2111a to 2111a) led out to the opposite side surfaces of the capacitor body. (That is, each of the electrode plates has one lead drawn to each of the opposite side surfaces). The leads 2111a to 2182a provide connection of the electrode plate to external electrodes (see the external electrodes 231 to 240 shown in FIG. 23), and electrically connect the internal electrode layers 2110 ′ to 2180 ′ to the external electrodes 231 to 240. To do.

  According to the present embodiment, each internal electrode layer 2110 ′ to 2180 ′ has only two leads (leads 2111a and 2112a, leads 2121a and 2122a, leads 2131a and 2132a, leads 2141a and 2142a, leads 2151a and 2152a, leads 2161a and 2162a, leads 2171a and 2172a, and leads 2181a and 2182a), the capacitor ESR can be set to an appropriate value without being excessively small.

  Further, since each internal electrode layer is made of a single piece (one electrode plate) that is not divided, there are few steps in the manufacturing process, and adverse effects due to steps are reduced. This embodiment shows a higher capacitance value than the embodiment with split slots, since there is no capacitance reduction due to split slots. Also in this embodiment, the leads (for example, the leads 2111a and 2121a) of electrode plates of different polarities adjacent to each other in the vertical direction are always arranged adjacent to each other in the horizontal direction. Therefore, an increase factor of ESL can be suppressed. Also in this embodiment, leads (for example, leads 2111a, 2121a, 2131a, 2141a, 2151a, 2161a, 2171a, and 2181a) drawn to one surface of the capacitor body are arranged in a zigzag shape along the stacking direction.

  FIG. 24 shows an internal electrode structure of a multilayer chip capacitor according to still another embodiment of the present invention. The capacitor of FIG. 24 corresponds to the internal electrode structure of an 8-terminal multilayer chip capacitor, and has an outer shape as shown in FIG. 18, for example.

  Referring to FIG. 24, the first to eighth internal electrode layers 1610 to 1680 sequentially disposed on the dielectric layer 1006 form one block. Within this block, of the eight internal electrode layers, two internal electrode layers have two leads and the other six internal electrode layers have only one lead. That is, each of the fourth internal electrode layer 1640 and the eighth internal electrode layer 1680 has a total of two leads (leads 1641a and 1642a, leads 1681a and 1682a) extending on both side surfaces of the capacitor body, and the other first to first Each of the third internal electrode layers 1610 to 1630 and the fifth to seventh internal electrode layers 1650 to 1670 has only one lead (the leads 1610a to 1630a and the leads 1650a to 1670a).

  In particular, in this embodiment, the fourth internal electrode layer 1640 and the eighth internal electrode layer 1680 are divided into two electrode plates (electrode plates 1641 and 1642, electrode plates 1681 and 1682) by dividing slots. The first to third internal electrode layers 1610 to 1630 and the fifth to seventh internal electrode layers 1650 to 1670 are formed of one non-divided electrode plate.

  Also in this embodiment, the leads of electrode plates having different polarities adjacent to each other are always adjacent along the horizontal direction. In order to realize such a feature, the capacitor shown in FIG. 24 employs the following lead arrangement structure.

  The leads 1610a to 1630a of the first to third internal electrode layers 1610 to 1630 are arranged so as to be sequentially adjacent in the horizontal direction. That is, the positions of the lead 1610a of the first internal electrode layer 1610, the lead 1620a of the second internal electrode layer 1620, and the lead 1630a of the third internal electrode layer 1630 on the upper side of the rectangular dielectric layer 1006 are horizontal (stacked). The distance from the angle formed by the left side and the upper side of the dielectric layer 1006 is in the order of the first internal electrode layer 1610, the second internal electrode layer 1620, and the third internal electrode layer 1630. It is set to be large. As a result, the leads 1610a to 1630a are arranged so as to be sequentially adjacent in the horizontal direction. Similarly, the leads 1650a to 1670a of the fifth to seventh internal electrode layers 1650 to 1670 are also arranged so as to be sequentially adjacent in the horizontal direction.

  The first lead 1641a of the fourth internal electrode layer 1640 is disposed adjacent to the lead 1630a of the third internal electrode layer 1630 in the horizontal direction. The second lead 1642a of the fourth internal electrode layer 1640 is disposed adjacent to the lead 1650a of the fifth internal electrode layer 1650 in the horizontal direction. Accordingly, the leads 1641a and 1642a of the fourth internal electrode layer 1640 are in the horizontal direction with the leads 1630a and 1650a of the third and fifth internal electrode layers (that is, the internal electrode layers vertically adjacent to the fourth internal electrode layer). They are arranged adjacent to each other.

  The third lead 1681a of the eighth internal electrode layer 1680 shown in FIG. 24 is disposed so as to be adjacent to the lead 1610a (NB) of the first internal electrode layer 1610 (NB) of the adjacent block (NB) in the horizontal direction. . The fourth lead 1682a of the eighth internal electrode layer 1680 is disposed so as to be adjacent to the lead 1670a of the seventh internal electrode layer 1670 in the horizontal direction. Therefore, the leads 1681a and 1682a of the eighth internal electrode layer 1680 are the same as the leads 1610a (NB) and 1670a of the first and seventh internal electrode layers (that is, internal electrode layers vertically adjacent to the eighth internal electrode layer). They are arranged adjacent to each other in the horizontal direction.

  Eventually, due to the overall internal structure of the capacitor, the leads of the electrode plates with different polarities adjacent to each other are always arranged adjacent to each other in the horizontal direction. This reduces the ESL of the capacitor due to flux cancellation between adjacent different polarity leads. Further, since each internal electrode layer has only one or two leads, the ESR of the capacitor can be set to an appropriate value without becoming an excessively small value.

  In addition, by disposing the internal electrode layers 1610, 1620, 1630, 1650, 1660, 1670 that are not divided between the internal electrode layers 1640, 1680 having divided slots, the applied pressure in the pressurizing and firing stages is reduced. Uniformity can be ensured and delamination can be greatly suppressed.

  FIG. 25 shows an internal electrode structure of a multilayer chip capacitor corresponding to the modification of FIG. The embodiment of FIG. 25 corresponds to a structure in which two electrode plates (electrode plates 1641 and 1642, electrode plates 1681 and 1682) divided on the same plane in the internal electrode structure of FIG. 24 are integrally connected.

  Referring to FIG. 25, the first to eighth internal electrode layers 1610, 1620, 1630, 1640 ′, 1650, 1670, and 1680 ′ are sequentially stacked to form one block. Each internal electrode layer comprises an undivided one electrode plate, each electrode plate having a lead that provides connection of the electrode plate to the external electrode.

  Each of the fourth internal electrode layer 1640 ′ and the eighth internal electrode layer 1680 ′ has a total of two leads (leads 1641a and 1642a, leads 1681a and 1682a) extending on both side surfaces of the capacitor body, and the other first Each of the third to third internal electrode layers 1610 to 1630 and the fifth to seventh internal electrode layers 1650 to 1670 has only one lead (lead 1610a to 1630a, lead 1650a to 1670a).

  The leads 1610a to 1630a of the first to third internal electrode layers 1610 to 1630 are sequentially arranged adjacent to each other along the horizontal direction, and the leads 1650a to 1670a of the fifth to seventh internal electrode layers 1650 to 1670 are also horizontal. It arrange | positions so that it may adjoin sequentially along a direction.

  The lead 1641a of the fourth internal electrode layer 1640 ′ is disposed so as to be adjacent to the lead 1630a of the third internal electrode layer 1630 in the horizontal direction, and the lead 1642a of the fourth internal electrode layer 1640 ′ is the lead of the fifth internal electrode layer 1650. The lead 1650a is disposed so as to be adjacent in the horizontal direction.

  The lead 1681a of the eighth internal electrode layer 1680 ′ is disposed so as to be adjacent to the lead 1610a (NB) of the first internal electrode layer 1610 (NB) of the adjacent block (NB) in the horizontal direction, and the eighth internal electrode layer The lead 1682a of 1680 ′ is disposed so as to be adjacent to the lead 1670a of the seventh internal electrode layer 1670 in the horizontal direction.

  Eventually, due to the overall internal structure of the capacitor, the leads of the electrode plates with different polarities adjacent to each other are always arranged adjacent to each other in the horizontal direction. Therefore, an increase factor of ESL can be suppressed. Further, since each internal electrode layer has only one or two leads, the ESR of the capacitor can be set to an appropriate value without becoming an excessively small value.

  In addition, each internal electrode layer consists of a single electrode plate (undivided integral electrode plate), so that there are few steps (or thickness differences) in the manufacturing process, and the adverse effects of steps are reduced. The Since there is no capacitance reduction due to the split slots, higher capacitance values are shown.

  The present invention is not limited by the above-described embodiment and the accompanying drawings, but is limited by the appended claims, and various forms are possible within the scope of the technical idea of the present invention described in the claims. It is obvious to those skilled in the art that substitutions, modifications and changes can be made. For example, it goes without saying that the shape of the internal electrodes and the number of external electrodes that can be employed in the multilayer capacitor of the present invention may be different from those of the above-described embodiments.

100, 200 Multilayer chip capacitor 120, 220 Capacitor body 131-138, 231-240 External electrode 1000-1002, 1004-1008, 2000, 2001, 3001, 4000
, 4001 Dielectric layer 1010 Internal electrode layer 1011, 1012 Electrode plate 1011a, 1012a Lead

Claims (24)

A capacitor body formed by laminating a plurality of dielectric layers;
A plurality of electrodes disposed in the capacitor body separated from each other by the dielectric layer, each including at least one electrode plate on the same plane, each having one or two leads extending toward an outer surface of the capacitor body; An internal electrode layer of
Including at least three or more external electrodes formed on the outer surface of the capacitor body and electrically connected to the electrode plate via the leads;
At least four or more internal electrode layers in which one lead of the one electrode plate is continuously arranged up and down form one basic structure (block), and the blocks are repeatedly stacked.
Each of the electrode plates has only one lead drawn to one surface where external electrodes of different polarities are alternately arranged on each of the two side surfaces facing the capacitor body,
In the one block, one lead of the electrode plate is zigzag along the stacking direction of the block, and the external electrodes having different polarities are alternately arranged on each of the two side surfaces facing the capacitor body. The leads of the electrode plates of different polarities adjacent to each other arranged vertically are always arranged adjacent to each other in the horizontal direction,
When the number of the external electrodes is increased by 1 on one side of the capacitor, the number of internal electrodes forming the block is increased by 2;
In the block, the lead exposed from one surface of the capacitor body is continuous in one direction of the one surface of the capacitor body and in the opposite direction of the stacking direction by the number of external electrodes, and one is subtracted from the number of external electrodes. A multilayer chip capacitor characterized in that it is defined that a portion is continuous in a direction opposite to one direction and in a direction opposite to the stacking direction. The external electrodes form six 6-terminal capacitors, one on each side of the capacitor body and three on the opposite side of the one side.
The one block is composed of four internal electrode layers arranged continuously in the vertical direction, and one lead formed on each electrode plate has external electrodes of different polarities on each of two side surfaces facing the capacitor body. The multilayer chip capacitor according to claim 1, wherein the multilayer chip capacitor is drawn on one surface arranged alternately. First to fifth external electrodes are sequentially disposed on one surface of the capacitor body,
In the one block, first to eighth electrode plates each having one lead drawn to the one surface of the capacitor body are sequentially stacked.
The leads of the first to fifth electrode plates are arranged to be connected to the first to fifth external electrodes, respectively.
The lead of the sixth electrode plate is arranged to be connected to the fourth external electrode, the lead of the seventh electrode plate is arranged to be connected to the third external electrode, and the lead of the eighth electrode plate The multilayer chip capacitor according to claim 1, wherein the lead is disposed so as to be connected to the second external electrode.   2. The multilayer chip capacitor according to claim 1, wherein the upper and lower adjacent leads connected to the same external electrode extend in different directions while forming a corner. 5. The multilayer chip capacitor according to claim 4 , wherein the adjacent leads connected to the same external electrode extend in different directions while forming an angle of 45 to 135 degrees.   2. Each of the internal electrode layers is divided into a plurality of the electrode plates on the same plane by dividing slots, and each of the electrode plates has a lead connected to the external electrode. A multilayer chip capacitor according to 1.   2. The multilayer chip capacitor according to claim 1, wherein each of the internal electrode layers is divided into two electrode plates on the same plane by the division slots. 8. The multilayer chip capacitor according to claim 7 , wherein the two electrode plates on the same plane have different polarities. The multilayer chip capacitor according to claim 7 , wherein the two electrode plates on the same plane have the same polarity. The multilayer chip capacitor according to claim 6 , wherein the divided slot extends parallel to a longitudinal direction of the capacitor body. The multilayer chip capacitor according to claim 6 , wherein the plurality of electrode plates on the same plane have the same area. The multilayer chip capacitor according to claim 6 , wherein the plurality of electrode plates on the same plane have different areas. Plane position of the divided slots of the internal electrode layer adjacent to the vertically and being different from each other, multilayer chip capacitor of claim 1 2. The multilayer chip capacitor according to claim 12 , wherein in-plane positions of the divided slots of the internal electrode layers adjacent to each other are the same. 9. The multilayer chip capacitor according to claim 8 , wherein the divided slot of the internal electrode layer extends in a diagonal direction of the capacitor body. 16. The multilayer chip capacitor according to claim 15 , wherein the divided slots of the internal electrode layers adjacent to each other vertically extend in different diagonal directions. 7. The multilayer chip capacitor according to claim 6 , wherein the divided slots of the internal electrode layers adjacent to each other in the vertical direction are arranged in parallel to each other in a direction orthogonal to each other. The division slot arranged parallel to the longitudinal direction of the capacitor body and the division slot arranged perpendicular to the longitudinal direction of the capacitor body are alternately arranged in the stacking direction. 18. A multilayer chip capacitor according to item 17 . The non-divided slot is formed on each of the electrode plates so as to change the flow of current in the electrode plate from one side surface to the center side of the electrode plate. 6. The multilayer chip capacitor according to 6 . 20. The multilayer chip capacitor according to claim 19 , wherein the divided slot and the non-divided slot extend parallel to a longitudinal direction of the capacitor body. The multilayer chip capacitor of claim 19 , wherein in-plane positions of the non-divided slots of the electrode plates adjacent to each other coincide with each other. 20. The multilayer chip capacitor according to claim 19 , wherein currents in opposite directions flow in regions adjacent to each other of the two electrode plates on the same plane. 20. The multilayer chip capacitor of claim 19 , wherein currents in opposite directions flow through the electrode plates adjacent to each other in the vertical direction. The multilayer chip capacitor according to any one of claims 1 to 23 , wherein a lowermost lead of the block and an uppermost lead of a block continuous with the block are adjacent in a horizontal direction. .

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