JP5172417B2 - Manufacturing method of silicon structure, manufacturing apparatus thereof, and manufacturing program thereof - Google Patents

Description

  The present invention relates to a method of manufacturing a silicon structure, a manufacturing apparatus thereof, and a manufacturing program thereof.

  The technical field to which MEMS (Micro Electro Mechanical Systems) devices using silicon are applied is steadily expanding, and in recent years, the technology has been applied not only to micro turbines and sensors but also to information communication field and medical field. Yes. One of the main elemental technologies that support this MEMS technology is anisotropic dry etching of silicon, and it can be said that the development of this elemental technology supports the development of MEMS technology. Although the technology of anisotropic dry etching of silicon has made great progress over the past few years, the demand for the formation of openings with a high aspect ratio is still not declining. Recently, when grooves and holes are formed, there is a strict requirement for an etching shape typified by a sidewall shape as well as an aspect ratio. In particular, when forming a groove or hole having a submicron opening width, it is very difficult to satisfy both requirements of a high aspect ratio and a high perpendicularity.

  Conventionally, as a means to form grooves and holes with high perpendicularity and high aspect ratio openings with respect to silicon material, parameters (gas flow rate, pressure, RF output, etc.) that determine etching conditions change with time. Is disclosed (see Patent Documents 1 and 2). However, the mode of change disclosed by these methods is a periodic or linear change. Also, there is no suggestion as to when the change should occur. Furthermore, there is no suggestion about the problem of consumption of an etching mask (hereinafter also simply referred to as a mask) by the above-described method.

In particular, consumption of an etching mask is one of the important problems that greatly affects the formation of grooves and holes having high aspect ratio openings. This is because it becomes difficult to achieve a high aspect ratio when the mask consumption by the etching process increases.
Japanese Patent Laid-Open No. 10-135192 JP-A-10-144654

  As described above, when an opening having a high aspect ratio is to be formed, it is not only necessary to solve the side wall erosion prevention for enhancing the verticality, but consideration must be given to the depletion of the mask.

  The problem of high verticality becomes apparent particularly in grooves and holes having openings with a high aspect ratio. This is because, in the case of openings with a high aspect ratio, the deeper the etched grooves and holes, the narrower the taper phenomenon, in other words, the narrower the width of their bottoms compared to the width of their openings (tops). This is because the phenomenon becomes easier to occur. Therefore, how to increase the width of the bottom portion without causing an abnormal shape of the side wall is an important issue.

  On the other hand, with respect to the problem of mask exhaustion, for example, a means of providing a sufficient etching mask thickness from the beginning can be considered. However, it is not easy to make the taper shape of the mask edge of the thick etching mask steep on the entire surface of the substrate. In order to obtain a high aspect ratio, it is preferable to use a silicon oxide film having high etching resistance as an etching mask. However, if this silicon oxide film is to be thickened, it becomes very difficult to form a mask capable of obtaining a sufficient selection ratio during anisotropic etching of the oxide film itself. Therefore, a decrease in production speed and yield caused by manufacturing various special masks as described above is inevitable.

  The present invention solves such technical problems and enables the formation of trenches and holes having high aspect ratio openings with high perpendicularity, thereby further improving the anisotropic dry etching performance of silicon. Contributes to improvement.

  The inventor first carefully compared and observed the shapes of the bottom and side walls of the grooves and holes in the initial time zone of the etching and the shapes of the bottom and side walls after the etching time had sufficiently passed while changing the etching time. . As a result, when forming an opening with a high aspect ratio, the etching conditions required in a certain time zone at the beginning of etching are obtained when the bottom of the groove or hole is etched deeper after a sufficient etching time has elapsed. It was found that the conditions should be different.

  Specifically, at the beginning of etching, even if the incidence of ions in the plasma formed from the etching gas to the substrate is weakened to some extent, the etching performance such as the sidewall and bottom shape is not impaired. However, after a considerable time has elapsed from the start of etching, it has become clear that satisfactory sidewall and bottom shapes cannot be obtained unless the incidence is increased with time. This is because the chemical reaction between the ions and radicals and the silicon surface at the bottom of the groove or hole occurs relatively easily at the beginning of etching, even if the above-described weak ions are incident, but at the bottom of the deep groove or hole. This is because it is considered that a fairly strong ion incidence is required for the chemical reaction with the silicon surface and the removal of organic deposits. In particular, in the case of a groove or hole having an opening with a high aspect ratio, as the etching depth becomes deeper, the incident of the ions is nonlinearly enhanced, so that a remarkable improvement in the shape of the bottom thereof has been confirmed. . In addition to this knowledge, the inventors have also found that the difference in etching conditions significantly affects the consumption of the mask, particularly at the beginning of etching. The present invention has been created based on the above-described findings.

  One method of manufacturing a silicon structure according to the present invention is a process of etching silicon using plasma formed by alternately introducing an etching gas and an organic deposit forming gas, and a predetermined time from the start of the etching, The first power application step for making the applied power to the substrate constant when the etching gas is introduced, and the second power application for increasing the applied power to the substrate when the etching gas is introduced after the predetermined time has elapsed. Process.

  According to this manufacturing method, the power applied to the substrate during etching is kept low for a predetermined time from the start of etching as compared to after the predetermined time has elapsed. As a result, since the incidence of ions on the substrate at the beginning of etching is weakened, consumption of the mask is suppressed, while good shapes of the side walls and bottom of the grooves and holes are maintained. Further, after the predetermined time has elapsed, it is thought that by increasing the ion incidence with time, the chemical reaction with the silicon surface at the bottom of deep grooves and holes and the removal of organic deposits are promoted, resulting in highly perpendicular etching. Shape and high mask selectivity are achieved simultaneously.

  The silicon structure manufacturing program of the present invention is a process for etching silicon using plasma formed by alternately introducing an etching gas and an organic deposit forming gas, and is predetermined from the start of the etching. A first power application step for making the applied power to the substrate constant when the etching gas is introduced, and a second power for increasing the applied power to the substrate when the etching gas is introduced after the predetermined time has elapsed. A power application step.

  By executing this program, the power applied to the substrate during etching is kept low for a predetermined time from the start of etching as compared to after the predetermined time has elapsed. As a result, since the incidence of ions on the substrate at the beginning of etching is weakened, consumption of the mask is suppressed, while good shapes of the side walls and bottom of the grooves and holes are maintained. Furthermore, after the predetermined time has elapsed, the program is designed to increase the incidence of ions with time, thereby promoting the chemical reaction with the silicon surface at the bottom of deep grooves and holes and the removal of organic deposits. In addition, a highly perpendicular etching shape and a high mask selectivity can be achieved at the same time.

  By the way, in the present application, “high aspect ratio” means a case where the aspect ratio is 10 or more in hole etching, and more narrowly means a case where the aspect ratio is 15 or more than 15. On the other hand, in trench etching, “high aspect ratio” means that the aspect ratio is 15 or more, and more narrowly means that the aspect ratio is 20 or more than 20. In addition, the upper limit of the aspect ratio obtained by the present application is not particularly limited, but a value calculated by the relationship with the thickness of silicon that is the material to be etched will be the upper limit.

  In the present invention, the “hole” includes not only a circular hole in the shape of the mask pattern on the outermost surface of the substrate but also an elliptical or square hole. More specifically, “hole” in the present invention means, for example, in the case of a square hole, the relationship between the long side and the short side means that the short side is 1 and the long side is up to 3 or less. In the present invention, “trench” means holes other than “holes”.

  According to the manufacturing method, manufacturing apparatus, or manufacturing program of the present invention, a highly perpendicular etching shape and a high mask selectivity can be achieved simultaneously in dry etching of silicon.

  Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In this description, common parts are denoted by common reference symbols throughout the drawings unless otherwise specified. In the drawings, the elements of the present embodiment are not necessarily shown to scale. Unless otherwise specified, the flow rates of the following various gases indicate the flow rates in the standard state.

<First Embodiment>
FIG. 1 is a cross-sectional view showing an example of a device configuration of a silicon structure manufacturing apparatus 100 (hereinafter also simply referred to as a manufacturing apparatus 100) according to the present embodiment. FIG. 2 is a graph showing the change over time of the applied power in the etching process for the silicon substrate in the present embodiment. 3A to 3C are cross-sectional views showing a process of the method for manufacturing the silicon structure 10 in the present embodiment.

  First, the configuration of the silicon structure manufacturing apparatus 100 shown in FIG. 1 will be described. A silicon substrate W to be etched (hereinafter also simply referred to as a substrate W) is placed on a stage 21 provided on the lower side of the chamber 20. The chamber 20 is supplied with at least one gas selected from an etching gas and an organic deposit forming gas (hereinafter also referred to as a protective film forming gas) from the cylinders 22a and 22b through gas flow controllers 23a and 23b, respectively. The These gases are turned into plasma by the coil 24 to which high frequency power is applied by the first high frequency power supply 25. Thereafter, high-frequency power is applied to the stage 21 using the second high-frequency power source 26, so that the generated plasma is drawn into the substrate W. A vacuum pump 27 is connected to the first process chamber 20 via an exhaust flow rate regulator 28 in order to decompress the inside of the chamber 20 and exhaust a gas generated after the process. The exhaust flow rate from the chamber 20 is changed by an exhaust flow rate regulator 28. The gas flow regulators 23 a and 23 b, the first high frequency power supply 25, the second high frequency power supply 26, and the exhaust flow regulator 28 are controlled by the control unit 29.

Next, the manufacturing process of the silicon structure 10 of this embodiment will be described. First, for anisotropic dry etching of silicon, this embodiment employs a method of sequentially repeating a protective film forming process in which a protective film forming gas is introduced and an etching process in which an etching gas is introduced. In this embodiment, the protective film forming gas is C ₄ F ₈ and the etching gas is SF ₆ .

  In this embodiment, in the protective film forming step, the protective film forming gas is 200 mL / min. In 2.5 seconds, which is a processing time as one unit time. The pressure in the chamber 20 is controlled to 4.65 Pa. A high frequency power of 13.56 MHz is applied to the coil 24 at 1800 W, but a high frequency power of 13.56 MHz is not applied to the stage 21. On the other hand, in the subsequent etching process, the etching gas is 300 mL / min. In 2 seconds, which is the processing time as one unit time. The pressure in the chamber 20 is controlled to 4 Pa. The coil 24 is applied with 3200 W of high frequency power of 13.56 MHz. On the other hand, as shown in FIG. 2, 120 W of high frequency power of 13.56 MHz is applied to the stage 21 for 5 minutes from the start of etching, but after 5 minutes, the applied power increases stepwise. It reaches 180 W at the end of etching. Here, the above-mentioned stepwise rise is set so that the difference in level, in other words, the applied power, increases with the passage of time. That is, the relationship between (a) to (d) in FIG. 2 is (a) <(b) <(c) <(d). In the present embodiment, the temperature of the fluid flowing in a chiller (not shown) for cooling the stage 21 is set to 0 ° C.

  Here, a more specific manufacturing method of the silicon structure 10 of the present embodiment will be described with reference to FIGS. 3A to 3C. In the etching process for 5 minutes from the start of etching, an etching condition is selected that places greater importance on suppressing mask consumption due to ion incidence than on the etching rate. That is, in this embodiment, as shown in FIG. 3A, anisotropic etching of the silicon substrate is performed by applying 120 W during the etching process. At this stage, even if the power applied to the silicon substrate W is low, it is relatively easy to remove the protective film at the bottom 16 of the etched silicon trench or hole, in other words, the organic deposit. On the other hand, since the applied power is low, the consumption of the mask 12 is suppressed. Further, as described above, since the power applied to the substrate W is low, an abnormal shape of the silicon side wall 14 due to the oblique incidence of ions (for example, a decrease in the verticality of the side wall 14 due to the disappearance of the protective film on the side wall) is almost seen. Absent.

Next, after 5 minutes from the start of etching, the value of the applied power to the substrate W increases stepwise. In the etching step in the initial stage of the step-like increase (from 5 minutes after the start of etching until 8 minutes in the present embodiment), as shown in FIG. 2, the increase in the applied power is relatively small. However, the small increase in the applied power facilitates the removal of the protective film on the bottom portion 16, which is generally difficult to remove as etching progresses. In addition, since the applied power to the substrate W is started to increase from this stage, a thicker mask 12 is left as compared with the case where the applied power is started to increase from the beginning of etching. At this stage, as shown in FIG. 3B, an abnormal shape of the silicon side wall 14 due to the oblique incidence of ions begins to occur, so the distance L ₂ between the side walls 14 in the vicinity of the opening is less than the initial width L _1. Spread a minute. However, in this embodiment, since the applied power to the substrate W is started to increase after 5 minutes have elapsed from the start of etching, the width of the spread is small compared to the case where the applied power is started to increase from the beginning of etching. .

Thereafter, in the etching process in the final stage of the step-like increase (from 8 minutes after the start of etching until 10 minutes in the present embodiment), as shown in FIG. large. However, this significant increase in applied power facilitates the removal of the protective film on the bottom 16 which is generally difficult to remove at the bottom 16 of a groove or hole having a high aspect ratio opening. That is, as shown in FIG. 3C, in the present embodiment, the applied power to the substrate W is increased nonlinearly. As a result, a sufficient gap (L in FIG. 3C) is maintained at the bottom 16 of the groove or hole while maintaining a high mask selection ratio. ₄ ) can be obtained. In other words, if a linear increase in applied power is employed as in the prior art, not only the mask selectivity is deteriorated, but also a part of the protective film is formed on the bottom 16 of the groove or hole having an opening with a high aspect ratio. As a result, the above-mentioned tapering phenomenon occurs. In addition, since the power applied to the substrate W is significantly increased in the final stage, consumption of the mask 12 can be remarkably suppressed. On the other hand, at this stage, as shown in FIG. 3C, the abnormal shape of the silicon side wall 14 due to the oblique incidence of non-linearly strengthened ions proceeds, so the distance L ₃ between the side walls 14 near the opening is the initial width. It spreads compared to L _1.

  Here, as an experiment, a comparative example in which anisotropic etching of the silicon substrate W was performed under the same conditions as in the present embodiment except that the applied power was set to increase linearly as shown in FIG. Contrast with this embodiment.

  Table 1 shows a result of comparing the silicon structure formed by the etching of the above-described comparative example with the silicon structure of the present embodiment when focusing on a groove having an opening with a width of about 0.5 μm as an example. Yes.

  As shown in Table 1, it can be seen that the silicon structure 10 of the present embodiment has a significantly improved mask selectivity as compared with the comparative example. This is because, as described above, the voltage applied to the substrate W was not increased for a predetermined time at the beginning of etching. By improving the mask selection ratio by the manufacturing method of the present embodiment, even if the silicon oxide film has conventionally been used as a mask, a resist mask can be substituted in some cases. Although the reason is not clear at this time, in the present embodiment, the etching rate is finally higher than that of the comparative example even though the voltage applied to the substrate W is not increased for a predetermined time at the beginning of etching. Yes. This improvement in the etching rate greatly contributes to the improvement in productivity.

Furthermore, in the silicon structure 10 of the present embodiment, the width of the bottom 16 of the groove (L _{4 in} FIG. 3C) is wider than that of the comparative example. This solves the so-called taper problem. By the way, in the above-mentioned experiment, the silicon structure 10 of the present embodiment is inferior to the comparative example at first glance in terms of verticality. However, when a high aspect ratio opening exceeding this experiment is formed, the present embodiment in which the protective film is more surely removed from the bottom of the groove or hole is superior in terms of verticality. In Table 1, “CD loss” has the same meaning as defined in FIG. 3 of JP-A-10-135192. The “side wall angle” in Table 1 is an angle represented by θ shown in FIG. The actual side wall is not a straight side wall as shown in FIG. Therefore, after measuring the upper groove width (L ₃ ), the lower groove width (L ₄ ), and the groove depth (D) in FIG. 3C, assuming that the side wall is pseudo linear, The side wall angle (θ) is calculated by the mathematical formula shown below.

  Here, for reference, scanning electron microscope (hereinafter referred to as SEM) photographs of the upper and lower cross-sections of the grooves in the silicon structure 10 of the present embodiment are shown in FIGS. 5A and 5B. In addition, in FIG. 5B which shows the lower cross section of a groove | channel, it adds that the groove | channel seems to be distorted because the silicon | silicone was not cut | disconnected perpendicularly downward and the SEM photograph was not image | photographed from the front of the groove | channel. deep.

  Incidentally, the control unit 29 provided in the above-described manufacturing apparatus 100 is connected to the computer 60. The computer 60 monitors or comprehensively controls each process described above by the manufacturing program of the silicon structure 10 for executing each process described above. Hereinafter, a manufacturing program for the silicon structure 10 will be described with reference to a specific manufacturing flowchart. In the present embodiment, the above-described manufacturing program is stored in a known recording medium such as an optical disk inserted in a hard disk drive in the computer 60 or an optical disk drive provided in the computer 60. The storage destination of is not limited to this. For example, a part or all of this manufacturing program may be stored in the control unit 29 provided in each process chamber in the present embodiment. The manufacturing program can also monitor or control each of the processes described above via a known technique such as a local area network or an Internet line.

  FIG. 6 is a manufacturing flowchart of the silicon structure 10 of this embodiment.

  As shown in FIG. 6, first, in step S <b> 101, after the substrate W is transferred into the chamber 20, the gas in the chamber 20 is exhausted. Thereafter, in steps S102 to S104, the substrate W is anisotropically dry etched in the chamber 20 under the above-described conditions.

  Specifically, first, in step S102, the etching of this embodiment is started. Until 5 minutes have elapsed from the start of etching, a constant power (120 W) is applied to the substrate W in the etching process as shown in step S103. After 5 minutes have elapsed from the start of etching, power is applied so that the applied power increases stepwise with respect to the substrate W in the etching process, as shown in step S104. In the present embodiment, the manufacturing program is set so that the steps of the stepped staircase increase with time. Thereafter, the etching is stopped in step S104, and the manufacturing program of the present embodiment ends. In FIG. 6, the transition of the applied power in the etching process is particularly mentioned, but other conditions such as each condition in the protective film forming process are also integratedly controlled in this manufacturing program. As described above, as a result of executing the manufacturing program of the silicon structure 10, a highly perpendicular anisotropic etching shape and a high mask selection ratio are achieved at the same time.

  By the way, in the above-described embodiment, the amount of electric power applied to the silicon substrate W is set to rise in a stepped manner after a predetermined time has elapsed, but the present invention is not limited to this. For example, even if it is set so as to rise in a quadratic curve, substantially the same effect as the effect of the present invention is exhibited.

  Further, in the above-described embodiment, the time during which the constant power is applied to the silicon substrate W at the beginning of etching is 5 minutes. However, the present invention is not limited to this. The time for applying a constant power for substantially achieving the effect of the present invention is not less than 3 minutes and not more than 6 minutes from the start of etching. This is because if the applied power to the substrate W starts to increase within 3 minutes from the start of etching, the applied power is unnecessarily increased when the depth of the grooves and holes is relatively shallow. This is because the amount of the mask consumed by the ions increases, and the risk that the mask selection ratio decreases is increased. On the other hand, applying a constant power over 6 minutes from the start of etching requires a long time to complete the etching, and as a result, the risk that the mask selection ratio is lowered is also increased.

  Furthermore, in the above-described embodiment, the power applied to the silicon substrate W is 120 W for a certain time from the beginning of etching. However, if the power is 160 W or less, the mask consumption is reduced and the mask selection ratio is high. Can be achieved. On the other hand, in order for the anisotropic etching of silicon to proceed substantially, it is preferable to apply 100 W or more.

  In the above-described embodiment, a silicon oxide film mask is used as an initial etching mask. However, a resist mask or a silicon nitride film mask may be used. Since a high mask selection ratio is achieved by the present invention, it is considered that there are more cases where a resist mask can be applied instead of a silicon oxide film mask or a silicon nitride film mask having high resistance to ion incidence.

In the above-described embodiment, as a means for etching silicon, a technique in which an etching gas and a protective film forming gas are alternately turned into plasma is used, but the etching means is not limited to this. For example, a method for converting a mixed gas of an etching gas and a protective film forming gas into a plasma as described in Japanese Patent Application Laid-Open No. 2004-296474 can also be used as anisotropic dry etching of silicon. This method is slower in etching rate than the method in which each of the above gases is simply turned into plasma, but is effective in that the unevenness on the side wall surface becomes smaller and smoother. Further, C ₅ F ₈ and C ₄ F ₆ may be used instead of C ₄ F ₈ which is the protective film forming gas, and NF ₃ and F ₂ are used instead of SF ₆ which is the etching gas. It may be used. Further, the etching gas and the protective film forming gas need not be a single gas. For example, the etching gas may contain oxygen gas or argon gas in addition to SF ₆ or the like, and the protective film forming gas may contain oxygen gas in addition to C ₄ F ₈ or the like.

  Moreover, although the silicon substrate is used in the above-described embodiment, the process target is not limited to the silicon substrate. For example, the present invention can be applied to a substrate including a silicon layer such as SOI (Silicon on Insulator).

  Furthermore, although ICP (Inductively Coupled Plasma) has been used as the plasma generating means in the embodiments so far, the present invention is not limited to this. The effects of the present invention can also be obtained using other high-density plasmas such as CCP (Capacitive-Coupled Plasma) and ECR (Electron-Cyclotron Resonance Plasma). As described above, modifications that exist within the scope of the present invention are also included in the claims.

It is sectional drawing which shows the structure of the manufacturing apparatus of the silicon structure in one embodiment of this invention. It is a graph which shows the time change of the applied electric power in the etching process to the silicon substrate in one embodiment of the present invention. It is sectional drawing which shows 1 process of the manufacturing method of the silicon structure in one embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the silicon structure in one embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the silicon structure in one embodiment of this invention. It is a graph which shows the time change of the applied electric power in the etching process to the silicon substrate in a comparative example. It is a SEM photograph which shows the upper cross section of the groove | channel of the silicon structure in one embodiment of this invention. It is a SEM photograph which shows the lower cross section of the groove | channel of the silicon structure in one embodiment of this invention. It is a manufacture flowchart of a silicon structure in one embodiment of the present invention. It is a conceptual diagram for demonstrating the definition of the side wall angle of an etching shape.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Silicon structure 12 Etching mask 14 Side wall 16 Bottom part 20 Chamber 21 Stage 22a, 22b Gas cylinder 23a, 23b Gas flow regulator 24 Coil 25 1st high frequency power supply 26 2nd high frequency power supply 27 Vacuum pump 28 Exhaust flow rate regulator 29 Control part 60 Computer 100 Silicon structure manufacturing apparatus

Claims (7)

In the process of etching silicon using plasma formed by introducing an etching gas and an organic deposit forming gas alternately or mixedly ,
A first power application step of making the applied power to the substrate constant when the etching gas is introduced for a predetermined time from the start of the etching;
After the predetermined time has elapsed, the etching power applied to the substrate during the gas introduction is raised together with the time, a second power to enhance the incidence over time into the substrate of ions in the plasma formed from the etch gas A method for manufacturing a silicon structure. The applied power in the second power application step increases stepwise, and any one step of the stepped applied power is larger than each step before the time when the step occurs. The manufacturing method of the silicon structure of description. The method for manufacturing a silicon structure according to claim 1, wherein the predetermined time is not less than 3 minutes and not more than 6 minutes from the start of etching. The method for manufacturing a silicon structure according to claim 1 or 2, wherein an applied power in the first power application step is 100 W or more . In the process of etching silicon using plasma formed by introducing an etching gas and an organic deposit forming gas alternately or mixedly ,
A first power application step of making the applied power to the substrate constant when the etching gas is introduced for a predetermined time from the start of the etching;
After the predetermined time has elapsed, the etching power applied to the substrate during the gas introduction is raised together with the time, a second power to enhance the incidence over time into the substrate of ions in the plasma formed from the etch gas A silicon structure manufacturing program comprising: an applying step.   A recording medium on which the manufacturing program according to claim 5 is recorded. A silicon structure manufacturing apparatus comprising a control unit controlled by the manufacturing program according to claim 5.