JP5163475B2 - Signal processing device - Google Patents

Description

  The present invention relates to a signal processing apparatus having an A / D conversion function.

  For example, a microcomputer equipped with an A / D converter is known as a microcomputer (hereinafter also referred to as a microcomputer) for controlling an automobile engine. In this type of microcomputer, the A / D converter is activated at regular intervals, and data is transferred from the A / D converter to the RAM at the same interval as the activation interval (that is, the A / D conversion data is converted). Storage in RAM) (see, for example, Patent Document 1).

  Here, a configuration example of such a microcomputer will be described with reference to FIG.

  The microcomputer 100 shown in FIG. 16 includes an A / D converter 11, an A / D activation timer 13, a DMA (Direct Memory Access) controller 15, a RAM 17, a ROM 19 in which a program is stored, and a program in the ROM 19. CPU 21 to be executed.

  The A / D converter 11 has a plurality of input terminals (four in this example) to which analog signals are input, and an A / D conversion request signal (TrgA in FIG. 16) that instructs execution of A / D conversion. ), An A / D conversion operation for A / D converting a plurality of analog signals from each input terminal is started, and when the A / D conversion operation is completed, an A / D conversion completion signal is output.

  The A / D activation timer 13 outputs the A / D conversion request signal to the A / D converter 11 at regular intervals set by the CPU 21. For this reason, the A / D converter 11 is activated at fixed time intervals when the A / D conversion request signal is output.

  The A / D converter 11 in this example is a multi-channel A / D converter that sequentially switches analog signals at each input terminal and performs A / D conversion with a single A / D conversion circuit. The channels ch1 to ch4 for A / D conversion are provided. In addition, since the A / D conversion request signal is a trigger for performing A / D conversion, the A / D conversion request signal is hereinafter also referred to as TrgA meaning trigger A.

  On the other hand, the A / D conversion completion signal from the A / D converter 11 is sent to the DMA controller 15 as a DMA transfer request signal (TrgB in FIG. 16) for instructing DMA transfer from the A / D converter 11 to the RAM 17. Given. Upon receiving the DMA transfer request signal, the DMA controller 15 converts A / D conversion data of all channels of the A / D converter 11 or channels specified in advance by the CPU 21 into the A / D converter 11. To the RAM 17 (DMA transfer). Since the DMA transfer request signal is a trigger for implementing DMA transfer, the DMA transfer request signal from the A / D converter 11 to the DMA controller 15 is also referred to as TrgB, which means trigger B, below.

  In such a microcomputer 100, the A / D converter 11 is activated and the A / D conversion data is transferred to the RAM 17 at regular intervals when the A / D conversion request signal (TrgA) is generated. It becomes.

A configuration in which data transfer from the A / D converter to the RAM is performed by the CPU is also conceivable. However, since the processing load on the CPU is excessively increased, for example, the CPU executes processing for engine control of the vehicle. In some cases, high-precision processing may not be possible. On the other hand, some microcomputers include a PWM signal output circuit (PWM signal generation circuit) that outputs a PWM signal having a period and a pulse width set by the CPU (see, for example, Patent Documents 2 and 3).
JP 2002-89346 A JP 11-214970 A Japanese Patent Laid-Open No. 10-2248

  In the above conventional technique, there is an inconvenience that activation of the A / D converter 11 and storage of the A / D conversion data in the RAM cannot be performed at different intervals.

  For this reason, for example, when analog signals having different required sampling intervals are A / D converted, analog signals that require A / D conversion data at short intervals TS (analog signals having a short sampling interval) and If there is an analog signal (analog signal having a long required sampling interval) that can acquire A / D conversion data at an interval TL longer than the interval TS, the storage capacity of the RAM 17 is wasted.

  That is, the interval at which the A / D converter 11 is activated is set to the short interval TS. However, an analog signal that only needs to acquire A / D conversion data at the long interval TL is set to an interval TS shorter than necessary. This is because the A / D conversion data is stored in the RAM 17. Further, although it is conceivable to delete the unnecessary A / D conversion data from the RAM 17 by the processing of the CPU 21, the processing load on the CPU increases excessively.

  The present invention has been made in view of these problems, and in a signal processing apparatus that activates an A / D converter at regular intervals to perform A / D conversion of a plurality of analog signals, It is an object to enable DMA transfer of A / D conversion data from an A / D converter to a memory at an arbitrary interval different from the activation interval of the A / D converter.

  The signal processing device according to claim 1 is a CPU for executing a program, an A / D converter, and an A / D conversion request signal for instructing the A / D converter to perform A / D conversion. A / D conversion requesting means for outputting at regular intervals, a memory for storing A / D conversion data which is data after A / D conversion by the A / D converter, and a DMA controller Yes.

  The A / D converter has a plurality of input terminals to which analog signals to be A / D converted are input, and each time the A / D conversion request signal is received, a plurality of analog terminals from each input terminal are received. When an A / D conversion operation for A / D converting the signal is started and the A / D conversion operation is completed, an A / D conversion completion signal is output.

  The DMA controller is configured such that the A / D conversion completion signal from the A / D converter is given as a DMA transfer request signal for instructing DMA transfer from the A / D converter to the memory. When the DMA transfer request signal is received, data transfer from the A / D converter to the memory is performed.

In particular, the signal processing apparatus according to claim 1 receives a PWM signal output circuit that outputs a PWM signal having a period and a pulse width arbitrarily set by the CPU, and a PWM signal output from the PWM signal output circuit. Data transfer requesting means.

  Then, when an edge in a specific direction is generated in the PWM signal from the PWM signal output circuit, the data transfer request means outputs a DMA transfer request signal different from the A / D conversion completion signal to the DMA controller.

  Further, the DMA controller designates which of the input terminals of the A / D converter the A / D conversion data corresponding to the input terminal of the A / D converter is transferred to the memory for each DMA transfer request signal given to itself. It is like that. When the DMA controller receives one of the DMA transfer request signals, the DMA controller corresponds to the input terminal designated in advance by the CPU for the received DMA transfer request signal among the input terminals of the A / D converter. A / D conversion data is transferred from the A / D converter to the memory. The A / D conversion data corresponding to the input terminal is A / D conversion data obtained by A / D converting an analog signal from the input terminal. Hereinafter, the A / D conversion data of the input terminal is simply referred to as A / D conversion data. Also called.

  According to such a signal processing device, a DMA transfer request signal (hereinafter also referred to as a first type DMA transfer request signal), which is an A / D conversion completion signal from the A / D converter, to the DMA controller. Another DMA transfer request signal (hereinafter also referred to as a second type DMA transfer request signal) can be given from the data transfer request means in the cycle of the PMW signal.

  The generation period of the second type DMA transfer request signal, which is the period of the PWM signal, can be arbitrarily set by the CPU (in other words, by the program) according to the period value set in the PWM signal output circuit. .

  In addition, the CPU can arbitrarily set which input terminal of the A / D converter the A / D conversion data is DMA-transferred to the memory when the DMA controller receives which DMA transfer request signal. .

  Therefore, for the A / D conversion data of the input terminal set as the DMA transfer target in response to the second type DMA transfer request signal, the PWM signal that can arbitrarily set the DMA transfer from the A / D converter to the memory. And can be performed at an arbitrary interval different from the activation interval of the A / D converter.

  For this reason, according to the signal processing apparatus of the first aspect, when the A / D converter is activated at regular intervals to perform A / D conversion of a plurality of analog signals, the A / D of any analog signal is obtained. DMA transfer of D conversion data from the A / D converter to the memory can be performed at an arbitrary interval different from the activation interval of the A / D converter.

  Furthermore, from this, the following effects [1] and [2] can be obtained.

  [1] An analog signal for which A / D conversion is performed on analog signals having different required sampling intervals and which requires A / D conversion data at a short interval TS (an analog signal having a required sampling interval of a short interval TS) ) Memory capacity when there is As1 and an analog signal (analog signal whose required sampling interval is a long interval TL) As2 that can acquire A / D conversion data at an interval TL longer than the interval TS Can be reduced as compared with the prior art.

  Specifically, in this case, the A / D converter activation interval (interval at which the A / D conversion request means outputs the A / D conversion request signal) is set to the fastest sampling which is the shorter interval TS. It will be adjusted to the interval.

  The analog signal As1 is set so that when the DMA controller receives the first type DMA transfer request signal (A / D conversion completion signal), the A / D conversion data of the analog signal As1 is transferred to the memory. Thus, the A / D conversion data at the short interval TS can be sequentially stored in the memory.

  As for the analog signal As2, the A / D conversion data of the analog signal As2 is set to be transferred to the memory when the DMA controller receives the second type DMA transfer request signal, and the cycle of the PWM signal is set. By setting the long interval TL, only A / D conversion data at an interval TL longer than the A / D conversion interval (= sampling interval of the analog signal As1) can be sequentially stored in the memory.

  Therefore, with respect to the analog signal As2, it is possible to avoid storing A / D conversion data at intervals TS shorter than necessary in the memory. Further, it is not necessary for the CPU to perform a process of thinning out unnecessary A / D conversion data from the memory.

  [2] The A / D conversion data of the analog signal As2 can be temporally correlated with the A / D conversion data of the analog signal As1.

  This is because if the period of the PWM signal that is the source of the second type DMA transfer request signal is set to n times the A / D conversion interval (n is an integer of 1 or more), the analog signal stored in the memory This is because the A / D conversion data of As2 is A / D converted data at an interval n times the sampling interval of the analog signal As1.

  For example, if an analog signal whose value gradually changes over a relatively long time, such as a signal from a water temperature sensor for detecting the cooling water temperature of the engine, is an A / D conversion target, The A / D conversion data can be read from the A / D converter and written to the memory when the CPU has a small processing load. On the other hand, in the present invention, since the A / D conversion data is stored in the memory by the DMA controller, the sampling interval as much as the A / D conversion interval is not required. An interval of several tens of times is particularly effective when A / D converting an analog signal to be sampled.

  On the other hand, the A / D conversion requesting unit may be a circuit different from the CPU, or may be a unit realized by the CPU executing a program.

  Next, an effective edge of the PWM signal, which is an edge in the specific direction of the PWM signal and that generates the second type DMA transfer request signal, will be described.

  First, the edge of the PWM signal output from the PWM signal output circuit includes a rising edge and a falling edge. In this specification, one of them is called a periodic edge and the other is called a duty edge.

  Here, among the period and pulse width values set in the PWM signal output circuit by the CPU, the generation interval changes depending on the period value, and the generation timing does not change depending on the pulse width value. The edge of the direction.

  The duty edge is an edge in the opposite direction to the periodic edge, and is an edge whose generation interval from the periodic edge changes depending on a pulse width value set by the CPU. Note that the generation interval of the duty edge is also the same as the interval of the periodic edge, and changes depending on the value of the cycle set by the CPU.

  The edge in the specific direction may be a periodic edge as described in claim 2 or a duty edge as described in claim 3.

  In particular, if the duty edge is an edge in the specific direction, it is advantageous in the following points.

  First, the generation timing of the second type DMA transfer request signal (that is, the timing at which the data transfer request means outputs the DMA transfer request signal and the DMA controller starts DMA transfer) is determined by the A / D converter. A specific timing during the A / D conversion stop period from the completion of the A / D conversion operation to the start of the next A / D conversion operation, and more specifically, the A / D in the A / D converter The timing should be set so that the DMA controller can complete the DMA transfer before conversion data is confirmed and the next A / D conversion operation is started. This is to ensure that A / D conversion data can be stored in the memory.

  Further, the generation timing of the duty edge of the PWM signal can be adjusted on the basis of the periodic edge according to the pulse width value set in the PWM signal output circuit.

  Therefore, if the second type DMA transfer request signal is generated by the duty edge of the PWM signal as in the signal processing device according to claim 3, the generation timing of the second type DMA transfer request signal is set to the generation timing. The pulse width value set in the PWM signal output circuit can be set with reference to the periodic edge of the PWM signal.

  Therefore, the difference between the timing at which the periodic edge occurs in the PWM signal and the timing at which the A / D conversion request means outputs the A / D conversion request signal (that is, the start timing of the A / D converter) is known. If the period value of the PWM signal is set to n times the A / D conversion interval (n is an integer of 1 or more), the second type DMA transfer is performed only by the pulse width value set in the PWM signal output circuit. The generation timing of the request signal can be matched with the specific timing during the A / D conversion stop period, and the timing adjustment becomes easy.

  According to a fourth aspect of the present invention, the edge in the specific direction is both a periodic edge and a duty edge, and when the data transfer requesting means generates a periodic edge in the PWM signal, and the duty edge in the PWM signal. If two separate DMA transfer request signals are output to the DMA controller at the time of occurrence of the above, two second type DMA transfer request signals can be generated by one PWM signal. Then, when the DMA transfer request signal corresponding to the periodic edge is generated and when the DMA transfer request signal corresponding to the duty edge is generated, A / D conversion data at different input terminals is stored in the memory. Since the data can be transferred, the A / D conversion data of the different input terminals is stored in the memory at the same interval longer than the A / D conversion interval and at a timing shifted in phase by the pulse width of the PWM signal. Can be stored.

  By the way, according to the signal processing device of claim 3 as described above, the generation timing of the second type DMA transfer request signal is determined during the A / D conversion stop period only by the pulse width value set in the PWM signal output circuit. However, if the pulse width value set in the PWM signal output circuit has changed for some reason (such as disturbance noise), the generation timing of the second type DMA transfer request signal Will deviate from the optimal timing. Therefore, in order to avoid such an inconvenience, the signal processing device of the fifth aspect may be configured.

  That is, in the signal processing device according to claim 5, in the signal processing device according to claim 3, the CPU sets the cycle of the PWM signal to n times (n) the output cycle (A / D conversion interval) of the A / D conversion request signal. Is an integer greater than or equal to 1), and the pulse width of the PWM signal is set to a predetermined value.

  Further, the CPU performs pulse width correction processing. In the pulse width correction processing, the timing at which the data transfer request means outputs the DMA transfer request signal is detected, and the data is determined based on the detection result. The output timing of the DMA transfer request signal from the transfer request means (generation timing of the second type DMA transfer request signal) is the next A / D conversion operation after the A / D converter completes the A / D conversion operation. The setting value of the pulse width of the PWM signal is corrected so that the specific timing during the period until the start is reached. That is, the actual generation timing of the second type DMA transfer request signal is confirmed, and the set value of the pulse width is reset so that the timing becomes the target specific timing.

  According to such a signal processing apparatus of the fifth aspect, it is possible to prevent the generation timing of the second type DMA transfer request signal from deviating from the target timing. Even if the predetermined value initially set as the pulse width value is an inappropriate value, the pulse width correction process is performed, so that the pulse width value is changed to an appropriate value (that is, the second value). The generation timing of the seed DMA transfer request signal can be automatically reset to a value that can be the specific timing).

  The pulse width correction process is preferably performed periodically, but may be performed only once at a predetermined timing after the signal processing apparatus is activated, for example.

  As the pulse width correction process, specifically, at least one of the first to third correction processes as described in claim 6 can be considered.

  In other words, the first correction processing is performed by the data transfer request unit receiving the DMA transfer request signal from the time when the A / D converter completes the A / D conversion operation immediately before the data transfer request unit outputs the DMA transfer request signal. The margin time after completion of A / D conversion, which is the time until output, is detected as the output timing of the DMA transfer request signal, and the margin time after completion of A / D conversion is completed based on the detection result This is a process of correcting the set value of the pulse width of the PWM signal so that the target value of the rear margin time is obtained.

  In the second correction process, A / D conversion start is a time from when the data transfer request means outputs a DMA transfer request signal until the A / D converter starts the next A / D conversion operation. The previous margin time is detected as the output timing of the DMA transfer request signal, and the PWM is set so that the margin time before the start of A / D conversion becomes the target value of the margin time before the start of A / D conversion based on the detection result. This is a process of correcting the set value of the pulse width of the signal.

  In the third correction process, the data transfer request means outputs the DMA transfer request signal from the time when the A / D converter starts the A / D conversion operation immediately before the data transfer request means outputs the DMA transfer request signal. The margin time after the start of A / D conversion, which is the time until output, is detected as the output timing of the DMA transfer request signal, and the margin time after the start of A / D conversion is started based on the detection result This is a process of correcting the set value of the pulse width of the PWM signal so that the target value of the rear margin time is obtained.

  In the case of the third correction process, the target value of the margin time after the start of A / D conversion is an A / D converter with respect to the target value of the margin time after the completion of A / D conversion in the first correction process. A / D conversion operation time is added.

  On the other hand, the signal processing device according to claim 4 is the same as the signal processing device according to claim 3 in that the second type DMA transfer request signal is generated by the duty edge of the PWM signal.

  Therefore, in the signal processing device according to claim 7, in the signal processing device according to claim 4, as in the signal processing device according to claim 5, the CPU sets the cycle of the PWM signal to the output cycle of the A / D conversion request signal. The DMA transfer request signal is set to n times (n is an integer of 1 or more), the pulse width of the PWM signal is set to a predetermined value, and the DMA transfer request signal corresponding to the duty edge. The same pulse width correction processing as that of the signal processing apparatus is performed. The DMA transfer request signal corresponding to the duty edge is a DMA transfer request signal output by the data transfer request means when a duty edge occurs in the PWM signal.

  According to the signal processing device of claim 7, the same effect as that described for the signal processing device of claim 5 can be obtained with respect to the DMA transfer request signal corresponding to the duty edge.

  Further, as the pulse width correction process according to claim 7, specifically, at least one of the first to third correction processes as described in claim 8 can be considered. In the first to third correction processes, the first to third correction processes described in claim 6 are performed on the DMA transfer request signal corresponding to the duty edge.

  By the way, in order to make the generation timing of the second type DMA transfer request signal always be the above-mentioned specific timing, the period of the PWM signal is set to n times the A / D conversion interval (n is an integer of 1 or more). However, if the period value set in the PWM signal output circuit by the CPU has changed for some reason (such as disturbance noise), the generation timing of the second type DMA transfer request signal is the optimum specific timing. It will shift from. Therefore, in order to avoid such an inconvenience, the signal processing device of the ninth aspect may be configured.

  That is, in the signal processing device according to claim 9, in the signal processing devices according to claims 1 to 3, 5, and 6, the CPU determines the period of the PWM signal as the output period of the A / D conversion request signal (A / D conversion interval). ) N times (n is an integer of 1 or more). Further, the CPU performs a period correction process. In the period correction process, the data transfer request unit outputs a DMA transfer request signal, and the A / D converter has an A / D converter. It is detected that the interval is n times the A / D conversion interval, which is an interval for performing the / D conversion operation, and the signal output interval is the n times the A / D conversion interval based on the difference between the detected values. The set value of the period of the PWM signal is corrected so as to be equal to. That is, the actual generation interval of the second type DMA transfer request signal is confirmed, and the set value of the cycle is reset so that the generation interval is n times the actual A / D conversion interval.

  According to such a signal processing apparatus of the ninth aspect, it is possible to prevent the generation timing of the second type DMA transfer request signal from deviating from the target timing.

  The period correction process is preferably performed periodically, but may be performed only once at a predetermined timing after the signal processing apparatus is activated, for example.

  Further, in the signal processing device according to claim 10, in the signal processing devices according to claims 4, 7, and 8, as in the case of the signal processing device according to claim 9, the CPU converts the period of the PWM signal into an A / D conversion request signal. Is set to n times (n is an integer equal to or greater than 1), and the DMA transfer request signal corresponding to the duty edge or the DMA transfer request signal corresponding to the cycle edge The same period correction processing as that of the signal processing device of claim 9 is performed. The DMA transfer request signal corresponding to the periodic edge is a DMA transfer request signal output by the data transfer request means when a periodic edge occurs in the PWM signal.

  Specifically, in the period correction processing in the signal processing device according to claim 10, the interval at which the data transfer request means outputs the DMA transfer request signal corresponding to the duty edge and the data transfer request means corresponding to the period edge. The interval of outputting the DMA transfer request signal is detected as a signal output interval, and an interval of n times the A / D conversion interval, which is the interval at which the A / D converter performs the A / D conversion operation, is detected. Based on the difference between the two detection values, the setting value of the period of the PWM signal is corrected so that the signal output interval is equal to the n times the A / D conversion interval.

  The signal processing device according to claim 10 can prevent the generation timing of the second type DMA transfer request signal from deviating from the target timing, similarly to the signal processing device according to claim 9. it can.

  Next, a signal processing device according to an eleventh aspect is the signal processing device according to the first to tenth aspects, comprising a plurality of sets of PWM signal output circuits and data transfer requesting means.

  According to the signal processing device of claim 11, a plurality of second type DMA transfer request signals can be generated at different periods, and the DMA controller performs A / D for each of the second type DMA transfer request signals. The CPU can arbitrarily set whether the A / D conversion data corresponding to which input terminal of the converter is DMA-transferred to the memory. For this reason, each A / D conversion data corresponding to a different input terminal of the A / D converter can be transferred to the memory in each of a plurality of periods different from the A / D conversion interval.

A microcomputer as a signal processing apparatus according to an embodiment to which the present invention is applied will be described below. The microcomputer of the present embodiment is mounted on, for example, an electronic control device (hereinafter referred to as an ECU) that controls a common rail diesel engine of a vehicle and executes processing for controlling the engine. The part directly related to the present invention will be described.
[First Embodiment]
As shown in FIG. 1, the microcomputer 10 of this embodiment is further provided with a PWM signal output circuit 23 and a timer unit 25 as compared with the microcomputer 100 shown in FIG. 16, and a DMA controller in place of the DMA controller 15. 16 is different. In FIG. 1, the same components as those in FIG. 16 are denoted by the same reference numerals, and description thereof is omitted.

  The PWM signal output circuit 23 includes a period value register 23a and a pulse width value register 23b into which a value of the PWM signal period (period value) and a value of the pulse width (pulse width value) are written by the CPU 21, respectively. A PWM signal having a period of the value written in the period value register 23a and a pulse width of the value written in the pulse width value register 23b is generated, and the PWM signal is used as a signal of the microcomputer 10 Output from the output terminal J1 to the outside. Such a PWM signal output circuit 23 is described in, for example, the above-described Patent Document 2, and in Patent Document 2, the pulse width value of the PWM signal is referred to as a duty value.

  In this embodiment, among the edges of the PWM signal, the rising edge is the above-described periodic edge, and the falling edge is the above-described duty edge. As shown in FIG. 2, in the PWM signal in the present embodiment, the high time from the rising edge to the falling edge (from the cycle edge to the duty edge) has a time width corresponding to the value of the pulse width value register 23b. The pulse width Tduty. In FIG. 2, Tpwm is the period of the PWM signal and is the interval between the periodic edges, but naturally the interval between the duty edges is also the same as Tpwm.

  The timer unit 25 is a block having a free-run timer circuit, a circuit for generating a timer interrupt, and a circuit for an input capture function. Although not shown in FIG. 16, the same unit as the timer unit 25 is also provided in the microcomputer 100 shown in FIG.

  However, the timer unit 25 provided in the microcomputer 10 of the present embodiment further completes the A / D conversion to the DMA controller 16 when an edge in a specific direction occurs in the input signal from the signal input terminal J2 of the microcomputer 10. A DMA transfer request function circuit 25a for outputting a DMA transfer request signal different from the signal (TrgB) is provided.

  The signal input terminal J2 is connected to the signal output terminal J1 by an external wiring of the microcomputer 10. For this reason, the PWM signal output to the outside of the microcomputer 10 by the PWM signal output circuit 23 is input to the timer unit 25 from the signal input terminal J2.

  In the present embodiment, the edge in the specific direction is a falling edge. That is, the timer unit 25 (specifically, the DMA transfer request function circuit 25a) outputs a DMA transfer request signal to the DMA controller 16 when a falling edge occurs in the input signal from the signal input terminal J2. ing.

  Therefore, the timer unit 25 outputs a DMA transfer request signal to the DMA controller 16 when a duty edge that is a falling edge occurs in the PWM signal from the PWM signal output circuit 23. Since the DMA transfer request signal from the timer unit 25 to the DMA controller 16 is also a trigger for DMA transfer, the DMA transfer request signal from the timer unit 25 means trigger C below. Also referred to as TrgC.

  For each of the DMA transfer request signals (TrgB from the A / D converter 11 and TrgC from the timer unit 25 in this embodiment) given to itself, the DMA controller 16 determines which of the A / D converters 11 The CPU 21 designates (sets) whether the A / D conversion data corresponding to the input terminal is transferred to the RAM 17 (that is, which channel of the A / D converter 11 is transferred to the RAM 17). It is like that. Upon receiving any of the DMA transfer request signals, the DMA controller 16 selects a channel of the A / D converter 11 that is designated as a transfer target in advance by the CPU 21 for the received DMA transfer request signal. The A / D conversion data is transferred from the A / D converter 11 to the RAM 17 (DMA transfer).

  On the other hand, as shown in FIG. 1, in the engine 3 that is the control target of the ECU 1 in which the microcomputer 10 is mounted, each fuel that is injected from the common rail into each cylinder of the engine 3 (four cylinders in the present embodiment). The injectors IJ1 to IJ4 are provided with pressure sensors S1 to S4 for detecting fuel pressure in the injectors IJ1 to IJ4 (hereinafter referred to as injector pressure).

  The injector pressure signals P1 to P4, which are analog signals from the pressure sensors S1 to S4, are sent to the channels (each of the A / D converter 11 in the microcomputer 10 via the input circuit 5 provided in the ECU 1). Input terminals) are input to ch1 to ch4.

  Next, the operation of each part in the microcomputer 10 will be described.

  As shown in FIG. 2, in the microcomputer 10, the A / D activation timer 13 outputs TrgA, which is an A / D conversion request signal, to the A / D converter 11 at regular intervals set by the CPU 21. The A / D converter 11 is activated each time the TrgA is output, and sequentially outputs the analog signals of the channels ch1 to ch4 (that is, the injector pressure signals P1 to P4 of each cylinder) (in this embodiment). When A / D conversion is performed (in order from the smallest channel number) and the A / D conversion operation is completed, an A / D conversion completion signal and TrgB which is a DMA transfer request signal are output to the DMA controller 16.

  In addition, the output time of TrgA from the A / D activation timer 13 and the above-mentioned fixed time which is the A / D conversion interval is the minimum interval for sampling the injector pressure signals P1 to P4 of any cylinder (this embodiment) For example, it is set to 20 μs).

  On the other hand, in the period value register 23a of the PWM signal output circuit 23, the CPU 21 sets a value corresponding to a time that is n times the output period of TrgA (n is an integer of 1 or more, and n = 2 in this embodiment). Is done.

  For this reason, as shown in FIG. 2, the PWM signal output circuit 23 outputs a PWM signal having a cycle Tpwm that is twice the cycle of TrgA.

  Each time a duty edge (falling edge) is generated in the PWM signal, TrgC, which is a DMA transfer request signal (second type DMA transfer request signal) different from TrgB, is output from the timer unit 25 to the DMA controller 16. Is done. Note that the duty edge of the PWM signal is also generated every period Tpwm of the PWM signal, similarly to the periodic edge, so that TrgC is generated at a period twice as long as the generation period of TrgA and TrgB.

  In addition, as shown in FIG. 3, the pulse width value register 23b of the PWM signal output circuit 23 indicates that the generation timing of TrgC is the next A / D converter after the A / D conversion operation of the A / D converter 11 is completed. A value is set by the CPU 21 so as to be a specific timing during the A / D conversion stop period until the D conversion operation is started. The specific timing means that the A / D conversion data of all channels in the A / D converter 11 is fixed and the DMA controller 16 performs DMA transfer until the next A / D conversion operation is started. It is time to finish. The reason for setting in this way is to ensure that DMA transfer of A / D conversion data to the RAM 17 by TrgC can be performed.

  Here, the pulse width value set in the pulse width value register 23b will be described in more detail with reference to FIG.

  First, the CPU 21 starts the operation, sets the output cycle of TrgA, sets the cycle value of the PWM signal and the pulse width value by the initial setting process, and then outputs the A / D start timer 13 and the PWM signal output. As shown in FIG. 4, the circuit 23 is activated, and the difference in activation time between the two causes a periodic edge in the output timing of the TrgA from the A / D activation timer 13 and the PWM signal from the PWM signal output circuit 23. It appears as a time difference Tsd from the timing. The time difference Tsd is known. In the present embodiment, the CPU 21 sequentially starts the A / D start timer 13 and the PWM signal output circuit 23 at successive processing steps in the program. The time difference Tsd is the difference between the execution time of each processing step and the time from when the CPU 21 starts the A / D start timer 13 until the A / D start timer 13 starts operating and outputs TrgA. It can be calculated from the time and the time from when the CPU 21 starts the PWM signal output circuit 23 to when the PWM signal output circuit 23 starts operating to first change the PWM signal to high.

  In FIG. 4, time Tsad is the output timing of TrgA serving as a reference for determining the pulse width value, time Ttrg is the target specific timing at which TrgC is to be generated, and time Ttg is time This is the time from Tsad to time Ttrg until TrgC is generated after TrgA is generated.

  Tiad is an A / D conversion time (time for the A / D conversion operation) from the output timing of TrgA until the A / D converter 11 completes the A / D conversion operation.

  The margin time Tma is the time from the time (A / D conversion completion time) Tead when the A / D converter 11 completes the A / D conversion operation to the target time Ttrg at which TrgC is to be generated. Whether the margin time Tma is the same as the maximum time from the completion of the A / D conversion operation in the A / D converter 11 until the A / D conversion data of all channels is determined and the DMA transfer can be started. It ’s a little longer than that.

  The margin time Tmb is the time from the target time Ttrg at which TrgC is to be generated to the next output timing of TrgA. The margin time Tmb is the same as the maximum time required for the DMA transfer by the DMA controller 16 or a time slightly longer than that.

  Furthermore, “Tma + Tmb” is the time from the A / D conversion completion time Tead to the next output timing of TrgA (in other words, the A / D conversion time Tad is subtracted from the A / D conversion interval Tad which is the output cycle of TrgA). The remaining time).

  On the other hand, in FIG. 4, Tduty is the pulse width of the PWM signal, and Tid is the delay time in hardware from when the duty edge occurs in the PWM signal until the timer unit 25 outputs TrgC.

  As is clear from FIG. 4, the following expression 1 is established, and when the expression 1 is modified, the following expression 2 is obtained.

Ttg = Tiad + Tma = Tsd + Tduty + Tid Equation 1
Tduty = Tad + Tma− (Tsd + Tid) Equation 2
Therefore, if a value corresponding to the time of “Tiad + Tma− (Tsd + Tid)” is set in the pulse width value register 23b, TrgC is generated at the above specific timing at which DMA transfer of the A / D conversion data to the RAM 17 can be performed reliably. Can be made.

  Therefore, the CPU 21 sets a value corresponding to the time “Tiad + Tma− (Tsd + Tid)” in the pulse width value register 23b in the initial setting process.

  It is also conceivable to set the pulse width Tduty of the PWM signal to a value greater than or equal to the A / D conversion interval Tad. If Tduty is set within a range that is greater than or equal to m times Tad (m is an integer equal to or greater than 1) and less than “m + 1” times Tad, “Tiad” in Equation 1 and Equation 2 above is set. , “Tad × m + Tiad”.

  On the other hand, for each of TrgB and TrgC, the CPU 21 switches the channel of the A / D converter 11 (hereinafter referred to as a transfer target A / D channel) that the DMA controller 16 targets for DMA transfer as follows.

  First, a transfer target A / D channel for TrgB is an injector for a cylinder that has fuel injection timing during the current 180 ° CA period for each period of 180 ° CA including the fuel injection timing of each cylinder. The channel is switched to the channel in which the pressure signals P1 to P4 are input. The transfer target A / D channel for TrgC is a cylinder for which the fuel injection timing does not arrive during the current 180 ° CA period (in this embodiment, for TrgB). The cylinder corresponding to the transfer target A / D channel is switched to the channel to which the injector pressure signals P1 to P4 of the cylinder whose stroke is shifted by 360 ° CA are input. CA is a common term meaning the rotation angle of the crankshaft of the engine 3.

  For this reason, in the period of 180 ° CA including the fuel injection timing of the first cylinder in the period of 180 ° CA of one cycle of the engine 3 (period of 720 ° CA) divided into four, FIG. As shown in FIG. 4, among the channels ch1 to ch4 of the A / D converter 11, the channel ch1 to which the injector pressure signal P1 of the first cylinder is input is set as the transfer target A / D channel for TrgB. The channel ch3 to which the injector pressure signal P3 for the third cylinder is input is set as the transfer target A / D channel for TrgC.

  In this case, every time TrgB from the A / D converter 11 is received, the DMA controller 16 performs A / D conversion data of the channel ch1 (that is, A / D conversion data of the injector pressure signal P1 of the first cylinder). Is transferred to the RAM 17 and every time TrgC is received from the timer unit 25, the A / D conversion data of the channel ch3 (that is, the A / D conversion data of the injector pressure signal P3 of the third cylinder) is DMA-transferred to the RAM 17. Will be transferred. In FIG. 2 and other figures to be described later, “DMA transfer B” refers to DMA transfer triggered by TrgB. Similarly, “DMA transfer C” refers to DMA transfer triggered by TrgC. That is.

  Thus, in this embodiment, the A / D conversion data of the injector pressure signal of the injection target cylinder where fuel injection is performed is DMA-transferred to the RAM 17 at the same interval as the A / D conversion interval, and in parallel therewith. The A / D conversion data of the injector pressure signal of the non-injection target cylinder where fuel injection is not performed is DMA-transferred to the RAM 17 at an interval twice the A / D conversion interval. The reason why this is done is as follows.

  First, in this embodiment, the actual fuel injection amount is calculated by integrating the injector pressure of the injection target cylinder when the fuel injection is performed on the injection target cylinder, and the fuel injection amount to the engine 3 is calculated. Control with high precision.

  However, if a change occurs in the pressure of the common rail, for example, when a high-pressure pump that pumps fuel to the common rail starts operation during the fuel injection, the influence of the change also appears in the injector pressure. For this reason, the correct injector pressure of the injection target cylinder is calculated by correcting the injector pressure of the non-injection target cylinder from the injector pressure of the injection target cylinder.

  Here, the injector pressure of the injection target cylinder shows a sudden change in a short time with the fuel injection, but the injector pressure of the non-injection target cylinder gradually and monotonously even if it changes. Therefore, it is possible to calculate the value at an arbitrary time point by a complementary calculation or the like by setting the sampling interval longer than the injector pressure of the injection target cylinder.

  Therefore, in the microcomputer 10 of the present embodiment, the injector pressure signal of the non-injection target cylinder is substantially transferred by DMA transfer of the A / D conversion data to the RAM 17 at an interval twice the A / D conversion interval. Non-injection target used for the subtraction correction by making the sampling interval twice the A / D conversion interval and the CPU 21 performing a complementary operation on any of the A / D conversion data transferred to the RAM 17 Cylinder injector pressure is obtained.

  According to the microcomputer 10 of the embodiment as described above, the DMA transfer request signal TrgC, which is different from the TrgB, can be given to the DMA controller 16 in the cycle of the PMW signal. It can be arbitrarily set by the CPU 21 (in other words, by a program) according to the value of the period set in the PWM signal output circuit 23.

  Furthermore, the transfer target A / D channel by the DMA controller 16 can be arbitrarily set by the CPU 21 for each of TrgB and TrgC.

  Therefore, for the A / D conversion data of the transfer target A / D channel for TrgC, the DMA transfer from the A / D converter 11 to the RAM 17 can be performed at an arbitrary interval different from the A / D conversion interval.

  For this reason, according to the microcomputer 10 of this embodiment, when the A / D converter 11 is activated at regular intervals to perform A / D conversion of a plurality of analog signals, the A / D of any analog signal is obtained. DMA transfer of D conversion data from the A / D converter 11 to the RAM 17 can be performed at an arbitrary interval different from the A / D conversion interval.

  Furthermore, from this, the effects [1] and [2] described above can be obtained. In this embodiment, the injector pressure signal of the cylinder to be injected corresponds to the analog signal As1 described in [1] and [2] (the analog signal having the shorter required sampling interval), and the cylinder of the non-injection target cylinder. The injector pressure signal corresponds to the analog signal As2 (analog signal having a longer required sampling interval) described in [1] and [2].

  In this embodiment, since TrgC is generated by the duty edge of the PWM signal, the generation timing of the TrgC is determined based on the pulse width value set in the PWM signal output circuit 23. There is an advantage that it is easy to set with reference.

In the present embodiment, the A / D activation timer 13 corresponds to A / D conversion request means, and the RAM 17 corresponds to a memory. Of the circuits in the timer unit 25, the DMA transfer request function circuit 25a that outputs TrgC corresponds to the data transfer request means.
[Second Embodiment]
The microcomputer according to the second embodiment differs from the microcomputer 10 according to the first embodiment in the following points. In the following description of the second embodiment, the same reference numerals as those in the first embodiment are used.

  That is, in the microcomputer 10 of the second embodiment, as shown in FIG. 5, the timer unit 25 (specifically, the DMA transfer request function circuit 25a) is an input signal from the signal input terminal J2 and outputs a PWM signal. When a periodic edge (rising edge) occurs instead of a duty edge in the PWM signal from the circuit 23, TrgC is output.

  Therefore, in the second embodiment, as shown in FIG. 5, the CPU 21 sets the A / D activation timer 13 so that the generation timing of TrgC becomes the specific timing during the A / D conversion stop period described above. The PWM signal output circuit 23 is activated after a predetermined time difference from the activation. That is, the activation timing of the A / D activation timer 13 and the activation timing of the PWM signal output circuit 23 are intentionally shifted so that the time difference Tsd in FIG. 4 becomes “Tiad + Tma−Tid” in FIG. In order to start the A / D start timer 13 and the PWM signal output circuit 23 by shifting, a timer interrupt may be used, for example.

The same effects as those of the first embodiment can be obtained by the second embodiment. Moreover, there is an advantage that the pulse width value of the PWM signal may be anything.
[Third Embodiment]
As shown in FIG. 6, the microcomputer 20 of the third embodiment differs from the microcomputer 10 of the first embodiment in the following points (1) to (3). In the following description, the same constituent elements as those of the other embodiments described above are denoted by the same reference numerals as those of the embodiments, and the description thereof is omitted.

  (1) The same PWM signal output circuit 24 as the PWM signal output circuit 23 is further provided.

  The PWM signal output circuit 24 outputs a PWM signal having the period of the value written in the period value register 24a by the CPU 21 and the pulse width of the value written in the pulse width value register 24b by the CPU 21. The PWM signal is generated and output from the signal output terminal J3 of the microcomputer 20 to the outside. Further, the signal output terminal J3 is connected to the signal input terminal J4 of the microcomputer 20 by wiring outside the microcomputer 20.

  (2) A DMA controller 26 is provided instead of the DMA controller 16.

  The DMA controller 26 is also supplied with a DMA transfer request signal (hereinafter referred to as TrgD) different from TrgB and TrgC. Further, in the DMA controller 26, the transfer target A / D channel is also set by the CPU 21 for the TrgD.

  (3) The timer unit 25 further includes a circuit 25b that is the same as the circuit 25a of the DMA transfer request function. When the circuit 25b generates an edge in a specific direction (a falling edge in this embodiment) in the input signal from the signal input terminal J4 of the microcomputer 20 (that is, the PWM signal from the PWM signal output circuit 24). The TrgD is output to the DMA controller 26.

  For this reason, TrgD is output from the timer unit 25 to the DMA controller 26 when a duty edge occurs in the PWM signal from the PWM signal output circuit 24. Similarly to the first embodiment, the PWM signal output circuit 23 outputs the TrgD. When a duty edge occurs in the PWM signal, TrgC is output.

  According to the microcomputer 20 of the third embodiment as described above, as shown in FIG. 7, the DMA controller 26 can generate two TrgCs and TrgDs with different periods separately from the TrgB. Since the CPU 21 can arbitrarily set the transfer target A / D channel for TrgD, a plurality of A / D conversion data of different channels of the A / D converter 11 are different from the A / D conversion interval. In each cycle, the data can be transferred to the RAM 17.

  In FIG. 7 and other figures to be described later, “PWM signal C” is a PWM signal from the PWM signal output circuit 23 serving as the source of TrgC, and similarly “PWM signal D” is the source of TrgD. The PWM signal output from the PWM signal output circuit 24 is “DMA transfer D”, which is DMA transfer triggered by TrgD. In the example of FIG. 7, the PWM signal output circuit 23 outputs a PWM signal having a period twice as long as the A / D conversion interval (the period of TrgA), so that TrgC is doubled as the A / D conversion interval. The PWM signal output circuit 24 generates a PWM signal having a period four times the A / D conversion interval, thereby generating TrgD at a period four times the A / D conversion interval. In FIG. 7, A / D conversion data of channel ch1 is DMA-transferred to RAM 17 by TrgB, A / D conversion data of channel ch3 is DMA-transferred to RAM 17 by TrgC, and A / D conversion data of channel ch4 is TrgD. Is shown in FIG.

  On the other hand, in the third embodiment, each of the circuits 25a and 25b in the timer unit 25 corresponds to a data transfer request unit.

Also, both or one of the circuits 25a and 25b in the timer unit 25 outputs a DMA transfer request signal (TrgC or TrgD) when a periodic edge occurs in the PWM signal, as in the second embodiment. You may comprise.
[Fourth Embodiment]
As shown in FIG. 8, the microcomputer 30 of the fourth embodiment is different from the microcomputer 10 of the first embodiment in the following points (a) and (b).

  (A) Instead of the DMA controller 16, the same DMA controller 26 as that of the third embodiment (FIG. 6) is provided.

  (B) The timer unit 25 includes a circuit 25c in place of the DMA transfer request function circuit 25a.

  When a falling edge occurs in the input signal from the signal input terminal J2 of the microcomputer 20, the DMA transfer request function circuit 25c outputs TrgC to the DMA controller 26, and the input signal from the signal input terminal J2 When a rising edge occurs, TrgD is output to the DMA controller 26.

  For this reason, from the timer unit 25 to the DMA controller 26, not only TrgC is output when a duty edge occurs in the PWM signal from the PWM signal output circuit 23, but also TrgD is output when a periodic edge occurs in the PWM signal. The Rukoto.

  And according to the microcomputer 30 of such 4th Embodiment, as shown in FIG. 9, two TrgC and TrgD are generable with one PWM signal. Since the transfer target A / D channel can be arbitrarily set by the CPU 21 for each of the TrgC and TrgD, the A / D conversion data of the different channels of the A / D converter 11 is converted to A / D conversion. It can be stored in the RAM 17 at an interval longer than the interval (in the example of FIG. 9, twice the A / D conversion interval) and at a timing shifted in phase by the pulse width Tduty of the PWM signal. become.

  9 also DMA-transfers the A / D conversion data of the channel ch1 to the RAM 17 by TrgB, and DMA-transfers the A / D conversion data of the channel ch3 to the RAM 17 by TrgC. A case where the A / D conversion data of the channel ch4 is DMA-transferred to the RAM 17 is shown.

  Also in the fourth embodiment, the TrgD generated by the periodic edge of the PWM signal is the method described in the second embodiment (the method of shifting the activation of the A / D activation timer 13 and the PWM signal output circuit 23). Therefore, the generation timing of TrgD may be set to the specific timing during the A / D conversion stop period. For TrgC generated by the duty edge of the PWM signal, the generation timing of the TrgC becomes a specific timing during the A / D conversion stop period by the method for setting the pulse width value of the PWM signal described in the first embodiment. You can do that.

On the other hand, in the fourth embodiment, the circuit 25c in the timer unit 25 corresponds to a data transfer request unit.
[Fifth Embodiment]
By the way, in the microcomputers 10, 20, and 30 of the first, third, and fourth embodiments that generate TrgC by the duty edge of the PWM signal from the PWM signal output circuit 23, the pulse width set in the PWM signal output circuit 23 is set. If the value (the value of the pulse width value register 23b) changes due to factors such as disturbance noise, the generation timing of the TrgC will deviate from the optimal timing. Further, since the microcomputer 20 of the third embodiment generates TrgD by the duty edge of the PWM signal from the PWM signal output circuit 24, the generation timing of the TrgD is also the pulse width value (set to the PWM signal output circuit 24 ( If the value of the pulse width value register 24b is changed due to disturbance noise or the like, the optimum timing is deviated.

  Therefore, as a fifth embodiment, a technique for avoiding such inconvenience will be described. Here, the case where the technique of the fifth embodiment is applied to the microcomputer 20 of the third embodiment will be described as an example. However, the technique of the fifth embodiment is the first and fourth embodiments. The present invention can be similarly applied to the form of the microcomputer. Moreover, in the following description regarding the fifth embodiment, the same reference numerals as those in the third embodiment are used.

  Compared with the microcomputer 20 of the third embodiment, the microcomputer 20 of the fifth embodiment has a PWM signal that is the source of each of the DMA transfer request signals (TrgC and TrgD) output from the timer unit 25 by the CPU 21. The difference is that, for example, the pulse width correction processing for correcting the pulse width setting value is periodically performed.

  For example, in the pulse width correction process, the timing at which the timer unit 25 outputs the TrgC is detected, and the output timing of the TrgC is determined based on the detection result in the A / D conversion stop period. The pulse width setting value of the PWM signal (hereinafter referred to as PWM signal C) from the PWM signal output circuit 23 which is the source of the TrgC is corrected so as to be at a specific timing.

  Next, specific contents of the pulse width correction process will be described. In the following, in order to simplify the description, TrgC is described as an example of TrgC and TrgD, but the same processing is performed for TrgD.

  The pulse width correction process includes first to third correction processes described below. When the regular timing at which the correction of the pulse width set value is to be performed, the first to third correction processes are repeatedly executed at regular intervals sufficiently shorter than the A / D conversion interval. When the pulse width set value is corrected by any of the processes, the execution of all of the first to third correction processes is stopped (that is, the execution of one pulse width correction process is ended).

[First correction processing]
First, in the first correction process, TrgC is output from the time t1 in FIG. 10 at the time when the A / D converter 11 completes the A / D conversion operation just before the TrgC is output from the timer unit 25. A margin time t1 after the completion of A / D conversion, which is a time until completion, is detected as an output timing of TrgC. Based on the detection result, the pulse width setting value of the PWM signal C (ie, the margin time t1 after completion of A / D conversion is equal to the margin time Tma in FIG. 4 which is the target value of the time t1). The value of the pulse width value register 23b) is corrected.

  Next, a more specific description will be given with reference to FIG. FIG. 11 is a flowchart showing the first correction process.

  As shown in FIG. 11, when the CPU 21 starts executing the first correction process, first, in S110, the current process timing is A / D conversion completion timing (ie, the A / D converter 11 is A / D converted). It is determined whether or not it is the timing at which the conversion operation is completed, that is, the timing of the Lead in FIGS.

  In the present embodiment, whether or not the A / D converter 11 has completed the A / D conversion operation can be determined from the status information in the A / D converter 11. Therefore, in S110, the status information is read, the previous status information indicates that the A / D conversion operation has not been completed (A / D conversion is being performed), and the current status information indicates that the A / D conversion operation has been completed. If it is shown, it is determined that this time is the A / D conversion completion timing.

  If it is determined in S110 that it is not the A / D conversion completion timing, the process directly proceeds to S130, but if it is determined that it is the A / D conversion completion timing, the process proceeds to S120 and the current time is reached. The current value of the corresponding free-run timer is updated and stored as the A / D conversion completion time Tead, and then the process proceeds to S130.

  In S130, it is determined whether or not the A / D conversion completion time Tead is already stored by the process of S120. If the A / D conversion completion time Tead is not stored, the first correction process is temporarily performed. If the A / D conversion completion time Tead is already stored, the process proceeds to S140.

  In S140, it is determined whether or not a DMA transfer request signal (TrgC in this example) due to the duty edge of the PWM signal has occurred.

  In this embodiment, when the timer unit 25 outputs TrgC, a trigger generation flag indicating the generation of TrgC is set in the timer unit 25 and the current value of the free-run timer is copied to the trigger generation time register. Is done. In S120 described above, the trigger generation flag is also reset. In S140, it is determined whether TrgC has occurred by referring to the trigger generation flag. That is, if the trigger generation flag is set, it is determined that TrgC has occurred.

  If it is determined in S140 that TrgC has not occurred, the first correction process is temporarily terminated. If it is determined that TrgC has occurred, the process proceeds to S150 and the timer unit 25 is processed. The value stored in the trigger generation time register (that is, the value of the free-run timer when TrgC is generated) is stored as the DMA transfer request signal generation time Tg, and then the process proceeds to S160. If there is no trigger generation time register, in S150, the current value of the free-run timer may be stored as the DMA transfer request signal generation time Tg.

  In S160, the pulse width correction value Tdm is calculated by substituting the latest A / D conversion completion time Tad stored in S120 and the DMA transfer request signal generation time Tg stored in S150 into the following Expression 3. .

Tdm = Tma− (Tg−Tead) (Formula 3)
In Equation 3, Tma is the margin time Tma in FIG. 4, and “Tg−Tead” is an actual measurement value of the margin time t1 after the A / D conversion is completed.

  Next, in S170, the pulse width correction value Tdm calculated in S160 is added to the current pulse width setting value Tduty of the PWM signal C, and the value “Tduty + Tdm” after the addition is added to the corrected pulse width setting value. As Tduty, the pulse width value register 23b in the PWM signal output circuit 23 is reset. That is, the pulse width set value Tduty is corrected by the difference between the measured value of the margin time t1 after completion of A / D conversion and the target value Tma.

  Note that if the generation timing of TrgC is significantly deviated from the target specific timing, for example, if it is delayed to just before the next A / D conversion completion timing, “Tg−Tead” in Expression 3 becomes large. Therefore, there is a possibility that the value “Tduty + Tdm” after the addition becomes 0 or less. Therefore, in S170, when “Tduty + Tdm” becomes 0 or less, a value obtained by adding the A / D conversion interval Tad to “Tduty + Tdm” is stored in the pulse width value register 23b as a corrected pulse width setting value Tduty. set. In S170, if “Tduty + Tdm” after the addition is equal to or greater than the period value Tpwm, a value obtained by subtracting the A / D conversion interval Tad from “Tduty + Tdm” is used as the corrected pulse width setting value Tduty. Is set in the pulse width value register 23b.

  And after such S170, the said 1st correction process is complete | finished.

  By the first correction process as described above, the pulse width setting value of the PWM signal C is corrected so that the margin time t1 after completion of A / D conversion of TrgC becomes equal to the margin time Tma of FIG.

  Similarly, from the PWM signal output circuit 24, the first correction process performed on TrgD causes the margin time t1 (see FIG. 10) after completion of A / D conversion of TrgD to be equal to the margin time Tma in FIG. The pulse width setting value (that is, the value of the pulse width value register 24b) of the PWM signal (hereinafter referred to as PWM signal D) is corrected.

[Second correction process]
First, in the second correction process, A / D conversion is time t2 in FIG. 10 and is the time from when TrgC is output until the A / D converter 11 starts the next A / D conversion operation. The pre-start margin time t2 is detected as the output timing of TrgC. Based on the detection result, the pulse width setting value of the PWM signal C is corrected so that the margin time t2 before the start of A / D conversion becomes equal to the margin time Tmb in FIG. 4 which is the target value of the time t2. .

  Next, a more specific description will be given with reference to FIG. FIG. 12 is a flowchart showing the second correction process.

  As shown in FIG. 12, when the CPU 21 starts executing the second correction process, first, in S210, the CPU 21 determines whether or not a DMA transfer request signal (TrgC in this example) due to the duty edge of the PWM signal has occurred. . In S210, as in S140 of FIG. 11, it is determined whether TrgC has occurred by referring to the trigger generation flag in the timer unit 25. The trigger generation flag is reset by the CPU 21 in advance before the second correction process is first executed.

  If it is determined in this S210 that TrgC has not occurred, the process proceeds to S230 as it is, but if it is determined that TrgC has occurred, the process proceeds to S220 and is similar to S150 in FIG. The value stored in the trigger generation time register in the timer unit 25 or the current value of the free-run timer is stored as the DMA transfer request signal generation time Tg, and then the process proceeds to S230.

  In S230, it is determined whether or not the DMA transfer request signal generation time Tg is already stored by the process of S220. If the DMA transfer request signal generation time Tg is not stored, the second correction process is temporarily performed as it is. If the DMA transfer request signal generation time Tg is already stored, the process proceeds to S240.

  In S240, is the current processing timing the A / D conversion start timing (that is, the timing at which the A / D converter 11 starts the A / D conversion operation, and the timing of Tsad in FIGS. 4 and 10)? Determine whether or not.

  In S240, the status information in the A / D converter 11 is read, the previous status information indicates the completion of the A / D conversion operation, and the current status information indicates that the A / D conversion operation is not completed. If it is shown, it is determined that this time is the A / D conversion start timing. Further, if the CPU 21 can monitor the occurrence of TrgA itself, in S240, it may be determined whether or not TrgA has occurred.

  If it is determined in S240 that it is not the A / D conversion start timing, the second correction process is temporarily terminated as it is, but if it is determined that it is the A / D conversion start timing, S250 is performed. , The current value of the free-run timer corresponding to the current time is stored as the A / D conversion start time Tsad, and then the process proceeds to S260.

  In S260, the pulse width correction value Tdm is calculated by substituting the DMA transfer request signal generation time Tg stored in S220 and the A / D conversion start time Tsad stored in S250 into the following equation 4.

Tdm = (Tsad−Tg) −Tmb Equation 4
In Equation 4, Tmb is the margin time Tmb in FIG. 4, and “Tsad−Tg” is an actual measurement value of the margin time t2 before the start of A / D conversion.

  Next, in S270, the pulse width correction value Tdm calculated in S260 is added to the current pulse width setting value Tduty of the PWM signal C, and the value “Tduty + Tdm” after the addition is added to the corrected pulse width setting value. As Tduty, the pulse width value register 23b in the PWM signal output circuit 23 is reset. That is, the pulse width setting value Tduty is corrected by the difference between the measured value of the margin time t2 before the start of A / D conversion and the target value Tmb.

  When the generation timing of TrgC is significantly deviated from the target specific timing, for example, when it is delayed to just after the next A / D conversion start timing, “Tsad−Tg” in Equation 4 is A / There is a possibility that the value “Tduty + Tdm” after the addition becomes equal to or greater than the period value Tpwm of the PWM signal. Therefore, in S270, when “Tduty + Tdm” becomes equal to or greater than the period value Tpwm, a value obtained by subtracting the A / D conversion interval Tad from “Tduty + Tdm” is used as the pulse width setting value Tduty after correction. Set to 23b. In S270, if “Tduty + Tdm” after the addition becomes 0 or less, a value obtained by adding the A / D conversion interval Tad to “Tduty + Tdm” is used as the corrected pulse width setting value Tduty. Set to the pulse width value register 23b.

  And after such S270, the said 2nd correction process is complete | finished.

  By the second correction process as described above, the pulse width setting value of the PWM signal C is corrected so that the margin time t2 before the start of A / D conversion of TrgC becomes equal to the margin time Tmb of FIG.

  Similarly, the pulse width of the PWM signal D is set so that the margin time t2 (see FIG. 10) before the start of A / D conversion of TrgD becomes equal to the margin time Tmb in FIG. 4 by the second correction process performed on TrgD. The set value is corrected.

[Third correction processing]
First, in the third correction processing, TrgC is output from the time t3 in FIG. 10 at the time when the A / D converter 11 starts the A / D conversion operation just before the TrgC is output from the timer unit 25. A margin time t3 after the start of A / D conversion, which is the time until start, is detected as the output timing of TrgC. Based on the detection result, the pulse width setting value of the PWM signal C is corrected so that the margin time t3 after the start of A / D conversion becomes equal to “Tiad + Tma” in FIG. 4 which is the target value of the time t3. .

  Next, a more specific description will be given with reference to FIG. FIG. 13 is a flowchart showing the third correction process.

  As shown in FIG. 13, when the CPU 21 starts executing the third correction process, first, in S310, whether or not the current processing timing is the A / D conversion start timing, as in S240 of FIG. judge.

  If it is determined that it is not the A / D conversion start timing, the process proceeds to S330 as it is, but if it is determined that it is the A / D conversion start timing, the process proceeds to S320, and the free time corresponding to the current time is reached. The current value of the run timer is updated and stored as the A / D conversion start time Tsad, and the trigger generation flag in the timer unit 25 is reset. Thereafter, the process proceeds to S330.

  In S330, it is determined whether or not the A / D conversion start time Tsad is already stored by the process of S320. If the A / D conversion start time Tsad is not stored, the third correction process is temporarily performed as it is. If the A / D conversion start time Tsad is already stored, the process proceeds to S340.

  In S340, it is determined whether or not a DMA transfer request signal (TrgC in this example) due to the duty edge of the PWM signal has occurred. In S340, as in S140 of FIG. 11, it is determined by referring to the trigger generation flag in the timer unit 25 whether TrgC has occurred.

  If it is determined in step S340 that TrgC has not occurred, the third correction process is temporarily terminated. If it is determined that TrgC has occurred, the process proceeds to step S350, and FIG. As in S150, the value stored in the trigger generation time register in the timer unit 25 or the current value of the free-run timer is stored as the DMA transfer request signal generation time Tg, and then the process proceeds to S360.

  In S360, the pulse width correction value Tdm is calculated by substituting the latest A / D conversion start time Tsad stored in S320 and the DMA transfer request signal generation time Tg stored in S350 into Equation 5 below. .

Tdm = (Tad + Tma) − (Tg−Tsad) (Formula 5)
In Equation 5, “Tad + Tma” is a time obtained by adding the margin time Tma of FIG. 4 to the A / D conversion time Tad shown in FIG. 4, and “Tg−Tsad” is a margin after the start of A / D conversion. It is an actual measurement value at time t3.

  Next, in S370, the pulse width correction value Tdm calculated in S360 is added to the current pulse width setting value Tduty of the PWM signal C, and the value “Tduty + Tdm” after the addition is added to the corrected pulse width setting value. As Tduty, the pulse width value register 23b in the PWM signal output circuit 23 is reset. That is, the pulse width setting value Tduty is corrected by the difference between the actually measured value of the margin time t3 after the start of A / D conversion and the target value “Tiad + Tma”.

  In S370, if “Tduty + Tdm” after the addition is equal to or greater than the period value Tpwm, a value obtained by subtracting the A / D conversion interval Tad from “Tduty + Tdm” is used as the corrected pulse width setting value Tduty. Is set in the pulse width value register 23b. If “Tduty + Tdm” after the addition becomes 0 or less, a value obtained by adding the A / D conversion interval Tad to “Tduty + Tdm” is used as the corrected pulse width setting value Tduty. Set in register 23b.

  And after such S370, the said 3rd correction process is complete | finished.

  By the third correction process as described above, the pulse width setting value of the PWM signal C is corrected so that the margin time t3 after the start of A / D conversion of TrgC becomes equal to “Tiad + Tma” in FIG.

  Similarly, the pulse width of the PWM signal D is set so that the margin time t3 (see FIG. 10) after the start of A / D conversion of TrgD becomes equal to “Tiad + Tma” in FIG. 4 by the third correction process performed on TrgD. The set value is corrected.

  According to the microcomputer 20 of the fifth embodiment as described above, the generation timing of TrgC and TrgD using the duty edge of the PWM signal as a source can be prevented from deviating from the target timing. . Even if the pulse width value of the PWM signal initially set by the above-described initial setting process is an inappropriate value, the pulse width value can be automatically reset to an appropriate value.

  In the microcomputer 30 of the fourth embodiment, the pulse width correction process (first to third correction processes) may be performed on TrgC out of TrgC and TrgD.

On the other hand, as the pulse width correction process, only one or two of the first to third correction processes may be performed. Further, the pulse width correction process may be performed not periodically but irregularly, or may be performed only once at a predetermined timing after the microcomputer is activated, for example.
[Sixth Embodiment]
In the microcomputers 10, 20, and 30 of each of the embodiments described above, if the period values (values of the period value registers 23 a and 24 a) set in the PWM signal output circuits 23 and 24 change due to factors such as disturbance noise, Since the multiple relationship between the period of the PWM signal and the A / D conversion interval is broken, the generation timing of TrgC and TrgD is deviated from the optimum specific timing.

  Therefore, as a sixth embodiment, a technique for avoiding such inconvenience will be described. Here, a case where the technique of the sixth embodiment is applied to the microcomputer 10 of the first embodiment will be described as an example, but the technique of the sixth embodiment is described in the second to fifth embodiments. The present invention can be similarly applied to the form of the microcomputer. Moreover, in the following description regarding the sixth embodiment, the same reference numerals as those in the first embodiment are used.

  The microcomputer 10 of the sixth embodiment is different from the microcomputer 10 of the first embodiment in that the CPU 21 periodically performs the period correction process shown in FIG.

  In the period correction process of FIG. 14, first, in S410, a process of measuring an actual A / D conversion interval is performed.

  Specifically, it is determined whether or not the A / D conversion start timing has arrived at a constant time sufficiently shorter than the A / D conversion interval by the same procedure as S240 in FIG. Each time it is determined as the / D conversion start timing, the value of the free-run timer at that time is stored as the A / D conversion start time Tsad. Then, as shown in FIG. 15, the interval of each A / D conversion start time Tsad stored twice is stored as a measured value of the actual A / D conversion interval Tad. The process of S410 is skipped after the A / D conversion interval Tad can be measured once. Further, the A / D conversion completion timing interval may be measured as the A / D conversion interval Tad.

  Next, in S420, processing for measuring the output interval of the DMA transfer request signal (TrgC in this example) from the timer unit 25 is performed.

  More specifically, first, as a preparation process, a process for resetting the trigger generation flag in the timer unit 25 is performed, and then the trigger generation flag is set at regular intervals sufficiently shorter than the A / D conversion interval. To determine whether TrgC has occurred. Each time it is determined that TrgC has occurred, the trigger generation flag is reset, and the value stored in the trigger generation time register in the timer unit 25, or the free value, as in 150 of FIG. The current value of the run timer is stored as the DMA transfer request signal generation time Tg. Further, as shown in FIG. 15, the interval between the DMA transfer request signal generation times Tg stored twice is stored as an output interval Tint of TrgC.

  Next, in S430, it is determined whether or not the measurement of the A / D conversion interval Tad and the output interval Tint of TrgC is completed, and if those measurements are completed, the process proceeds to S440.

  In S440, the A / D conversion interval Tad measured in the process of S410 and the output interval Tint of TrgC measured in the process of S420 are substituted into Equation 6 below, thereby correcting the period of the PWM signal. A period correction value Ttm is calculated.

Ttm = Tad × n−Tint Equation 6
Note that “n” in Equation 6 is an integer value indicating how many times the PWM signal cycle is initially set to the output cycle (A / D conversion interval) of TrgA. In this embodiment, as described above. “N = 2”.

  Next, in S450, the period correction value Ttm calculated in S440 is added to the current period setting value Tpwm of the PWM signal, and the value “Tpwm + Ttm” after the addition is used as the period setting value Tpwm after correction. Reset to the period value register 23a in the signal output circuit 23. And the period correction process is completed by this resetting.

  That is, in the period correction process, an interval n times the A / D conversion interval Tad (= Tad × n) and an output interval Tint of TrgC that should be the same as that of the A / D conversion interval Tad are detected. By correcting the cycle setting value Tpwm, the output interval Tint of TrgC is made equal to the interval n times the actual A / D conversion interval Tad.

  According to the microcomputer 10 of the sixth embodiment, it is possible to prevent the generation timing of TrgC from being deviated from the target timing.

  In addition, after correcting the cycle setting value by the cycle correction processing (specifically after S450), it is preferable to perform the pulse width correction processing described in the fifth embodiment to also correct the pulse width setting value. . This is to prevent the generation timing of TrgC from deviating from the optimal timing due to the change in the period of the PWM signal.

  Moreover, said period correction process can be implemented similarly in the microcomputers of the second to fifth embodiments. In the microcomputer 20 of the third embodiment, the period correction process may be performed not only for the TrgC and the PWM signal C but also for the TrgD and the PWM signal D. In the microcomputer 30 of the fourth embodiment, the output interval of either one of TrgC and TrgD may be measured in S420 of FIG.

  On the other hand, the period correction process may be performed not regularly but irregularly, or may be performed only once at a predetermined timing after the microcomputer is activated, for example.

  In the process of S410, a slight error occurs in the measured value of the A / D conversion interval Tad. This is because, in the present embodiment, by monitoring the state of the A / D converter 11 at regular time intervals, it is determined that the A / D conversion start timing is detected and the A / D conversion start timing is determined. This is because there is a slight processing delay until the value of the free-run timer is stored, and more strictly speaking, the time for one count of the free-run timer also causes a measurement error. This also applies to the case where the A / D conversion completion timing interval is measured as the A / D conversion interval Tad.

  For this reason, for example, in S410, the A / D conversion interval Tad is measured a plurality of times, and the average value is used to correct the cycle setting value (specifically, substituted into the above-described equation 6). You may make it reduce the influence by the measurement error of / D conversion space | interval Tad. Furthermore, the average value of the measured A / D conversion interval Tad is not used as it is, but the median value of the measurement error (measurement value variation) assumed in design is subtracted from the average value, and the value after the subtraction May be substituted into Equation 6 as a measurement value of the A / D conversion interval Tad.

  If the value of the free-run timer is copied to a specific register at the A / D conversion start timing (or A / D conversion completion timing) of the A / D converter 11, Since the A / D conversion start time (or A / D conversion completion time) can be acquired from a specific register, an error caused by monitoring the state of the A / D converter 11 at regular intervals and a free-run timer There is no worry of errors due to processing delays until the value is stored.

  As mentioned above, although one Embodiment of this invention was described, this invention is not limited to such Embodiment at all, Of course, in the range which does not deviate from the summary of this invention, it can implement in a various aspect. .

  For example, the A / D converter 11 may be configured to A / D-convert analog signals at each input terminal in parallel by a plurality of A / D conversion circuits.

  Further, the transfer target A / D channel set for the DMA controller 16 is not limited to one for each DMA transfer request signal (TrgB, TrgC, TrgD), and a plurality of transfer target A / D channels may be set.

  Further, the microcomputers 10, 20, and 30 are not limited to one-chip microcomputers, and some of the above-described constituent elements may be separate chips. That is, the signal processing apparatus of the present invention may be in the form of a microcomputer composed of a plurality of chips, or may be in a form other than the microcomputer.

  Further, the A / D activation timer 13 is not limited to a timer composed entirely of hardware, but may be a timer using software.

  The A / D conversion target is not limited to the injector pressure signal, but may be, for example, a signal from a cylinder pressure sensor for detecting the pressure in the cylinder of the engine.

  The PWM signal output circuits 23 and 24 output a PWM signal that is low for a time corresponding to the value written in the pulse width value registers 23b and 24b (that is, a PWM signal whose low time is a pulse width). It may be.

It is a block diagram showing the microcomputer of 1st Embodiment and ECU which mounts it. It is a time chart showing operation | movement of each part in the microcomputer of 1st Embodiment. It is explanatory drawing for demonstrating the timing which generates a DMA transfer request signal (TrgC). It is explanatory drawing for demonstrating the pulse width Tduty of the PWM signal set to a pulse width value register. It is a time chart showing operation | movement of each part in the microcomputer of 2nd Embodiment. It is a block diagram showing the microcomputer of 3rd Embodiment, and ECU which mounts it. It is a time chart showing operation | movement of each part in the microcomputer of 3rd Embodiment. It is a block diagram showing the microcomputer of 4th Embodiment and ECU which mounts it. It is a time chart showing operation | movement of each part in the microcomputer of 4th Embodiment. It is explanatory drawing for demonstrating the 1st-3rd correction process performed with the microcomputer of 5th Embodiment. It is a flowchart showing a 1st correction process. It is a flowchart showing a 2nd correction process. It is a flowchart showing a 3rd correction process. It is a flowchart showing the period correction process performed with the microcomputer of 6th Embodiment. It is explanatory drawing for demonstrating a period correction process. It is explanatory drawing for demonstrating the conventional microcomputer.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... ECU (electronic control apparatus), 3 ... Engine, 5 ... Input circuit, IJ1-IJ4 ... Injector, S1-S4 ... Pressure sensor, 10, 20, 30 ... Microcomputer, 11 ... A / D converter, 13 ... A / D start timer, 16, 26 ... DMA controller, 17 ... RAM, 19 ... ROM, 21 ... CPU, 23,24 ... PWM signal output circuit, 23a, 24a ... period value register, 23b, 24b ... pulse width value register, 25 ... Timer unit, 25a, 25b, 25c ... DMA transfer request function circuit, J1, J3 ... Signal output terminal, J2, J4 ... Signal input terminal

Claims (11)

A CPU for executing the program;
When a plurality of input terminals to which analog signals to be A / D converted are input and an A / D conversion request signal instructing execution of A / D conversion is received, a plurality of analog signals from the input terminals are converted to A An A / D converter that outputs an A / D conversion completion signal when the A / D conversion operation is started and the A / D conversion operation is completed;
A / D conversion request means for outputting the A / D conversion request signal to the A / D converter at regular intervals;
A memory for storing A / D conversion data which is data after A / D conversion by the A / D converter;
The A / D conversion completion signal from the A / D converter is provided as a DMA transfer request signal for instructing DMA transfer from the A / D converter to the memory. When receiving a signal, a DMA controller for transferring data from the A / D converter to the memory;
A signal processing apparatus comprising:
A PWM signal output circuit for outputting a PWM signal having a period and a pulse width arbitrarily set by the CPU;
When a PWM signal output from the PWM signal output circuit is input and an edge in a specific direction occurs in the PWM signal, a DMA transfer request signal different from the A / D conversion completion signal is output to the DMA controller. Data transfer request means,
Further, the CPU determines whether the A / D conversion data corresponding to which input terminal of the A / D converter is transferred to the memory for each of the DMA transfer request signals given to the DMA controller. When any of the DMA transfer request signals is received, the received DMA transfer request signal is designated in advance by the CPU among the input terminals of the A / D converter. Transferring A / D conversion data corresponding to the input terminal from the A / D converter to the memory;
A signal processing device. The signal processing device according to claim 1,
The edge of the PWM signal is generated depending on the value of the period among the values of the period and pulse width set in the PWM signal output circuit by the CPU, and is generated depending on the value of the pulse width. There is a periodic edge which is an edge whose timing does not change, and an edge in a direction opposite to the periodic edge, and a duty edge whose generation interval from the periodic edge changes according to the value of the pulse width,
The edge in the specific direction is the periodic edge;
A signal processing device. The signal processing device according to claim 1,
The edge of the PWM signal is generated depending on the value of the period among the values of the period and pulse width set in the PWM signal output circuit by the CPU, and is generated depending on the value of the pulse width. There is a periodic edge which is an edge whose timing does not change, and an edge in a direction opposite to the periodic edge, and a duty edge whose generation interval from the periodic edge changes according to the value of the pulse width,
The edge in the specific direction is the duty edge;
A signal processing device. The signal processing device according to claim 1,
The edge of the PWM signal is generated depending on the value of the period among the values of the period and pulse width set in the PWM signal output circuit by the CPU, and is generated depending on the value of the pulse width. There is a periodic edge which is an edge whose timing does not change, and an edge in a direction opposite to the periodic edge, and a duty edge whose generation interval from the periodic edge changes according to the value of the pulse width,
The edge in the specific direction is both the periodic edge and the duty edge,
The data transfer request means outputs different DMA transfer request signals to the DMA controller when the periodic edge occurs in the PWM signal and when the duty edge occurs in the PWM signal. That
A signal processing device. The signal processing device according to claim 3.
The CPU sets the period of the PWM signal to n times the output period of the A / D conversion request signal (n is an integer of 1 or more), and sets the pulse width of the PWM signal to a predetermined value. And
Further, the CPU detects the timing at which the data transfer request means outputs the DMA transfer request signal, and based on the detection result, the output timing of the DMA transfer request signal from the data transfer request means is The setting value of the pulse width of the PWM signal is set so that it becomes a specific timing during a period from when the A / D converter completes the A / D conversion operation to when the next A / D conversion operation starts. Performing pulse width correction processing to correct,
A signal processing device. The signal processing device according to claim 5,
The CPU performs the pulse width correction process as follows.
From the time when the A / D converter completes the A / D conversion operation immediately before the data transfer request means outputs the DMA transfer request signal, until the data transfer request means outputs the DMA transfer request signal. A margin time after completion of A / D conversion is detected as the output timing of the DMA transfer request signal, and the margin time after completion of A / D conversion is determined based on the detection result after completion of the A / D conversion. A first correction process for correcting a set value of a pulse width of the PWM signal so as to be a target value of a margin time;
A margin time before the start of A / D conversion, which is a time from when the data transfer request means outputs the DMA transfer request signal to when the A / D converter starts the next A / D conversion operation, The pulse of the PWM signal is detected as the output timing of the DMA transfer request signal, and based on the detection result, the margin time before the start of A / D conversion becomes the target value of the margin time before the start of A / D conversion. A second correction process for correcting the set value of the width;
From the time when the A / D converter starts the A / D conversion operation immediately before the data transfer request means outputs the DMA transfer request signal, until the data transfer request means outputs the DMA transfer request signal. A margin time after the start of A / D conversion is detected as an output timing of the DMA transfer request signal, and based on the detection result, the margin time after the start of A / D conversion is Among the third correction processes for correcting the setting value of the pulse width of the PWM signal so as to be the target value of the margin time,
A signal processing device that performs at least one. The signal processing device according to claim 4,
The CPU sets the period of the PWM signal to n times the output period of the A / D conversion request signal (n is an integer of 1 or more), and sets the pulse width of the PWM signal to a predetermined value. And
Further, the CPU detects the timing at which the data transfer request means outputs the DMA transfer request signal corresponding to the duty edge, and based on the detection result, the DMA transfer request corresponding to the duty edge. The PWM signal is set so that the output timing of the signal becomes a specific timing during a period from when the A / D converter completes the A / D conversion operation until the next A / D conversion operation starts. Performing pulse width correction processing to correct the set value of the pulse width of
A signal processing device. The signal processing device according to claim 7,
The CPU performs the pulse width correction process as follows.
From the time when the A / D converter completes the A / D conversion operation immediately before the data transfer request means outputs the DMA transfer request signal corresponding to the duty edge, the data transfer request means The margin time after completion of A / D conversion, which is the time until the DMA transfer request signal corresponding to the edge is output, is detected as the output timing of the DMA transfer request signal corresponding to the duty edge, and the detection result A first correction process for correcting the set value of the pulse width of the PWM signal so that the margin time after completion of A / D conversion becomes a target value of the margin time after completion of A / D conversion, based on
A / D conversion which is the time from when the data transfer request means outputs the DMA transfer request signal corresponding to the duty edge to when the A / D converter starts the next A / D conversion operation A margin time before start is detected as an output timing of the DMA transfer request signal corresponding to the duty edge, and based on the detection result, the margin time before A / D conversion start is the margin before the A / D conversion start. A second correction process for correcting the set value of the pulse width of the PWM signal so as to be a target value of time;
From the time when the A / D converter starts the A / D conversion operation immediately before the data transfer request means outputs the DMA transfer request signal corresponding to the duty edge, the data transfer request means The margin time after the start of A / D conversion, which is the time until the DMA transfer request signal corresponding to the edge is output, is detected as the output timing of the DMA transfer request signal corresponding to the duty edge, and the detection result And a third correction process for correcting the set value of the pulse width of the PWM signal so that the margin time after the start of A / D conversion becomes the target value of the margin time after the start of A / D conversion. home,
A signal processing device that performs at least one. In the signal processing device according to any one of claims 1 to 3, claim 5, and claim 6,
The CPU sets the period of the PWM signal to n times the output period of the A / D conversion request signal (n is an integer of 1 or more),
The CPU further includes a signal output interval that is an interval at which the data transfer request means outputs the DMA transfer request signal and an A / D conversion that is an interval at which the A / D converter performs the A / D conversion operation. The interval of the PWM signal is detected so that the interval of the PWM signal is equal to the interval of n times the A / D conversion interval based on the difference between the detected values. Performing a period correction process to correct the set value,
A signal processing device. In the signal processing device according to any one of claims 4, 7, and 8,
The CPU sets the period of the PWM signal to n times the output period of the A / D conversion request signal (n is an integer of 1 or more),
Further, the CPU outputs an interval at which the data transfer request means outputs a DMA transfer request signal corresponding to the duty edge and a data transfer request means at which the data transfer request means corresponds to the periodic edge. A signal output interval that is any one of the intervals, and an interval that is n times the A / D conversion interval that is the interval at which the A / D converter performs the A / D conversion operation, and both detected values thereof Performing a period correction process for correcting a set value of the period of the PWM signal so that the signal output interval is equal to the interval of n times the A / D conversion interval based on the difference of
A signal processing device. The signal processing device according to any one of claims 1 to 10,
A plurality of sets of the PWM signal output circuit and the data transfer request means;
A signal processing device.