JP5162877B2 - Asynchronous clock switching device, noise cancellation circuit, noise cancellation method and program - Google Patents

Description

  The present invention relates to a clock asynchronous switching device, a noise canceling circuit, a noise canceling method, and a program, and more particularly to a clock asynchronous switching device in a dual (active (ACTIVE) and standby (STANDBY)) configuration used in a switching system of a mobile communication system. The present invention relates to a noise cancellation circuit, a noise cancellation method, and a program.

  FIG. 8 is a block diagram of an example of a conventional clock asynchronous switching device. This shows an example of a clock asynchronous switching device in a duplex (active system (ACTIVE) and standby system (STANDBY)) configuration used for an exchange apparatus of a mobile communication system.

  Referring to FIG. 1, the clock asynchronous switching device 1 includes an LSI (large scale integrated circuit) card substrate 10, a semiconductor device device 20, and a digital signal processing device (DSP: digital signal processor) 30. .

  The LSI card substrate 10 includes a data communication control bus (ACTIVE system) 11, a data communication control bus (STANDBY system) 12, and a selection unit (SELECT) 13.

  Further, a data communication control bus format generation card (ACTIVE system) 40 and a data communication control bus format generation card (STANDBY system) 50 are provided on the input side of the clock asynchronous switching device 1, and each of these cards has a control bus frame. Is generated and output. This control bus frame is synchronized between the ACTIVE system and the STANDBY system.

  On the other hand, in the data communication control bus (ACTIVE system) 11 and the data communication control bus (STANDBY system) 12 in the LSI card substrate 10, the clock field is sampled from the control bus frame at a constant sampling clock c1 (frequency y (kHz)). The generated clocks c2 (frequency x (kHz)) and c4 (frequency x (kHz)) are respectively generated. Thus, the frequency of the sampling clock c1 is set to be the same in the ACTIVE system and the STANDBY system.

  One of the generated clocks c2 and c4 is selected by the selection unit (SELECT) 13, and is output as the clock c5b.

  The clock c5b is supplied to the output semiconductor device device 20. The semiconductor device device 20 outputs a clock c5a corresponding to the clock c5b to the digital signal processing device (DSP) 30.

  Thus, the physical configuration and function of the ACTIVE system and the STANDBY system are the same. For this reason, even if a failure occurs in one of the systems, the function is complemented in the other system so that the exchange does not stack. When complementing this function, work called system switching is performed. However, this system switching is performed asynchronously.

On the other hand, Patent Documents 1 to 3 describe examples of conventional techniques for clock signal switching . In Patent Document 1, a control signal generation circuit generates a stop control signal for stopping each clock signal by several pulses based on the selected original signal, and also generates a delay selection signal. Based on the above, there is described an invention in which the selection system is switched while each clock signal is stopped for several pulses .
Further, in Patent Document 2, the extraction circuit switches and outputs one of the clock signals A or B based on the selection signal, and the output control circuit outputs a short-width pulse in the output of the extraction circuit as the first and first pulses. An invention is described in which a two-detection circuit suppresses a selection signal with a signal generated as a trigger.
Patent Document 3 describes an invention in which hazards in a clock asynchronous switching output signal are removed by an analog integration circuit.

JP 2001-332961 A (paragraphs 0020 to 0026 and FIGS. 1 to 5) Japanese Patent Laid-Open No. 10-154021 Japanese Patent No. 2789811

  However, since this type of clock asynchronous switching device is not synchronized between the sampling clock c1 (ACTIVE system) for sampling the clock field and the sampling clock c3 (STANDBY system), noise at the hazard level at the moment of system switching. (Hereinafter referred to as “hazard noise”) may occur.

  On the other hand, the timing at which hazard noise occurs is only at the moment of system switching, and a normal signal is supplied thereafter. However, the semiconductor device device 20 in the subsequent stage that performs various exchange control using the clock c5b obtained as a result of sampling actually generates erroneous time information once the hazard noise is recognized, and the digital signal processing device (DSP) ) Tell 30. For this reason, the digital signal processing device (DSP) 30 cannot perform processing on the correct time axis, resulting in a system abnormality.

  In other words, in the conventional switching system of a mobile communication system, there is a background in which synchronization is not established between physical cards constituting a duplex. If you only need to switch the system programmatically, the task of removing the faulty card or inserting a new card is done artificially. A complicated circuit must be constructed.

  On the other hand, the inventions described in Patent Documents 1 to 3 are hazard noise cancellation circuits at the time of asynchronous clock switching that can be applied even when there is no limitation on the phase difference between the clock signals of a plurality of systems. This is a hazard noise cancellation circuit at the time of asynchronous clock switching when there is a limit to the maximum value of the signal phase difference.

  In addition, when the rising edge of the noise pulse is detected when the input clock is at a low level, the present invention holds the high level of the noise pulse until the input clock changes to a high level (this is indicated as “mask” in the present invention). However, none of Patent Documents 1 to 3 discloses such a configuration.

As described above, the inventions described in Patent Documents 1 to 3 do not disclose any technique for switching the clock signals of a plurality of systems having a limit on the maximum phase difference value by canceling the hazard noise.

  Therefore, an object of the present invention is to provide a clock asynchronous switching device capable of preventing the occurrence of hazard noise during system switching even when the sampling clock for sampling the clock field is not synchronized between the ACTIVE system and the STANDBY system, and It is an object to provide a noise canceling circuit, a noise canceling method, and a program.

  In order to solve the above problem, a clock asynchronous switching device according to the present invention is a clock asynchronous switching device that selects and outputs one of a plurality of clock signals at an asynchronous timing, and the plurality of clock signals have a frequency. A pulse width that is generated based on different sampling clocks that are equal and asynchronous, monitors the level change of the selected clock signal, and monitors whether the pulse width after the level change is equal to or less than one period of the sampling clock. And a masking unit for masking the selected clock signal in accordance with a monitoring result of the pulse width monitoring unit.

  The noise cancellation circuit according to the present invention is a noise cancellation circuit of a clock asynchronous switching device that selects and outputs one of a plurality of clock signals at an asynchronous timing, and the plurality of clock signals are equal in frequency and asynchronous. Pulse width monitoring means that is a signal generated based on a different sampling clock, monitors the level change of the selected clock signal, and monitors whether the pulse width after the level change is equal to or less than one period of the sampling clock; Masking means for masking the selected clock signal in accordance with the monitoring result of the pulse width monitoring means.

  The noise canceling method according to the present invention is a noise canceling method of a clock asynchronous switching device that selects and outputs one of a plurality of clock signals at an asynchronous timing, and the plurality of clock signals are equal in frequency and asynchronous. A pulse width monitoring step that is a signal generated based on a different sampling clock, monitors a level change of the selected clock signal, and monitors whether the pulse width after the level change is equal to or less than one period of the sampling clock; And a masking step of masking the selected clock signal in accordance with a monitoring result in the pulse width monitoring step.

A program according to the present invention is a program for a noise cancellation method for a clock asynchronous switching device that selects and outputs one of a plurality of clock signals at an asynchronous timing, and the plurality of clock signals are equal in frequency and asynchronous. This is a signal generated based on a different sampling clock, and the computer monitors the level change of the selected clock signal and monitors whether the pulse width after the level change is equal to or less than one period of the sampling clock. A monitoring step;
It is a program for executing a mask step for masking the selected clock signal in accordance with a monitoring result in the pulse width monitoring step.

  Next, the operation of the present invention will be described. The timing at which hazard noise occurs is only at the moment of system switching, and a normal signal is supplied thereafter. Therefore, the pulse width of the hazard noise is limited to a length not longer than one period of the sampling clock.

  In the present invention, as an example, a case is considered in which system switching is performed when a low-level time display clock is input, and then the rising edge of the clock is detected. In this case, if the pulse width of the clock is not more than one period of the sampling clock, it can be determined as hazard noise. Therefore, when the clock is determined to be hazard noise, the high level of the rising pulse is held (masked) until the time display clock changes to the high level next time.

  Focusing on the number of rises of the time display clock, when one hazard noise occurs, the number of rises of the time display clock increases by one. Therefore, by holding (masking) the high level of hazard noise until the time display clock changes to the next high level according to the present invention, the number of rising edges of the time display clock can be reduced by one. The time display clock can be handled in the same manner as when no hazard noise occurs.

  According to the present invention, even when the sampling clock for sampling the clock field is not synchronized between the ACTIVE system and the STANDBY system, it is possible to prevent the occurrence of hazard noise during system switching.

  Embodiments of the present invention will be described below with reference to the accompanying drawings. The present invention includes a noise cancellation circuit 21 for preventing hazard noise in the semiconductor device device 20 in the clock asynchronous switching device 1 of FIG.

  FIG. 1 is a block diagram of an example of a noise cancellation circuit according to the present invention. Referring to the figure, an example of the noise cancellation circuit 21 according to the present invention includes flip-flops 22 and 23, a counter circuit 24, a flip-flop 25, a control unit 26, and a storage unit 27. Is done. The flip-flops 22, 23 and 25 are constituted by D flip-flop circuits as an example.

  The counter circuit 24 includes an exclusive OR circuit (hereinafter referred to as “EX / OR circuit”) 28, a count-up unit 29, and a noise mask circuit 35. As an example, the count-up unit 29 includes a plurality of D flip-flops.

  A common system clock c6 is input to the CLK terminals of the flip-flops 22, 23, 25 and 29. An input clock c5b from the LSI card substrate 10 is input to the input terminal D of the flip-flop 22 as a time display clock. The input clock c5b is equivalent to the selected clock of the generated clock c2 (frequency x (kHz)) and the generated clock c4 (frequency x (kHz)), and includes hazard noise as an example.

  The output terminal Q of the flip-flop 22 is connected to the input terminal D of the flip-flop 23 and one input terminal of the EX / OR circuit 28.

  The output terminal Q of the flip-flop 23 is connected to the other input terminal of the EX / OR circuit 28 and to one input terminal of the noise mask circuit 35.

  The output terminal of the EX / OR circuit 28 is inputted to the input terminal D of the first stage flip-flop constituting a part of the flip-flop 29.

  The output terminal Q of the final stage flip-flop constituting the other part of the flip-flop 29 is connected to the other input terminal of the noise mask circuit 35. The output terminal of the noise mask circuit 35 is connected to the input terminal D of the flip-flop 25.

  From the output terminal Q of the flip-flop 25, a noise-canceled clock (time display clock) c5a is output.

  In other words, the time display clock c5b before noise cancellation is input to the input terminal D of the flip-flop 22, and the time display clock c5a after noise cancellation is output from the output terminal Q of the flip-flop 25.

  The storage unit 27 stores a program for a noise cancellation method described later. The control unit 26 reads out a noise cancellation method program from the storage unit 27 and controls the counter circuit 24 according to the program.

  Next, a process in which hazard noise occurs will be described. 2 and 3 are timing charts showing an example of a process in which hazard noise occurs.

  Referring to FIG. 2, (A) shows the waveform of the sampling clock c1 (ACTIVE system), (B) shows the waveform of the generated clock c2 (ACTIVE system), and (C) shows the sampling clock c3 (STANDBY system). (D) shows the waveform of the generated clock c4 (STANDBY system), and (E) shows the waveform of the input clock c5b to the semiconductor device device 20, respectively.

  The frequency of the generated clocks c2 and c4 is x (kHz), the period is Tx (msec), and the duty is 50%. Therefore, the frequency, period, and duty of the clock (time display clock) c5b input to the semiconductor device device 20 are also x (kHz), Tx (msec), and 50%, respectively.

  The frequencies of the sampling clocks c1 and c3 are common to both systems, and the frequency is y (kHz). On the other hand, the cycle Ty (msec) of the sampling clocks c1 and c3 is set sufficiently shorter than the cycle Tx of the time display clock c5b.

  However, as can be seen from FIGS. 3A and 3C, the sampling clocks are not synchronized between the two systems, so that a phase difference within a cycle Ty (msec) occurs in the sampling clocks between the two systems. FIG. 3A shows a case where the phase difference is relatively small, and FIG. 3 shows a case where the phase difference is maximum.

  In FIG. 2, the clock is switched from the ACTIVE system to the STANDBY system after t1 (msec) from the fall of the pulse of the sampling clock c1, and the generated clock is changed from the generated clock c2 shown in FIG. An example of switching to the generated clock c4 is shown. At this time, a hazard noise pulse p1 is generated in the input clock c5b in FIG. The pulse width of the hazard noise pulse p1 is t2.

  FIG. 3 shows a case where the delay difference between the sampling clocks c1 and c3 is the maximum Ty (msec), and the pulse width of the hazard noise pulse at this time is equal to Ty (msec) and exceeds this. Absent.

  FIG. 4 is a timing chart showing the relationship between the system clock c6 and the sampling clocks c1 and c3. FIG. 4A shows an example of the waveform of the system clock c6, and FIG. 4B shows an example of the waveform of the sampling clocks c1 and c3.

  The system clock c6 is a clock for controlling the clock asynchronous switching device 1.

  Now, assuming that the frequency of the system clock c6 is z (kHz) and the period is Tz (msec), there is a relationship of z> y between the sampling clocks c1 and c3 and the frequency y (kHz). Therefore, there is a relationship of Tz <Ty with respect to the period.

  As described above, since the pulse width of the hazard noise is equal to or less than the pulse width Ty (msec) of the sampling clocks c1 and c3, the pulse width is measured by counting the number of the system clock c6.

  That is, the period Ty (msec) of the sampling clocks c1 and c3 is divided by the period Tz (msec) of the system clock c6, and the result is N. If a fractional part occurs in the value of N, it is rounded down. Then, counting is started from 1, and if the pulse width of the generated pulse is equal to or less than the count number N, it is determined as hazard noise.

  FIG. 5 is a timing chart showing an example of a process for masking the hazard noise of the time display clock c5b. FIG. 4A shows an example of a waveform of a noise mask pulse c7 described later, and FIG. 4B shows an example of a waveform of a time display clock c5b.

  As an example, the level of the time display clock c5b is low when the system is switched, and the pulse width of the rising pulse generated thereafter is equal to or less than N pulses of the system clock c6 (that is, one cycle of the sampling clocks c1 and c3). If it is, it is determined as hazard noise.

  Therefore, when a rising pulse is detected, a noise mask pulse c7 is generated, and the high level p1h of the rising pulse of the hazard noise is held until the time display clock c5b changes to a high level (during time t3) (masking). (See (B) in the same figure).

  Specifically, focusing on the number of rises of the time display clock c5b, when one hazard noise occurs, the number of rises of the time display clock c5b increases by one. Therefore, by holding (masking) the high level of the hazard noise until the time display clock c5b changes to the next high level according to the present invention, the number of rises of the time display clock c5b can be reduced by one. As a result, the time display clock c5b can be handled in the same manner as when no hazard noise is generated.

  Next, an example of the operation of the present invention will be described with reference to FIGS. FIG. 6 is a flowchart showing an example of the operation of the noise cancellation circuit according to the present invention, and FIG. 7 is a timing chart showing an example of the operation of the noise cancellation circuit.

  The counter circuit 24 of the noise cancellation circuit 21 has an up-counter configuration based on the system clock c6 as an example, and the bit width depends on the sampling cycle Ty (msec) in the preceding LSI card substrate 10 in FIG. This is because the value obtained by dividing the sampling period Ty (msec) by the period Tz (msec) of the system clock c6 is set as the maximum counter value N (count) of the counter circuit 24.

  That is, when the pulse width of the time display clock c5b is equal to or smaller than the count value N counts of the counter circuit 24, the pulse is determined to be a hazard noise pulse.

  Specifically, the counter circuit 24 always counts up to the N value, constantly monitors the change of the time display clock c5b with the input hazard noise, and changes the counter value according to the situation.

  For example, if the time display clock c5b does not change even after counting up to the N value, the N value is fixedly output and held until the time display clock c5b is changed. Therefore, the counter circuit 24 recognizes that a correct pulse is input, and outputs the time display clock c5b as it is.

  On the other hand, if the time display clock c5b has changed before reaching the N value, the counter value is forcibly cleared to "0", and then "0" until the time display clock c5b changes. Holds the value. That is, during the period in which the “0” value is held, the hazard noise pulse is input, and during that period, the counter circuit 24 masks and outputs the time display clock c5b (noise cancellation).

  On the other hand, when the time display clock c5b is changed again, the count circuit starts counting up and the counter circuit 24 cancels the mask control.

  Hereinafter, the operation of the noise cancellation circuit 21 will be described in detail with reference to FIGS. 6 and 7.

  The rising edge of the one-stage latch data (one-stage latch data of the time display clock c5b) is detected from the output terminal Q of the flip-flop 22 (FIG. 7A), and the two-stage latch from the output terminal Q of the flip-flop 23 When the rising edge of the data (two-stage latch data of the time display clock c5b) is detected ((B) in FIG. 7), the EX / OR circuit 28 of the counter circuit 24 outputs a high level counter clearing pulse c7. ((C) of FIG. 7). The count-up unit 29 is reset by the counter clearing pulse c7 (step S1 in FIG. 6), and the count-up is started (step S2 in FIG. 6 and (D) in FIG. 7).

  In this case, the noise mask circuit 35 of the counter circuit 24 selects the time display clock c5b output from the output terminal Q of the flip-flop 23 and outputs it to the flip-flop 25 as the time display clock c5a (FIG. 7). (E) This is a case where no hazard noise is generated in the time display clock.

  Next, it is checked whether or not the counter value has reached “N” count. N count has not been reached (in the case of “N” in step S3 in FIG. 6), and the counter value is not “0” count (see FIG. 6). 6 is “N” in step S6), and the level (“0” or “1”) of the time display clock c5b is not changed (in the case of “N” in step S7 in FIG. 6) (F) of FIG. 7), it returns to step S2.

  On the other hand, when the counter value becomes N counts in step S3 in FIG. 6 (in the case of “Y” in step S3 in FIG. 6 and (G) in FIG. 7), there is no change in the level of the time display clock c5b. (In the case of “N” in step S4 in FIG. 6), the counter value is held at N count (step S5 in FIG. 6 and (H) in FIG. 7), and the process returns to step S3.

  Therefore, the time display clock c5b is continuously output to the flip-flop 25 as the time display clock c5a without noise (FIG. 7 (I)).

  On the other hand, if the level of the time display clock c5b has changed in step S4 ("Y" in step S4 and (J) in FIG. 7), the counter clearing pulse c7 ((K in FIG. 7) )), The count-up unit 29 is cleared to "1" (step S9 and (L) in FIG. 7), and the process returns to step S3.

  This indicates that the level of the time display clock c5b has changed normally from the high level to the low level.

  Then, it is assumed that the count is incremented from “1”, the count value reaches “N”, and the “N” value is held ((N) in FIG. 7).

  In this case, the time display clock c5b is continuously output to the flip-flop 25 as the noise-free time display clock c5a (FIG. 7M).

  Next, when the level of the time display clock c5b changes when the count value is held at "N" (in the case of "Y" in step S4), the counter clear pulse c7 (FIG. 7 (O)), the count-up unit 29 is cleared to “1” (step S9 in FIG. 6), the process returns to step S3, and starts counting up again ((P) in FIG. 7).

  Next, when the level of the time display clock c5b is changed before the count value becomes “N” (“N” in step S3, “N” in step S6, “Y” in step S7). "And (Q) in FIG. 7), that is, when the level change of the time display clock c5b is detected with the count value" 2 "((R) in FIG. 7) as an example, the count value is set to" 0 ". Clear (step S8 and (S) of FIG. 7).

  This indicates that the pulse shown in (Q) of FIG. 7 was hazard noise.

When the count value is cleared to “0”, a noise mask pulse ((T) in FIG. 7) is output from the noise mask circuit 35 of the counter circuit 24 to the flip-flop 25.

  Then, a high level signal is output from the output terminal Q of the flip-flop 25 only during the period (t10) when the noise mask pulse is input ((U) in FIG. 7).

  That is, since the high level of the hazard noise is extended by the time (t10), the number of rises of the time display clock increased by one due to the occurrence of the hazard noise is offset.

  Then, the process returns to step S3.

  Next, when there is no change in the level of the time display clock c5b (in the case of “N” in step S3, “Y” in step S6, and “N” in step S10), the count value “0” is set. If the level of the time display clock c5b has changed ("N" in step S3, "Y" in step S6, and "Y" in step S10). ), The counter value is cleared to “1” (step S11), and the process returns to step S3.

  As described above, according to the present invention, after system switching, it is monitored whether or not a pulse having a pulse width equal to or shorter than the sampling period is generated, and when such a pulse is generated, until the next pulse is generated. Since the time display clock is masked, it is possible to prevent the occurrence of hazard noise during system switching even when the sampling clock for sampling the clock field is not synchronized between the ACTIVE system and the STANDBY system. Become.

  Next, the noise cancellation method program will be described. As described above, the semiconductor device device 20 according to the present invention includes the control unit 26 and the storage unit 27 (see FIG. 1).

  The storage unit 27 stores a noise cancellation method program shown in the flowchart of FIG. The control unit (“computer”) 26 reads a program for the noise cancellation method from the storage unit 27 and controls the counter circuit 24 according to the program. Since the control contents have already been described, the description thereof is omitted here.

  In this embodiment, the case where high level hazard noise is generated when the time display clock level is low is described. However, the present invention is not limited to this, and the time display clock level is high. It is clear from the above description that the present invention can also be applied to cases in which low level hazard noise sometimes occurs.

  In the present embodiment, the duplex configuration of the exchange apparatus has been described. However, when the maximum delay difference is clear in an apparatus that selects signals asynchronously, the application of the present invention may be applied to such other apparatuses. Is possible.

  As described above, according to the present invention, a noise canceling circuit can be configured with a relatively simple circuit configuration called a counter circuit, thereby limiting the maximum phase difference value of a plurality of clock signals. In asynchronous clock switching, it is possible to prevent hazard noise from occurring during system switching.

  In addition, since the noise cancellation circuit of the present invention has a circuit configuration that is completely synchronized with the system clock, it can be easily mounted on the apparatus. Further, since the signal can be controlled by the counter circuit, noise can be canceled digitally.

  The operation program of the counter circuit is RTL (register transfer level) description in a general hardware language (VHDL (VHSIC hardware description language, VHSIC: VHSIC: Very High Speed Integral Circuit) or Verilog). Can be easily understood, has no dependency on the silicon process, and has the effect of high diversion.

It is a block diagram of an example of the semiconductor device apparatus which concerns on this invention. It is a timing chart which shows an example of the process in which hazard noise generate | occur | produces. It is a timing chart which shows an example of the process in which hazard noise generate | occur | produces. It is a timing chart which shows the relationship between system clock c6 and sampling clocks c1 and c3. It is a timing chart which shows an example of the process which masks the hazard noise of the clock c5b for time display. 3 is a flowchart showing an example of the operation of the noise cancellation circuit according to the present invention. It is a timing chart which shows an example of operation of the noise cancellation circuit. It is a block diagram of an example of the conventional clock asynchronous switching apparatus.

Explanation of symbols

1 Clock asynchronous switching device
20 Semiconductor device equipment
21 Noise cancellation circuit 22, 23, 25 Flip flop
24 Counter circuit
26 Control unit
27 Storage unit
28 Exclusive OR circuit (EX / OR circuit)
29 Count-up part
35 Noise mask circuit

Claims (15)

A clock asynchronous switching device that selects and outputs one of a plurality of clock signals at an asynchronous timing,
The plurality of clock signals are signals generated based on different sampling clocks having the same frequency and asynchronousness,
Pulse width monitoring means for monitoring the level change of the selected clock signal and monitoring whether the pulse width after the level change is equal to or less than one period of the sampling clock;
Masking means for masking the selected clock signal according to the monitoring result of the pulse width monitoring means;
A clock asynchronous switching device comprising:   The pulse width monitoring means includes an exclusive OR circuit that detects a level change of the selected clock signal, and a counter circuit that counts a time equal to one period of the sampling clock. 1. The clock asynchronous switching device according to 1.   The masking means masks the selected clock signal when the pulse width monitoring means determines that the pulse width of the selected clock signal is equal to or less than one period of the sampling clock. The clock asynchronous switching device according to 1 or 2.   4. The clock asynchronous switching device according to claim 3, wherein the masking means performs masking by holding the level of the clock signal having a pulse width of one cycle or less of the sampling clock until the next level change. .   5. The clock asynchronous switching device according to claim 1, wherein the pulse width monitoring unit and the masking unit are operated by a common system clock. A noise cancellation circuit for a clock asynchronous switching device that selects and outputs one of a plurality of clock signals at an asynchronous timing,
The plurality of clock signals are signals generated based on different sampling clocks having the same frequency and asynchronousness,
Pulse width monitoring means for monitoring the level change of the selected clock signal and monitoring whether the pulse width after the level change is equal to or less than one period of the sampling clock;
Masking means for masking the selected clock signal according to the monitoring result of the pulse width monitoring means;
A noise canceling circuit comprising:   The pulse width monitoring means includes an exclusive OR circuit that detects a level change of the selected clock signal, and a counter circuit that counts a time equal to one period of the sampling clock. 6. The noise canceling circuit according to 6.   The masking means masks the selected clock signal when the pulse width monitoring means determines that the pulse width of the selected clock signal is equal to or less than one period of the sampling clock. The noise cancellation circuit according to 6 or 7.   9. The noise canceling circuit according to claim 8, wherein the masking by the masking means is performed by holding the level of the clock signal having a pulse width of one cycle or less of the sampling clock until the next level change.   10. The noise canceling circuit according to claim 6, wherein the pulse width monitoring unit and the masking unit operate with a common system clock. A noise canceling method for a clock asynchronous switching device that selects and outputs one of a plurality of clock signals at an asynchronous timing,
The plurality of clock signals are signals generated based on different sampling clocks having the same frequency and asynchronousness,
A pulse width monitoring step of monitoring the level change of the selected clock signal and monitoring whether the pulse width after the level change is equal to or less than one period of the sampling clock;
A masking step of masking the selected clock signal according to a monitoring result in the pulse width monitoring step;
A noise canceling method comprising:   The pulse width monitoring step includes an exclusive OR circuit that detects a level change of the selected clock signal and a counter circuit that counts a time equal to one period of the sampling clock. 11. The noise canceling method according to 11.   The masking step masks the selected clock signal when the pulse width of the selected clock signal is determined to be equal to or less than one period of the sampling clock in the pulse width monitoring step. The noise canceling method according to 11 or 12.   14. The noise canceling method according to claim 13, wherein the masking by the masking step is performed by holding the level of the clock signal having a pulse width of one cycle or less of the sampling clock until the next level change.   15. The noise canceling method according to claim 11, wherein the pulse width monitoring step and the masking step are operated by a common system clock.

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