JPS63196114A - Noise removing circuit - Google Patents

Abstract

PURPOSE:To surely remove noise component having a width close to the pulse width of a signal component by providing the sampling circuit of an input signal and a delay circuit giving a delay more than the sampling period to the output signal, comparing the output signals of the circuit so as to control the operation of the holding circuit. CONSTITUTION:A DFF 3 constitutes a sampling circuit, a DFF 4 constitutes a delay circuit, an EXOR 5 forms a comparator and an NOR 6 and a DFF 7 constitute a holding circuit respectively. The DFF 4 gives the delay of a length more than the sampling period to the output signal of the DFF 3. The EXOR 5 outputs a control signal to the NOR 6 when each output signal of the DFFs 3, 4 is not in the same signal level. The DFF 7 holds the output signal from the DFF 4 based on a synchronizing signal (d) and said control signal. When the noise component having a shorter pulse width than said delay time is inputted, a state that each output signal of the DFFs 3, 4 reaches the same signal level and a state that is does not reach the same level are generated depending on the length. The control signal is not outputted in the former state. A control signal is outputted in the latter state, but the output signal of the DFF 4 is not inputted to the holding circuit when the holding circuit is on, and no noise component is outputted from the holding circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a noise removal circuit used in audio and video equipment and the like.

2. Description of the Related Art Conventionally, this type of noise removal circuit has been constructed as shown in FIG. In FIG. 11, 1 is an integrating circuit, 2 is a buffer circuit, and the output side of the integrating circuit 1 is connected to the input side of the buffer 7 circuit 2.

The operation of the noise removal circuit configured as described above will be described below. Figure 12 shows a, b in Figure 11,
c is a waveform diagram showing signal waveforms at each point. In FIG. 12, tl and t2 are the pulse width t1 of the noise component of the input signal of the integrating circuit 1 and the pulse width t2 of the signal component.

If the pulse width t1 of the noise component is sufficiently shorter than the time constant of the integrating circuit, and the pulse width t2 of the signal component is sufficiently longer than the time constant (signal a), the noise component is The pulse is removed (signal b), and only the signal component is output to the output side of the buffer circuit 2.

Problems to be Solved by the Invention Conventional noise removal circuits have the ability to remove noise components with pulse widths that are sufficiently shorter than the time constant of the integrating circuit, as described above, but due to variations in resistance values of resistors, capacitors, etc. The time constant of the integrating circuit changes due to variations in the capacitance of the circuit, and changes in resistance value and capacitance due to temperature changes.

As a result, depending on these conditions, noise components with the same pulse width may be removed in some cases and not in others, and because of this variation, noise components with a pulse width close to the pulse width of the signal component may be removed. There was a problem that it was not suitable for removing.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a noise removal circuit that can reliably remove noise components having a pulse width close to the pulse width of a signal component.

Means for Solving the Problems In order to achieve the above object, the noise removal circuit of the present invention has the following features:
Samples the input signal based on the synchronization signal,
a sampling circuit, a delay circuit that delays the output signal of the sampling circuit by a delay time longer than the sampling period of the sampling circuit, and a comparison between the output signal of the sampling circuit and the output signal of the delay circuit; The delay circuit includes a comparison circuit that outputs a control signal when the output signals are not at the same signal level, and a holding circuit that holds the output signal from the delay circuit based on the synchronization signal and the control signal of the comparison circuit.

Effect According to the above configuration, when a noise component with a pulse width shorter than the delay time of the delay circuit is input, the output signal of the sampling circuit input to the comparator circuit and the output signal of the delay circuit are different depending on the length of the delay time. A first state in which the signal level is the same and a second state in which the signal level is not the same occur.

First, in the first state, the comparison circuit does not output a control signal, and the holding circuit holds and does not output the output signal from the delay circuit.

Next, in the second state, the control signal from the comparison circuit is output, but the output signal of the delay circuit is not input to the holding circuit during the period when the holding circuit is in the on state, and as a result, the noise component is held. No output from the circuit.

That is, noise components having a pulse width shorter than the delay time of the delay circuit are reliably removed.

Embodiment Hereinafter, a noise removal circuit according to an embodiment of the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram showing a noise removal circuit according to an embodiment of the present invention.

In FIG. 1, 3 is a D-type flip-flop circuit (hereinafter abbreviated as DFF) that constitutes a sampling circuit, 4 is a DFF that constitutes a delay circuit, and 6 is a logic that performs an exclusive OR logical operation that constitutes a comparison circuit. circuit (hereinafter abbreviated as XXOR circuit), 6 and 7 are a NOR circuit and D that constitute a holding circuit.
It is FF.

The operation of the above configuration will be explained below.

In addition, in the typing chart explaining the operation, t3
is the period of the clock signal, and t4 is the pulse width of the signal input to the DFF3.

First, a case in which the sampling period of the sampling circuit DFF3 and the delay time of the delay circuit DFF4 match the period of the clock signal will be described with reference to FIGS. 2 to 5.

When a pulse signal e with a pulse width t4 shorter than the period t3 of the clock signal d is input to the DFF3 (Fig. 2), during the period from time t6 to time t7, the output signal r of the DFF3 and the output signal g of the DFF4 is a signal with the opposite level of the H level signal and the L level signal, so the output signal of the XXOR circuit 6 becomes an H level signal for the period from time t6 to time t7. As a result, during the period from time t6 to time t7, the NOR circuit output signal i becomes an L level signal, no clock signal is input to the clock terminal of DFF7, and the DFFT output signal j maintains the state before time t6. However, the signal corresponding to the input signal e to the DFF 3 is not output.

Next, a pulse signal e having a pulse width t4 that is longer than the period ts of the clock signal d and less than twice the period t3 is input to the DFF3, and the pulse of the pulse signal e corresponds to one rising edge of the clock signal d. If it only takes (3rd)
(Figure), during the period from time t6 to time t7, the signal levels of the output signal f of DFFs and the output signal g of DFF4 are at opposite levels, and when a pulse signal with a pulse width shorter than the cycle of the clock signal mentioned above is input to DFF3. Similarly, DFF
The output signal j of 7 retains the state before time t6, and the DFF
The signal corresponding to the input signal 0 to 3 is not output.

Next, a pulse signal e having a pulse width t4 that is longer than the period t3 of the clock signal d and less than twice the period t3 is input to the DFF3, and the pulse of the pulse signal e is generated at two rising edges of the clock signal d. (FIG. 4), the clock signal d rises at times t8 and t9, and the pulse signal e is output from the DFF 3 from time t8 to time t1.
An H level signal is output for G (signal f). Therefore, the DFF 4 outputs an output signal g delayed by the time t3. Therefore I! , from the OR circuit 6, the time t
8 to time t, period from 1 to time t10 to time t1
A signal that is an H level signal is output for 10 periods. As a result, from time t8 to time t
An H level signal is output from time t12 to time t11 in the period of 11, and the H level signal is output from time t1 from DFF7.
A pulse signal j corresponding to the H level signal e is output from time t13 to time t13.

Next, the pulse width t is twice as long as the clock period t5.
<When no pulse signal e is input to DFF3 (6th
), in response to the input signal e, the DFF3 outputs a signal f which is an H level signal for the period from time t14 to time t15.
is output. DFF4 has a period t for the signal ffC.
An H level signal g is output for the period from time t16 to time t17 delayed by 5, and the RxOR circuit 6
An H level signal is output for a period from time t14 to time t169 and time t1s to time t17.

A clock signal indicated by signal i is inputted to the DFF 7, and the DFF 7 outputs a clock signal from time t19 to time tl? An H level signal j is output for a period of .

Therefore, according to this embodiment (according to the present embodiment), at least a noise component whose pulse period is shorter than period t5 and
When a signal having a signal component whose length is twice or more is input to DFF3, the noise component is removed as shown in the second diagram, and the signal component is not removed and is passed from DFF7 as shown in FIG. Output. That is, according to this embodiment, it is possible to remove noise components having a pulse width shorter than half of the signal component.

Next, a case where the delay time of the delay circuit is longer than the sampling period of the sampling circuit will be explained.

FIG. 6 is a circuit diagram showing a noise removal circuit according to another embodiment of the present invention. In FIG. 6, the configuration except for the delay circuit is the same as the configuration shown in FIG. 1, so the same reference numerals are given and detailed explanation thereof will be omitted.

In Fig. 6, 3 is a DF that constitutes a sampling circuit.
F, 5 is an RXOR circuit forming a comparison circuit, and 6.7 is a NOR circuit and DFF forming a holding circuit. The delay circuit is composed of DFF8 and DFF9.

The above configuration will be explained below with reference to FIGS. 7 to 10. It is assumed that the period of the lock signal d is t5, the sampling period of the sampling circuit 3 is 13%, and the delay time t3' of the delay circuit is twice the period t3.

First, when a signal e with a pulse width t4 that is twice as short as the period t5 of the clock signal d is input to the DFF3 (Figure 7).
, the output signal f of the DFF3 is an H level signal for the period from time t20 to time t21, and the output signal g of the DFFs is an H level signal for the period from time t22 to time t25. The output signal of the KxOR circuit 6 is
The signal becomes an H level signal during the period from time t2G to time t21 and from time t22 to time t23. As a result, during the period when the output signal g of the DFF9 is an H level signal,
No clock signal is input to the DFF 9, the output signal j of the DFF 9 is an L level signal, and the pulse signal corresponding to the signal e is not output.

Next, a pulse signal with a pulse width t4 that is more than twice the period t5 of the clock signal d and less than three times the period t3 is input to the DFF3, and the pulse of the pulse signal e is
When two clock signals rise (Figure 8),
With respect to the signal e, the output signal f of the DFF3 is an R level signal for the period from time t24 to time tzs9.
The output signal g of the output signal g of No. 4 is from time t25 to time t2.
The signal becomes an H level signal for a period of 6. and E, OR
The output signal of the circuit 5 is not an H level signal during the period from time t24 to time t26. As a result, during the period when the output signal g of the DFF9 is an H level signal, no clock signal is input to the DFF9, and the DFF9 is not inputted with a clock signal. The output signal j becomes an L level signal, and the pulse signal corresponding to the signal e is not output.

Next, a pulse signal e having a pulse width t4, which is more than twice the period t5 of the clock signal d and less than three times the period t3, is input to the DFF3, and the pulse signal e is divided into three clock signals. (Figure 9), when I
) The output signal g of the DFF9 in response to the signal input to the FF3 changes from time t28 to time t2? The signal becomes an H level signal for the period , and a clock signal is input to the DFF 9 for the period from time t3a to time t31. As a result, a signal j corresponding to the pulse signal of the signal e is outputted from the DFF 9 during a period from time t30 to time t32.Next, a signal having a pulse width t4 that is three times longer than the period t5 of the clock signal d is output. If e is input to DFF3 (
(Fig. 10), the output signal g of DFF9 with respect to the input signal
becomes an H level signal for the period from time tss to time ts4, and DFF9 receives a signal from time tss to time t1.
A clock signal is input for a period of 6. As a result, the DFF 9 outputs a signal j corresponding to the pulse signal of the signal e during a period from time tss to time t37.

Therefore, according to this embodiment, a signal having at least a noise component whose pulse period is twice as short as the period t5 and a signal component whose pulse period is at least three times as long as the period t3 is input to the DFF 3. In this case, the noise component is removed as shown in FIG. 7, and the signal component is output from the DFFT without being removed as shown in FIG. That is, according to this embodiment, it is possible to remove a noise component having a pulse width shorter than that of the signal component.

In addition, in the above-mentioned first example and second example,
A signal having a pulse width less than or equal to W in period t3 of the clock signal is a DFF that is applied to the rising edge of the clock signal.
3, the signal j corresponding to the pulse signal of the input signal e is not sampled and the signal j corresponding to the pulse signal of the input signal e is not output from the DFFT. and a delay circuit that delays the output signal of the sampling circuit by a delay time longer than the sampling period of the sampling circuit, and a comparator circuit compares the output signals of the sampling circuit and the delay circuit to control the operation of the holding circuit. Therefore, when a signal with a pulse width shorter than the delay time of the delay circuit is input, that signal is removed. Therefore, when a noise component with a pulse width shorter than the delay time and a signal component longer than the pulse width of this noise component are input, the noise component can be removed. the result,
Compared to conventional noise removal circuits, it can also remove noise components with long pulse widths, making it possible to improve product reliability.

[Brief explanation of the drawing]

Figure M1 is a circuit diagram showing a noise removing circuit according to an embodiment of the present invention, Figures 2 to 6 are timing charts explaining the operation of the same noise eliminating circuit, and Figure 6 is a circuit diagram showing a noise eliminating circuit according to another embodiment of the present invention. A circuit diagram showing the noise removal circuit, FIGS. 7 to 10 are timing charts explaining the operation of the noise removal circuit, FIG. 11 is a circuit diagram of a conventional noise removal circuit, and FIG. 12 is a diagram of the noise removal circuit. FIG. 3 is a signal waveform diagram of main parts. 3, 4, T...-DFF,!・−・
-・IC2OR circuit, 6...NOR circuit. Name of agent: Patent attorney Toshi Nakao Male #1 or 1st person 1 Figure 3'fight・7−° "D脣ふっしふ°ふ°ふT3y7"MOUNID! ;---Exo Zojiro G----A/ wo shaku 3 sanmen 2 Figure 3 (j) □ Figure 4 Figure 5 (ri Q) 1
a Figure 7 Figure 8 (J) Figure 9 Figure 10 (C) Figure 11 Figure 12

Claims (2)

[Claims] (1) A sampling circuit that samples an input signal based on a synchronization signal, a delay circuit that delays an output signal of the sampling circuit by a delay time longer than the sampling period of the sampling circuit, and an output signal of the sampling circuit. and a comparison circuit that compares the output signal of the delay circuit and outputs a control signal when these output signals are not at the same signal level; and a comparison circuit that outputs a control signal when the output signals are not at the same signal level; A noise removal circuit comprising a holding circuit and a holding circuit. (2) a sampling circuit consisting of a D-type flip-flop circuit that samples an input signal based on a synchronization signal; and at least one circuit that delays the output signal of the sampling circuit by a delay time longer than the sampling period of the sampling circuit. a delay circuit comprising a D-type flip-flop circuit; a comparison circuit comprising an exclusive OR circuit that compares the output signal of the sampling circuit with the output signal of the delay circuit; Basically, the holding circuit includes a holding circuit that holds the output signal from the delay circuit, and the holding circuit includes a NOR circuit that performs a NOR logical operation on the synchronization signal and the output signal of the delay circuit, and the holding circuit that uses the output signal of the NOR circuit as the synchronization signal. 2. The noise removal circuit according to claim 1, further comprising a D-type flip-flop circuit for holding the output signal of the delay circuit for a certain period of time.