JPH08330915A - Clock signal switching circuit - Google Patents

Abstract

PURPOSE: To provide a clock signal switching circuit which prevents generation of whisker (glitches) of the old clock signal when clock signals are switched. CONSTITUTION: A clock signal switching circuit includes a 1st and 3rd D-FF 1 and 5 which output the data according to the level of a selection signal and synchronously with the leading edge of an input clock signal when the level of the selection signal is switched, a 2nd and 4th D-FF 2 and 6 which output the data according to the selection signal level and synchronously with the trailing edge of the clock signal, a 1st NAND 3 to which the output data on both D-FF 1 and 2 and the clock signal are inputted, and a 2nd NAND 7 to which the output data on both D-FF 5 and 6 and the clock signal are inputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal switching circuit for switching an asynchronous clock signal having a redundant structure at the same frequency by a selection signal.

[0002]

2. Description of the Related Art A conventional clock signal switching circuit is disclosed in, for example, Japanese Patent Laid-Open No. 2-290322. The clock signal switching circuit includes a plurality of D-type flip-flops each having a clock signal input section and a selection signal input, and a clock signal that is provided corresponding to each D-type flip-flop and is input to the corresponding D-type flip-flop. A clock signal, which is composed of a 3-input NAND to which a selection signal and output data of the D-type flip-flop are respectively input, and a 2-input NAND to which each output of the 3-input NAND is input, and which is switched by the selection signal is asynchronous. The signals have different frequencies.

[0003]

In the above-mentioned conventional clock signal switching circuit, when the selection signal is switched from non-selection to selection, it is synchronized with each clock signal, whereas the selection signal is selected from non-selection. Since the clock signals are not synchronized with each other when they are switched to, when the clock signals are asynchronous at the same frequency, for example, when the clock signals are switched at the timing (T0 or T2) shown in FIG. A whisker (glitch) is generated in the signal and is output.

Further, the publication discloses a clock signal switching circuit for selecting a clock signal by a selection signal which is asynchronous with respect to a plurality of clock signals. The clock signal switching circuit using the switching circuit has the same frequency and is asynchronous. When a signal is selected, for example, when the selection signal is switched when the level of the selected clock signal is low, one clock is selected and output even though the clock signal is not selected. The selection output of the new clock signal was delayed.

[0005]

A clock signal switching circuit according to the present invention, when the level of a selection signal is switched,
The first and second data corresponding to the level of the selection signal are respectively generated in synchronization with the rising and falling edges of the input clock signal, and the input clock signal of the input clock signal is generated only when the first and second data are at the high level. A plurality of clock output control circuits that output negative-phase clock signals, and a gate circuit that has an input unit connected to the output units of the respective clock output control circuits and that inverts the level of the negative-phase clock signals and outputs Is.

[0006]

In the present invention, when the level of the selection signal is switched, each clock output control circuit generates the first data according to the level of the selection signal in synchronization with the rising edge of the input clock signal, and , The second data corresponding to the level of the selection signal is generated in synchronization with the falling edge of the clock signal. And the first and second
When the data is at the high level, the reverse phase clock signal of the input clock signal is output to the gate circuit. The gate circuit inverts the level of the anti-phase clock signal and outputs it as the clock signal selected by the selection signal.

[0007]

1 is a circuit diagram showing an embodiment of the present invention, FIG.
Is a timing chart for explaining the operation of the circuit.

In the figure, reference numeral 1 denotes a first D-FF, a selection signal SEL is inputted to an input portion D1, a clock signal CLK1 is inputted to a clock input portion C1, and an output portion Q1 is inputted to a first NAND3 having three inputs. It is connected and outputs data according to the level of the selection signal in synchronization with the rising edge of the input clock signal CLK1. When the selection signal is high level, the high level data is output, and when the selection signal is low level, the low level data is output in synchronization with the rising edge of the clock signal CLK1.

Reference numeral 2 is a second D-FF, the selection signal SEL is input to the input section D2, the clock signal CLK1 is input to the clock input section C2, and the output section Q2 is the first NAN described above.
It is connected to D3 and outputs data in the same manner as above in synchronization with the falling edge of the input clock signal CLK1. The first NAND3 has a clock signal CLK1 in addition to the above-mentioned data.
Is input and the output side is connected to the 2-input NAND 8.

Reference numeral 4 is an inverter for inverting the level of the selection signal SEL, 5 is a third D-FF, and the selection signal a whose level has been inverted by the inverter 4 is input to the input section D3 and the clock signal CLK2 is input to the clock input section C3. Are input to the output section Q3, which is connected to the 3-input second NAND 7, and outputs data corresponding to the level of the selection signal in synchronization with the rising edge of the input clock signal CLK2. As described above, when the selection signal is high level, the high level data is output, and when the selection signal is low level, the low level data is output in synchronization with the rising edge of the clock signal CLK2.

A fourth D-FF 6 receives the selection signal a whose level has been inverted by the inverter 4 at the input portion D4 and the clock signal CLK2 at the clock input portion C4, and the output portion Q4 at the above-mentioned first portion. 2 connected to NAND7,
Data is output in the same manner as described above in synchronization with the falling edge of the input clock signal CLK2. The data from the third D-FF 5 and the fourth D-FF 6 and the clock signal CLK2 are input to the second NAND 7, and the output side is the NAND 8 described above.
It is connected to the. The output of the NAND8 is connected to the selected clock output unit SEL-CLK. It should be noted that the first and second D-FFs 1 and 2 and the first NAND 3, and the third NAND
And the fourth D-FFs 5 and 6 and the second NAND 7 constitute the clock output control circuit of the present invention.
D8 corresponds to the gate circuit of the present invention.

Next, the operation will be described based on the timing chart of FIG. First, when the selection signal SEL switches from low level to high level, that is, the clock signal CL
The operation when switching from K2 to the clock signal CLK1 will be described. When the selection signal SEL switches from the low level to the high level at the timing of T0, the second D-FF2 switches the data from the low level to the high level in synchronization with the first falling edge of the clock signal CLK1, and the first D-FF2. F
F1 switches from the low level to the high level in synchronization with the first rising edge of the clock signal CLK1, and outputs from the output sections Q2 and Q1 to the first NAND3.
At this time, the inverter 4 inverts the level of the selection signal to the low level, and the fourth D-FF 6 switches the data from the high level to the low level in synchronization with the first falling edge of the clock signal CLK2, and the third D-FF 6 -FF5 switches from the high level to the low level in synchronization with the first rising edge of the clock signal CLK2, and the output section Q respectively.
4, Q3 outputs to the second NAND7.

On the other hand, the second NAND 7 has a third DF
While the output part Q3 of F5 and the output part Q4 of the fourth D-FF6 are both in the high level, they are in the enabled state and output the reverse phase clock of the clock signal CLK2 (see c in FIG. 2). As described above, when the output sections Q3 and Q4 are switched to the low level, the state becomes disable and the output is fixed to the high level (see T1 timing in FIG. 2). Also,
Although the first NAND3 is in a disable state while the output section Q1 of the first D-FF1 and the output section Q2 of the second D-FF2 are low level, the output is fixed to the high level (see FIG. 2). B) of the output section Q1,
When Q2 is switched to the high level, it becomes the enable state and the anti-phase clock of the clock signal CLK1 is NAND8.
(See T2 timing in Fig. 2). At this time, N
The AND8 outputs the clock signal CLK2 to the selected clock output unit SEL-CLK until the T1 timing, but at that timing, the level of the clock signal CLK2 is set to the low level and continues until the T2 timing, and thereafter, the clock signal CL.
Switch to K1 and output to the selected clock output block SEL-CLK.

Then, when the selection signal SEL switches from the high level to the low level at the timing of T3, the second D-
The FF2 switches data from the high level to the low level in synchronization with the first falling edge of the clock signal CLK1, and the first D-FF1 switches from the high level to the low level in synchronization with the first rising edge of the clock signal CLK1. , The first NAN from the output sections Q2, Q1 respectively
Output to D3. At this time, the inverter 4 inverts the level of the selection signal to the high level, and the fourth D-FF 6 accordingly switches the data from the low level to the high level in synchronization with the first falling edge of the clock signal CLK2. The third D-FF 5 switches the data from the low level to the high level in synchronization with the first rising edge of the clock signal CLK2, and outputs the data from the output parts Q4 and Q3 to the second NAND 7, respectively.

On the other hand, the first NAND 3 has a first DF
While the output section Q1 of F1 and the output section Q2 of the second D-FF2 are in the high level, the reverse phase clock of the clock signal CLK1 is output to the NAND8 (see b in FIG. 2). As described above, when the output sections Q1 and Q2 are switched to the low level, the disable state is set and the output is fixed to the high level (see T4 timing in FIG. 2). In addition, the second NAND7 is connected to the third D-FF5.
Output section Q3 and the output section Q4 of the fourth D-FF 6 are in the disable state while the output level is fixed to the high level (see c in FIG. 2). , Q4 is switched to a high level, it becomes an enable state and outputs a reverse phase clock of the clock signal CLK2 to the NAND8 (see timing T5 in FIG. 2). At this time, the NAND8 outputs the clock signal CLK1 to the selected clock output unit SEL-CLK until the T4 timing, but at that timing, the clock signal CLK1 is set to the low level and continues until the T5 timing, and thereafter, the clock signal CLK2. Switch to and select Clock output block SEL-CLK
Output to.

In this embodiment, the selection signal SEL is set to the first D-
The FF1 synchronizes with the rising edge of the clock signal CLK1, the second D-FF2 synchronizes with the falling edge of the clock signal CLK1, and the level-inverted selection signal a is clocked by the third D-FF5. CLK2
Since the fourth D-FF6 synchronizes on the rising edge of the clock signal and synchronizes on the falling edge of the clock signal CLK2, even if the selection signal SEL is switched, the clock signal selected until then is immediately reset. There is no loss in the waveform of the clock signal because it is output until the next rising or falling, that is,
The effect that the new clock signal can be easily switched without generating a beard (glitch) is obtained.

In the above embodiment, the operation when selecting the clock signals having the same frequency and asynchronous is explained. However, as shown in the timing chart of FIG. 3, clock signals CLK1 and CLK2 which are asynchronous and have different frequencies are used. Selection signal
The effect is also obtained that whiskers do not occur even if selected by SEL. Also, the first to nth
When there is a clock signal of, for example, expansion to a clock signal switching circuit to which a decoder is added is easily possible without complicating the circuit configuration (see FIG. 4).

[0018]

As described above, according to the present invention, when the level of the selection signal is switched, the first and second levels corresponding to the level of the selection signal are synchronized with the rising and falling edges of the input clock signal. Since each data is generated, the old clock signal that has been selected until then is output until the next rising or falling without being immediately reset even if the selection signal is switched. It is possible to prevent the occurrence of a beard (glitch) due to lack of a clock and to easily switch to a new clock signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart for explaining the circuit operation of the embodiment.

FIG. 3 is a timing chart when asynchronously selecting clock signals having different frequencies.

FIG. 4 is a circuit diagram showing an application example of the clock signal switching circuit of the present embodiment.

FIG. 5 is a timing chart when asynchronous clock signals having the same frequency are selected by using the conventional clock signal switching circuit.

[Explanation of symbols]

 1 1st D-FF 2 2nd D-FF 3 1st 3-input NAND 4 Inverter 5 3rd D-FF 6 4th D-FF 7 2nd 3-input NAND 8 2-input NAND

Claims (2)

[Claims] 1. When the level of the selection signal is switched,
The first and second data corresponding to the level of the selection signal are respectively generated in synchronization with the rising and falling edges of the input clock signal, and the input clock signal of the input clock signal is generated only when the first and second data are at the high level. A plurality of clock output control circuits that output negative-phase clock signals, and a gate circuit that has an input unit connected to the output units of the respective clock output control circuits and that inverts and outputs the level of the negative-phase clock signal Clock signal switching circuit characterized by. 2. Each clock output control circuit outputs first data according to the level of the selection signal in synchronization with the rising edge of the input clock signal when the level of the selection signal is switched. Type flip-flop, the selection signal and the clock signal are branched and input, and when the level of the selection signal is switched, the second data corresponding to the level of the selection signal is synchronized with the falling edge of the clock signal. A second D-type flip-flop for outputting and a NAND gate for outputting the negative phase clock signal of the input clock signal only when the clock signal is branched and input and the first and second data are at a high level are provided. The clock signal switching circuit according to claim 1, wherein: