JP5160465B2 - Test circuit, semiconductor integrated circuit, and power supply device - Google Patents

Description

  This application relates to a test circuit, a semiconductor integrated circuit, and a power supply device.

  In recent years, switching regulators (DC / DC converters: power supply devices) that convert and output a constant power supply voltage to a desired power supply voltage are widely used in various electronic devices including portable terminals.

  FIG. 1 is a block diagram for explaining a test state of a conventional power supply apparatus, and shows a state in which a switching regulator is tested by a tester (not shown).

  In FIG. 1, reference numeral 1 is a PWM (Pulse Width Modulation) controller, 21 is a pMOS transistor, 22 is an nMOS transistor, 3 is a coil, 4 is a smoothing capacitor, 100 is an operational amplifier, and 200 is a semiconductor integrated circuit. Yes.

  The switching regulator in FIG. 1 includes a pMOS transistor 21 and an nMOS transistor 22 provided in series between a high potential power supply line to which the power supply voltage VIN is applied and a ground line to which the ground potential GND is applied.

  An output signal of the PWM controller 1 is supplied to the gates of the pMOS transistor 21 and the nMOS transistor 22, and the on / off of the transistors 21 and 22 is controlled.

  The PWM controller 1 uses, for example, an AST (Anti Shoot Through) circuit to prevent the through current from flowing from the high-potential power line to the ground line when both the transistors 21 and 22 are turned on. Is controlled by providing a period Poff in which both are off.

  The node LX is connected to the output terminal OUT via the coil 3, and a smoothing capacitor 4 is provided between the output terminal OUT and the ground line, and an output corresponding to on / off control of the transistors 21 and 22 is provided. The voltage Vout is taken out from the output terminal OUT.

  Here, the signal waveform (LX waveform) at the node (terminal) LX of the switching regulator is important in managing the characteristics of the switching regulator such as power conversion efficiency.

  That is, if the LX waveform changes due to manufacturing variations in the semiconductor integrated circuit used for the switching regulator, etc., the power conversion efficiency also changes. Therefore, the LX waveform test (measurement and evaluation) using a tester is performed during shipping tests. ing.

  Specifically, for example, in a shipment test of a semiconductor integrated circuit used for a switching regulator, an LX waveform test using a tester is performed, and defective products are discarded based on the evaluation result.

  In recent years, switching regulators have increased in operating frequency, for example, in order to improve power conversion efficiency, and even if a tester probe is directly connected to the node LX, the parasitic LCR is large, so that it is accurate. It has become difficult to measure LX waveforms.

  Therefore, in the block diagram of FIG. 1, the LX waveform is shaped using a voltage follower by the operational amplifier 100, and the shaped waveform is sent to a tester for testing (measurement and evaluation).

  Here, the operational amplifier 100 can also be incorporated in the semiconductor integrated circuit 200 for switching regulators having the PWM controller 1 and the transistors 21 and 22, for example. The transistors 21 and 22 may be provided outside the switching regulator semiconductor integrated circuit 200 together with the coil 3 and the smoothing capacitor 4.

Tokai University, "Computer Application Experiment I", Tokai University Faculty of Electronic Information Science, Department of Computer Applied Engineering, 2007, 40-43

  As shown in FIG. 1, a conventional switching regulator test is performed by, for example, shaping an LX waveform using a voltage follower by an operational amplifier 100, and sending the shaped waveform to a tester to perform a test (measurement and evaluation). To do.

  However, the operating frequency of switching regulators is becoming higher, and even if the LX waveform is shaped by the voltage follower, the waveform measured by the tester becomes dull due to the parasitic LCR, making it difficult to perform a correct test. It is becoming.

  Specifically, for example, even if the operating frequency of the switching regulator can be accurately evaluated, the rise / fall (Tr / Tf) evaluation of the LX waveform and the period Poff (OFF-OFF time) in which both the transistors 21 and 22 are turned off. : For example, about 10 ns) is difficult to evaluate.

  That is, for example, a pulse width of 10 ns corresponds to a signal having a frequency of 100 MHz, and it is difficult to take out a signal having such a short pulse width outside the semiconductor integrated circuit and supply it to a tester for testing. Furthermore, ringing may occur even if an operational amplifier with high driving capability is used.

  The problem of the short pulse width described above applies not only to the period when both the transistors 21 and 22 in the switching regulator are turned off, but also to the case where the frequency of the signal to be used is high (for example, a signal having a frequency of 100 MHz or more). is there.

  In this specification, the PWM regulator (PWM controller 1) is described as an example of the switching regulator. However, the switching regulator is not limited thereto, and may be a PFM (Pulse Frequency Modulation) system or the like.

  Furthermore, the signal under test for performing the test is not limited to the LX waveform of the switching regulator but may be signals of various other circuits.

  In view of the above-described problems, an object of the present application is to provide a test circuit, a semiconductor integrated circuit, and a power supply device that can correctly test a signal under test.

  According to the first embodiment, at least one comparator that compares a signal under test with a reference voltage, an oscillator that generates a first signal having a first frequency, a first logic circuit, and at least one frequency divider, A test circuit is provided.

  The first logic circuit takes the logic of the output signal of the comparator and the first signal, and at least one divider divides the output of the first logic circuit and the first signal.

  According to each embodiment, it is possible to provide a test circuit, a semiconductor integrated circuit, and a power supply device that can correctly test a signal under test.

FIG. 1 is a block diagram for explaining a test state of a conventional power supply apparatus. It is a block diagram which shows the test circuit of 1st Example. It is a figure for demonstrating schematically operation | movement of the test circuit of 1st Example. It is a wave form diagram which shows an example of the simulation to which the test circuit of 1st Example is applied. It is a block diagram which shows the test circuit of 2nd Example. It is a block diagram which shows the test circuit of 3rd Example. It is a figure for demonstrating operation | movement of the test circuit of 3rd Example. It is a block diagram which shows the test circuit of 4th Example.

  Embodiments of a test circuit, a semiconductor integrated circuit, and a power supply device will be described in detail below with reference to the accompanying drawings.

  FIG. 2 is a block diagram showing the test circuit of the first embodiment, and shows how the switching regulator is tested by a tester (not shown).

  In FIG. 2, reference numeral 1 is a PWM controller, 21 is a pMOS transistor (first element), 22 is an nMOS transistor (second element), 3 is a coil, 4 is a smoothing capacitor, 5 is a test circuit, and 200 is 1 shows a semiconductor integrated circuit.

  The test circuit 5 includes a diode 51, a comparator (first comparator) 52, an oscillator 53, an AND gate (logical product circuit) 54, a first frequency divider 55, a second frequency divider 56, and a selection circuit (first selection circuit). 57.

  The switching regulator includes a pMOS transistor 21 provided in series between a high potential power supply line (first power supply line) to which the power supply voltage VIN is applied and a ground line (second power supply line) to which the ground potential GND is applied. And an nMOS transistor 22.

  An output signal of the PWM controller 1 is supplied to the gates of the pMOS transistor 21 and the nMOS transistor 22, and the on / off of the transistors 21 and 22 is controlled.

  For example, the PWM controller 1 uses an AST circuit to turn off both the transistors 21 and 22 in order to prevent the transistors 21 and 22 from turning on and the through current from flowing from the high potential power supply line to the ground line. Control is performed by providing a period Poff.

  The node LX is connected to the output terminal OUT via the coil 3 and is connected to the ground line via the diode 51.

  A smoothing capacitor 4 is provided between the output terminal OUT and the ground line, and the output voltage Vout corresponding to the on / off control of the transistors 21 and 22 is smoothed by the smoothing capacitor 4 and taken out from the output terminal OUT.

  Here, the waveform (LX waveform) of the signal (signal under test) at the node (terminal) LX of the switching regulator is supplied to the inverting input (negative input) of the comparator 52 and to the non-inverting input (positive input) of the comparator 52. The first reference voltage Vref1 is applied.

  Note that the first reference voltage Vref1 is set to Vref1 = GND−Vf / 2, for example, where the forward voltage of the diode 51 is Vf, and the both ends of the period Poff in which both the transistors 21 and 22 are off in the LX waveform. The comparator 52 can compare and detect.

FIG. 3 is a diagram for schematically explaining the operation of the test circuit of the first embodiment.
As shown in FIGS. 2 and 3, the output signal COMPout of the comparator 52 is obtained by comparing the LX waveform with the first reference voltage Vref1 to obtain a signal (COMPout) having a pulse (Tpulse) corresponding to the period Poff. It is done.

  The output signal COMPout of the comparator 52 is supplied to the other input of the AND gate 54 in which the output signal (first signal) fosc of the oscillator 53 is supplied to one input. The AND gate 54 calculates the logical product of the output signal COMPout of the comparator 52 and the output signal fosc of the oscillator 53, and the output signal ANDout is supplied to the input of the first frequency divider 55.

  The first frequency divider 55 divides the output signal ANDout of the AND gate 54 by m and supplies the output signal fm to the selection circuit 57. Here, the output signal fosc of the oscillator 53 is also supplied to the input of the second frequency divider 56, and the output signal fout of the second frequency divider 56 obtained by dividing the output signal fosc of the oscillator 53 by n is also sent to the selection circuit 57. Supplied.

  In response to the selection signal S, the selection circuit 57 outputs the output signal fm of the first frequency divider 55 (for example, S is low level “L”) or the output signal fout of the second frequency divider 56 (for example, S is high level). Select “H”) to supply to the tester. The selection signal S is supplied from, for example, a tester, and the tester can recognize whether the signal from the selection circuit 57 is fm or fout.

In FIG. 3, when m is divided by a value obtained by dividing 1 / fm by 1 / fsw, the number of fosc included in ANDout in the period of 1 / fsw is calculated. That is, the following equation (1) is obtained.
m / {(1 / fm) ÷ (1 / fsw)} = (m × fm) / fsw (1)

In addition, the number of fosc included in ANDout in the 1 / fsw period is the number of fosc in the pulse width Tpulse, and the fosc cycle is 2 / (n × fosc). Therefore, the following equation (2) is obtained. It is done.
Tpulse = {(m × fm) / fsw} × {1 / (n × fout)}
= (M × fm) / (n × fout × fsw) (2)

  Accordingly, the pulse width Tpulse in the output signal COMPout of the comparator 52 is calculated by Tpulse = (m × fm) / (n × fout × fsw). Here, the period fsw is known, and the signals fm and fout supplied to the tester are both low frequency signals after frequency division.

  Therefore, even if the low-frequency signals fout and fm are output from the selection circuit 57 to the tester, there is no adverse effect such as waveform dullness due to the parasitic LCR.

  Note that a period fsw that is half the period for driving the switching regulator corresponds to a time from the rising timing of the pulse width (Tpulse) in the output signal COMPout of the comparator 52 to the next rising timing.

  The oscillator 53 can use, for example, a ring oscillator including an odd number of inverters. That is, in the calculation formula of the pulse width Tpulse, the output signal fosc of the oscillator 53 is not directly used, but the signal ratio is used. Therefore, the oscillator 53 does not need to have a particularly high oscillation accuracy, and is simple. A simple ring oscillator can be used.

  In this way, the tester receives the output signal fm of the first frequency divider 55 and the output signal fout of the second frequency divider 56 supplied from the test circuit 5, and the period during which both the transistors 21 and 22 are turned off. A pulse Tpulse corresponding to Poff can be obtained and evaluated.

  As described above, the test circuit 5 can be incorporated in the semiconductor integrated circuit 200 for switching regulator having the PWM controller 1 and the transistors 21 and 22. The transistors 21 and 22 may be provided outside the switching regulator semiconductor integrated circuit 200 together with the coil 3 and the smoothing capacitor 4.

  Thus, according to the test circuit of the first embodiment, it is possible to measure and evaluate an accurate LX waveform even for a switching regulator having a high operating frequency, for example, in order to improve power conversion efficiency. become.

  The switching regulator is not limited to the PWM type, and may be a PFM type or the like. Furthermore, as described above, the signal under test to be tested may be not only the LX waveform of the switching regulator but also signals of various other circuits.

  FIG. 4 is a waveform diagram showing an example of simulation to which the test circuit of the first embodiment is applied. Note that FIG. 4A and FIG. 4B are different in the scale of the time axis in the horizontal direction.

  Here, as a mere example, the frequency division number m of the first frequency divider 55 is, for example, 512 frequency division, and the frequency division number n of the second frequency divider 56 is, for example, 2048 frequency division. In addition, the period fsw that is half the period for driving the switching regulator is 1.0 MHz.

  Since the frequency of the output signal fosc of the oscillator 53 does not need to be set to an accurate value, the frequency is approximately 1.6 GHz, but the simulation results show that the frequency is approximately 1.618 GHz.

  From the above simulation, it can be seen that fm = 31.2373 KHz and fout = 7899989 KHz, and applying the above equation (2) gives the following.

Tpulse = (m × fm) / (n × fout × fsw)
= (512 x 31.2373KHz) ÷ (2048 x 789.989KHz x 1.0MHz)
= 9.9 ns.

  That is, by supplying a signal fm of approximately 30 KHz and a signal fout of approximately 800 KHz to the tester, an extremely narrow pulse width Tpulse of approximately 9.9 ns (approximately 10 ns: corresponding to a signal having a frequency of 100 MHz) can be obtained. I understand.

  Therefore, for example, the test circuit 5 is built in the semiconductor integrated circuit 200 for switching regulator, and the signals having very high frequency components are measured by supplying the low frequency signals fm and fout after frequency division to the tester. And can be evaluated. Needless to say, the test circuit 5 may be provided outside the semiconductor integrated circuit 200.

  FIG. 5 is a block diagram showing a test circuit according to the second embodiment, and shows how the switching regulator is tested by a tester (not shown).

  In FIG. 5, reference numeral 1 is a PWM controller, 21 is a pMOS transistor (first element), 22 is an nMOS transistor (second element), 3 is a coil, 4 is a smoothing capacitor, 5 is a test circuit, and 200 is 1 shows a semiconductor integrated circuit.

  The test circuit 5 includes a comparator (second comparator) 521, a comparator (third comparator) 522, an EOR gate (exclusive OR circuit) 523, an oscillator 53, an AND gate 54, a selection circuit (second selection circuit) 58 and a component. A frequency divider (third frequency divider) 59 is included.

  The switching regulator is the same as that of the first embodiment, and includes a high potential power line (first power line) to which the power supply voltage VIN is applied and a ground line (second power line) to which the ground potential GND is applied. In between, transistors 21 and 22 are provided in series.

  For example, the PWM controller 1 uses an AST circuit to turn off both the transistors 21 and 22 in order to prevent the transistors 21 and 22 from turning on and the through current from flowing from the high potential power supply line to the ground line. Control is performed by providing a period Poff.

  Further, a smoothing capacitor 4 is provided between the output terminal OUT and the ground line, and the output voltage Vout corresponding to on / off control of the transistors 21 and 22 is smoothed by the smoothing capacitor 4 and taken out from the output terminal OUT. This is the same as in the first embodiment.

  The LX waveform at node LX of the switching regulator is supplied to the negative inputs of comparators 521 and 522. The second reference voltage Vref2 is applied to the positive input of the comparator 521, and the third reference voltage Vref3 is applied to the positive input of the comparator 522.

  Here, the second reference voltage Vref2 is set to a voltage slightly lower than the voltage VIN of the high-potential power supply line, for example, a voltage of VIN × 0.9. The third reference voltage Vref3 is set to a voltage slightly higher than the ground potential GND of the low potential power supply line, for example, a voltage of GND + VIN × 0.1.

  As shown in FIG. 5, the LX waveform is compared with the second reference voltage Vref <b> 2 by the comparator 521 and also compared with the third reference voltage Vref <b> 3 by the comparator 522.

  The output signal of the comparator 521 and the output signal of the comparator 522 are supplied to the EOR gate 523, and the characteristics of rising (Tr) and falling (Tf) edges of the LX waveform are expressed by the output signal of the EOR gate 523. It has become.

  That is, the pulse width Tpulse in the output signal of the EOR gate 523 corresponds to the time Ptf when the falling edge of the LX waveform changes from the level of the third reference voltage Vref3 to the level of the second reference voltage Vref2. Alternatively, the pulse width Tpulse corresponds to the time Ptr when the rising edge of the LX waveform changes from the level of the second reference voltage Vref2 to the level of the third reference voltage Vref3.

  The output signal of the EOR gate 523 is supplied to the AND gate 54, and the logical product with the output signal fosc of the oscillator 53 is taken.

  In the test circuit of the first embodiment shown in FIG. 2 described above, the output signal ANDout of the AND gate 54 is m-divided by the first frequency divider 55, and the output signal fosc of the oscillator 53 is the second frequency divider 56. And the signal selected by the selection circuit 57 is supplied to the tester.

  In contrast, in the test circuit of the second embodiment, the output signal ANDout of the AND gate 54 and the output signal fosc of the oscillator 53 are supplied to the selection circuit 57, and the signal selected by the selection circuit 58 is divided by the third frequency. The frequency is divided by a by the vessel 59 and supplied to the tester.

  Here, if the output signal ANDout of the AND gate 54 is a × fm and the output signal fosc of the oscillator 53 is a × fout, the signal frequency-divided by a by the frequency divider 59 via the selection circuit 58 is fm and fout.

As a result, the following expression (3) is obtained.
Tpulse = fm / (fout × fsw) (3)
Thereby, the tester can obtain the pulse width Tpulse.

  Here, the selection signal S supplied to the selection circuit 58 is output from, for example, a tester, and the tester can recognize whether the signal from the selection circuit 58 is a signal based on ANDout or fosc.

  In the second embodiment, the output signal ANDout of the AND gate 54 is divided by m by the first divider 55 and the output signal fosc of the oscillator 53 is divided by the second frequency, as in the first embodiment. It is also possible to supply the signal selected by the selection circuit 57 after being divided by n by the device 56 to the tester.

  As described above, according to the test circuit of the second embodiment, the characteristics of the falling edge or rising edge of the LX waveform (change time between the second and third reference voltage levels) are measured and evaluated as the pulse width Tpulse. be able to.

  The measurement of the pulse width Tpulse is performed by supplying a signal having a reduced frequency to the tester via the third frequency divider 59, as in the first embodiment described above. An extremely narrow pulse width Tpulse can be obtained without being affected.

  In the test circuit of the second embodiment shown in FIG. 5 described above, the second reference voltage Vref2 is set to the first reference voltage Vref1, and the third reference voltage Vref3 is set to the power supply voltage VIN (high level “H”). A circuit equivalent to the test circuit of the first embodiment shown in FIG. 2 can be obtained.

  FIG. 6 is a block diagram showing the test circuit of the third embodiment, and FIG. 7 is a diagram for explaining the operation of the test circuit of the third embodiment.

  That is, the test circuit of the third embodiment discriminates whether the measured pulse width Tpulse, which was not recognized in the second embodiment, exhibits the characteristics of the rising edge or the falling edge of the LX waveform. It is possible.

  As is clear from the comparison between FIG. 6 and FIG. 5 described above, the test circuit of the third embodiment is obtained by providing a selection circuit (third selection circuit) 524 with respect to the test circuit of the second embodiment. Equivalent to.

  The selection circuit 524 is inserted between the EOR gate 523 and the AND gate 54, and indicates whether the pulse width Tpulse exhibits the characteristics of the rising edge or the falling edge of the LX waveform with the signal under test (LX waveform) as the selection signal. Is to be determined.

  That is, as shown in FIG. 7, when the selection signal (LX waveform) of the selection circuit 524 is at a high level “H”, the tester recognizes that the pulse width Tpulse represents the characteristic Ptr of the rising edge of the LX waveform. To do.

  When the selection signal of the selection circuit 524 is at the low level “L”, the tester recognizes that the pulse width Tpulse represents the characteristic Ptf of the falling edge of the LX waveform. The signal under test (selection signal of the selection circuit 524) is supplied to the tester.

  As described above, according to the test circuit of the third embodiment, measurement and evaluation can be performed by recognizing whether the pulse width Tpulse relates to the rising edge or the falling edge of the signal under test.

  Here, also in the third embodiment, as in the second embodiment, when the output signal ANDout of the AND gate 54 is a × fm and the output signal fosc of the oscillator 53 is a × fout, the selection circuit 58 is used. Thus, the signals divided by a by the frequency divider 59 become fm and fout.

Then, as shown in FIG. 7, since fsw ′ is twice fsw, the following equation (4) is obtained.
Tpulse = fm / (fout × 2 × fsw) (4)
Thereby, the tester can obtain the pulse width Tpulse.

  FIG. 8 is a block diagram showing the test circuit of the fourth embodiment. The function of the test circuit of the second embodiment shown in FIG. 5 is added to the test circuit of the first embodiment shown in FIG. It corresponds to a thing. Here, the semiconductor integrated circuit 200 is for, for example, three switching regulators that output three different output voltages Vout1, Vout2, and Vout3.

  That is, the semiconductor integrated circuit 200 includes three switching regulator PWM controllers 11 to 13, pMOS transistors 211 to 213, and nMOS transistors 221 to 223.

  Further, the power supply device corresponds to three switching regulators, three coils 31 to 33, three smoothing capacitors 41 to 43, and three diodes 511 to 111 corresponding to the diode 51 described in the first embodiment. 513.

  The test circuit 5 includes first to third comparators 52, 521, 522, an EOR gate 523, an oscillator 53, an AND gate 54, first and second frequency dividers 55, 56, and a first selection circuit 57. The above-described diodes 511 to 513 are built in the semiconductor integrated circuit 200 as the test circuit 5, for example.

  Further, the test circuit 5 selects a selection circuit 501 for selecting three signals under test from the nodes LX1 to LX3 of the three switching regulators, and a selection for selecting an output signal of the thirteenth comparator 52 or an output signal of the EOR gate 523. A circuit 502 is included.

  The selection signals S1, S2, and S3 from the tester are supplied to the selection circuit 501, the selection circuit 502, and the first selection circuit 57, and the period Poff and the edge characteristics Ptr and Ptf in each of the test signals described above are supplied. Measurement and evaluation are to be performed. Note that the number of switching regulators is not limited to three.

  Here, the switching regulator is not limited to the PWM type, and the output transistor of the switching regulator is not limited to one using both pMOS and nMOS.

  Furthermore, the signal under test to be tested is not limited to the LX waveform of the switching regulator, but may be signals of various other circuits.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
At least one comparator for comparing the signal under test with a reference voltage;
An oscillator for generating a first signal of a first frequency;
A first logic circuit that takes the logic of the output signal of the comparator and the first signal;
A test circuit comprising: an output of the first logic circuit; and at least one frequency divider that divides the first signal.

(Appendix 2)
In the test circuit described in Appendix 1,
The test circuit according to claim 1, wherein the at least one comparator includes a first comparator that compares the signal under test with a first reference voltage.

(Appendix 3)
In the test circuit described in Appendix 2,
The test circuit, wherein the first reference voltage is a voltage for measuring a time width with respect to a certain level in the waveform of the signal under test.

(Appendix 4)
In the test circuit described in Appendix 1,
The at least one comparator includes a second comparator that compares the signal under test with a second reference voltage, and a third comparator that compares the signal under test with a third reference voltage. .

(Appendix 5)
In the test circuit described in Appendix 4,
The test circuit, wherein the second reference voltage and the third reference voltage are voltages for measuring time widths for two different levels in the waveform of the signal under test.

(Appendix 6)
In the test circuit according to appendix 4 or 5,
A second logic circuit for receiving the output signal of the second comparator and the output signal of the third comparator;
The test circuit according to claim 1, wherein the first logic circuit takes a logic of an output signal of the second logic circuit and the first signal.

(Appendix 7)
In the test circuit described in Appendix 6,
The test circuit, wherein the second logic circuit is an exclusive OR circuit.

(Appendix 8)
In the test circuit according to any one of appendices 4 to 7,
An edge corresponding to an output signal received from the second logic circuit, selected according to the level of the signal under test, which signal is related to a rising edge or a falling edge of the signal under test and supplied to the first logic circuit A test circuit comprising a signal selection circuit.

(Appendix 9)
In the test circuit according to any one of appendices 1 to 8,
The test circuit according to claim 1, wherein the first logic circuit is an AND circuit.

(Appendix 10)
In the test circuit according to any one of appendices 1 to 9,
The at least one divider has a first divider that divides the output signal of the first logic circuit by m, and a second divider that divides the first signal by n.
The test circuit further includes a first selection circuit that selects and outputs one output signal of the first frequency divider or the second frequency divider according to a selection signal.

(Appendix 11)
In the test circuit according to any one of appendices 1 to 9,
A second selection circuit for selecting and outputting one of the output signal of the first logic circuit or the first signal;
The test circuit according to claim 1, wherein the at least one frequency divider includes a third frequency divider that divides the output signal of the second selection circuit by a.

(Appendix 12)
In the test circuit according to any one of appendices 1 to 11,
A test circuit comprising a third selection circuit for selecting a plurality of the signals under test.

(Appendix 13)
In a test circuit having the first comparator according to appendix 2 or 3, and the second and third comparators according to appendix 4 or 5,
A test circuit comprising a fourth selection circuit that selects and outputs one of the output signal of the first comparator or the output signal of the second or third comparator.

(Appendix 14)
In the test circuit according to any one of appendices 1 to 13,
An output signal of the test circuit is supplied to a tester and measured and evaluated.

(Appendix 15)
The test circuit according to any one of the supplementary notes 1 to 14,
A first switch element and a second switch element provided in series between the first power line and the second power line;
A control circuit that controls on / off of the first and second switch elements by providing a period during which both the first and second switch elements are turned off. A semiconductor integrated circuit characterized by being a signal of a connection node of the second switch element.

(Appendix 16)
The semiconductor integrated circuit according to appendix 15, and
A coil having one end connected to a common connection node of the first and second switch elements;
And a smoothing capacitor provided between the other end of the coil and the second power supply line.

(Appendix 17)
The power supply device according to attachment 16, wherein the test circuit further includes:
A diode element provided between a common connection node of the first and second switch elements and the second power supply line, wherein the first reference voltage is reduced from a ground potential to a forward drop voltage of the diode element; A power supply device characterized in that the voltage is set to a value obtained by subtracting half.

DESCRIPTION OF SYMBOLS 1,11-13 PWM controller 3,31-33 Coil 4,41-43 Smoothing capacitor 5 Test circuit 21 pMOS transistor 22 nMOS transistor 51,511-513 Diode 52 1st comparator 53 Oscillator 54 1st logic circuit (AND gate) )
55 1st frequency divider 56 2nd frequency divider 57 1st selection circuit 58 2nd selection circuit 59 3rd frequency divider 521 2nd comparator 522 3rd comparator 100 Operational amplifier 200 Semiconductor integrated circuit

Claims (7)

At least one comparator for comparing the signal under test with a reference voltage;
An oscillator for generating a first signal of a first frequency;
A first logic circuit that takes the logic of the output signal of the comparator and the first signal;
A test circuit comprising: an output of the first logic circuit; and at least one frequency divider that divides the first signal. The test circuit according to claim 1,
The test circuit according to claim 1, wherein the at least one comparator includes a first comparator that compares the signal under test with a first reference voltage. The test circuit according to claim 1,
The at least one comparator includes a second comparator that compares the signal under test with a second reference voltage, and a third comparator that compares the signal under test with a third reference voltage. . The test circuit of claim 3, further comprising:
A second logic circuit for receiving the output signal of the second comparator and the output signal of the third comparator;
The test circuit according to claim 1, wherein the first logic circuit takes a logic of an output signal of the second logic circuit and the first signal. In the test circuit according to any one of claims 1 to 4,
The at least one divider has a first divider that divides the output signal of the first logic circuit by m, and a second divider that divides the first signal by n.
The test circuit further includes a first selection circuit that selects and outputs one output signal of the first frequency divider or the second frequency divider according to a selection signal. The test circuit according to any one of claims 1 to 5,
A first switch element and a second switch element provided in series between the first power line and the second power line;
A control circuit that controls on / off of the first and second switch elements by providing a period during which both the first and second switch elements are turned off. A semiconductor integrated circuit characterized by being a signal of a connection node of the second switch element. A semiconductor integrated circuit according to claim 6;
A coil having one end connected to a common connection node of the first and second switch elements;
And a smoothing capacitor provided between the other end of the coil and the second power supply line.

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