JP2014106112A - Voltage variation detection circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the sensitivity of detecting a voltage variation during voltage variation detection.SOLUTION: An operation voltage generation unit 12 generates an operation voltage of an oscillation circuit 11 by lowering a voltage to be detected (a potential difference (power supply voltage) between wiring vdd (power supply wiring) and wiring vss (ground line) in an example of Figure 1). The oscillation circuit 11 performs an oscillation operation by receiving the operation voltage. A variation detection unit 13 detects the variation of the voltage to be detected by measuring the oscillation frequency of the oscillation circuit 11. Accordingly, the variation rate of the oscillation frequency of the oscillation circuit 11 increases, thereby allowing the sensitivity of detecting a voltage variation during voltage variation detection to be improved.

Description

  The present invention relates to a voltage fluctuation detection circuit and a semiconductor integrated circuit.

  Conventionally, there has been a technique using an oscillation circuit (for example, a ring oscillator) in order to detect a fluctuation in power supply voltage due to the influence of noise generated in a semiconductor integrated circuit. In this method, the fluctuation of the power supply voltage is detected by measuring the oscillation frequency of the oscillation circuit driven by the power supply voltage.

JP-A-8-18339 JP 2010-103971 A JP-A-8-68814

  The conventional method using the oscillation circuit has a problem that the fluctuation of the oscillation frequency with respect to the fluctuation of the power supply voltage is small and the detection sensitivity as a voltage sensor is small.

  According to one aspect of the invention, an oscillation circuit that performs an oscillation operation in response to an operation voltage, an operation voltage generation unit that generates the operation voltage by lowering a voltage to be detected, and an oscillation frequency of the oscillation circuit are measured A voltage fluctuation detection circuit is provided that includes a fluctuation detection unit that detects fluctuations in the voltage.

  According to another aspect of the invention, an oscillation circuit that receives an operating voltage to perform an oscillation operation, an operating voltage generation unit that generates the operating voltage by lowering a voltage to be detected, and an oscillation frequency of the oscillation circuit are measured Thus, there is provided a semiconductor integrated circuit having a voltage fluctuation detecting circuit including a fluctuation detecting unit that detects the voltage fluctuation.

  According to the disclosed voltage fluctuation detection circuit and semiconductor integrated circuit, it is possible to increase sensitivity for detecting voltage fluctuation.

1 is a diagram illustrating an example of a semiconductor integrated circuit and a voltage variation detection circuit according to a first embodiment; It is a figure which shows an example of the semiconductor integrated circuit and voltage fluctuation detection circuit of 2nd Embodiment. It is a timing chart which shows the 1st operation example of the voltage variation detection circuit of 2nd Embodiment. It is the figure which expanded a part of FIG. 12 is a timing chart illustrating a second operation example of the voltage variation detection circuit according to the second embodiment. It is a figure which shows the example of a simulation result of the power supply voltage _VDD dependence of the operating voltage _VDDV of the oscillation circuit by the difference in PSRR of an operating voltage generation part. It is a figure which shows the simulation result of the power supply voltage _VDD dependence of the oscillation frequency f of the oscillation circuit by the presence or absence of an operating voltage production | generation part, and the oscillation frequency fluctuation rate (lambda). It is a figure which shows an example of the semiconductor integrated circuit and voltage fluctuation detection circuit of 3rd Embodiment. 12 is a timing chart illustrating an operation example of the voltage variation detection circuit according to the third embodiment. It is a figure which shows the example of a simulation result of the voltage V _CC dependence of the operating voltage V _CCV of the oscillation circuit due to the difference in PSRR of the operating voltage generator. It is a figure which shows the simulation result of the voltage _VCC dependence of the oscillation frequency f of the oscillation circuit by the presence or absence of an operating voltage generation part, and the oscillation frequency fluctuation rate (lambda). It is a figure which shows an example of the semiconductor integrated circuit and voltage fluctuation detection circuit of 4th Embodiment. It is a figure which shows the example of a simulation result of the voltage _VCC dependence of the operating voltage _VCCC of the oscillation circuit of the voltage variation detection circuit of 4th Embodiment. It is a figure which shows the simulation result of the voltage _VCC dependence of the oscillation frequency f of the oscillation circuit by the presence or absence of an operating voltage generation part, and the oscillation frequency fluctuation rate (lambda). It is a figure which shows an example of the semiconductor integrated circuit and voltage fluctuation detection circuit of 5th Embodiment. This is a circuit in which an operating voltage generation unit and an oscillation circuit are represented by a resistance component and a capacitance component. Is a diagram showing an example state of the transient response of the operating voltage V _CCV voltage V _CC and the oscillation circuit. It is a figure which shows an example of the semiconductor integrated circuit and voltage fluctuation detection circuit of 6th Embodiment. It is sectional drawing which shows an example of pMOS contained in an oscillation circuit. It is a figure which shows the example of a simulation result of the voltage _VCC dependence of the operating voltage _VCCC of the oscillation circuit of the voltage variation detection circuit of 6th Embodiment. It is a figure which shows the simulation result of the voltage _VCC dependence of the oscillation frequency f of an oscillation circuit, and the oscillation frequency variation rate (lambda). It is a figure which shows an example of the semiconductor integrated circuit and voltage fluctuation detection circuit of 7th Embodiment. 16 is a timing chart illustrating an operation example of the voltage variation detection circuit according to the seventh embodiment. It is a figure which shows an example of the semiconductor integrated circuit and voltage fluctuation detection circuit of 8th Embodiment. It is a figure which shows an example of the semiconductor integrated circuit and voltage fluctuation detection circuit of 9th Embodiment. It is sectional drawing which shows an example of nMOS contained in an oscillation circuit. It is a figure which shows an example of the semiconductor integrated circuit and voltage fluctuation detection circuit of 10th Embodiment. It is a timing chart which shows the operation example of the voltage fluctuation detection circuit of 10th Embodiment.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating an example of a semiconductor integrated circuit and a voltage variation detection circuit according to the first embodiment.

  The semiconductor integrated circuit 1 includes a wiring (power supply wiring) vdd, a wiring (ground line) vss, and a voltage fluctuation detection circuit 10. In the example of the semiconductor integrated circuit 1 according to the first embodiment, it is assumed that the wiring vdd has a power supply potential and the wiring vss has a reference potential (ground potential). Note that the waveform w1 indicates a change in the power supply potential due to the noise source ns connected to the wiring vdd.

  The voltage fluctuation detection circuit 10 of the first embodiment detects fluctuations in the voltage (power supply voltage) between the wiring vdd and the wiring vss. The oscillation circuit 11, the operating voltage generation unit 12, the fluctuation detection unit 13, A level shifter 14 is provided.

  The oscillation circuit 11 performs an oscillation operation in response to the operation voltage generated by the operation voltage generation unit 12. An output signal (oscillation signal) of the oscillation circuit 11 is input to the fluctuation detection unit 13 via the level shifter 14. The oscillation circuit 11 is connected to the wiring vss. The oscillation circuit 11 is, for example, a ring oscillator.

  The operating voltage generator 12 generates operating voltages for the oscillation circuit 11 and the level shifter 14 by reducing the voltage to be detected. In the example of the voltage fluctuation detection circuit 10, the voltage to be detected is a power supply voltage. The operating voltage generation unit 12 is connected to the wiring vdd, generates a voltage lower than the potential of the wiring vdd, and supplies the voltage to the oscillation circuit 11 as the operating voltage of the oscillation circuit 11. In this way, the operating voltage generator 12 functions as a step-down circuit that lowers the power supply voltage.

  The operating voltage generator 12 generates an operating voltage that varies according to the variation in the voltage to be detected. That is, the operating voltage generation unit 12 transmits the fluctuation of the power supply voltage to the operating voltage of the oscillation circuit 11 to be generated. For this reason, it is desirable that the operating voltage generation unit 12 has a small PSRR (Power Supply Rejection Ratio). This is because the influence of the fluctuation of the power supply voltage on the oscillation frequency of the oscillation circuit 11 is increased, and the detection accuracy in the fluctuation detector 13 is increased. In addition, when PSRR is small, there is an effect that power consumption can be reduced (for details, see formulas (6) and (8) described later). In the case of this example, PSRR is expressed by a change in potential of the wiring vdd / change in operating voltage. An example of the operating voltage generator 12 having a low PSRR is a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) having its gate and drain connected (diode-connected).

  The fluctuation detecting unit 13 receives the output signal (an example is shown by the waveform w2) of the oscillation circuit 11 sent via the level shifter 14, and measures the oscillation frequency of the oscillation circuit 11 to thereby change the voltage. Is detected. The detection result is output outside the voltage fluctuation detection circuit 10 and is output from, for example, an external terminal (not shown) of the semiconductor integrated circuit 1. For example, the fluctuation detection unit 13 counts the number of rising edges of the waveform w2 within a unit time, and detects a voltage fluctuation from the change. For example, when the voltage decreases due to the influence of noise, the number of counts per unit time decreases.

  The level shifter 14 adjusts the amplitude of the output signal of the oscillation circuit 11 according to the amplitude of the operating voltage of the fluctuation detector 13. In the example of the voltage fluctuation detection circuit 10 of the first embodiment, the fluctuation detection unit 13 is assumed to operate at the potential level (that is, the power supply voltage) of the wiring vdd. Therefore, the level shifter 14 is connected to the wiring vdd, and changes the amplitude of the stepped-down output signal of the oscillation circuit 11 to the potential level of the wiring vdd. Thereby, the fluctuation | variation detection part 13 can detect an oscillation frequency accurately. For example, the fluctuation detector 13 operates even at the signal level of the output signal of the oscillation circuit 11, and if the output signal of the oscillation circuit 11 can be detected, the level shifter 14 may be omitted.

  In such a voltage fluctuation detection circuit 10, the oscillation circuit 11 is operated with an operating voltage in which the voltage to be detected is reduced, so that the oscillation frequency fluctuation rate of the oscillation circuit 11 can be increased. Since the oscillation frequency variation rate is a sensitivity with which the voltage variation detection circuit 10 can detect the voltage variation, the sensitivity can be increased by increasing the oscillation frequency variation rate. Further, by increasing the oscillation frequency variation rate, the power consumption of the oscillation circuit 11 can be suppressed, and as a result, the power consumption of the voltage variation detection circuit 10 and the semiconductor integrated circuit 1 can be suppressed.

The reason will be described below using mathematical expressions.
In the following formulas (1) to (7), assuming that the operating voltage of the oscillation circuit 11 is the power supply voltage V _DD , the relationship between the magnitude of the power supply voltage V _DD and the consumed energy E _total will be described.

Assuming that, for example, a ring oscillator is used as the oscillation circuit 11, the oscillation frequency f _rosc of the oscillation circuit 11 is expressed by the following equation (1), for example.

  In Expression (1), 2N + 1 is the number of stages of the inverter circuit included in the oscillation circuit 11, and τ is the signal propagation delay of the inverter circuit. On the other hand, the signal propagation delay τ of the inverter circuit is expressed by the following equation (2).

In Expression (2), β is β = μCox (W / L) (μ is the mobility of electrons, Cox, W, and L are gate capacitance per unit area of the transistor used in the oscillation circuit 11, gate width, Gate length). K is a proportional coefficient, V _DD is a power supply voltage, V _th is a threshold voltage of the transistor, α is a value given empirically depending on the short channel effect, and is a value of about 1-2. Cinv is an average load capacity seen when driving one inverter circuit.
Substituting equation (2) into equation (1) leads to the following equation (3).

If Expression (3) is used, the energy consumption E _total of the voltage fluctuation detection circuit 10 can be expressed by the following Expression (4), for example.

In equation (4), E _rosc and E _counter indicate the energy consumption of the oscillation circuit 11 and the energy consumption of the fluctuation detection unit 13, respectively. Further, α _gate is the operation rate of the fluctuation detection unit 13, n _gate is the number of _gates of the fluctuation detection unit 13, and C _gate is an average load that can be seen when driving one logic gate circuit included in the fluctuation detection circuit 13. Indicates capacity. T _meas indicates the measurement time.

As in equation (4), the energy consumption E _total is proportional to the measurement time T _meas .
On the other hand, the relationship represented by the following equation (5) holds among the oscillation frequency f _rosc , the measurement time T _meas, and the measurement accuracy S.

The measurement accuracy S is proportional to the oscillation frequency f _rosc and the measurement time T _meas as shown in Equation (5). In the case of using the counter with the fluctuation detecting unit 13, for example, variation rate due to power supply voltage V _DD of the count value C _ount of the rising edge of the waveform w2 (differential value) is defined as. λ (V _DD , V _th ) is sensitivity (oscillation frequency fluctuation rate). From the equations (4) and (5), the energy consumption E _total , the measurement accuracy S, and the oscillation frequency fluctuation rate λ have the following relationship (6).

As in Expression (6), under the condition where the measurement accuracy S is constant, the energy consumption E _total decreases as the oscillation frequency variation rate λ increases.
Here, when the equation (5) is modified by paying attention to the oscillation frequency variation rate λ, the oscillation frequency variation rate λ (V _DD , V _th ) at a certain power supply voltage V _DD and threshold voltage V _th is expressed by the following equation: It can be expressed as (7).

From equation (7), if the power supply voltage V _DD is decreased or the threshold voltage V _th is increased, the oscillation frequency variation rate λ (V _DD , V _th ) can be increased.
In the voltage variation detection circuit 10 according to the first embodiment, the operating voltage generation unit 12 reduces the power supply voltage V _DD (potential difference between the wiring vdd and the wiring vss) to be the operating voltage of the oscillation circuit 11. Therefore, the oscillation frequency variation rate λ of the oscillation circuit 11 can be increased.

Therefore, as is clear from the equation (6), even when the measurement accuracy S is constant, the energy consumption E _total of the voltage fluctuation detection circuit 10 can be reduced, and the power consumption can be reduced.
In the voltage fluctuation detection circuit 10 of the first embodiment, the oscillation frequency fluctuation rate λ can also be expressed as the following formula (8).

In Expression (8), V _DDV is an operating voltage generated by reducing the power supply voltage V _DD in the operating voltage generator 12. The amount of change in power supply voltage V _DD / the amount of change in operating voltage V _DDV is the aforementioned PSRR. As is clear from the equation (8), by reducing PSRR, the oscillation frequency fluctuation rate λ can be increased, the energy consumption E _total of the voltage fluctuation detection circuit 10 can be reduced, and the power consumption can be reduced.

Further, as shown in the equation (4), the power consumption of the oscillation circuit 11 using the ring oscillator is proportional to the number of stages of the inverter circuit (the measurement time T _meas in the above equation (6) depends on the number of stages of the inverter circuit). In order to reduce power consumption, the number of inverter circuits can be reduced. As shown in Equation (3), the number of stages of the inverter circuit is inversely proportional to the delay time of the inverter circuit. Therefore, in order to suppress power consumption, the delay time of the inverter is increased to reduce the number of stages of the inverter circuit. . Since the delay time of the inverter circuit can be increased by lowering the operating voltage of the oscillation circuit or increasing the threshold voltage V _th , power consumption can be suppressed by reducing the operating voltage with the above method. .

(Second Embodiment)
FIG. 2 is a diagram illustrating an example of a semiconductor integrated circuit and a voltage variation detection circuit according to the second embodiment.

  The semiconductor integrated circuit 1a includes a wiring (power supply wiring) vdd, a wiring (grounding line) vss, a voltage fluctuation detection circuit 10a, a control signal generator 20, and a reference clock generator 21. Also in the example of the semiconductor integrated circuit 1a of the second embodiment, the wiring vdd is a power supply potential, and the wiring vss is a reference potential (ground potential).

The voltage fluctuation detection circuit 10a includes an oscillation circuit 11a, an operating voltage generation unit 12a, a fluctuation detection unit 13a, and a level shifter 14a.
The oscillation circuit 11a functions as a ring oscillator having an oscillation control function, and includes a NAND circuit 111 and a plurality of inverter circuits 112. A control signal from the control signal generator 20 is input to one input terminal of the NAND circuit 111, and oscillation in the ring oscillator is controlled according to the value of the control signal. In FIG. 2, the NAND circuit 111 and a part of the inverter circuits 112 are connected to the operation voltage generation unit 12 a in order to avoid complication of the illustration. However, the operation voltage generation unit 12 a is connected to the NAND circuit 111 and each inverter circuit 112. The power supply voltage stepped down at is supplied. Further, although not shown, the wiring vss is connected to the NAND circuit 111 and each inverter circuit 112.

  When the control signal is “1”, the oscillation circuit 11a performs an oscillation operation by receiving the operation voltage generated by the operation voltage generation unit 12a. When the control signal is “0”, the output of the NAND circuit 111 is fixed to “1”, so that the oscillation operation is not performed. The oscillation frequency of the oscillation circuit 11a is adjusted by the number of stages of the inverter circuit 112, for example.

The oscillation circuit 11a is not particularly limited to a ring oscillator, and may be any circuit that receives an operating voltage and performs an oscillation operation.
The operating voltage generation unit 12a is also connected to the wiring vdd in the example of the voltage variation detection circuit 10 of the second embodiment, and generates the operating voltage of the oscillation circuit 11a and the level shifter 14a by reducing the power supply voltage. In the example of the voltage variation detection circuit 10a of the second embodiment, the operating voltage generation unit 12a functions as a step-down circuit that lowers the power supply voltage. As shown in FIG. 2, the operating voltage generator 12a has a diode-connected p-channel MOSFET (hereinafter abbreviated as pMOS) 121. The source of the pMOS 121 is connected to the wiring vdd, and the drain is connected to the oscillation circuit 11a and the level shifter 14a. Furthermore, the gate of the pMOS 121 is connected to its own drain, and the back gate is connected to its source.

  The operating voltage generator 12a may be a diode-connected n-channel MOSFET (hereinafter abbreviated as nMOS). In that case, the drain of the nMOS is connected to the wiring vdd and its gate, and the source is connected to the oscillation circuit 11a.

The fluctuation detection unit 13a includes a counter 131 and a storage unit (hereinafter, described as a register as an example of a storage unit) 132.
The counter 131 counts the number of oscillations of the oscillation circuit 11a. As shown in FIG. 2, the counter 131 receives the output signal of the oscillation circuit 11a sent via the level shifter 14a at the terminal cclk. The counter 131 outputs the number of oscillations as a count value, for example, by counting the number of rising edges of the output signal within a certain period. The counter 131 receives a reference clock (for example, a system clock) generated by the reference clock generator 21 at a terminal reset. For example, when the rising of the reference clock is detected, the counter 131 resets the count value to “0”. That is, the count value is reset every fixed period (period of the reference clock).

The register 132 captures the count value of the counter 131 in synchronization with the reference clock. The register 132 outputs the fetched count value.
The fluctuation detector 13a is not particularly limited to that shown in FIG. 2, and may be any one that can detect fluctuations in the oscillation frequency.

  The level shifter 14a adjusts the amplitude of the output signal of the oscillation circuit 11a according to the amplitude of the operating voltage of the fluctuation detecting unit 13a. Also in the example of the voltage fluctuation detection circuit 10a of the second embodiment, the fluctuation detection unit 13a operates at the potential level of the wiring vdd. Therefore, the level shifter 14a is connected to the wiring vdd, and changes the signal level of the output signal of the oscillation circuit 11a to the potential level of the wiring vdd. Thereby, the fluctuation | variation detection part 13a can detect an oscillation frequency accurately. For example, the fluctuation detector 13a operates even at the signal level of the output signal of the oscillation circuit 11a. If the output signal of the oscillation circuit 11a can be detected, the level shifter 14a may be omitted.

FIG. 3 is a timing chart illustrating a first operation example of the voltage variation detection circuit according to the second embodiment.
FIG. 3 shows the potential difference between the wiring vdd and the wiring vss, the potential difference between the wiring vddv and the wiring vss connecting the operating voltage generator 12a and the oscillation circuit 11a, and the state of the control signal rsen generated by the control signal generator 20. Has been. Moreover, (the potential of the output signal of the level shifter 14a) terminal cclk the potential of the counter 131, the count value C _ount of the counter 131, the terminal rclk counter 131 potential (potential of the reference clock), the value of the register 132 is shown . Incidentally, an example of the count value C _ount, because too fine, not shown in FIG.

When the control signal rsen is at L (Low) level, the oscillation circuit 11a does not oscillate, and the potential of the terminal cclk is fixed at H level. Therefore, the count value C _ount is "0", the potential of the terminal rclk rises (the timing t1), the register 132 takes in the "0".

When the control signal rsen rises to H level (timing t2), the oscillation circuit 11a starts oscillation. Thereby, the counter 131 counts rising of the potential of the terminal cclk. Then, the register 132, in synchronization with the rising timing of the potential of the terminal rclk (timing t3), captures the count value C _ount (in the example of FIG. 3 "80"). Thereafter, the same operation is performed. An enlarged view of the timing t4 portion is shown below.

FIG. 4 is an enlarged view of a part of FIG.
Count value C _ount is reset at the rising timing t4 of the potential of the terminal rclk becomes "0", the count value C _ount immediately before reset "105" is taken into the register 132.

As in Figure 3, for example, noiseless, when the potential difference between the wiring vdd wiring vss (power supply voltage) hardly vary, the count value C _ount stored in the register 132 is substantially equal.

FIG. 5 is a timing chart illustrating a second operation example of the voltage variation detection circuit according to the second embodiment. The types of signals shown are the same as those shown in FIG.
In the example of FIG. 5, between timings t10 and t12, the potential difference between the wiring vdd and the wiring vss is reduced due to, for example, power supply noise (voltage drop occurs).

At this time, the potential difference between the wiring vddv and the wiring vss is also reduced, and in response to this change, the oscillation frequency of the oscillation circuit 11a is reduced. Thus the count value C _ount between the rise of potential of the terminal rclk to the next rising decreases. In the example of FIG. 5, at the timing t11, the count value C _ount is taken into the register 132 when the potential of the terminal rclk rises is reduced to "85" to "105". When the potential difference between the wiring vdd and the wiring vss is restored at the timing t12, the potential difference between the wiring vddv and the wiring vss and the oscillation frequency of the oscillation circuit 11a are also restored. Thus the count value C _ount be "65", "90", "105" and go back to the timing t10 previous value.

Count value C _ount taken into the register 132, in synchronization with the reference clock, as a plurality of bits of information, for example, is output from the external terminal (not shown) of the semiconductor integrated circuit 1a. For example, the user, by detecting the change in the output count value C _ount, it is possible to detect the fluctuation of the power supply voltage.

Hereinafter, the effect of the voltage fluctuation detection circuit 10a of the second embodiment will be described.
FIG. 6 is a diagram illustrating a simulation result example of the dependency of the operating voltage V _DDV of the oscillation circuit on the power supply voltage V _DD due to the difference in PSRR of the operating voltage generator. The vertical axis represents the operating voltage V _DDV [V] of the oscillation circuit, and the horizontal axis represents the power supply voltage V _DD [V].

As a simulation condition, the steady value of the oscillation frequency when the power supply voltage V _DD is 1.2 V is about 256 MHz. The simulation result V1 indicates the dependency of the operating voltage V _{DDV on} the power supply voltage V _DD when the PSRR of the operating voltage generator 12a is assumed to be 100. The simulation result V2 shows the dependency of the operating voltage V _{DDV on} the power supply voltage V _DD when the operating voltage generator 12a (PSRR≈1.3) to which the pMOS 121 as shown in FIG. 2 is applied.

As shown in the simulation result V1, when PSRR is large, even if the power supply voltage V _DD changes, the operating voltage V _DDV hardly changes. On the other hand, in the simulation result V2 when the operating voltage generator 12a having a small PSRR is applied, the fluctuation of the power supply voltage V _DD is transmitted to the operating voltage V _DDV . Further, as shown in the simulation result V2, the operating voltage generator 12a having a small PSRR can step down from the power supply voltage V _DD = 1.2 [V] to the operating voltage V _DDV = 0.7V. Yes.

FIG. 7A is a diagram showing a simulation result of the dependency of the oscillation frequency f of the oscillation circuit on the power supply voltage V _DD depending on the presence or absence of the operating voltage generation unit. FIG. 7B is a diagram illustrating a simulation result of the dependency of the oscillation frequency variation rate λ on the power supply voltage V _DD depending on the presence or absence of the operating voltage generation unit. In FIG. 7A, the horizontal axis indicates the power supply voltage V _DD [V], and the vertical axis indicates the oscillation frequency f [MHz]. In FIG. 7B, the horizontal axis indicates the power supply voltage V _DD [V], and the vertical axis indicates the oscillation frequency variation rate λ.

As a simulation condition, the steady value of the oscillation frequency when the power supply voltage V _DD is 1.2 V is about 256 MHz.
In FIG. 7 (A), the simulation results and V3, in the case of applying the power supply voltage V _DD without providing the operating voltage generation unit 12a to the oscillating circuit 11a, the power supply voltage V _DD dependence of the oscillation frequency f of the oscillation circuit 11a Show. The simulation result V4 shows the dependency of the oscillation frequency f of the oscillation circuit 11a on the power supply voltage V _DD when the operation voltage generator 12a is provided and the operation voltage V _DDV obtained by stepping down the power supply voltage V _DD is applied to the oscillation circuit 11a. ing.

As shown in the simulation results V3 and V4, the oscillation frequency f greatly varies with the change of the power supply voltage V _DD when the operating voltage generation unit 12a is provided.
In FIG. 7B, the simulation result V5 is dependent on the power supply voltage V _DD of the oscillation frequency fluctuation rate λ of the oscillation circuit 11a when the power supply voltage V _DD is applied to the oscillation circuit 11a without providing the operating voltage generation unit 12a. Showing sex. The simulation result V6 is dependent on the power supply voltage V _DD of the oscillation frequency variation rate λ of the oscillation circuit 11a when the operation voltage generator 12a is provided and the operation voltage V _DDV obtained by stepping down the power supply voltage V _DD is applied to the oscillation circuit 11a. Is shown.

As shown in the simulation results V5 and V6, the oscillation frequency variation rate λ increases when the operating voltage generation unit 12a is provided. That is, the sensitivity for detecting voltage fluctuation can be improved. When the power supply voltage V _DD is 1.2 V, the oscillation frequency variation rate λ without the operating voltage generator 12a is about 1.3, whereas the oscillation with the operating voltage generator 12a is performed. The frequency variation rate λ is about 4.3, which is about 3.3 times.

Further, from the relationship of Expression (6), when the measurement accuracy S is constant, the operating voltage generator 12a is provided and the energy consumption E _total is about 3.3 compared to the case where the operating voltage generator 12a is not provided. It can be reduced by a factor.

(Third embodiment)
FIG. 8 is a diagram illustrating an example of a semiconductor integrated circuit and a voltage fluctuation detection circuit according to the third embodiment.

In the semiconductor integrated circuit 1b according to the third embodiment, the operating voltage generation unit 12a of the voltage fluctuation detection circuit 10b is connected to a wiring vcc having an arbitrary potential instead of the wiring vdd serving as a power supply potential. As a result, the operating voltage generator 12a lowers the potential of the wiring vcc and applies a voltage obtained by reducing the potential difference between the wiring vcc and the wiring vss to the oscillation circuit 11a via the wiring vccv as the operating voltage V _CCV . Others are the same as those of the voltage fluctuation detection circuit 10a of the second embodiment. Such a voltage fluctuation detection circuit 10b can detect a potential fluctuation of the wiring vcc due to noise or the like.

FIG. 9 is a timing chart illustrating an operation example of the voltage variation detection circuit according to the third embodiment.
FIG. 9 shows the potential difference between the wiring vcc and the wiring vss, the potential difference between the wiring vccv and the wiring vss connecting the operating voltage generating unit 12a and the oscillation circuit 11a, and the state of the control signal rsen generated by the control signal generating unit 20. Has been. Moreover, (the potential of the output signal of the level shifter 14a) terminal cclk the potential of the counter 131, the count value C _ount of the counter 131, the terminal rclk counter 131 potential (potential of the reference clock), the value of the register 132 is shown . Incidentally, an example of the count value C _ount, because too fine, not shown in FIG. 9.

  In the example of FIG. 9, the potential difference between the wiring vcc and the wiring vss is reduced between timings t20 and t22 due to, for example, the influence of power supply noise (voltage drop occurs).

At this time, the potential difference between the wiring vccv and the wiring vss is also reduced, and in response to this change, the oscillation frequency of the oscillation circuit 11a is shortened. Thus the count value C _ount between the rise of potential of the terminal rclk to the next rising decreases. In the example of FIG. 9, at the timing t21, the count value C _ount is taken into the register 132 when the potential of the terminal rclk rises is reduced to "85" to "105". When the potential difference between the wiring vcc and the wiring vss is restored at the timing t22, the potential difference between the wiring vccv and the wiring vss and the oscillation frequency of the oscillation circuit 11a are also restored. Thus the count value C _ount be "65", "90", "105" and the timing t20 go back to its previous value.

Count value C _ount taken into the register 132, in synchronization with the reference clock, as a plurality of bits of information, for example, is output from the external terminal (not shown) of the semiconductor integrated circuit 1b. For example, the user, by detecting the change in the output count value C _ount, it is possible to detect the variation of the potential difference between the wiring vcc line vss.

Hereinafter, the effect of the voltage fluctuation detection circuit 10b of the third embodiment will be described.
FIG. 10 is a diagram illustrating a simulation result example of the voltage V _CC dependency of the operating voltage V _CCV of the oscillation circuit due to the difference in PSRR of the operating voltage generation unit. The vertical axis represents the operating voltage V _CCV [V] of the oscillation circuit, and the horizontal axis represents the voltage V _CC [V] between the wiring vcc and the wiring vss.

As a simulation condition, the steady value of the oscillation frequency when the voltage V _CC and the power supply voltage V _DD are 1.2 V is about 256 MHz. The simulation result V10 indicates the dependence of the operating voltage V _CCV of the oscillation circuit 11a on the voltage V _CC when it is assumed that the PSRR of the operating voltage generator 12a is 100. The simulation result V11 shows the dependence of the operating voltage V _CCV of the oscillation circuit 11a on the voltage V _CC when the operating voltage generator 12a (PSRR≈1.3) to which the pMOS 121 as shown in FIG. 8 is applied. ing.

As shown in the simulation result V10, when PSRR is large, the operating voltage V _CCV does not substantially change even if the voltage V _CC changes. On the other hand, in the simulation result V11 when the operating voltage generation unit 12a having a small PSRR is applied, the fluctuation of the voltage V _CC is transmitted to the operating voltage V _CCV . Further, as shown in the simulation result V11, even the operating voltage generator 12a having a small PSRR can step down from the voltage V _CC = 1.2 [V] to the operating voltage V _CCV = 0.7V.

FIG. 11A is a diagram illustrating a simulation result of the voltage V _CC dependency of the oscillation frequency f of the oscillation circuit with and without the operating voltage generation unit. FIG. 11B is a diagram illustrating a simulation result of the voltage V _CC dependency of the oscillation frequency variation rate λ with and without the operating voltage generation unit. In FIG. 11A, the horizontal axis indicates the voltage V _CC [V], and the vertical axis indicates the oscillation frequency f [MHz]. In FIG. 11B, the horizontal axis indicates the voltage V _CC [V], and the vertical axis indicates the oscillation frequency variation rate λ.

As a simulation condition, the steady value of the oscillation frequency when the voltage V _CC and the power supply voltage V _DD are 1.2 V is about 256 MHz.
In FIG. 11 (A), the simulation results V12 is the case of applying a voltage V _CC without providing the operating voltage generation unit 12a to the oscillating circuit 11a, shows the voltage V _CC dependence of the oscillation frequency f of the oscillation circuit 11a Yes. The simulation result V13 indicates the dependency of the oscillation frequency f of the oscillation circuit 11a on the voltage V _CC when the operation voltage generator 12a is provided and the operation voltage V _CCV obtained by stepping down the voltage V _CC is applied to the oscillation circuit 11a. .

As shown in the simulation results V12 and V13, the oscillation frequency f greatly fluctuates with respect to the change of the voltage V _CC when the operating voltage generator 12a is provided.
In FIG. 11 (B), simulation results V14 is the case of applying a voltage V _CC without providing the operating voltage generation unit 12a to the oscillating circuit 11a, a voltage V _CC dependence of the oscillation frequency variation rate of the oscillation circuit 11a lambda Show. Simulation results V15 is the operating voltage generation unit 12a is provided, in the case of applying the operating voltage V _CCV obtained by stepping down the voltage V _CC to the oscillation circuit 11a, shows the voltage V _CC dependence of the oscillation frequency variation rate of the oscillation circuit 11a lambda ing.

As shown in the simulation results V14 and V15, the oscillation frequency variation rate λ increases when the operating voltage generation unit 12a is provided. That is, the sensitivity for detecting voltage fluctuation can be improved. When the voltage V _CC is 1.2 V, the oscillation frequency variation rate λ when the operating voltage generator 12a is not provided is about 1.3, whereas the oscillation frequency when the operating voltage generator 12a is provided. The variation rate λ is about 4.3, which is about 3.3 times.

Further, from the relationship of the expression (6) in which the power supply voltage V _DD is replaced with the voltage V _CC , in the condition where the measurement accuracy S is constant, the operation voltage generation unit 12a is provided and the operation voltage generation unit 12a is not provided. Also, the energy consumption E _total can be reduced to about 1 / 3.3.

As described above, in the voltage fluctuation detection circuit 10b, as in the case of detecting the fluctuation of the power supply voltage, the sensitivity for detecting the voltage fluctuation can be improved, the consumed energy E _total can be reduced, and the power consumption can be reduced.

(Fourth embodiment)
FIG. 12 is a diagram illustrating an example of a semiconductor integrated circuit and a voltage fluctuation detection circuit according to the fourth embodiment. The same elements as those of the voltage fluctuation detection circuit 10b according to the third embodiment are denoted by the same reference numerals.

In the semiconductor integrated circuit 1c of the fourth embodiment, the operating voltage generation unit 12b of the voltage fluctuation detection circuit 10c has two diode-connected pMOSs 121-1 and 121-2, and the wiring vcc is larger. The potential can be lowered. As a result, the operating voltage V _CCV of the oscillation circuit 11a can be further reduced, so that the oscillation frequency variation rate λ of the oscillation circuit 11a can be further increased. That is, the sensitivity for detecting voltage fluctuations can be further improved.

Two level shifters 14a-1 and 14a-2 are provided. The level shifter 14a-1 is connected to the oscillation circuit 11a, the drains of the pMOSs 121-1 and 121-2, and the wiring vss. The level shifter 14a-1 raises the potential level (amplitude) of the output signal of the oscillation circuit 11a from the potential level of the operating voltage V _{CCV to} the potential level of the drain of the pMOS 121-1. The level shifter 14a-2 is connected to the output terminal of the level shifter 14a-1, the drain of the pMOS 121-1, and the wirings vdd and vss. The level shifter 14a-2 raises the potential level of the output signal from the level shifter 14a-1 from the potential level of the drain of the pMOS 121-1 to the potential level (power supply potential) of the wiring vdd.

  When one level shifter 14a is used, there is a concern that the level shifter 14a may not operate if the potential difference between the power supply potential and the wiring vccv is too large. can do.

Since the operation of the voltage fluctuation detection circuit 10c is the same as that of the voltage fluctuation detection circuit 10b of the third embodiment (see FIG. 9 and the like), the description thereof is omitted.
Hereinafter, the effect of the voltage fluctuation detection circuit 10c of the fourth embodiment will be described.

FIG. 13 is a diagram illustrating a simulation result example of the voltage V _CC dependency of the operating voltage V _CCV of the oscillation circuit of the voltage variation detection circuit according to the fourth embodiment. The vertical axis represents the operating voltage V _CCV [V] of the oscillation circuit, and the horizontal axis represents the voltage V _CC [V] between the wiring vcc and the wiring vss.

As a simulation condition, the steady value of the oscillation frequency when the voltage V _CC and the power supply voltage V _DD are 1.2 V is about 70 MHz. The simulation result V21 is the voltage of the operating voltage V _CCV of the oscillation circuit 11a when the operating voltage generator 12b (PSRR≈2.5) to which the pMOSs 121-1 and 121-2 as shown in FIG. 12 are applied. It shows V _CC dependency.

As shown in the simulation result V21, the fluctuation of the voltage V _CC is transmitted to the operating voltage V _CCV . Further, when the voltage V _CC = 1.2 [V], the operating voltage V _CCV is about 0.42 V, which can be stepped down more than the voltage fluctuation detection circuits 10a and 10b of the second and third embodiments. Yes.

FIG. 14A is a diagram illustrating a simulation result of the voltage V _CC dependency of the oscillation frequency f of the oscillation circuit with and without the operating voltage generation unit. FIG. 14B is a diagram illustrating a simulation result of the voltage V _CC dependency of the oscillation frequency variation rate λ with and without the operating voltage generation unit. In FIG. 14A, the horizontal axis indicates the voltage V _CC [V], and the vertical axis indicates the oscillation frequency f [MHz]. In FIG. 14B, the horizontal axis indicates the voltage V _CC [V], and the vertical axis indicates the oscillation frequency variation rate λ.

As a simulation condition, the steady value of the oscillation frequency when the voltage V _CC and the power supply voltage V _DD are 1.2 V is about 70 MHz.
In FIG. 14 (A), the simulation results V22 is the case where the voltage V _CC without providing the operating voltage generation unit 12b is applied to the oscillation circuit 11a, shows the voltage V _CC dependence of the oscillation frequency f of the oscillation circuit 11a Yes. The simulation result V23 is dependent on the voltage V _CC of the oscillation frequency f of the oscillation circuit 11a when the operation voltage generator 12b is provided and the operation voltage V _CCV generated by stepping down the voltage V _CC is applied to the oscillation circuit 11a. Is shown.

As shown in the simulation results V22 and V23, the fact that the oscillation frequency f greatly fluctuates with respect to the change of the voltage V _CC when the operating voltage generator 12b is provided is the second and third described above. This is the same as the voltage fluctuation detection circuits 10a and 10b of the embodiment.

In FIG. 14 (B), the simulation results V24 is the case of applying a voltage V _CC without providing the operating voltage generating portion 12b to the oscillation circuit 11a, a voltage V _CC dependence of the oscillation frequency variation rate of the oscillation circuit 11a lambda Show. Simulation results V25 is the operating voltage generation unit 12b is provided, in the case of applying the operating voltage V _CCV generated by stepping down the voltage V _CC to the oscillation circuit 11a, the voltage V _CC of the oscillation frequency variation rate of the oscillation circuit 11a lambda Shows dependency.

As shown in the simulation results V24 and V25, the fact that the oscillation frequency variation rate λ increases when the operating voltage generation unit 12b is provided is the voltage variation of the second and third embodiments described above. It is the same as the detection circuits 10a and 10b. Furthermore, in the voltage variation detection circuit 10c of the fourth embodiment, when the voltage V _CC is 1.2V, the oscillation frequency variation rate λ when the operation voltage generation unit 12b is included is about 7.8. This is about 5.6 times the oscillation frequency fluctuation rate λ (about 1.4) when the operating voltage generation unit 12b is not provided. This value is larger than the voltage fluctuation detection circuits 10a and 10b of the second and third embodiments described above. That is, the sensitivity for detecting voltage fluctuations can be further improved.

From the relationship of the expression (6) in which the power supply voltage V _DD is replaced with the voltage V _CC , the provision of the operating voltage generator 12b under the condition where the measurement accuracy S is constant is greater than the case where the operating voltage generator 12b is not provided. The consumed energy E _total can be reduced to about 1 / 5.5.

  Thus, in the voltage fluctuation detection circuit 10c, the potential of the wiring vcc is further lowered by the pMOSs 121-1 and 121-2, and the operating voltage of the oscillation circuit 11a is reduced. As a result, it is possible to improve sensitivity for detecting voltage fluctuations and to reduce power consumption more than the voltage fluctuation detection circuits 10a and 10b of the second and third embodiments.

  In the example of the voltage fluctuation detection circuit 10c described above, the operating voltage of the oscillation circuit 11a becomes smaller, so the upper limit value of the oscillation frequency decreases. Therefore, it is preferable to apply when the oscillation frequency may be small (for example, when the time during which voltage fluctuation occurs is long).

  Further, in the voltage fluctuation detection circuit 10c described above, the case where the two-stage pMOSs 121-1 and 12-2 are provided has been described. It is good also as three steps or more. Also, a plurality of diode-connected nMOSs may be used instead of the pMOS.

(Fifth embodiment)
FIG. 15 is a diagram illustrating an example of a semiconductor integrated circuit and a voltage variation detection circuit according to the fifth embodiment. The same elements as those of the voltage fluctuation detection circuit 10b according to the third embodiment are denoted by the same reference numerals.

In the semiconductor integrated circuit 1d according to the fifth embodiment, the voltage fluctuation detection circuit 10d includes a wiring vccv (wiring for applying an operating voltage to the oscillation circuit 11a) between the operating voltage generator 12a and the oscillation circuit 11a, and a wiring. A capacitive element C1 is connected to the vcc. The capacitive element C1 functions as a coupling capacitor. By providing the capacitive element C1, it is possible to reduce the transient PSRR compared to the case where the capacitive element C1 is not provided. From equation (8), if PSRR can be reduced, the oscillation frequency fluctuation rate λ can be increased, and therefore the sensitivity for detecting voltage fluctuation can be improved. Therefore, it is possible to detect voltage fluctuation with high accuracy, and it is possible to reduce the energy consumption E _total when the measurement accuracy S is constant from the equation (6).

Since the operation of the voltage fluctuation detection circuit 10d is the same as the operation of the voltage fluctuation detection circuit 10b of the third embodiment, the description thereof is omitted.
Hereinafter, the reason why the PSRR can be made smaller by providing the capacitive element C1 than when the capacitive element C1 is not provided will be described.

In order to see the transient response of the operating voltage with respect to the voltage drop, the operating voltage generator 12a and the oscillation circuit 11a are represented by a resistance component and a capacitance component as follows.
FIG. 16 is a circuit in which the operating voltage generation unit and the oscillation circuit are represented by resistance components and capacitance components.

Between the wiring vcc and the wiring vss, a parallel circuit including a resistor r1 and a capacitor c1 and a parallel circuit including a resistor r2 and a capacitor c2 are connected.
The resistor r1 indicates the resistance component of the operating voltage generator 12a, and the capacitor c1 corresponds to the capacitor element C1 in FIG. The resistor r2 is a resistance component of the oscillation circuit 11a, and the capacitor c2 is a capacitance component of the oscillation circuit 11a.

In the following description, the resistance value of the resistor r1 is R _PSW , the capacitance value of the capacitor c1 (capacitance element C1) is C _VCCV , the resistance value of the resistor r2 is R _eff , and the capacitance value of the capacitor c2 is C _eff .
FIG. 17 is a diagram illustrating an example of a transient response between the voltage V _CC and the operating voltage V _CCV of the oscillation circuit. V _CC (t) indicates the time change of the voltage V _CC , and V _CCV (t) indicates the time change of the operating voltage V _CCV . FIG. 17 shows the transient response of the operating voltage V _CCV when a voltage drop of ΔV _CC occurs at the voltage V _CC at t = + 0 (at the time of the black circle in the figure).

  This transient response is expressed by the following equation (9).

In Expression (9), V _CC (−0) is the value of the voltage V _CC at t = −0 (at the time of the white circle in the figure). u (t) is a unit step function.
Solving V _CCV (t) in equation (9) using Laplace transform yields:

From the results of equation (10), t = + 0 value of the operating voltage V _CCV in a V _CCV (+0), the value (convergence value) of the operating voltage V _CCV at _{t = ∞, V CCV (∞} ) is the following It can be expressed by equations (11) and (12).

From the equation (11), it can be seen that the value of the operating voltage V _CCV at t = + 0 becomes smaller as C _VCCV which is the capacitance value of the capacitive element C1 is larger.
Here, since ΔV _CCV (t) is expressed by the following equation (13), ΔV _CCV (+0) and ΔV _CCV (∞) can be expressed by equations (14) and (15).

_Assuming that the time until the operating voltage V _CCV converges is Td (which becomes longer as C _VCCV increases), PSRR can be expressed by the following equation (16).

From Expressions (14) to (16), PSRR when C _VCCV = 0 and PSRR when C _VCCV > 0 can be expressed by the following Expressions (17) and (18).

From equations (17) and (18), it can be seen that PSRR (C _VCCV > 0) <PSRR (C _VCCV = 0), and the larger C _VCCV , the smaller the PSRR when viewed transiently. Recognize.

Thus, by providing the capacitive element C1, PSRR can be made smaller than when the capacitive element C1 is not provided. If PSRR can be reduced, the oscillation frequency fluctuation rate λ can be increased, so that the sensitivity for detecting voltage fluctuation can be improved, the energy consumption E _total can be reduced, and the power consumption can be suppressed.

(Sixth embodiment)
FIG. 18 is a diagram illustrating an example of a semiconductor integrated circuit and a voltage variation detection circuit according to the sixth embodiment. The same elements as those of the voltage fluctuation detection circuit 10b according to the third embodiment are denoted by the same reference numerals.

  In the semiconductor integrated circuit 1e and the voltage fluctuation detection circuit 10e of the sixth embodiment, a voltage higher than the operating voltage is applied to the n well of the pMOS included in the oscillation circuit 11b. For example, the wiring vdd at the power supply potential and the n well are electrically connected. In FIG. 18, the pMOS is not shown, but is included in the NAND circuit 111 and the inverter circuit 112.

FIG. 19 is a cross-sectional view showing an example of a pMOS included in the oscillation circuit.
The pMOS 150 is formed on the n well 152 formed on the substrate 151, the p-type source / drain regions 153 and 154, the gate oxide film 155 formed so as to straddle the source / drain regions 153 and 154, and the gate oxide film 155. The gate electrode 156 is provided. In the n-well 152, a high-concentration n-type layer 157 for contact is formed, and a via 158 is connected thereto. The via 158 is connected to the wiring vdd. As a result, the n well 152 and the wiring vdd are electrically connected, and the n well 152 is reverse-biased, whereby the threshold voltage V _th of the pMOS 150 is increased.

Since the oscillation frequency fluctuation rate λ can be increased by increasing the threshold voltage V _th as shown in the equation (7), as can be seen from the equation (6), the measurement accuracy S is under a constant condition. The energy consumption E _total can be reduced, and the power consumption can be reduced.

Since the operation of the voltage fluctuation detection circuit 10e is the same as the operation of the voltage fluctuation detection circuit 10b of the third embodiment, the description thereof is omitted.
Hereinafter, the effect of the voltage fluctuation detection circuit 10e of the sixth embodiment will be described.

FIG. 20 is a diagram illustrating a simulation result example of the voltage V _CC dependency of the operating voltage V _CCV of the oscillation circuit of the voltage variation detection circuit according to the sixth embodiment. The vertical axis represents the operating voltage V _CCV [V] of the oscillation circuit, and the horizontal axis represents the voltage V _CC [V] between the wiring vcc and the wiring vss.

As a simulation condition, the steady value of the oscillation frequency when the voltage V _CC and the power supply voltage V _DD are 1.2 V is about 256 MHz. The simulation result V31 shows the voltage V _CC dependency of the operating voltage V _CCV of the oscillation circuit 11b when the operating voltage generator 12a (PSRR≈1.4) as shown in FIG. 18 is applied.

As shown in the simulation result V31, the fluctuation of the voltage V _CC is transmitted to the operating voltage V _CCV . Further, when the voltage V _CC = 1.2 [V], the operating voltage V _CCV is about 0.7 V, and the voltage can be lowered by about 0.5 V.

FIG. 21A is a diagram showing a simulation result of the voltage V _CC dependency of the oscillation frequency f of the oscillation circuit. FIG. 21B is a diagram illustrating a simulation result of the voltage V _CC dependency of the oscillation frequency variation rate λ. In FIG. 21A, the horizontal axis indicates the voltage V _CC [V], and the vertical axis indicates the oscillation frequency f [MHz]. In FIG. 21B, the horizontal axis indicates the voltage V _CC [V], and the vertical axis indicates the oscillation frequency variation rate λ.

As a simulation condition, the steady value of the oscillation frequency when the voltage V _CC and the power supply voltage V _DD are 1.2 V is about 256 MHz.
In FIG. 21 (A), the simulation results V32 is the case where the voltage V _CC without providing the operating voltage generation unit 12a is applied to the oscillation circuit 11b, which shows the voltage V _CC dependence of the oscillation frequency f. As shown in FIG. 8, the simulation result V33 includes the operating voltage generator 12a, and the oscillation frequency of the oscillation circuit 11a when the operating voltage V _CCV generated by stepping down the voltage V _CC is applied to the oscillation circuit 11a. The voltage V _CC dependency of f is shown. Further, the simulation result V34 shows the oscillation of the oscillation circuit 11b when the operating voltage generation unit 12a is provided as shown in FIG. 18 and the wiring vdd is electrically connected to the n well of the pMOS included in the oscillation circuit 11b. The voltage V _CC dependency of the frequency f is shown.

As shown by the simulation results V32 and V34, when the operating voltage generation unit 12a is provided, the oscillation frequency f varies more greatly with respect to the change in the voltage V _CC than without the operation voltage generation unit 12a. Further, as represented by simulation results V33 and V34, when the wiring vdd is electrically connected to the n-well of the pMOS included in the oscillation circuit 11b, the voltage V is higher than that of the voltage fluctuation detection circuit 10b shown in FIG. _The oscillation frequency f varies greatly with respect to the change in _CC .

In FIG. 21 (B), the simulation results V35 is the case of applying a voltage V _CC without providing the operating voltage generation unit 12a to the oscillating circuit 11a, a voltage V _CC dependence of the oscillation frequency variation rate of the oscillation circuit 11a lambda Show. The simulation result V36 includes the operating voltage generator 12a as shown in FIG. 8, and the oscillation frequency of the oscillation circuit 11a when the operating voltage V _CCV generated by stepping down the voltage V _CC is applied to the oscillation circuit 11a. The voltage V _CC dependency of the variation rate λ is shown. Further, the simulation result V37 shows the oscillation frequency of the oscillation circuit 11b when the operating voltage generation unit 12a is provided and the wiring vdd is electrically connected to the n well of the pMOS included in the oscillation circuit 11b as shown in FIG. The voltage V _CC dependency of the variation rate λ is shown.

As shown in the simulation results V35 and V37, in the voltage fluctuation detection circuit 10e, the oscillation frequency fluctuation rate λ is larger than that without the operating voltage generator 12a. That is, the sensitivity for detecting voltage fluctuation can be improved. For example, when the voltage V _CC is 1.2 V, the oscillation frequency fluctuation rate λ without the operating voltage generator 12a is about 1.3, whereas the voltage fluctuation detection circuit 10e has an oscillation frequency fluctuation. The rate λ is about 5.4, which is about 4.2 times. Further, as shown in the simulation results V36 and V37, in the voltage fluctuation detection circuit 10e, the oscillation frequency fluctuation rate λ is larger than that in the voltage fluctuation detection circuit 10b as shown in FIG.

Therefore, the voltage fluctuation detection circuit 10e can further improve the sensitivity for detecting voltage fluctuation than the voltage fluctuation detection circuit 10b, reduce the consumed energy E _total, and reduce the power consumption.

(Seventh embodiment)
FIG. 22 is a diagram illustrating an example of a semiconductor integrated circuit and a voltage variation detection circuit according to the seventh embodiment. Elements similar to those of the voltage fluctuation detection circuit 10b of the third embodiment shown in FIG. 8 are denoted by the same reference numerals.

  In the semiconductor integrated circuit 1f and the voltage fluctuation detection circuit 10f of the seventh embodiment, the operating voltage generation unit 12c is connected to the wiring vss that is the reference potential (ground potential). The operating voltage generation unit 12c raises the potential of the wiring vss, thereby lowering the voltage between the wiring vcc and the wiring vss to be detected to be the operating voltage of the oscillation circuit 11c and the level shifter 14a. That is, the operating voltage generator 12c functions as a booster circuit that raises the ground potential. As illustrated in FIG. 22, the operating voltage generation unit 12 c includes a diode-connected nMOS 122. The nMOS 122 has a source connected to the wiring vss and a drain connected to the oscillation circuit 11c. Further, the gate of the nMOS 122 is connected to its own drain.

  The operating voltage generation unit 12c may be a diode-connected pMOS. In that case, the drain of the pMOS is connected to the wiring vss and its gate, and the source is connected to the oscillation circuit 11c and the level shifter 14a.

  The oscillation circuit 11c includes a NAND circuit 111 and a plurality of inverter circuits 112, similarly to the oscillation circuit 11a of the voltage fluctuation detection circuit 10b of the third embodiment. However, unlike the oscillation circuit 11a, the oscillation circuit 11c is supplied to the NAND circuit 111 and each inverter circuit 112 through the wiring vssv by the ground potential raised by the operation voltage generation unit 12c. In FIG. 22, the NAND circuit 111 and a part of the inverter circuits 112 are illustrated as being connected to the operating voltage generation unit 12 c in order to avoid complication of the illustration.

  A wiring vcc is connected to the NAND circuit 111 and each inverter circuit 112. In FIG. 22, the NAND circuit 111 and some of the inverter circuits 112 are illustrated as being connected to the wiring vcc in order to avoid complication of the illustration.

FIG. 23 is a timing chart illustrating an operation example of the voltage variation detection circuit according to the seventh embodiment.
FIG. 23 shows the potential difference between the wiring vcc and the wiring vss, the potential difference between the wiring vssv and the wiring vcc connecting the operating voltage generator 12c and the oscillation circuit 11c, and the state of the control signal rsen generated by the control signal generator 20. Has been. Moreover, (the potential of the output signal of the level shifter 14a) terminal cclk the potential of the counter 131, the count value C _ount of the counter 131, the terminal rclk counter 131 potential (potential of the reference clock), the value of the register 132 is shown . Incidentally, an example of the count value C _ount, because too fine, are not shown.

In the example of FIG. 23, the potential difference between the wiring vcc and the wiring vss is small between timings t30 and t32 due to the influence of power supply noise, for example.
At this time, the potential difference between the wiring vssv and the wiring vcc is also reduced, and in response to this change, the oscillation frequency of the oscillation circuit 11c is shortened. Thus the count value C _ount between the rise of potential of the terminal rclk to the next rising decreases. In the example of FIG. 23, at timing t31, the count value C _ount is taken into the register 132 when the potential of the terminal rclk rises is reduced to "85" to "105". When the potential difference between the wiring vcc and the wiring vss is restored at the timing t32, the potential difference between the wiring vssv and the wiring vss and the oscillation frequency of the oscillation circuit 11c are also restored. Thus the count value C _ount be "65", "90", "105" and the timing t30 go back to its previous value.

Thus, by detecting the change in the count value C _ount taken into the register 132, it is possible to detect the variation of the potential difference between the wiring vcc line vss.
The voltage fluctuation detection circuit 10f has the same effect as the voltage fluctuation detection circuit 10b of the third embodiment shown in FIG. That is, the operating voltage generator 12c raises the ground potential and reduces the potential difference between the wiring vcc and the wiring vss to generate the operating voltage of the oscillation circuit 11c. The oscillation frequency fluctuation rate λ of 11c can be increased. Thereby, the sensitivity for detecting the voltage fluctuation can be improved, and the above-described energy consumption E _total can be reduced, and the power consumption can be reduced.

(Eighth embodiment)
FIG. 24 is a diagram illustrating an example of a semiconductor integrated circuit and a voltage fluctuation detection circuit according to the eighth embodiment. Elements similar to those of the voltage fluctuation detection circuit 10f of the seventh embodiment shown in FIG. 22 are denoted by the same reference numerals.

In the semiconductor integrated circuit 1g according to the eighth embodiment, the voltage variation detection circuit 10g includes a capacitive element C10 connected between the wiring vssv between the operating voltage generation unit 12c and the oscillation circuit 11c and the wiring vss. Yes. The capacitive element C10 functions as a coupling capacitor. Similar to the voltage variation detection circuit 10d of the fifth embodiment, by providing the capacitive element C10, PSRR can be reduced as compared with the case where the capacitive element C1 is not provided. From Equation (8), if PSRR can be reduced, the oscillation frequency variation rate λ can be increased, so that the sensitivity for detecting voltage variation can be improved, and the energy consumption E _total can be calculated as shown in Equation (6). Can be reduced.

Since the operation of the voltage fluctuation detection circuit 10g is the same as that of the voltage fluctuation detection circuit 10f of the seventh embodiment (see FIG. 23 and the like), the description thereof is omitted.
(Ninth embodiment)
FIG. 25 is a diagram illustrating an example of a semiconductor integrated circuit and a voltage variation detection circuit according to the ninth embodiment. Elements similar to those of the voltage fluctuation detection circuit 10f of the seventh embodiment shown in FIG. 22 are denoted by the same reference numerals.

  In the semiconductor integrated circuit 1h and the voltage fluctuation detection circuit 10h of the ninth embodiment, a voltage equal to or lower than the operating voltage is applied to the p-well of the nMOS included in the oscillation circuit 11d. For example, the wiring vss that is at the ground potential and the p-well are electrically connected. Although nMOS is not shown in FIG. 25, it is included in the NAND circuit 111 and the inverter circuit 112.

FIG. 26 is a cross-sectional view showing an example of an nMOS included in the oscillation circuit.
The nMOS 160 is formed on the p well 162 formed on the substrate 161, the n-type source / drain regions 163 and 164, the gate oxide film 165 formed so as to straddle the source / drain regions 163 and 164, and the gate oxide film 165. The gate electrode 166 is provided. In the p-well 162, a high-concentration p-type layer 167 for contact is formed, and a via 168 is connected thereto. The via 168 is connected to the wiring vss. As a result, the p well 162 and the wiring vss are electrically connected, and the p well 162 is reverse-biased, whereby the threshold voltage V _th of the nMOS 160 is raised.

As shown in the equation (7), by increasing the threshold voltage V _th , the oscillation frequency variation rate λ can be increased, so that the sensitivity for detecting the voltage variation can be improved. Further, as shown in Expression (6), the energy consumption E _total can be reduced, and the power consumption can be reduced.

Since the operation of the voltage fluctuation detection circuit 10h is the same as the operation of the voltage fluctuation detection circuit 10f of the seventh embodiment, the description thereof is omitted.
(Tenth embodiment)
FIG. 27 is a diagram illustrating an example of a semiconductor integrated circuit and a voltage variation detection circuit according to the tenth embodiment. The same elements as those of the voltage fluctuation detection circuit 10b according to the third embodiment are denoted by the same reference numerals.

In the semiconductor integrated circuit 1 i and the voltage fluctuation detection circuit 10 i according to the tenth embodiment, the fluctuation detection unit 13 includes a frequency comparison unit 133.
The frequency comparison unit 133 compares the count value output from the register 132 (indicating the magnitude of the oscillation frequency of the oscillation circuit 11a) with the determination reference value, and outputs the comparison result. The frequency comparison unit 133 includes a storage unit 134 and a comparison unit 135.

  The storage unit 134 is a ROM (Read Only Memory) or the like, and stores a determination reference value. The comparison unit 135 compares the count value output from the register 132 with the determination reference value stored in the storage unit 134, and outputs a comparison result. For example, if the count value is equal to or greater than the determination reference value, an H level signal is output, and if the count value is smaller than the determination reference value, an L level signal is output.

FIG. 28 is a timing chart illustrating an operation example of the voltage variation detection circuit according to the tenth embodiment.
FIG. 28 shows the potential difference between the wiring vcc and the wiring vss, the potential difference between the wiring vccv and the wiring vss connecting the operating voltage generation unit 12a and the oscillation circuit 11a, and the state of the control signal rsen generated by the control signal generation unit 20. Has been. Moreover, (the potential of the output signal of the level shifter 14a) terminal cclk the potential of the counter 131, the count value C _ount of the counter 131, the terminal rclk counter 131 potential (potential of the reference clock), the value of the register 132 is shown . Further, an output signal out of the comparison unit 135 is shown. Incidentally, an example of the count value C _ount, because too fine, are not shown.

In the example of FIG. 28, for example, the determination reference value stored in the storage unit 134 is 70.
As shown in FIG. 28, when the count value taken into the register 132 reaches 80 (timing t40), the comparison unit 135 outputs the output signal out to H because the count value is 70 or more of the determination reference value. Level.

  At the timing t41, the potential difference between the wiring vcc and the wiring vss becomes smaller due to the influence of, for example, power supply noise, and the count value taken into the register 132 from the timing t42 starts to become smaller. However, since the count value is equal to or greater than the determination reference value at timing t42, the output signal out remains at the H level. When the count value falls below the determination reference value at timing t43, the comparison unit 135 sets the output signal out to the L level. In the example of FIG. 28, the potential difference between the wiring vcc and the wiring vss returns to the original at the timing t44, and the count value taken into the register 132 is 90. At this time, since the count value is equal to or greater than the determination reference value, the comparison unit 135 sets the output signal out to the H level.

  In this manner, by detecting a change in the count value taken into the register 132, a change in potential difference between the wiring vcc and the wiring vss can be detected. Further, by comparing the determination reference value with the count value and outputting the comparison result, it becomes easy to detect a large variation in potential difference.

As described above, one aspect of the voltage variation detection circuit and the semiconductor integrated circuit of the present invention has been described based on a plurality of embodiments.
In recent years, with the spread of smartphones and sensor devices, there has been an increasing demand for lower power consumption of semiconductor integrated circuits. In general, performance and power (energy consumption) are in a trade-off relationship, and it is regarded as a problem that the performance is lowered in order to satisfy the demand for lower power consumption.

The voltage fluctuation detection circuit according to each of the above-described embodiments operates the oscillation circuit with an operating voltage obtained by reducing the voltage to be detected. As a result, the oscillation frequency variation rate λ of the oscillation circuit is increased, and voltage measurement with reduced energy consumption E _total can be performed without reducing performance (measurement accuracy S) from the relationship of Equation (6). Further, even if the manufacturing technology changes, the voltage fluctuation detection circuit can be designed with a digital circuit, so that there is an advantage that the design is easier than a voltage sensor using an analog circuit. For this reason, the applicability of the voltage fluctuation detection circuit is considered wide.

In the above, one aspect of the voltage variation detection circuit and the semiconductor integrated circuit of the present invention has been described. However, these are merely examples, and the present invention is not limited to the above description.
For example, the above embodiments may be combined. For example, also in the voltage fluctuation detection circuit 10a of the second embodiment, the pMOS 121 and the level shifter 14a of the operating voltage generation unit 12a may be provided in a plurality of stages, or a capacitance element is connected between the wiring vdd and the wiring vddv. May be. Also in the voltage fluctuation detection circuit 10a of the second embodiment, the operating voltage generation unit 12a may be connected to the wiring vss instead of connecting to the wiring vdd to raise the ground potential. In the above example, the frequency comparison unit 133 in the voltage fluctuation detection circuit 10i according to the tenth embodiment is combined with the voltage fluctuation detection circuit 10b according to the third embodiment. Can also be used.

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 10 Voltage fluctuation detection circuit 11 Oscillation circuit 12 Operating voltage generation part (step-down circuit)
13 fluctuation detector 14 level shifter ns noise source vdd, vss wiring w1, w2 waveform

Claims (11)

An oscillation circuit that oscillates in response to an operating voltage;
An operating voltage generator for generating the operating voltage by lowering the voltage to be detected;
A fluctuation detector for detecting fluctuations in the voltage by measuring the oscillation frequency of the oscillation circuit;
A voltage fluctuation detection circuit comprising:   The voltage fluctuation detection circuit according to claim 1, wherein the operating voltage generation section generates the operating voltage that varies according to the fluctuation of the voltage.   The voltage fluctuation detection circuit according to claim 1, further comprising a level shifter that aligns an amplitude of an output signal of the oscillation circuit with an amplitude of an operation voltage of the fluctuation detection unit.   The voltage is a potential difference between a first wiring having a first potential and a second wiring having a second potential lower than the first potential, and the operating voltage generation unit lowers the first potential. The voltage fluctuation detection circuit according to claim 1, wherein the voltage is lowered.   5. The voltage variation detection circuit according to claim 4, wherein a voltage equal to or higher than the operating voltage is applied to an n-well of a p-channel MOSFET included in the oscillation circuit.   The voltage is a potential difference between a first wiring having a first potential and a second wiring having a second potential lower than the first potential, and the operating voltage generator raises the second potential. The voltage fluctuation detection circuit according to claim 1, wherein the voltage is lowered.   The voltage fluctuation detection circuit according to claim 6, wherein a voltage equal to or lower than the operating voltage is applied to a p-well of an n-channel MOSFET included in the oscillation circuit.   8. The apparatus according to claim 4, further comprising: a wiring between the operating voltage generation unit and the oscillation circuit; and a capacitor connected to the first wiring or the second wiring. The voltage fluctuation detection circuit described.   The voltage fluctuation detection circuit according to claim 1, wherein the operating voltage generation unit is one or a plurality of MOSFETs that are diode-connected. The fluctuation detection unit compares a counter that counts the number of oscillations of the oscillation circuit, a storage unit that holds a count number for a certain period, and compares the count number held with a predetermined determination reference value. A comparator that outputs the results;
The voltage fluctuation detection circuit according to claim 1, comprising: An oscillation circuit that oscillates in response to an operating voltage;
An operating voltage generator for generating the operating voltage by lowering the voltage to be detected;
A fluctuation detector for detecting fluctuations in the voltage by measuring the oscillation frequency of the oscillation circuit;
Voltage fluctuation detection circuit,
A semiconductor integrated circuit comprising:

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