JP5159470B2 - Signal processing apparatus and signal processing method - Google Patents

Description

  The present invention relates to a signal processing device including a plurality of processing units and a signal processing method in the signal processing device.

  FIG. 1 is a block diagram showing a configuration of a conventional signal processing apparatus 1. The signal processing apparatus 1 is realized by an IC (Integrated Circuit), and includes a control register group 2 and a plurality of processing units (hereinafter, the processing units are referred to as modules) A, B, and C. The register group 2 operates in synchronization with a CPU (Central Processing Unit) 3 and is connected to the CPU 3 via a bus. The register group 2 includes various setting registers from the CPU 3 and a data transfer register. The register group 2 operates by receiving a clock signal (CPUCLK) of the CPU 3. The register group 2 is reset by receiving an asynchronous reset signal (RST_X).

  Modules A, B, and C are supplied with clock signals having different periods (hereinafter referred to as clocks) and perform predetermined processing asynchronously with each other. Modules A, B, and C are different from the external IC connected to the input clock, but the basic operation is the same, so any module among modules A, B, and C is referred to as module X. The clock input to the module X will be described as a clock X (CLK_X), and an external IC connected to the module X will be described as an external IC (X).

  The module X operates by receiving a clock X (CLK_X). Each module X is connected to an external IC (X), receives transmission data set in the register group 2 from the CPU 3, encodes and modulates it, and transmits it to the external IC (X). The module X demodulates and decodes the received data from the external IC (X) and transfers it to the register group. Data received from the external IC (X) is used by the CPU 3. The module X is reset when RST_X is given.

  FIG. 2 is a diagram showing a part of the circuit configuration in modules A, B, and C. Each of the modules A, B, and C includes a flip-flop 5. Here, the flip-flop 5 shows a D flip-flop, and includes a D pin, a Cp pin, a Q pin, an S pin, and an R pin. Input data (data_in) is supplied to the D pin, a clock is supplied to the Cp pin, and data is output from the Q pin. The S pin is connected to the ground, and RST_X is given to the R pin via an inverter (not) 6. RST_X is a signal for resetting asynchronously with the clock input to the flip-flop 5.

  The asynchronous reset signal is similarly input to all flip-flops 5 in the signal processing device 1. For this reason, when the signal level of RST_X is switched from a high (Hi) level to a low (Lo) level, all flip-flops 5 are reset. Therefore, for example, when a trouble occurs in communication between the module A and the external IC (A) and the modules B and C are operating normally, the module A is reset by an asynchronous reset signal. If an attempt is made to set the flip-flops in the initial state, all of the modules B and C and the register group will be reset. Further, an asynchronous reset signal is provided from the CPU 3 which is provided outside the signal processing apparatus 1 and is the control source of the entire system, so that the load on the CPU 3 increases, and after reset, the CPU 3 again sets the settings for the modules A, B and C. There is a problem in that the load on the CPU 3 further increases because it needs to be performed on the register group 2.

  In view of such a problem, in order to individually reset the modules A, B, and C, it is conceivable that the register group 2 has a function of generating a reset signal for each module. This is because when a “1” is written in a corresponding bit of a predetermined address of the register group 2, a negative synchronous reset signal having a length corresponding to one cycle (1shot) of the CPUCLK in the register group 2 may be generated for each module. It is a function that can be. The synchronous reset signal is described as sync_clr. FIG. 3 is a timing chart showing an example of CPUCLK and sync_clr. As shown in FIG. 3, the length T1 of the Lo level portion of sync_clr is equal to the length T1 of one cycle of CPUCLK. The Lo level portion of sync_clr is called a 1shot signal.

  FIG. 4 is a diagram illustrating a part of the circuit configuration of modules A, B, and C when resetting is performed by sync_clr. Modules A, B, and C include an AND circuit (and) 7 in addition to the circuit configuration shown in FIG. data_in and sync_clr are respectively input to the AND circuit 7 and the output of the AND circuit 7 is given to the D pin. In such a circuit configuration, as shown in FIG. 3, at the rising edge t1 of CPUCLK, if sync_clr is at Lo level, that is, if sync_clr = 0, the Lo level from the Q pin regardless of the signal level of data_in. Is output, and the flip-flop 5 can be reset.

  With the circuit configuration shown in FIG. 4, it is possible to individually reset each of the modules A, B, and C. However, in order to individually reset, a predetermined condition must be satisfied. The predetermined condition is that the synchronous reset signal is due to writing to the register group 2 from the CPU 3, and the 1shot signal is synchronized with the CPUCLK, and the modules A, B, and C to be reset The flip-flop itself needs to operate in synchronization with the CPUCLK. Therefore, in the case of the signal processing device 1 shown in FIG. 1, it is possible to individually reset the modules A, B, and C only when CLK_A, CLK_B, and CLK_C are CPUCLK.

  However, the modules A, B, and C of the signal processing device 1 configured separately from the CPU 3 rarely operate only with the CPU 3 bus clock. For example, the communication between the module A and the external IC (A) conforms to a predetermined standard, and has a completely different period from the clock period of the bus clock of the CPU 3, and the clock accuracy is strict and the bus clock is multiplied or divided. CPUCLK and CLK_A must be asynchronous if the clock cannot be generated by FIG. 5 is a timing chart showing an example of CPUCLK, CLK_A, and sync_clr. The period T2 of CLK_A is selected to be longer than the period T1 of CPUCLK. In such a case, at the rising time t1 of CLK_A, there is a case where sync_clr is at the Lo level, that is, sync_clr = 0, and the flip-flop 5 may not be reset.

  Further, Patent Document 1 describes that when a plurality of circuit modules are reset, the reset signal is held for a certain period and the circuit modules are synchronously reset.

  Further, in Patent Document 2, when the CPU clock is faster than the clock of the operation block, the asynchronous soft reset signal is held and synchronized, and the circuit operating at a different frequency is compared with the reference clock. It is described that the frequency comparison circuit determines whether the frequency is high or low, and if it is high, the reset signal is extended, and if it is low, the reset signal is output as it is.

Japanese translation of PCT publication No. 2004-524631 JP 2005-78147 A

  In the technique described in Patent Document 1, although the reset signal extended in time is synchronized with a different clock for each module, there is no description on how to generate the reset signal. When the above-mentioned 1shot signal is input to “reset_in_n” described in Patent Document 1, there is a problem that a module operating at a frequency lower than a certain frequency may not be reset.

  In the technique described in Patent Document 2, it is necessary to mount a frequency comparison circuit in the apparatus, which causes a problem that the circuit scale increases. In Patent Document 2, a signal from a gate such as an AND circuit is input to the reset terminal of the flip-flop. When a signal from the gate is input to the reset terminal as described above, the signal is input to the gate. There is a problem in that an undesired signal is output from the gate due to a difference in timing of the signal to be generated, so-called whiskers occur, and a malfunction of the circuit and a difference between the simulation result and the operation of the actual machine occur.

  Accordingly, an object of the present invention is to provide a signal processing device that can reliably reset a plurality of processing units that are supplied with clock signals having different periods and perform predetermined processing asynchronously with a simple configuration. And providing a signal processing method.

The present invention (1) includes a one-cycle reset signal generator that operates with a first clock signal;
A plurality of second clock signals having different periods, each having a second clock signal having a period longer than the period of the first clock signal , and performing a predetermined process asynchronously with each other A processing unit of
A synchronous reset signal generator,
The one-cycle reset signal generation unit includes a signal for designating the predetermined processing unit when a reset command to the predetermined processing unit among the plurality of processing units is given from the outside, and includes a first clock signal Configured to generate a reset signal having a length of one period;
The synchronous reset signal generation unit is provided with the reset signal generated by the one-cycle reset signal generation unit, and generates an extended reset signal by extending the length of the reset signal to a length corresponding to the predetermined processing unit and the generated extended reset signal in synchronization with the second clock signal is configured to generate a synchronization reset signal,
The pre-determined processing unit, while the synchronization reset signal from the synchronous reset signal generation section is provided, when the second clock signal rises or falling down, is configured so that the reset,
The synchronous reset signal generator is
One is provided including one counter,
After the reset signal generated by the one-cycle reset signal generation unit is given, the number of set values of the one counter is counted in accordance with the first clock signal, thereby allowing a plurality of predetermined processing units to Configured to decompress a corresponding reset signal to generate the decompressed reset signal;
The set value of the one counter is such that the length of the decompression reset signal is longer than one cycle of the second clock signal having the longest cycle among the second clock signals of the plurality of predetermined processing units. The signal processing apparatus is characterized by being set as described above .

The present invention ( 5 ) includes a one-cycle reset signal generation unit that operates with a first clock signal and a plurality of second clock signals with different periods , which are longer than the cycle of the first clock signal. A signal processing method in a signal processing device including a plurality of processing units that are given a second clock signal having a period and perform predetermined processing asynchronously with each other, and a synchronous reset signal generation unit ,
Wherein one cycle reset signal generating unit, the plurality of processing units a reset command supplied et been externally against previously determined processor in the includes signals specifying the pre-determined processing unit, and the first clock signal generating a reset signal having a length of one period,
The synchronous reset signal generation unit is given a reset signal generated by said one cycle reset signal generating unit, generates an extended reset signal is stretched to a length corresponding to the processing unit to determine the length of the reset signal the advance And synchronizing the generated decompression reset signal with the second clock signal to generate a synchronous reset signal;
Previously determined processing unit comprises while the synchronization reset signal from the synchronous reset signal generation section is provided, when the second clock signal rises or falling down, and a step that will be reset,
The synchronous reset signal generator is
One is provided including one counter,
After the reset signal generated by the one-cycle reset signal generation unit is given, the number of set values of the one counter is counted in accordance with the first clock signal, thereby allowing a plurality of predetermined processing units to Configured to decompress a corresponding reset signal to generate the decompressed reset signal;
The set value of the one counter is such that the length of the decompression reset signal is longer than one cycle of the second clock signal having the longest cycle among the second clock signals of the plurality of predetermined processing units. It is the signal processing method characterized by setting as follows.

According to the present invention (1), the one-cycle reset signal generator operates with the first clock signal. The one-cycle reset signal generation unit includes a signal for designating the predetermined processing unit when a reset command to the predetermined processing unit among the plurality of processing units is given from the outside, and one cycle of the first clock signal A reset signal having a length of minutes is generated. The synchronous reset signal generation unit is provided with the reset signal generated by the one-cycle reset signal generation unit, generates an extended reset signal in which the length of the reset signal is extended to a length corresponding to the predetermined processing unit, The generated decompression reset signal is synchronized with the second clock signal to generate a synchronous reset signal. In this way, the synchronous reset signal generation unit generates the synchronous reset signal by extending the reset signal having a length corresponding to one period of the first clock signal, and therefore, by a simple process of extending the reset signal, A synchronous reset signal for resetting a predetermined processing unit can be generated. Therefore, it is possible to suppress an increase in the scale of a circuit constituting the device. In addition, since the output from the AND circuit as in the prior art is different from the configuration in which the flip-flop reset terminal is input, it is possible to suppress the malfunction of the circuit and the difference between the simulation result and the operation of the actual machine. The

According to the present invention ( 5 ), when a reset command for a predetermined processing unit among a plurality of processing units is given from the outside, the signal includes a signal designating the predetermined processing unit and 1 of the first clock signal. A reset signal having a length corresponding to the period is generated. A generated reset signal is provided, an extended reset signal is generated by extending the length of the reset signal to a length corresponding to the predetermined processing unit, and the generated extended reset signal is synchronized with the second clock signal. To generate a synchronous reset signal. In this way, the reset signal having a length corresponding to one cycle of the first clock signal is stretched to generate the synchronous reset signal, so that the predetermined processing unit is reset by a simple process of stretching the reset signal. A synchronous reset signal can be generated. Therefore, an increase in the scale of the circuit forming the device is suppressed. In addition, since the output from the AND circuit as in the prior art is different from the configuration in which the flip-flop reset terminal is input, it is possible to suppress the malfunction of the circuit and the difference between the simulation result and the operation of the actual machine. The

  FIG. 6 is a block diagram illustrating a configuration of the signal processing device 11 according to the embodiment of this invention. FIG. 6 shows not only the signal processing device 11 but also the CPU 13 and the external ICs (A), (B), and (C).

  The signal processing device 11 is realized by an IC, and includes a module circuit unit 14 including a control register group and a one-cycle reset signal generation unit, a synchronous reset generation circuit unit 15, and a plurality of processing units (hereinafter referred to as modules). A, B, C. The synchronous reset generation circuit unit 15 is a synchronous reset signal generation unit.

  The module circuit unit 14 operates in synchronization with the CPU 13 and is connected to the CPU 13 via a bus. The control register group of the module circuit unit 14 includes various setting registers from the CPU 13 and a data transfer register. The module circuit unit 14 operates by receiving a clock signal (CPUCLK) of the CPU 13. CPUCLK is a first clock signal.

  When a reset command for any one of the modules A, B, and C is given, the one cycle reset signal generation unit of the module circuit unit 14 includes a signal designating the module to be reset, and one cycle of the CPUCLK. A reset signal having a length of (1shot) is generated. This reset signal is given from the module circuit unit 14 to the synchronous reset generation circuit unit 15.

  Hereinafter, the reset signal may be referred to as a 1shot reset signal. For example, when predetermined data is stored at a predetermined address of a control register group, the one-cycle reset signal generation unit generates and outputs a 1-shot reset signal. Here, the 1shot reset signal is a negative logic signal having a length corresponding to one cycle (1shot) of the CPUCLK.

  Modules A, B, and C operate with a clock signal having a period longer than the period of CPUCLK. Modules A, B, and C are supplied with clocks (CLK) having different periods and perform predetermined processing asynchronously with each other. Here, the modules A and B operate without synchronizing with the CPUCLK, and the module C operates with synchronizing with the CPUCLK.

  FIG. 7 is a diagram illustrating a part of the circuit configuration of modules A, B, and C. Each of the modules A, B, and C includes a flip-flop (FF) 16 and an AND circuit (and) 17. Here, the flip-flop 16 shows a D flip-flop, and includes a D pin, a Cp pin, and a Q pin. The output of the AND circuit 7 is given to the D pin. The AND circuit 17 is supplied with input data (data_in) and a synchronous reset signal (sync_clr), a clock is supplied to the Cp pin, and data is output from the Q pin. The operation is the same as that of the circuit shown in FIG. 4. When sync_clr is Lo level, that is, sync_clr = 0 at the rising edge of CLK, a Lo level signal is output from the Q pin regardless of the signal level of data_in. The flip-flop 16 can be reset.

  Modules A, B, and C have different external ICs connected to the input clock, but the basic operation is the same. Therefore, any of the modules A, B, and C is designated as module X. The clock input to the module X will be described as a clock X (CLK_X), and an external IC connected to the module X will be described as an external IC (X).

  The module X operates by receiving a clock X (CLK_X). Each module X is connected to an external IC (X), receives transmission data set in the register group 2 from the CPU 13, encodes and modulates it, and transmits it to the external IC (X). The module X demodulates and decodes the received data from the external IC (X) and transfers it to the register group. Data received from the external IC (X) is used by the CPU 13.

  The synchronous reset generation circuit unit 15 is supplied with a 1shot reset signal from the module circuit unit 14 and extends the length of the 1shot reset signal to a length corresponding to one of the modules A, B, and C. And the generated decompression reset signal is synchronized with a clock signal corresponding to any one of the modules A, B, and C to generate a synchronous reset signal (sync_clr). The synchronous clock signal corresponding to module A may be described as sync_clrA, the synchronous clock signal corresponding to module B may be described as sync_clrB, and the synchronous clock signal corresponding to module C may be described as sync_clrC.

  That is, when the 1-shot reset signal corresponding to the module X is given from the module circuit unit 14 to the synchronous reset generation circuit unit 15, the extended reset signal X1 obtained by extending the length of the 1-shot reset signal to the length corresponding to the module X is obtained. And the generated decompression reset signal X1 is synchronized with CLK_X to generate the synchronous reset signal X2.

  FIG. 8 is a diagram showing a part of the configuration of the synchronous reset generation circuit unit 15. Here, only the configuration of the portion that generates the synchronous reset signal A2 that is synchronized with CLK_A will be described, and the portions that generate the synchronous reset signals B2 and C2 have the same configuration, and the description thereof will be omitted.

  A configuration (hereinafter referred to as a synchronization reset signal generation unit) 18 that generates a synchronization reset signal of the synchronization reset generation circuit unit 15 includes a counter 21, a setting value storage unit 22, and a CPUCLK synchronization flip-flop for synchronizing with the CPUCLK. 23 and a CLK_A synchronizing flip-flop group 24 for synchronizing with CLK_A.

  The counter 21 receives a 1shot reset signal and CPUCLK, and inputs the 1shot reset signal in accordance with information representing the setting value stored in the setting value storage unit 22, and then the setting value in accordance with the CPUCLK. Is generated by extending the predetermined number of cycles of the 1shot reset signal. It is assumed that the initial value of the counter 21 is 0, and the counter 21 returns to 0 when the count is completed. A set value used by the counter 21 is stored in the set value storage unit 22. The set value represents the number counted by the counter 21. Since the counter 21 performs counting in accordance with CPUCLK, an extension reset signal having a length that is a multiple of the period of CPUCLK is generated.

  The setting value stored in the setting value storage unit 22 may be determined in advance, or may be provided so as to be changeable by a setting unit provided with a setting unit. The setting unit includes, for example, the CPU 13 and an input device such as a keyboard, and the CPU 13 can rewrite the setting value in the setting value storage unit 22 when the user operates the input device. By making the setting value changeable in this way, when the specifications of the modules A, B, and C are changed, the setting value can be changed to a new setting value, and convenience is improved.

  The CPUCLK synchronization flip-flop 23 is realized by a D flip-flop, and an output signal from the counter 21 is input to the D pin, and CPUCLK is input to the Cp pin. As a result, an expansion reset signal synchronized with CPUCLK is output from the Q pin.

  The CLK_A synchronization flip-flop group 24 includes at least two D flip-flops. The output signal from the CPUCLK synchronization flip-flop 23 is input to the D pin of the D flip-flop that is the upstream synchronization flip-flop 24A in the direction in which the signal is transmitted. The output signal from the Q pin of the upstream D flip-flop is input to the D pin of the D flip-flop which is the downstream synchronization flip-flop 24B. In addition, CLK_A is input to the Cp pin of each D flip-flop, whereby a synchronous reset signal synchronized with CLK_A can be generated from the decompression reset signal. Further, the CLK_A synchronization flip-flop group 9 can suppress metastable by including at least two D flip-flops.

  In this embodiment, the case where CLK_A is not synchronized with CPUCLK is described. However, when CLK_A is synchronized with CPUCLK and when CPUCLK is used as CLK_A, the Q of CPUCLK synchronization flip-flop 23 is set. An extended reset signal synchronized with CPUCLK from the pin may be output as it is as a synchronous reset signal.

  FIG. 9 is a flowchart showing a procedure of reset processing in the signal processing device 11. Here, only the case of resetting the module A is shown, but the same applies to the case of resetting the modules B and C. When the reset process is started, the process proceeds from step s0 to step s1. In step s1, the CPU 13 sets a synchronous reset for the module A, and the control register group of the module circuit unit 14 is set in advance at a predetermined address (for example, the position of bit “0” of the address “0x2”). The determined data (for example, “1”) is stored, and the process proceeds to step s2.

  In step s2, the CPU 13 performs a ride operation, and the control register group of the module circuit unit 14 stores predetermined data at a predetermined address as in step s1, so that the one-cycle reset signal generation unit is Corresponding to the module A, a 1shot reset signal having a width of one cycle of the CPUCLK is output to the synchronous reset generation circuit unit 15, and the process proceeds to step s3.

  In step s3, in the synchronous reset generation circuit, the 1shot reset signal having a width of one cycle of CPUCLK is extended using the counter 21 operating with CPUCLK, and the extended extension reset signal is hit twice or more with CLK_A to CLK_A. Synchronize and output to module A. Here, hitting with CLK_A means that a signal is input to a flip-flop using CLK_A as a clock signal and a signal synchronized with CLK_A is output.

  In step s4, the synchronous reset signal input to the module A by the synchronous reset generation circuit unit 15 "extended" from the 1shot reset signal and synchronized with "CLK_A" is applied to all flip-flops in the module A. It is done. The synchronous reset signal sync_clrA is input to the input terminal of the AND circuit to which the sync_clrA shown in FIG. 7 of the module circuit unit 14 is to be input, thereby resetting only the module A among the modules A, B, and C. can do.

  FIG. 10 is a timing chart showing the operation of the signal processing device 11. In FIG. 10, (1) CPUCLK, (2) ADDR / DATA (address / data) signal, (3) CS (chip select) signal, (4) WE (write enable) signal, (5) WAIT (hard wait) signal, (6) 1shot reset signal, (7) counter value, (8) decompression reset signal, (9) CLK_A, and (10) decompression reset signal were hit once by CLK_A And (11) a synchronous reset signal when the decompression reset signal is tapped twice by CLK_A. ADDR / DATA (address / data) is given from the CPU 13 to the module circuit unit 14. The CS signal is a signal that is maintained at the H level when the CPU 13 does not select the module circuit unit 14 and is maintained at the L level when the CPU 13 selects the module circuit unit 14. The WE signal is a signal that is maintained at the H level when the CPU 13 does not write to the register of the module circuit unit 14, and is maintained at the L level when writing. The WAIT signal is a signal for the CPU 13 to temporarily stop the processing of the one-cycle reset signal generation unit of the module circuit unit 14, and is maintained at the H level when the module circuit unit 14 can be processed. When the process 14 is stopped, the signal is maintained at the L level.

  At time t1, the CS signal and the WE signal are changed from H level to L level, and ADDR / DATA writing is started. When the writing of ADDR / DATA is started, the WAIT signal is changed from H level to L level at time t2, and the processing of the one-cycle reset signal generation unit of the module circuit unit 14 is temporarily stopped. When the ADDR / DATA writing is completed, the WAIT signal is changed from the L level to the H level, the CPU signal rises when the CS signal and the WE signal are at the L level and the WAIT signal is at the H level. The one-cycle reset signal generation unit starts processing, and generates and outputs a 1shot reset signal at time t3. The module circuit unit 14 generates the 1shot reset signal by changing the output signal maintained at the H level to the L level.

  When the 1 shot reset signal is given to the counter 21 and the output from the module circuit section 14 rises from the L level to the H level, the counter 21 starts counting in accordance with the rise of the CPUCLK. Here, the setting value is “5”. When the counter 21 starts counting, at time t3, the output of the CPUCLK synchronization FF 23 is switched from the H level to the L level. The CPUCLK synchronization FF 23 generates the decompression reset signal by maintaining the output at the L level only while the counter 21 is counting.

  Here, how to select the setting value of the counter 21 will be described. Here, one period of CLK_A is T1, and one period of CLK_A is T2. The set value of the counter 21 is determined by sequentially performing the following procedures (1) to (3).

(1) One cycle (T1) of CPUCLK is calculated. For example, when the frequency of CPUCLK is 41 Mhz, T1 is about 24.4 ns.
(2) One period (T2) of CLK_A is calculated. For example, when the frequency of CLK_A is 18 Mhz, T2 is about 55.6 ns.
(3) T1 is multiplied by an integer (n) until n (n is a natural number) × T1> T2, and the number “n” multiplied when T1> T2 is satisfied becomes a set value for the purpose. For example, if 24.4 ns is doubled, it is 48.8 ns, but this is less than 55.6 ns, and if 24.4 ns is tripled, it is 73.2 ns, which exceeds 55.6 ns. “3”. That is, the length of the 1shot reset signal may be increased by a factor of three. However, it is preferable that the set value is “n + 1” with a margin.

  The synchronization FF 24A outputs an L level signal when an expansion reset signal is given at the rise of CLK_A, that is, when an L level signal is given from the CPUCLK synchronization FF 23, and at the rise of CLK_A, the CPUCLK When an H level signal is given from the synchronization FF 23, an H level signal is output. Here, after the extension reset signal is given and CLK_A rises, the FF 24A for synchronization is set to L for two cycles (2 × T2) of CLK_A from t5 slightly after the rise time t4 of CLK_A. A level signal is output.

  The synchronizing FF 24B outputs an L level signal when an L level signal is given from the synchronizing FF 24A at the rising edge of CLK_A, and an H level signal is given from the synchronizing FF 24B at the rising edge of CLK_A. And an H level signal is output. Here, an L level signal is given from the synchronization FF 24A, and after CLK_A rises, the CLK_A rises slightly after the rise time t6, and for two cycles (2 × T2) of CLK_A from time t7. The synchronization FF 24B outputs an L level signal as a synchronization reset signal. The module A is reset when the synchronization reset signal from the synchronization FF 24B is given to the module A and CLK_A is given.

  As described above, in the signal processing device 11, the synchronization reset signal generation unit 15 generates the synchronization reset signal by extending the 1shot reset signal having a length corresponding to one cycle of the CPUCLK, and therefore, the signal processing device 11 simply extends the 1shot reset signal. Through a simple process, a synchronous reset signal for resetting modules A, B, and C can be generated. Therefore, it is possible to suppress an increase in the scale of a circuit constituting the device. In addition, since the output from the AND circuit as in the prior art is different from the configuration in which the flip-flop reset terminal is input, it is possible to suppress the malfunction of the circuit and the difference between the simulation result and the operation of the actual machine. The

  The modules A, B, and C operate with a clock signal that is asynchronous with the CPUCLK, but the modules other than at least one of the modules A, B, and C operate with a clock signal that is synchronized with the CPUCLK or with the CPUCLK. In this case, the synchronization reset generation circuit unit 15 may be configured to give the above-described decompression reset signal as the synchronization reset signal.

  In the present embodiment, the synchronous reset generation circuit unit 15 includes the synchronous reset generation circuit unit 15 shown in FIG. 8 for each of the modules A, B, and C. In the embodiment, each module A, B, C may be configured to have only one synchronous reset generation circuit unit 15. In this case, since one counter 21 is shared and a synchronous reset signal for the modules A, B, and C is generated, the set value of the counter 21 has the longest cycle among the clock signals of the modules A, B, and C. The clock signal is obtained based on the above-described conditions. The synchronous clock signal is given in common to modules A, B, and C. Here, the synchronous reset generation circuit unit 15 is shared for the modules A, B, and C. However, the synchronous reset generation circuit unit 15 may be shared for any two of the modules A, B, and C. Good.

  FIG. 11 is a block diagram showing a partial configuration of a signal processing device 41 according to another embodiment of the present invention. The signal processing device 41 has a configuration similar to that of the signal processing device 11 shown in FIG. 6 described above. In the signal processing device 11, data is transferred between the module A and the module B. Since the configuration is the same as that of the signal processing device 11, the same reference numerals are given to the same configuration, and the description thereof is omitted.

  The signal processing device 41 includes a clock changing unit 42 in addition to the configuration of the signal processing device 11. The clock transfer unit 42 constitutes a module D together with the module A and the module B. Here, it is assumed that CLK_A of module A is synchronous with CPUCLK and equal to CPUCLK, CLK_B of module B is asynchronous with CPUCLK, and its period is, for example, about 2.5 times that of CPUCLK.

  The clock transfer unit 42 is realized by a circuit that contracts the difference in the clock signal cycle when data is transferred between the module A and the module B having different clock signal cycles.

  FIG. 12 is a diagram illustrating a configuration of the clock transfer unit 42. The clock change unit 42 transmits information (signal_a_to_b) such as control signals and data from the module A to the module B, and transmits information (signal_b_to_a) such as control signals and data from the module B to the module A. Second portion 42b. Each of the first and second parts includes three or more flip-flops 5 and is connected to a plurality of stages, that is, the Q pin of the preceding flip-flop 5 and the D pin of the succeeding flip-flop 5 are connected. . Each Cp pin of each slip flop 5 receives the clock of the module that receives the information, that is, CLK_A is given to the slip flop 5 of the first part 42a, and CLK_B is given to the slip flop 5 of the second part 42b. Given.

  Module A and module B are communicating, for example, a request signal (data transfer request) is output from module A, and module B outputs an acknowledgment signal (data acceptance OK) in response to this request. Assume that a synchronous reset signal with a time lag is input to module A and module B in a state where they are not simultaneously. Here, a case is considered where a synchronous reset signal is first input to module A, and then a synchronous reset signal is input to module B.

  In this case, the module A is reset, and as a result, the request signal output from the module A is cleared. However, since the module B is not reset, the ACK signal continues to be output, and the ACK signal is input to the module A.

  Here, when the reset of the module A is released, the ACK signal is input even though the module A has not issued a request, and the internal circuit of the module A may operate. As a result, the module A is not reset.

  Next, when the module B is reset, the ACK signal is cleared. In module A, there is a possibility that the circuit malfunctions on the assumption that an ACK signal is input, and an unexpected ACK signal is withdrawn, which further increases the risk of malfunction. If an incorrect request signal is input to module B when module A is malfunctioning, module B may respond to the request signal of module A and return an ACK signal. Module D may not be reset and may malfunction.

  Therefore, in the signal processing device 41, when a synchronous reset signal is given from the CPU 13 to the module A, the synchronous reset signal is also given to the module B, and the modules A and B are reset almost simultaneously.

  FIG. 13 is a timing chart showing the operation in the signal processing device 41. In FIG. 12, (1) CPUCLK, (2) ADDR / DATA (address / data) signal, (3) CS (chip select) signal, (4) WE (write enable) signal, (5) WAIT (hard wait) signal, (6) 1shot reset signal, (7) counter value, (8) decompression reset signal, (9) CLK_A, and (10) decompression reset signal were hit once by CLK_A The synchronous reset signal at the time, (11) the synchronous reset signal when the expansion reset signal is tapped twice by CLK_A, and (12) CLK_B are shown.

  In the present embodiment, the set value of the counter 21 is determined by sequentially performing the following procedures (4) to (5).

(4) Calculate one cycle (T1) of CPUCLK.
(5) Calculate one period (T3) of CLK_B.
(6) T1 is multiplied by an integer (n) until n (n is a natural number) × T1> T3, and the number “n” multiplied when T1> T3 is satisfied becomes a set value for the purpose. However, it is preferable that the set value is “n + 1” with a margin. Here, the set value is indicated as “5”.

  An output signal from the CPUCLK synchronization FF 23 is input to an input terminal of an AND circuit to which the sync_clrA of the module A is to be input. The output signal from the synchronization FF 24B is input to the input terminal of the AND circuit to which the sync_clrA of the module B should be input. With this configuration, the period T4 during which the decompression reset signal is output and the period T5 during which the synchronization reset signal is output can overlap each other during the period T6. During this overlapping period T6, CLK_A and CLK_B rise and modules A and B can be reset almost simultaneously. This makes it possible to reset the modules A and B almost simultaneously and reliably with a simple configuration, and to prevent the modules A and B from malfunctioning.

  The modules A, B, and C of the above-described embodiments are configured to be reset when a synchronous reset signal is given and the clock signal rises. However, the synchronous reset signal is given, Further, it may be configured to be reset when the clock signal falls.

  FIG. 14 shows a navigation device 50 including the signal processing device 11 described above. The navigation device 50 displays the current position of the navigation device 50 on a map such as a road map, or searches for a route from a departure point to a destination set by the user based on map data such as a road map. The current position of the navigation device 50 and a map are displayed so as to enable movement along the searched route, and route guidance is performed. The navigation device 50 is provided and used in a moving body such as a vehicle.

  The navigation device 50 includes a GPS (Global Positioning System) receiver 51, a main storage unit 52, a temporary storage unit 53, an operation unit 54, a display unit 55, and a navigation processing unit (hereinafter referred to as “navigation processing unit”) 56. The signal processing device 11 and the communication unit 57 are basically included. In addition to the navigation device 50, a GPS antenna 58, a microphone 59, and a speaker 60 are included.

  The GPS receiver 51 receives a plurality of radio signals transmitted from GPS satellites via the GPS antenna 58. The GPS receiver 51 gives a plurality of received radio wave signals to the navigation processing unit 56.

  The main storage unit 52 is realized by a nonvolatile recording medium such as a flash ROM (Read Only Memory) and a hard disk. The main memory 52 includes a control program for comprehensively controlling hardware resources constituting the navigation device 50, map data representing a map used for route guidance, setting information set in the navigation device 50, In addition, voice information related to a predetermined voice is stored. The predetermined voice is, for example, a beep sound and a synthesized voice output from the speaker 60 when performing route guidance. The setting information is, for example, information on the scale of the displayed map, information on the starting point and destination of navigation, and the like.

The temporary storage memory 24 is, for example, an SDRAM (Synchronous Dynamic Random Access).
This is realized by a volatile semiconductor memory such as a memory. The temporary storage memory 24 temporarily stores the calculation result in the processing of the navigation processing unit 50, the control program read from the main storage unit 52 and executed, the position information of the navigation device 50 generated by the navigation processing unit 56, and the like. Remember me.

  The operation unit 55 is an input unit, and includes an operation switch for inputting predetermined information including a command operated by the user and given to the navigation device 50. The display unit 55 is realized by, for example, a liquid crystal display (abbreviation: LCD) or an organic EL (Electro Luminescence) display capable of color display. Display unit 55 displays predetermined characters and images in accordance with instructions given from navigation processing unit 56. The images displayed on the display unit 55 are a road map, the position of the navigation device 50, route guidance, sightseeing guidance, and the like.

  The microphone 59 inputs sound emitted by a user, for example. Voice information representing the voice input to the microphone 59 is given to the navigation processing unit 56. The navigation processing unit 56 may recognize predetermined voice information given from the microphone 59 and perform route guidance processing, for example.

  When a predetermined sound stored in the main storage unit 52, specifically, data such as a beep sound and a synthesized sound is given as an electric signal, the speaker 60 acousticizes and outputs the electric signal.

  The communication unit 57 includes an IrDA (Infrared Data Association) module that performs infrared communication, and an interface (I / F) module that is connected to an external electronic device by wire. The IrDA module and the I / F module are the external ICs described above.

  In such a navigation device 50, the signal processing device 11 operates in response to a command from the navigation processing unit 56, and the IrDA module and the I / F module of the communication unit 57 can be individually reset. And the reliability of communication between the external electronic devices.

It is a block diagram which shows the structure of the signal processing apparatus 1 of a prior art. It is a figure which shows a part of circuit structure in modules A, B, and C. It is a timing chart which shows an example of CPUCLK and sync_clr. It is a figure which shows a part of circuit structure of the modules A, B, and C in the case of resetting by sync_clr. It is a timing chart which shows an example of CPUCLK, CLK_A, and sync_clr. It is a block diagram which shows the structure of the signal processing apparatus 11 of one Embodiment of this invention. It is a figure which shows a part of circuit structure of modules A, B, and C. 3 is a diagram illustrating a part of the configuration of a synchronous reset generation circuit unit 15. FIG. 5 is a flowchart showing a reset process procedure in the signal processing apparatus 11; 3 is a timing chart showing the operation of the signal processing device 11. It is a block diagram which shows the structure of a part of signal processing apparatus 41 of other embodiment of this invention. 3 is a diagram illustrating a configuration of a clock transfer unit 42. FIG. 4 is a timing chart showing an operation in the signal processing device 41. The navigation device 50 includes the signal processing device 11.

Explanation of symbols

11, 41 Signal processor 13 CPU
DESCRIPTION OF SYMBOLS 14 Module circuit part 15 Synchronous reset production | generation part 16 Flip-flop 17 AND circuit 18 Synchronous reset signal production | generation part 21 Counter 22 Setting value memory | storage part 42 Clock transfer part A, B, C, D Processing part

Claims (5)

A one-cycle reset signal generator that operates with a first clock signal;
A plurality of second clock signals having different periods, each having a second clock signal having a period longer than the period of the first clock signal , and performing a predetermined process asynchronously with each other A processing unit of
A synchronous reset signal generator,
The one-cycle reset signal generation unit includes a signal for designating the predetermined processing unit when a reset command to the predetermined processing unit among the plurality of processing units is given from the outside, and includes a first clock signal Configured to generate a reset signal having a length of one period;
The synchronous reset signal generation unit is provided with the reset signal generated by the one-cycle reset signal generation unit, and generates an extended reset signal by extending the length of the reset signal to a length corresponding to the predetermined processing unit and the generated extended reset signal in synchronization with the second clock signal is configured to generate a synchronization reset signal,
The pre-determined processing unit, while the synchronization reset signal from the synchronous reset signal generation section is provided, when the second clock signal rises or falling down, is configured so that the reset,
The synchronous reset signal generator is
One is provided including one counter,
After the reset signal generated by the one-cycle reset signal generation unit is given, the number of set values of the one counter is counted in accordance with the first clock signal, thereby allowing a plurality of predetermined processing units to Configured to decompress a corresponding reset signal to generate the decompressed reset signal;
The set value of the one counter is such that the length of the decompression reset signal is longer than one cycle of the second clock signal having the longest cycle among the second clock signals of the plurality of predetermined processing units. The signal processing apparatus is characterized by being set as follows. A processing unit that operates with the first clock signal;
The one-cycle reset signal generation unit includes a signal for designating the processing unit when a reset command for the processing unit operating with the first clock signal is given from the outside, and for one cycle of the first clock signal. Generating a reset signal having a length;
The processing unit that operates with the first clock signal is reset when the first clock signal rises or falls while the reset signal is supplied from the one-cycle reset signal generation unit. The signal processing apparatus according to claim 1.   The signal processing apparatus according to claim 1, wherein the synchronous reset signal generation unit includes a setting unit capable of setting a length for extending the reset signal. A processing unit that operates on the first clock;
A processing unit that operates with a first clock and the predetermined processing unit are provided so as to be able to exchange data with each other,
When a reset command is given to the processing unit that operates with the first clock, the synchronous reset signal generation unit includes a first synchronous reset signal that is synchronized with the clock signal of the processing unit that operates with the first clock, A second synchronization reset signal to be supplied to the processing unit to be determined, and a second synchronization reset signal is supplied to the predetermined processing unit while the first synchronization reset signal is being supplied to the processing unit operating with the first clock. The signal processing apparatus according to claim 1, wherein a synchronous reset signal is provided. A one-cycle reset signal generator that operates with the first clock signal, and a second clock that has a plurality of second clock signals with different periods and a period longer than the period of the first clock signal A signal processing method in a signal processing device including a plurality of processing units that are given signals and perform predetermined processing asynchronously with each other, and a synchronous reset signal generation unit ,
Wherein one cycle reset signal generating unit, the plurality of processing units a reset command supplied et been externally against previously determined processor in the includes signals specifying the pre-determined processing unit, and the first clock signal generating a reset signal having a length of one period,
The synchronous reset signal generation unit is given a reset signal generated by said one cycle reset signal generating unit, generates an extended reset signal is stretched to a length corresponding to the processing unit to determine the length of the reset signal the advance And synchronizing the generated decompression reset signal with the second clock signal to generate a synchronous reset signal;
Previously determined processing unit comprises while the synchronization reset signal from the synchronous reset signal generation section is provided, when the second clock signal rises or falling down, and a step that will be reset,
The synchronous reset signal generator is
One is provided including one counter,
After the reset signal generated by the one-cycle reset signal generation unit is given, the number of set values of the one counter is counted in accordance with the first clock signal, thereby allowing a plurality of predetermined processing units to Configured to decompress a corresponding reset signal to generate the decompressed reset signal;
The set value of the one counter is such that the length of the decompression reset signal is longer than one cycle of the second clock signal having the longest cycle among the second clock signals of the plurality of predetermined processing units. A signal processing method characterized by being set as follows.

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