JP4290412B2 - Data transfer device - Google Patents

Data transfer device Download PDF

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Publication number
JP4290412B2
JP4290412B2 JP2002333435A JP2002333435A JP4290412B2 JP 4290412 B2 JP4290412 B2 JP 4290412B2 JP 2002333435 A JP2002333435 A JP 2002333435A JP 2002333435 A JP2002333435 A JP 2002333435A JP 4290412 B2 JP4290412 B2 JP 4290412B2
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Japan
Prior art keywords
signal
clock
data
metastable
means
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JP2002333435A
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JP2004171102A (en
Inventor
哲郎 原
英昭 小田切
直哉 木村
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Okiセミコンダクタ株式会社
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Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data transfer technique in a system in which a clock on a transmission side and a clock on a reception side are different from each other.
[0002]
[Prior art]
A flip-flop used as an element constituting a circuit such as a register has a setup time and a hold time, so that the value of the input signal is not changed during a certain period (setup time + hold time) before and after the rising edge of the clock. There is a need. However, in a system in which data is transferred between devices using different clocks, the value of the input signal may change within the period, and in this case, the output signal of the flip-flop oscillates and becomes unstable ( Lasts for a period of time (commonly referred to as metastable state). If this metastable occurs, there is a possibility that correct data may not be sent to subsequent logic circuits.
[0003]
As countermeasures, it has been proposed that data from the transmission side is not directly input to the logic, but one or a plurality of flip-flops are provided in front of the logic, and the output of this flip-flop is input to the logic. For example, refer nonpatent literature 1). This is because the metastable period is relatively short, and even if a metastable occurs in the output signal of a certain flip-flop, the metastable state is not reached until the next flip-flop captures this signal at the rising edge of the next clock. Is based on the fact that it is almost over.
[0004]
[Non-Patent Document 1]
“Design Wave Magazine 2001 September CQ Publishing Co., Ltd.“ HDL Description Style 7th Data Transfer Between Asynchronous Clocks ”
[0005]
[Problems to be solved by the invention]
However, even if the metastable state is prevented from propagating with the above configuration, the frequency of the receiving clock is lower than the frequency of the transmitting clock or the frequency and phase of the receiving clock are the frequencies of the transmitting clock. If the phase is close to the phase, a change in the value of the transmission data (the value of the transmission signal on the transmission side) cannot be detected on the reception side, causing a problem that data is lost.
[0006]
The present invention has been made in view of the above problem, and prevents propagation of the metastable state, and when the frequency of the clock on the reception side is lower than the frequency of the clock on the transmission side or the frequency and phase of the clock on the reception side It is an object of the present invention to provide a data transfer device in which no data is lost even when the frequency and phase of the clock on the transmission side are close.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a data transfer device of the present invention is connected to a first device using a first clock and a second device using a second clock. A data transfer device between different clocks for receiving a first clock, receiving the second clock from the second device, and transferring the pulse signal from the first device to the second device; disposed downstream of the first device logic, the pulse width of the pulse signal to be transferred, first to extend in accordance with a ratio between the first frequency and the second clock frequency of the clock The first meta step comprises pulse width expanding means and at least one flip-flop arranged in front of the logic of the second device, and removes the metastable of the transferred pulse signal. And a table removal means, the width of the first clock frequency ÷ the second clock what one frequency by rounding up the decimal point of the value added is n, the first clock of the clock pulse When w, the first pulse width extending means extends the pulse width of the signal to be transferred to n · w .
[0008]
DETAILED DESCRIPTION OF THE INVENTION
The block diagram of FIG. 1 shows the configuration of a data transfer device between different clocks according to the first embodiment of the present invention. The apparatus of this embodiment includes a pulse register 102 and a final output stage flip-flop 104 on the transmission side, and a synchronizer 120 including flip-flops 107 and 109 on the reception side.
[0009]
A Request signal to be transferred between different clocks or between a plurality of clock domains is input to the pulse register 102, the pulse width is widened, and input to the flip-flop 104 at the final stage. A clock A is supplied to the pulse register 102 and the flip-flop 104.
[0010]
On the reception side, the Request signal transferred from the transmission side is received via the synchronizer 110 in order to prevent the metastable state from propagating to the internal logic 120. The Request signal with the metastable state removed is sent from the synchronizer 110 to the logic 120. A clock B is supplied to the flip-flops 107 and 109 constituting the synchronizer 110.
[0011]
When the rising phases of the clock A and the clock B are very close, a change in the value of the transferred signal may not be detected on the receiving side in the conventional transfer device, and data loss has occurred. In the mode, the pulse width of the signal to be transferred is expanded by the pulse register 102 and then transferred to the receiving side. Therefore, even if the change in the value of the transferred signal cannot be detected at the rising edge of the clock B on the receiving side. However, it can be detected at the next rising edge, and no data is lost.
[0012]
In general, the setup time (x) and hold time (y) of the flip-flop are very short compared to the clock cycle, and there is a relationship of x + y <1 clock pulse width. Therefore, when the frequency of the clock A is f (Clock A) and the frequency of the clock B is f (Clock B), in order to prevent the occurrence of a metastable state and data loss, transfer to the cycle of the clock A is performed. The pulse width of the signal to be transferred may be widened so that the ratio of the period of the signal to be transmitted is at least the value of the expression [roundup {f (Clock A) / f (Clock B) +1}]. Here, roundup {} represents an integer value obtained by rounding up the numbers in {}. FIG. 2 shows the values of the above formulas for various combinations of the clock frequency (clk_a) on the transmitting side and the clock frequency (clk_b) on the receiving side.
[0013]
The Request signal whose pulse width is widened by the pulse register 102 is received by the flip-flop 107 of the synchronizer on the receiving side. If no metastable occurs, the received Request signal is supplied to the internal logic via the flip-flop 109 as it is. When a metastable is generated due to the phase relationship between the clock A and the clock B, the metastable is removed by passing through the flip-flop 109 and then supplied to the internal logic.
[0014]
FIG. 3 is a timing chart showing the above signal transfer operation. Here, the clock A is 33 MHz and the clock B is 20 MHz, and the pulse width of the Request signal is extended to 3 pulses of the clock A and transferred. It can be seen that a metastable occurs at the output of the flip-flop 107 but is removed by the flip-flop 109 and the Request signal is transferred correctly.
[0015]
FIG. 4 shows an example in which the functions of the pulse register 102 and the synchronizer 110 of the present embodiment are described in RTL (register transfer level) of HDL (hardware description language).
[0016]
As described above, according to the present embodiment, in the data transfer device between different clocks for transferring a signal from the first device using the first clock to the second device using the second clock, 1st pulse width expansion means which is arranged after the logic of one device and expands the pulse width of the pulse signal to be transferred in accordance with the ratio between the frequency of the first clock and the frequency of the second clock And a first metastable removing means for removing the metastable of the transferred pulse signal, comprising at least one flip-flop arranged in front of the logic of the second device. Prevent metastable state propagation, and if the frequency of the receiving clock is lower than the frequency of the transmitting clock, or the frequency of the receiving clock The number and phase are realized data transfer between different clocks data loss does not occur even when close to the frequency and phase of the clock of the sender.
[0017]
FIG. 5 shows the configuration of a data transfer apparatus between different clocks according to the second embodiment of the present invention. As in the first embodiment, the apparatus of this embodiment includes a pulse register 202 and a final output stage flip-flop 204 on the transmission side, and a synchronizer 210 including flip-flops 207 and 209 on the reception side. .
[0018]
A Request signal to be transferred between different clocks or between a plurality of clock domains is input to the pulse register 202, the pulse width thereof is widened, and input to the flip-flop 204 at the final stage. A clock A is supplied to the pulse register 202 and the flip-flop 204.
[0019]
On the reception side, the Request signal transferred from the transmission side is received via the synchronizer 210 in order to prevent the metastable state from propagating to the internal logic 220. The Request signal with the metastable state removed is sent from the synchronizer 210 to the logic 220. A clock B is supplied to the flip-flops 207 and 209 constituting the synchronizer 210.
[0020]
In the second embodiment, as shown in FIG. 5, a plurality of logics are included, but no logic is inserted between the flip-flop 204 of the final output stage on the transmission side and the synchronizer 210 on the reception side. Also, the output of the flip-flop 204 at the final output stage is not branched to the other logic 221 on the receiving side, but is branched after the synchronizer as shown by the dotted line, and the point-to-multipoint connection is prohibited. A circuit configuration is adopted.
[0021]
By not inserting logic between the final flip-flop 204 and the receiver-side synchronizer 210, a metastable or data loss occurs between the final flip-flop 204 and the synchronizer. In this state, it is possible to avoid transfer to the receiver-side synchronizer.
[0022]
Further, by not branching the output of the flip-flop 204 at the final stage to other logic on the receiving side, it is possible to prevent the occurrence of missing metastable or data in all the logic on the receiving side. Further, since there is no increase in wiring load due to branching, there is an effect that a metastable state is hardly generated in the synchronizer.
[0023]
In addition, since the circuit configuration is simple with no logic insertion or branching, the number of backward search and forward search is not enormous when analyzing the circuit topology in the circuit design of the data transfer device. (Execution time, memory, disk capacity) is reduced, and analysis tools can be used.
[0024]
As described above, according to the second embodiment, since logic is inserted between the flip-flop 204 at the final output stage and the synchronizer 210 on the receiving side, the flip-flop 204 at the final output stage It is possible to avoid occurrence of a metastable or data loss with the synchronizer 210 and transfer to the synchronizer on the receiving side in that state. Further, since the output of the flip-flop 204 at the final output stage is not branched to other logic on the receiving side, occurrence of missing metastable or data can be prevented in all the logic on the receiving side. Furthermore, since there is no increase in wiring load due to branching, it becomes difficult for the synchronizer to generate a metastable state.
[0025]
Furthermore, according to the second embodiment, since the circuit configuration is simple without logic insertion and branching, the clock is supplied through the search for the output terminal connected to the clock input terminal of the flip-flop when designing the circuit. Any location in the circuit is detected from both the detection of the clock source to be detected (backward search) and the operation of detecting the flip-flop through the search of the input terminal connected to the output terminal of the detected clock source (forward search). The circuit topology analysis can be automatically performed using an analysis tool.
[0026]
6 and 7 show examples in which the backward search function of the circuit topology analysis tool is described in RTL, and FIG. 8 shows an example in which the forward search function of the circuit topology analysis tool is described in RTL.
[0027]
FIG. 9 shows the configuration of a data transfer apparatus between different clocks according to the third embodiment of the present invention. This apparatus includes a state machine on the transmission side, and has a configuration that enables handshake access by sending a Request signal to the reception side via this state machine and returning an Acknowledge signal from the reception side.
[0028]
In FIG. 9, the state machine 302 outputs a transmission request in response to a request from the transmission side logic 350. The decoder 304 decodes this transmission request and outputs a Request signal to the pulse register 306 having the same configuration as the pulse register 106 of the first embodiment. The Request signal is transferred to the receiving side with the pulse width expanded by the pulse register 306.
[0029]
On the other hand, a data signal having a bit width, that is, a parallel data signal composed of a plurality of bits is output from the logic 350 to the flip-flop 308 via the bus. Although only one flip-flop 308 is shown in the figure, actually, the number of bits constituting the data signal is provided, and each bit is input to the corresponding flip-flop. The output of the flip-flop 308 is also transferred to the receiving side.
[0030]
Although not shown in the drawing, the clock A is supplied to the state machine 302, the decoder 304, the pulse register 306, and the flip-flop 308. Similarly to the second embodiment, in this embodiment, no logic is inserted between the transmission side and the reception side, and the output on the transmission side is not branched.
[0031]
The Request signal transferred from the transmission side is received by the synchronizer 311 for countermeasure against metastable on the reception side. The output signal of the synchronizer 311 is input to the forward differentiator 313. The forward differentiator 313 generates a timing signal that defines the timing for taking in the data signal from the received Request signal. The timing signal generated by the forward differentiator 313 is output to the subsequent logic 351 through the state machine 314.
[0032]
On the other hand, the data signal having the bit width transferred from the receiving side is input to the metastable countermeasure flip-flop 315, and the output signal of the flip-flop 315 is the enable signal which is the timing signal output by the forward differentiator 313. Is input to the flip-flop 329. The flip-flop 329 takes in the data signal in accordance with this timing signal and sends it to the logic 351.
[0033]
The output signal (Request signal) of the state machine 314 is also output to the logic 352, and the logic 352 generates an Acknowledge signal that is a pulse signal in response thereto. This Acknowledge signal is input to a pulse register 319 having the same configuration as the pulse register 306, where the pulse width is widened.
[0034]
A data signal having a bit width output from the logic is output to the flip-flop 320. The flip-flop 320 uses the Acknowledge signal generated by the logic 352 as an enable signal, and transfers this data signal.
[0035]
A clock B is supplied to the synchronizer 311, the forward differentiator 313, the flip-flops 315 and 329, the pulse register 319, and the flip-flop 320. As in the case of the second embodiment, no logic is inserted after the pulse register 319 and the flip-flop 320, and the output is not branched.
[0036]
The Acknowledge signal transferred from the pulse register 319 is input to the metastable countermeasure synchronizer 323, and the output signal of the synchronizer 323 is a timing signal that defines the timing for fetching the data signal on the data bus. It is input to a forward differentiator 325 generated from the output signal. The timing signal generated by the forward differentiator 325 is sent to the state machine 302. This realizes handshake access for confirming on the transmission side that the transfer data has been received on the reception side.
[0037]
The data signal transferred from the flip-flop 320 is input to the flip-flop 331 that uses the timing signal generated by the forward differentiator 325 as an enable signal via the metastable countermeasure flip-flop 326. The flip-flop 331 takes in the data signal according to this timing signal and sends it to the logic 350.
[0038]
The clock A is supplied to the synchronizer 323, the forward differentiator 325, and the flip-flops 326 and 331.
[0039]
FIG. 10 is a timing chart showing the operation of the third embodiment. As shown in the figure, when the state machine 302 transitions to the request generation state (S1), the decoder 304 decodes the output of the state machine 302 and generates a Request signal. Data having a bit width (received-data) is transferred using the Request signal as an enable signal.
[0040]
The Request signal is received by the synchronizer 311 for countermeasure against metastable, and the forward differentiator 313 differentiates the output of the synchronizer 311 and outputs a timing signal (req-pulse). Data (received-data) having a bit width is taken into a flip-flop 329 using this timing signal as an enable signal. A signal (ack) indicating that the transfer data has been received is received by the metastable countermeasure synchronizer 323, and the synchronizer 323 outputs (ack_sync). The output signal (ack_sync) of the synchronizer 323 is differentiated by the forward differentiator 325, and a pulse signal (ack_pulse) is output.
[0041]
When the state machine 302 receives this pulse signal (ack_pulse), the state machine 302 transitions to the request transmission completion state (S2). The decoder 304 decodes the request transmission completion state (S2), whereby the Request signal is deasserted and the handshake access is realized.
[0042]
FIG. 11 shows an example in which the functions of the transmission-side state machine 302, decoder 304, synchronizer 323, forward differentiator 325, etc. are described in RTL. FIG. 12 shows an example in which the functions of the receiver-side synchronizer 311, forward differentiator 313, pulse generator 319 and the like are described in RTL.
[0043]
As described above, the third embodiment has a simple circuit configuration without logic insertion and branching. Therefore, when designing a circuit of a transfer device having a handshake access function, the clock input terminal of the flip-flop is used. An operation for detecting a clock source that supplies a clock through a search for a connected output terminal (backward search) and an operation for detecting a flip-flop connected to the output terminal of the detected clock source through a search for an input terminal (forward search) The circuit topology analysis for detecting an arbitrary location in the circuit from both of them can be automatically performed using an analysis tool.
[0044]
In the third embodiment, the timing signal that defines the timing for holding the transferred data signal is generated by the differentiating circuit. However, the present invention is not limited to this, and the received enable signal (Request signal) is used. Any other circuit can be used as long as it can generate a pulse signal synchronized with the signal.
[0045]
【The invention's effect】
According to the present invention, the metastable state is prevented from being propagated, and when the frequency of the receiving side clock is lower than the frequency of the transmitting side clock, or the frequency and phase of the receiving side clock are There is provided a data transfer device between different clocks in which data loss does not occur even when the phase is close.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a data transfer device between different clocks according to a first embodiment of the present invention.
FIG. 2 is a diagram showing an example of extending a pulse width for each combination of various clock frequencies.
FIG. 3 is a timing chart for explaining the operation of the transfer apparatus according to the first embodiment.
FIG. 4 is a diagram illustrating an example in which functions of a pulse register and a synchronizer of the transfer apparatus according to the first embodiment are described in hardware description language RTL.
FIG. 5 is a block diagram showing a configuration of a data transfer device between different clocks according to a second embodiment of the present invention.
FIG. 6 is a diagram illustrating an example in which a backward search function of the circuit topology analysis tool of the transfer device according to the second embodiment is described in RTL.
FIG. 7 is a diagram illustrating an example in which a backward search function of a circuit topology analysis tool of the transfer device according to the second embodiment is described in RTL.
FIG. 8 is a diagram illustrating an example in which a forward search function of a circuit topology analysis tool of the transfer apparatus according to the second embodiment is described in RTL.
FIG. 9 is a block diagram showing a configuration of a data transfer device between different clocks according to a third embodiment of the present invention.
FIG. 10 is a timing chart illustrating the operation of the transfer device according to the third embodiment.
FIG. 11 is a diagram illustrating an example in which functions such as a state machine, a decoder, a synchronizer, and a forward differentiator on the transmission side of the transfer apparatus according to the third embodiment are described in RTL.
FIG. 12 is a diagram illustrating an example in which functions of a receiver-side synchronizer, forward differentiator, pulse generator, and the like of the transfer apparatus according to the third embodiment are described in RTL.
[Explanation of symbols]
102, 202, 306, 319 Pulse register, 110, 210, 311, 323 Synchronizer, 313, 325 Forward differentiator, 302, 314 State machine.

Claims (7)

  1. Connected to a first device using a first clock and a second device using a second clock, receiving a pulse signal and the first clock from the first device, and receiving the pulse signal and the first clock from the second device; A data transfer device between different clocks that receives two clocks and transfers the pulse signal from the first device to the second device;
    Disposed downstream of the first device logic, the pulse width of the pulse signal to be transferred, first to extend in accordance with a ratio between the first frequency and the second clock frequency of the clock Pulse width expansion means;
    A first metastable removing unit comprising at least one stage flip-flop arranged in front of the logic of the second device, and removing the metastable of the transferred pulse signal ;
    The frequency obtained by adding 1 to the frequency of the first clock divided by the frequency of the second clock is rounded up to the nearest decimal point.
    When the width of the clock pulse of the first clock is w,
    The first pulse width extending means extends the pulse width of a signal to be transferred to n · w .
  2. First data signal transmission means for transferring a first data signal, which is parallel data composed of a plurality of bits, from the first device to the second device via a first data bus;
    At least one stage of it from the flip-flop, comprising a second metastable removing means for removing metastable said has been transferred first data signal, the first of the first data signal transmission means outputs First data signal receiving means for receiving a data signal via the second metastable removing means;
    First timing signal generating means for generating a timing signal synchronized with the output signal of the first metastable removing means;
    The first data signal receiving means fetches the first data signal from the first data bus when receiving the first timing signal from the first timing signal generating means. Item 4. The data transfer device according to Item 1 .
  3. 3. The data transfer apparatus according to claim 2 , wherein the first timing signal generation unit includes a differentiation circuit.
  4. A reception completion signal generating means for generating a reception completion signal when the first device receives the first data signal;
    Second pulse width expanding means for expanding the pulse width of the reception completion signal in accordance with a ratio between the frequency of the first clock and the frequency of the second clock;
    A third metastable removing unit that comprises at least one flip-flop, and removes a metastable of the reception completion signal returned to the first device via the second pulse width extending unit;
    Second timing signal generating means for generating a second timing signal synchronized with the output signal of the third metastable removing means;
    Second data signal transmission means for transferring a second data signal, which is parallel data composed of a plurality of bits, from the second device to the first device via a second data bus;
    A second data signal output from the second data signal transmitting means, comprising a fourth metastable removing means which comprises a flip-flop of at least one stage and removes the metastable of the transferred second data signal; And a second data signal receiving means for receiving the data via the fourth metastable removing means,
    The second data signal receiving means fetches the second data signal from the second data bus when receiving a second timing signal from the second timing signal generating means. 2. The data transfer device according to 2 or 3 .
  5. Those obtained by rounding up the decimal point of the second clock frequency ÷ the first value obtained by adding 1 to the frequency of the clock and n a,
    When the width of the clock pulse of the second clock is w a ,
    It said second pulse width extension means, the data transfer apparatus according to claim 4, characterized in that to extend the pulse width of the reception completion signal to be transferred to n a · w a.
  6. The signals transferred by the data transfer device between the first and second devices, from claim 1, wherein the directly be transferred without passing through the logic of any one of 5 Data transfer device.
  7. The signals transferred by the data transfer device between the first and second devices, any one of claims 1 to 6, characterized in that it is transferred directly without having to be branched to the logic in the middle The data transfer device according to item.
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JP4841927B2 (en) * 2005-10-20 2011-12-21 富士通株式会社 Asynchronous transmission device and asynchronous transmission method
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JP5159470B2 (en) * 2008-06-27 2013-03-06 富士通テン株式会社 Signal processing apparatus and signal processing method
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