JP5157081B2 - Semiconductor light emitting device and method for manufacturing semiconductor light emitting device - Google Patents

Semiconductor light emitting device and method for manufacturing semiconductor light emitting device Download PDF

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JP5157081B2
JP5157081B2 JP2006118855A JP2006118855A JP5157081B2 JP 5157081 B2 JP5157081 B2 JP 5157081B2 JP 2006118855 A JP2006118855 A JP 2006118855A JP 2006118855 A JP2006118855 A JP 2006118855A JP 5157081 B2 JP5157081 B2 JP 5157081B2
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semiconductor
light emitting
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semiconductor light
emitting device
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量平 広瀬
将嗣 市川
雅彦 佐野
貴彦 坂本
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Nichia Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor light emitting element having an appropriate structure for extracting light to the outside, and to provide its manufacturing method. <P>SOLUTION: The semiconductor light emitting element has a semiconductor light emitting element structure 30 having a laminate structure 10 containing a light emitting layer 3 formed on a substrate 1. The semiconductor light emitting element structure 30 has first side faces 20a on a recessed region 20 having a bottom face 20b, with a layer closer to a substrate surface 1a than the light emitting layer 3 exposed on an upper end surface 4a of the laminate structure 10; and second side faces 7 formed along the outer periphery of the laminate structure 10. The first side faces 20a are formed to be approximately vertical to the light emitting layer 3 or the substrate surface 1a, and to be at least partially opposite to each other. The second side faces 7 connect the upper end surface 4a of the laminate structure 10 with the lower end surface of the structure 10 in contact with the substrate surface 1a, and are formed as slopes inclined inwardly from the upper end surface 4a toward the lower end surface. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

半導体を用いて発光素子構造を形成した半導体発光素子において、光出射面と光反射面を備えた半導体発光素子及びその製造方法に関する。   BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device having a light emitting surface and a light reflecting surface in a semiconductor light emitting device in which a light emitting device structure is formed using a semiconductor, and a manufacturing method thereof.

従来の半導体発光素子は、半導体発光素子によって発光した光を効率的に半導体発光素子外部に取り出すために、光取り出し面と、当該光取り出し面に光を集めるための光反射面を、その構造面に備えた半導体発光素子が提案されている。   A conventional semiconductor light emitting device has a light extraction surface and a light reflection surface for collecting light on the light extraction surface in order to efficiently extract light emitted from the semiconductor light emitting device to the outside. A semiconductor light emitting device provided for the above has been proposed.

特開平10−308532号公報(段落0032〜段落0042、図3)JP-A-10-308532 (paragraphs 0032 to 0042, FIG. 3) 特開平10−341035号公報(段落0012〜段落0017、図2)Japanese Patent Laid-Open No. 10-341035 (paragraphs 0012 to 0017, FIG. 2) 特開2002−026382号公報(段落0014〜段落0015、図1、図2)JP 2002-026382 A (paragraphs 0014 to 0015, FIGS. 1 and 2) 特開平06−244458号公報(段落0006〜段落0008、図1)Japanese Patent Laid-Open No. 06-244458 (paragraphs 0006 to 0008, FIG. 1) 特開平08−102549号公報(段落0016〜段落0021、図1)Japanese Unexamined Patent Publication No. 08-102549 (paragraphs 0016 to 0021, FIG. 1) 特開2004−006662号公報(段落0006〜段落0009、図1)Japanese Patent Laying-Open No. 2004-006662 (paragraphs 0006 to 0009, FIG. 1) Jpn. J. Appl. Phys. Vol.42(2003), L1405-L1407, Part 2, No.12A, 1 December 2003.Jpn. J. Appl. Phys. Vol. 42 (2003), L1405-L1407, Part 2, No. 12A, 1 December 2003. J. of Crystal Growth 182(1997), 17-22.J. of Crystal Growth 182 (1997), 17-22.

しかしながら、特許文献1及び特許文献4から特許文献6に記載されたLEDのように、基板材料と半導体材料が異種の材料であるヘテロ構造体の場合には、一般的には、半導体層と基板に対する加工方法がそれぞれ異なるため、それぞれの主面に対して別々の工程において加工する必要がある。この加工上の制約のため、反射面や光取り出し構造などにも制約が生じることになる。   However, in the case of a heterostructure in which the substrate material and the semiconductor material are different materials, such as the LEDs described in Patent Document 1 and Patent Document 4 to Patent Document 6, generally, the semiconductor layer and the substrate Therefore, it is necessary to process each main surface in a separate process. Due to this processing restriction, there are restrictions on the reflection surface and the light extraction structure.

したがって、特許文献3の図2に示されるような半導体層と基板とを一体的に加工して連続した反射面を形成することは、ヘテロ構造体の場合には困難であった。特に、窒化物半導体を用いる半導体発光素子においては、その基板としてサファイア基板、SiC基板が好適に用いられるが、これらの基板材料はそれぞれ硬度が高く(サファイアのモース硬度は9[修正モース硬度は12]、SiCの修正モース硬度は13)、機械加工が困難であった。さらに、サファイアのように、劈開性に乏しく、化学エッチングも困難である場合には、基板の劈開性及びエッチング性を利用した加工が困難であった。このような基板に所望の反射面、傾斜面を形成するには、相応の加工時間を要し、生産性が低下する傾向があった。また、加工時における半導体への衝撃による損傷の問題もあった。
また、非特許文献1、非特許文献2には、KOHエッチングによるGaNの各結晶面の異方性エッチング、各極性面による選択エッチングについての開示がある。
Therefore, it has been difficult to form a continuous reflecting surface by integrally processing the semiconductor layer and the substrate as shown in FIG. 2 of Patent Document 3 in the case of a heterostructure. In particular, in a semiconductor light emitting device using a nitride semiconductor, a sapphire substrate or a SiC substrate is preferably used as the substrate, but these substrate materials each have a high hardness (the sapphire has a Mohs hardness of 9 [modified Mohs hardness of 12 The modified Mohs hardness of SiC was 13) and machining was difficult. Further, when sapphire has poor cleaving property and chemical etching is difficult, processing using the cleaving property and etching property of the substrate is difficult. In order to form a desired reflecting surface and inclined surface on such a substrate, it takes a corresponding processing time, and the productivity tends to decrease. There is also a problem of damage due to impact on the semiconductor during processing.
Non-Patent Document 1 and Non-Patent Document 2 disclose the anisotropic etching of each crystal plane of GaN by KOH etching and the selective etching by each polar plane.

このため、半導体と基板とを一体的に加工すること、双方を覆う反射面(傾斜面)を形成することは困難であり、半導体、基板のいずれか一方の加工による反射面の形成に留まるのが実情であった。また、特許文献2の図11に記載のLEDのように、p側電極及びn側電極を同一面側として基板を光取り出し方向にする場合には、基板上にメサ形状、すなわち側面の傾斜勾配の角度が90°未満の半導体層を形成するため、基板主面上から比較的容易に加工することができる。他方、特許文献1の図3に記載のLEDのように、逆メサ形状の半導体層を形成するには、加工の制御が難しく、精度よく形状を形成することが困難であった。そして、傾斜面と発光構造とを好適に連携させた構造にしないと、良好な光取り出しが実現できず、従来の加工方法を用いたのでは製造コスト増につながる傾向にあった。   For this reason, it is difficult to process the semiconductor and the substrate integrally, and to form a reflective surface (inclined surface) that covers both, and the formation of the reflective surface is limited to the processing of either the semiconductor or the substrate. Was the actual situation. Further, as in the LED shown in FIG. 11 of Patent Document 2, when the substrate is in the light extraction direction with the p-side electrode and the n-side electrode on the same surface side, a mesa shape on the substrate, that is, a slope of the side surface is formed. Since the semiconductor layer having an angle of less than 90 ° is formed, it can be processed relatively easily from the main surface of the substrate. On the other hand, as in the LED shown in FIG. 3 of Patent Document 1, it is difficult to form a semiconductor layer having a reverse mesa shape because it is difficult to control the processing and form the shape with high accuracy. If the inclined surface and the light emitting structure are not properly linked, good light extraction cannot be realized, and using a conventional processing method tends to increase the manufacturing cost.

本発明は、このような問題を解決するために創案されたものであり、好適な外部光取り出し構造を有する半導体発光素子と、その製造方法を提供することを目的とする。   The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor light emitting device having a suitable external light extraction structure and a method for manufacturing the same.

前記目的を達成するために、一実施形態に係る半導体発光素子は、窒化ガリウム系化合物半導体からなるn型半導体層と、発光層と、p型半導体層とがこの順で積層してなる半導体構造を有する半導体発光素子構造を、サファイアからなりサファイア結晶のC面を基板面とする基板上に設けた半導体発光素子であって、前記半導体構造は、上端面に開口部を有する前記n型半導体層が露出した凹部を有し、上面視で、前記p型半導体層が前記凹部の全周を囲み、前記半導体発光素子構造は、当該半導体発光素子構造の外周の全域に形成された側面を有し、前記側面は、前記半導体構造の上端面と前記基板面に接する前記半導体構造の下端面とを接続し、前記上端面から前記下端面に向かって内側に傾斜する傾斜面として形成され、凹凸形状を有し、当該凹凸形状を構成する凹部又は凸部の少なくとも一方が、前記半導体構造と前記基板との界面である前記窒化ガリウム系化合物半導体の(000−1)面(N極性面)からウェットエッチングされて形成された{1−102}面の多面体によって構成されたことを特徴とする。 In order to achieve the above object, a semiconductor light emitting device according to an embodiment has a semiconductor structure in which an n-type semiconductor layer made of a gallium nitride-based compound semiconductor , a light emitting layer, and a p-type semiconductor layer are stacked in this order. A semiconductor light emitting device having a semiconductor light emitting device structure on a substrate made of sapphire and having a C surface of a sapphire crystal as a substrate surface, wherein the semiconductor structure has an opening at an upper end surface In the top view, the p-type semiconductor layer surrounds the entire periphery of the recess, and the semiconductor light emitting device structure has side surfaces formed over the entire outer periphery of the semiconductor light emitting device structure. The side surface is formed as an inclined surface that connects the upper end surface of the semiconductor structure and the lower end surface of the semiconductor structure in contact with the substrate surface, and is inclined inward from the upper end surface toward the lower end surface. The And, at least one of the concave portions or convex portions constituting the irregularities, wet etched from the semiconductor structure and the substrate surface at which the gallium nitride-based compound semiconductors (000-1) plane (N-polar surface) It is characterized by comprising {1-102} face polyhedrons formed in the above manner.

かかる構成によれば、半導体発光素子構造内を外周に形成された側面方向に向かって進行する光は、傾斜して形成された側面によって観測面方向である上方向に反射され、外部に取り出される有効な光量を増加させる。 According to such a configuration, light traveling toward the semiconductor light emitting device structure on the outer periphery which is formed in the lateral direction is reflected in the upward direction is the observation surface direction by the side surface formed to be inclined, to the outside Increase the effective amount of light extracted.

また、側面がウェットエッチングによって窒化物半導体の結晶面として形成されるため、安定した傾斜角度の傾斜面が形成される。また、側面が窒化物半導体結晶の{1−102}面によって形成されるため、好適な傾斜角度の傾斜面が形成される。また、半導体発光素子構造内を横方向に導波して、側面に到達した光の一部を側面に設けた凹凸形状によって乱反射等で端面から出射・反射し、半導体発光素子構造の外部に取り出されるため、側面によって繰り返し反射され、減衰していた光を外部に取り出すことができ、結果として、外部に取り出される光量を増加させる。また、凹凸形状が、ウェットエッチングにより安定した形状で周期的に配されるため、側面全域からムラなく光を取り出すことができる。 Further, since the side surface is formed as a crystal plane of the nitride semiconductor by wet etching, the inclined surface of the stable tilt angle is formed. Further, since the side surface is formed by a {1-102} plane of the nitride semiconductor crystal, the inclined surface of a suitable tilt angle is formed. Further, the semi-conductor light emitting device structure laterally guided, a part of light reaching the side surfaces and emitted and reflected from the end face in the irregular reflection by the concave-convex shape provided on the side surface, of the semiconductor light emitting device structure since extracted outside is repeatedly reflected by the side surface, it is possible to extract light that has been attenuated outside, as a result, increases the amount of light extracted to the outside. Further, concave convex shape, since the periodically arranged in a stable shape by wet etching, can be taken out without unevenness light from the side surface areas.

また、半導体発光素子構造内を側面方向に向かって進行する光は、半導体発光素子構造の全周に形成された逆傾斜した側面によって観測面方向である上方向に反射され、外部に取り出される有効な光量を増加させる。 In addition, light traveling in the lateral direction in the semiconductor light emitting device structure is reflected upward in the observation surface direction by the reversely inclined side surface formed on the entire circumference of the semiconductor light emitting device structure, and is effectively extracted outside. Increase the amount of light.

一実施形態に係る半導体発光素子の製造方法は、窒化ガリウム系化合物半導体を積層してなる半導体構造を有する半導体発光素子構造を、サファイアからなりサファイア結晶のC面を基板面とする基板上に設けた半導体発光素子の製造方法であって、基板のC面上に窒化ガリウム系化合物半導体からなるn型半導体層と、発光層と、p型半導体層とをこの順で積層した半導体構造を有する半導体発光素子構造を形成する工程と、前記半導体発光素子構造の端部における前記半導体構造を、上面視で凹凸形状を有するように前記基板面に略垂直に除去して、前記基板面を露出する工程と、前記基板面が露出した前記半導体発光素子構造の端部を、当該半導体構造と前記基板との界面である前記窒化ガリウム系化合物半導体の(000−1)面(N極性面)からウェットエッチングして、前記半導体構造の上端面から前記基板面に向かって内側に傾斜する側面を形成する工程と、をこの順で含み、さらに、前記半導体構造の一部を上端面側から除去して前記n型半導体層が露出する凹部を、上面視で、前記p型半導体層が前記凹部の全周を囲むように形成する工程を前記内側に傾斜する側面を形成する工程より後に含むことを特徴とする。 According to one embodiment, a method for manufacturing a semiconductor light emitting device includes providing a semiconductor light emitting device structure having a semiconductor structure formed by stacking gallium nitride compound semiconductors on a substrate made of sapphire and having a C surface of a sapphire crystal as a substrate surface. A method for manufacturing a semiconductor light emitting device, comprising a semiconductor structure in which an n-type semiconductor layer made of a gallium nitride-based compound semiconductor , a light emitting layer, and a p-type semiconductor layer are stacked in this order on a C-plane of a substrate. A step of forming a light emitting element structure, and a step of exposing the substrate surface by removing the semiconductor structure at an end of the semiconductor light emitting element structure substantially perpendicularly to the substrate surface so as to have an uneven shape when viewed from above. When the end portion of the semiconductor light emitting device structure in which the substrate surface is exposed, the semiconductor structure and the gallium nitride compound semiconductor (000-1) plane is the interface with the substrate ( And wet etching the polar face), the comprising the steps of forming a side surface that is inclined inwardly from the upper end surface toward the substrate surface of the semiconductor structure, in this order, further, the upper end surface portion of the semiconductor structure The step of forming the recess where the n-type semiconductor layer is exposed from the side and exposing the n-type semiconductor layer so that the p-type semiconductor layer surrounds the entire periphery of the recess as viewed from above is the step of forming the side surface inclined inward. It is characterized by including later .

かかる手順によれば、半導体構造を基板との界面側からウェットエッチングするため、側面として、窒化ガリウム化合物半導体の{1−102}面の多面体によって構成され、上端面から下端面に向かって内側に傾斜する逆傾斜面が形成される。 According to such a procedure, since the semiconductor structure is wet-etched from the interface side with the substrate, the side surface is constituted by a polyhedron of {1-102} plane of the gallium nitride compound semiconductor, and inward from the upper end surface toward the lower end surface. An inclined reverse inclined surface is formed.

他の態様に係る半導体発光素子の製造方法には、半導体構造を形成する工程において、有機金属化学気相成長法(MOCVD法)によって前記半導体構造を形成する、がある。
これにより、基板との界面が半導体結晶のN極性面となる半導体構造が形成される。
The manufacturing method of a semiconductor light emitting device according to another aspect, in the step of forming a semi-conductor structure, forming the semiconductor structure by metal organic chemical vapor deposition (MOCVD), there is.
As a result, a semiconductor structure is formed in which the interface with the substrate is the N-polar plane of the semiconductor crystal.

本発明の一実施形態によれば、半導体発光素子内で発光した光を側面によって効果的に観測面方向に偏向することができるため、外部への光取り出し効率の良好な半導体発光素子とすることができる。また、半導体発光素子の外周側面に、好適な傾斜角度の傾斜面が安定して形成されるため、外部への光の取り出し効率が良好で、かつチップ毎のばらつきが少ない半導体発光素子とすることができる。 According to one embodiment of the present invention, the light emitted from the semiconductor light emitting device can be effectively deflected in the direction of the observation surface by the side surface, so that the semiconductor light emitting device having good light extraction efficiency to the outside can be obtained. Can do. Further, on the outer peripheral side surface of the semi-conductor light emitting device, the inclined surface of a suitable inclination angle to be formed stably, the light extraction efficiency to the outside is good, and variation in each chip is less semiconductor light emitting element be able to.

また、半導体発光素子の製造方法の一実施形態に係る発明によれば、ウェットエッチングによって逆傾斜面を形成するため、逆傾斜面の形状を容易に、かつ安定して形成することができる In addition, according to the invention according to an embodiment of the method for manufacturing a semiconductor light emitting device, the reversely inclined surface is formed by wet etching, so that the shape of the reversely inclined surface can be formed easily and stably .

以下、発明の実施の形態について適宜図面を参照して説明する。
本実施の形態にかかる半導体発光素子は、窒化物半導体を積層してなるLEDである。
Hereinafter, embodiments of the invention will be described with reference to the drawings as appropriate.
The semiconductor light emitting device according to the present embodiment is an LED formed by laminating nitride semiconductors.

(実施の形態1)
<構成>
図1を参照して、実施の形態1のLED100の構成について説明する。ここで、図1(a)は、実施の形態1のLEDを電極配置面側からみた平面図であり、図1(b)は、図1(a)のA−A線における断面図である。
(Embodiment 1)
<Configuration>
With reference to FIG. 1, the structure of LED100 of Embodiment 1 is demonstrated. Here, FIG. 1A is a plan view of the LED of Embodiment 1 as viewed from the electrode arrangement surface side, and FIG. 1B is a cross-sectional view taken along the line AA of FIG. .

実施の形態1のLED100は、サファイア、SiC等からなる基板1と、その基板面1a上に、窒化物半導体からなるn型半導体層2と発光層3とp型半導体層4とを積層した積層構造10(半導体構造)を有する半導体発光素子構造30と、から構成される。   The LED 100 according to the first embodiment includes a substrate 1 made of sapphire, SiC or the like, and a laminate in which an n-type semiconductor layer 2 made of a nitride semiconductor, a light emitting layer 3 and a p-type semiconductor layer 4 are laminated on the substrate surface 1a. And a semiconductor light emitting device structure 30 having a structure 10 (semiconductor structure).

半導体発光素子構造30は、積層構造10の上端面4a(すなわちp型半導体層4の上端面4a)において凹状に形成された部位(凹部20)を有する。凹部20の底面20bは、n型半導体層2の露出面である。凹部の底面20b上には金属等からなるn側電極5(n側パッド電極)が設けられている。また、凹部20の底面20bを囲む第1の側面20aが発光層3若しくは基板面1aに対して略垂直に若しくは凹部20の底面20b側より開口部側が幅広となるように傾斜して形成されると共に、第1の側面20aは、少なくとも一部が互いに対向するように設けられている。   The semiconductor light emitting device structure 30 has a portion (concave portion 20) formed in a concave shape on the upper end surface 4a of the stacked structure 10 (that is, the upper end surface 4a of the p-type semiconductor layer 4). The bottom surface 20 b of the recess 20 is an exposed surface of the n-type semiconductor layer 2. An n-side electrode 5 (n-side pad electrode) made of metal or the like is provided on the bottom surface 20b of the recess. The first side surface 20a surrounding the bottom surface 20b of the recess 20 is formed so as to be substantially perpendicular to the light emitting layer 3 or the substrate surface 1a or inclined so that the opening side is wider than the bottom surface 20b side of the recess 20. At the same time, the first side surface 20a is provided so that at least a part thereof faces each other.

半導体発光素子構造30若しくは積層構造10(半導体構造)の端部として、例えば、外周を形成する第2の側面7は、基板面から半導体発光素子構造30の積層構造10の上端面4aから基板面1aにかけて内側に傾斜する傾斜面として形成され、基板1上には、いわゆる逆メサ形状の半導体発光素子構造30が構成される。
なお、本明細書において、半導体の順メサ形状あるいは積層方向に幅が狭くなる形状を構成する傾斜を順傾斜、逆メサ形状あるいは積層方向に幅が広くなる形状を構成する傾斜を逆傾斜ともいう。
As an end of the semiconductor light emitting device structure 30 or the stacked structure 10 (semiconductor structure), for example, the second side surface 7 forming the outer periphery is from the substrate surface to the substrate surface from the upper end surface 4a of the stacked structure 10 of the semiconductor light emitting device structure 30. A so-called inverted mesa-shaped semiconductor light emitting device structure 30 is formed on the substrate 1 as an inclined surface inclined inward toward 1a.
Note that in this specification, an inclination that forms a forward mesa shape of a semiconductor or a shape that narrows in the stacking direction is also referred to as a forward tilt, and an inclination that forms an inverted mesa shape or a shape that increases in width in the stacking direction is also referred to as a reverse tilt. .

また、積層構造10の上にはp側電極6が設けられている。p側電極6は、積層構造10の上端面、すなわちp型半導体層4の上端面4aの略全領域に設けられた透光性の導電性材料からなるp側全面電極6aと、p側全面電極6aの一部に設けられた金属等からなるp側パッド電極6bとから構成される。   A p-side electrode 6 is provided on the laminated structure 10. The p-side electrode 6 includes a p-side full-surface electrode 6a made of a translucent conductive material provided on substantially the entire region of the upper end surface of the stacked structure 10, that is, the upper end surface 4a of the p-type semiconductor layer 4, and the p-side full-surface electrode 6a. And a p-side pad electrode 6b made of metal or the like provided in a part of the electrode 6a.

次に、図1を参照して各部の構成について詳細に説明する。
(基板)
基板1は、半導体として窒化物半導体を用いた半導体発光素子用の基板として好適な、サファイア、SiC等からなる厚さ50〜200μm程度の基板を用いることができる。
Next, the configuration of each unit will be described in detail with reference to FIG.
(substrate)
As the substrate 1, a substrate made of sapphire, SiC or the like and having a thickness of about 50 to 200 μm, which is suitable as a substrate for a semiconductor light emitting element using a nitride semiconductor as a semiconductor can be used.

より好適には、半導体発光素子構造30の積層構造10を構成する半導体の屈折率より、基板1の屈折率のほうが小さい基板を用いることができる。基板1の屈折率が半導体の屈折率より小さいと、半導体側から基板1側に向かって進行する光は、両者の界面において、入射角がスネルの法則によって算出される臨界角より大きいときには、この界面で全反射し、半導体内から外に出ることができず、半導体の積層構造10内を横方向に伝播する。本発明における第2の側面7は、このように積層構造10内を横方向に伝播して半導体発光素子構造30の外周側面である第2の側面7で観測面方向である上方向に反射され、有効に外部に取り出すことができる。半導体と基板1との界面で全反射するような低屈折率の基板を用いることで、基板1内を横方向に伝播する光が少ないため、基板1側に逆傾斜面を設けずとも、積層構造10の外周側面に逆傾斜面を設けるだけで効果的に光を外部に取り出すことができる。   More preferably, a substrate having a refractive index smaller than that of the semiconductor constituting the stacked structure 10 of the semiconductor light emitting element structure 30 can be used. When the refractive index of the substrate 1 is smaller than the refractive index of the semiconductor, the light traveling from the semiconductor side toward the substrate 1 side has an incident angle greater than the critical angle calculated by Snell's law at the interface between the two. It is totally reflected at the interface and cannot go out of the semiconductor, but propagates in the semiconductor laminated structure 10 in the lateral direction. The second side surface 7 in the present invention propagates in the lateral direction in the stacked structure 10 in this way and is reflected upward in the observation surface direction by the second side surface 7 which is the outer peripheral side surface of the semiconductor light emitting element structure 30. Can be effectively taken out. Since a low refractive index substrate that totally reflects at the interface between the semiconductor and the substrate 1 is used, the amount of light that propagates in the lateral direction in the substrate 1 is small. Light can be effectively extracted to the outside simply by providing a reverse inclined surface on the outer peripheral side surface of the structure 10.

半導体として窒化物半導体であるGaN系化合物半導体を用いた場合は、GaN系化合物半導体の屈折率は2.5であるから、これより小さな屈折率の基板を用いることが好ましい。例えば、サファイアの屈折率は1.8程度であり、SiCの屈折率は2.6程度であるから、サファイア基板を好適に用いることができる。   When a GaN-based compound semiconductor that is a nitride semiconductor is used as the semiconductor, the refractive index of the GaN-based compound semiconductor is 2.5. Therefore, it is preferable to use a substrate having a smaller refractive index. For example, since the refractive index of sapphire is about 1.8 and the refractive index of SiC is about 2.6, a sapphire substrate can be suitably used.

また、本発明によれば、基板1を加工して斜面を形成せずとも光取り出し効率を高くすることができる。また、より好適には、GaN系化合物半導体との組み合わせにおいて、サファイアからなる基板1を用い、半導体の積層構造10を設ける基板面1aをサファイア結晶のC面とした基板1を用いることができる。このような基板1を用いることにより、基板面1a上には、(000−1)面、すなわちN極性面を下面側とし、(0001)面、すなわちGa極性面を上面側として、c軸方向に成長したGaN系化合物半導体結晶を形成することができる。このような半導体結晶を用いる利点については後記する。   Further, according to the present invention, the light extraction efficiency can be increased without processing the substrate 1 to form a slope. More preferably, in the combination with the GaN-based compound semiconductor, the substrate 1 made of sapphire can be used, and the substrate surface 1a on which the semiconductor laminated structure 10 is provided has the C-plane of sapphire crystal. By using such a substrate 1, on the substrate surface 1a, the (000-1) plane, that is, the N polar plane is the lower surface side, and the (0001) plane, that is, the Ga polar surface is the upper surface side, in the c-axis direction. A GaN-based compound semiconductor crystal grown on the substrate can be formed. The advantage of using such a semiconductor crystal will be described later.

(半導体発光素子構造)
半導体発光素子構造30は、基板1の基板面1a上に設けられ、窒化物半導体からなるn型半導体層2と発光層3とp型半導体層4とを積層した積層構造10と、積層構造10に電流を供給するためのn側電極5及びp側電極6と、から構成される。
半導体発光素子構造30は、積層構造10の上端面4aにおいて凹状に形成された部位(凹部20)を有し、凹部20の底面20bを囲む第1の側面20aと、外周に形成された第2の側面7とを有する。
(Semiconductor light emitting device structure)
The semiconductor light emitting device structure 30 is provided on the substrate surface 1a of the substrate 1, and includes a stacked structure 10 in which an n-type semiconductor layer 2, a light emitting layer 3, and a p-type semiconductor layer 4 made of a nitride semiconductor are stacked, and a stacked structure 10 And an n-side electrode 5 and a p-side electrode 6 for supplying a current.
The semiconductor light emitting element structure 30 has a portion (concave portion 20) formed in a concave shape on the upper end surface 4a of the laminated structure 10, and includes a first side surface 20a surrounding the bottom surface 20b of the concave portion 20 and a second side formed on the outer periphery. Side surface 7.

(積層構造(半導体構造))
基板上に設けられる半導体構造は、半導体発光素子構造となる第1導電型半導体層及び第2導電型半導体層を少なくとも有し、より好適には、その間に発光層を有する。半導体構造の具体的な例として、積層構造10は、基板1側から順に、n型半導体層2、発光層3及びp型半導体層4が積層された構成を有する。例えば窒化物半導体であるGaN系化合物半導体を用い、基板面1aをC面とした基板1上に、異種基板上では核形成層等のバッファ層を含む1〜2μm程度の厚さの下地層を介して、1〜2μm程度の厚さのn型半導体層2、50〜150nm程度の厚さの発光層3、100〜300nm程度の厚さのp型半導体層4を形成する。各層は2層以上で構成されていてもよい。
n型半導体層2は、例えばn型不純物としてSiがドープされたGaN、又はSiがドープされたGaNからなるn型コンタクト層と、n型AlGaNからなるn型クラッド層とをこの順に積層した2層構成としてもよい。
本実施の形態1の半導体発光素子構造30は、発光層3としてダブルへテロ構造の活性層を有する構成としたが、n型半導体層2とp型半導体層4の界面(pn接合面)を発光層とする半導体発光素子構造30としてもよい。また、発光層3として、例えばアンドープGaNからなる障壁層とアンドープInGaNからなる井戸層を交互に積層し、多重井戸構造からなる活性層を形成してもよい。
(Laminated structure (semiconductor structure))
The semiconductor structure provided on the substrate has at least a first conductivity type semiconductor layer and a second conductivity type semiconductor layer to be a semiconductor light emitting element structure, and more preferably has a light emitting layer therebetween. As a specific example of the semiconductor structure, the stacked structure 10 has a configuration in which an n-type semiconductor layer 2, a light emitting layer 3, and a p-type semiconductor layer 4 are stacked in this order from the substrate 1 side. For example, a GaN-based compound semiconductor that is a nitride semiconductor is used, and an underlayer having a thickness of about 1 to 2 μm including a buffer layer such as a nucleation layer is formed on a substrate 1 having a substrate surface 1a having a C-plane and on a different substrate. Then, an n-type semiconductor layer 2 having a thickness of about 1 to 2 μm, a light emitting layer 3 having a thickness of about 50 to 150 nm, and a p-type semiconductor layer 4 having a thickness of about 100 to 300 nm are formed. Each layer may be composed of two or more layers.
The n-type semiconductor layer 2 is formed by stacking, for example, an n-type contact layer made of GaN doped with Si as an n-type impurity or GaN doped with Si, and an n-type cladding layer made of n-type AlGaN in this order. It is good also as a layer structure.
The semiconductor light emitting device structure 30 of the first embodiment is configured to have a double hetero structure active layer as the light emitting layer 3, but the interface (pn junction surface) between the n type semiconductor layer 2 and the p type semiconductor layer 4 is formed. It is good also as the semiconductor light emitting element structure 30 used as a light emitting layer. Further, as the light emitting layer 3, for example, a barrier layer made of undoped GaN and a well layer made of undoped InGaN may be alternately stacked to form an active layer having a multiple well structure.

p型半導体層4は、例えばp型不純物としてMgがドープされたGaNからなるp型半導体層4、又はp型AlGaNからなるp型クラッド層と、MgがドープされたGaNからなるp型コンタクト層とをこの順に積層した2層構成としてもよい。
なお、n型半導体層2、発光層3及びp型半導体層4は、半導体発光素子(LED)として機能する構成であれば、他のどのような構成を採用してもよい。
The p-type semiconductor layer 4 includes, for example, a p-type semiconductor layer 4 made of GaN doped with Mg as a p-type impurity, or a p-type cladding layer made of p-type AlGaN, and a p-type contact layer made of GaN doped with Mg. It is good also as a 2 layer structure which laminated | stacked these in this order.
The n-type semiconductor layer 2, the light-emitting layer 3, and the p-type semiconductor layer 4 may adopt any other configuration as long as it functions as a semiconductor light-emitting element (LED).

(n側電極(負電極)、p側電極(正電極))
n側電極5は、半導体発光素子構造30の積層構造10の上端面4aから凹状に形成された凹部20の底面20b上に形成され、LED100に電流を供給するためのAu線等の電流供給線と接続するための電極パッドを兼ねている。底面20bは、n型半導体層2の露出面である。n側電極5は、底面20b側から順にW、Pt、Auが積層されてなり、700〜2300nm程度の厚さに形成される。なお、n側電極5を構成する材料は、n型半導体層2とオーミック接触することができる材料であれば、他の金属を組み合わせた積層物、合金等、他の材料を用いることもできる。
(N-side electrode (negative electrode), p-side electrode (positive electrode))
The n-side electrode 5 is formed on the bottom surface 20b of the recess 20 formed in a concave shape from the upper end surface 4a of the stacked structure 10 of the semiconductor light emitting element structure 30, and a current supply line such as an Au wire for supplying current to the LED 100. It also serves as an electrode pad for connection. The bottom surface 20 b is an exposed surface of the n-type semiconductor layer 2. The n-side electrode 5 is formed by laminating W, Pt, and Au in order from the bottom surface 20b side, and has a thickness of about 700 to 2300 nm. In addition, as long as the material which comprises the n side electrode 5 is a material which can be in ohmic contact with the n-type semiconductor layer 2, other materials, such as a laminated body and an alloy which combined another metal, can also be used.

p側電極6は、半導体の積層構造10の最上層であるp型半導体層4の上端面4aの上に形成される。p側電極6は、p型半導体層4の上端面4aの略全領域であって発光層3の略全領域に対応する領域に形成される透光性の導電性材料からなるp側全面電極6aから構成される。また、p側全面電極6aの一部の面上にp側パッド電極6bを設けて構成してもよい。p側パッド電極6bは、LED100に電流を供給するためのAu線等の電流供給線と接続するためのパッド電極である。n側電極5と同様に、W、Pt、Auを順に積層して形成することができる。p側パッド電極6bは0.7〜2.3μm程度の厚さに形成される。   The p-side electrode 6 is formed on the upper end surface 4 a of the p-type semiconductor layer 4 that is the uppermost layer of the semiconductor multilayer structure 10. The p-side electrode 6 is a p-side full-surface electrode made of a translucent conductive material that is formed in a substantially entire region of the upper end surface 4 a of the p-type semiconductor layer 4 and corresponding to substantially the entire region of the light-emitting layer 3. 6a. Further, the p-side pad electrode 6b may be provided on a part of the p-side full surface electrode 6a. The p-side pad electrode 6 b is a pad electrode for connecting to a current supply line such as an Au line for supplying current to the LED 100. Similar to the n-side electrode 5, W, Pt, and Au can be stacked in order. The p-side pad electrode 6b is formed to a thickness of about 0.7 to 2.3 μm.

p側全面電極6aは、p側パッド電極6bなどを介して供給される電流を、発光層3が形成された発光領域に対応するp型半導体層4の略全面にムラなく拡散するために設けられ、電流拡散機能を有する。n型半導体層2側では、n側電極5の形成面と基板1との間に位置するn型半導体層2が、電流拡散機能を有する。また、本実施の形態のLED100は、主として電極配置面側から光を取り出す構成であるため、p側全面電極6aは、発光層3から放出される光の波長において透光性を有することが必要である。このような透光性と導電性とを兼ね備えた材料として、ITO(酸化インジウムスズ)、ZnO、p型半導体層4側から順にNi、Auを積層した金属薄膜、Ni、Auの合金の薄膜等を用いることができる。特にITOは透光性及び導電性が優れ、光の外部取り出し効率向上の点で好適である。なお、p側全面電極6aの材料は、p型半導体層4と、オーミック接触できる材料であれば、前記した材料以外の材料を用いることもできる。   The p-side full surface electrode 6a is provided in order to diffuse the current supplied through the p-side pad electrode 6b and the like over the substantially entire surface of the p-type semiconductor layer 4 corresponding to the light emitting region where the light emitting layer 3 is formed. And has a current spreading function. On the n-type semiconductor layer 2 side, the n-type semiconductor layer 2 located between the formation surface of the n-side electrode 5 and the substrate 1 has a current spreading function. Further, since the LED 100 of the present embodiment is configured to extract light mainly from the electrode arrangement surface side, the p-side full surface electrode 6a needs to have translucency at the wavelength of light emitted from the light emitting layer 3. It is. As a material having both translucency and conductivity, ITO (indium tin oxide), ZnO, a metal thin film in which Ni and Au are laminated in order from the p-type semiconductor layer 4 side, a thin film of Ni, Au alloy, etc. Can be used. In particular, ITO is excellent in translucency and conductivity, and is preferable in terms of improving the efficiency of external light extraction. As the material of the p-side full surface electrode 6a, materials other than those described above can be used as long as they are in ohmic contact with the p-type semiconductor layer 4.

(第1の側面、凹部(凹状の形成された部位))
凹部20(凹状に形成された部位)は、半導体発光素子構造30の一部において、積層構造10の上端面4aからn型半導体層2が露出するように空けられた穴であり、その底面20bには、LED100に電流を供給するためのn側電極5が配置される。
(First side surface, concave portion (part where concave shape is formed))
The concave portion 20 (portion formed in a concave shape) is a hole formed in a part of the semiconductor light emitting element structure 30 so that the n-type semiconductor layer 2 is exposed from the upper end surface 4a of the stacked structure 10, and its bottom surface 20b. The n-side electrode 5 for supplying a current to the LED 100 is disposed.

底面20bは、図1の例では、電極配置面方向からみて略矩形状に形成され、底面20bを囲む第1の側面20aは、発光層3若しくは基板面1aに略垂直に、又は順傾斜して形成されている。また、第1の側面20aは、少なくともその一部が互いに対向するように形成されている。実施の形態1における第1の側面20aは、略矩形状の底面20bの全周を囲むように形成されており、略4面から構成される。この4面は、それぞれ2面ずつ互いに対向するように形成されており、略全面が互いに対向する面を有するように形成されている。   In the example of FIG. 1, the bottom surface 20b is formed in a substantially rectangular shape when viewed from the electrode arrangement surface direction, and the first side surface 20a surrounding the bottom surface 20b is inclined substantially perpendicularly or forward to the light emitting layer 3 or the substrate surface 1a. Is formed. The first side surface 20a is formed so that at least a part thereof faces each other. The first side surface 20a in the first embodiment is formed so as to surround the entire circumference of the substantially rectangular bottom surface 20b, and is composed of approximately four surfaces. The four surfaces are formed so that two surfaces face each other, and substantially the entire surface has surfaces facing each other.

なお、底面20bの形状は矩形に限定されるものではなく、円形状、多角形状等とすることもできる。また、第1の側面20aは、全周が互いに対向するように形成されることが好ましいが、図4(a)に示す実施の形態2のように、一部が互いに対向するように形成してもよい。   Note that the shape of the bottom surface 20b is not limited to a rectangle, but may be a circular shape, a polygonal shape, or the like. The first side surface 20a is preferably formed so that the entire circumference faces each other. However, as in the second embodiment shown in FIG. 4A, the first side surface 20a is formed so that parts thereof face each other. May be.

(第2の側面)
第2の側面7は、半導体構造の端部、具体的には半導体発光素子構造30における積層構造10の外周を囲む側面であり、積層構造10の厚さ方向全域に渡り、積層構造10の上端面4aから基板面1aに向かって内側に傾斜する傾斜面として形成される。
(Second aspect)
The second side surface 7 is a side surface that surrounds the end of the semiconductor structure, specifically, the outer periphery of the stacked structure 10 in the semiconductor light emitting element structure 30, and extends over the entire thickness direction of the stacked structure 10. It is formed as an inclined surface inclined inward from the end surface 4a toward the substrate surface 1a.

このような傾斜面は、積層構造10を構成する半導体の特定の結晶面として形成した場合には、傾斜面の傾斜角度の精度が結晶構造によって規制されるため、安定した傾斜面を形成することができる。結晶面はエッチング法によって形成することができる。結晶をエッチングすると、その結晶構造に依存してエッチングレートが異なり、特定の結晶面を形成することができる。とりわけウェットエッチング法により特定の結晶面を高精度に形成することができる。   When such an inclined surface is formed as a specific crystal plane of the semiconductor constituting the stacked structure 10, the accuracy of the inclination angle of the inclined surface is regulated by the crystal structure, so that a stable inclined surface is formed. Can do. The crystal plane can be formed by an etching method. When a crystal is etched, the etching rate varies depending on the crystal structure, and a specific crystal plane can be formed. In particular, a specific crystal plane can be formed with high accuracy by a wet etching method.

エッチングによって形成される傾斜面について具体的に説明する。半導体として六方晶のGaN系化合物半導体を用いた場合は、第2の側面7として、積層構造10を構成する半導体結晶の結晶面として形成することができる。   The inclined surface formed by etching will be specifically described. When a hexagonal GaN-based compound semiconductor is used as the semiconductor, the second side surface 7 can be formed as a crystal plane of a semiconductor crystal constituting the stacked structure 10.

詳細に説明すると、基板1としてサファイアを用い、さらにサファイア結晶のC面を基板面1aとし、有機金属化学気相成長法(MOCVD法)によってGaN系化合物半導体の結晶を成長させると、半導体結晶のN極性面である(000−1)面を基板1との界面とし、c軸方向に成長した半導体結晶を形成することができる。このようにして形成した半導体結晶からなる半導体の積層構造10の側面は、半導体結晶と基板1との界面を露出させ、半導体結晶の(000−1)面からウェットエッチング法(化学エッチング法)によりエッチングすることにより、{1−102}面(R面)、若しくは当該面からc軸で30°回転した面(以下、30°回転R面という)を形成することができる。{1−102}面は(1−102)面と同価な6つの面の集合であり、積層構造10の上端面4aから基板面1aに向かって内側に傾斜した傾斜面となる。十分な時間をかけてエッチングを行うことにより、半導体発光素子構造30の第2の側面7は、六角錐台若しくは、上記30°回転R面を加えた十二角錐台の形状、若しくはその一部形状となる。   More specifically, when sapphire is used as the substrate 1, the C surface of the sapphire crystal is the substrate surface 1a, and a GaN compound semiconductor crystal is grown by metal organic chemical vapor deposition (MOCVD), A semiconductor crystal grown in the c-axis direction can be formed using the (000-1) plane which is an N-polar plane as an interface with the substrate 1. The side surface of the semiconductor laminated structure 10 made of the semiconductor crystal formed in this way exposes the interface between the semiconductor crystal and the substrate 1, and wet etching (chemical etching) from the (000-1) plane of the semiconductor crystal. By etching, a {1-102} plane (R plane) or a plane rotated by 30 ° about the c axis from the plane (hereinafter referred to as a 30 ° rotated R plane) can be formed. The {1-102} plane is a set of six planes equivalent to the (1-102) plane, and is an inclined plane inclined inward from the upper end surface 4a of the laminated structure 10 toward the substrate surface 1a. By etching for a sufficient time, the second side surface 7 of the semiconductor light emitting element structure 30 is shaped like a hexagonal frustum, a dodecagonal frustum including the 30 ° rotation R plane, or a part thereof. It becomes a shape.

第2の側面7は、半導体結晶の{1−102}面又は30°回転R面に属し、傾斜の向きの異なる複数の傾斜面の組み合わせによる多面体として構成することにより、傾斜角度が半導体結晶の結晶構造によって規制されるため、精度の安定した面を形成することができる。基板面での平面視における半導体発光素子構造30の構成辺、例えば図1の矩形状の半導体発光素子構造30の一辺を、この多面体の第2の側面7とすることで、粗面による反射、出射がなされ、光取り出しの向上が期待できる。   The second side surface 7 belongs to the {1-102} plane of the semiconductor crystal or the 30 ° rotation R plane, and is configured as a polyhedron by a combination of a plurality of inclined surfaces having different inclination directions, so that the inclination angle of the semiconductor crystal is Since it is regulated by the crystal structure, a surface with stable accuracy can be formed. By making one side of the semiconductor light emitting device structure 30 of the semiconductor light emitting device structure 30 in plan view on the substrate surface, for example, one side of the rectangular semiconductor light emitting device structure 30 of FIG. The light is emitted and an improvement in light extraction can be expected.

<動作>
次に、図1を参照して、本発明の実施の形態に係るLED100の動作について説明する。
LED100は、p側パッド電極6bを正電極、n側電極5を負電極として直流電源に接続することにより、半導体発光素子構造30(LED構造)に対して順方向に電圧が印加され、発光層3からランダムな方向に光が放出される。発光層3から様々な方向に放出される光は、前記した経路によってLED100の外部に取り出される。
<Operation>
Next, with reference to FIG. 1, operation | movement of LED100 which concerns on embodiment of this invention is demonstrated.
The LED 100 is connected to a DC power source using the p-side pad electrode 6b as a positive electrode and the n-side electrode 5 as a negative electrode, whereby a voltage is applied in the forward direction to the semiconductor light-emitting element structure 30 (LED structure). 3 emits light in a random direction. Light emitted from the light emitting layer 3 in various directions is extracted to the outside of the LED 100 through the above-described path.

ここで、図2を参照して、本発明に係るLED100における、光の外部取り出しについて説明する。図2は、図1に示したLEDにおいて、発光層から放出された光線が外部に取り出される様子を説明するための模式図である。   Here, with reference to FIG. 2, the external extraction of light in the LED 100 according to the present invention will be described. FIG. 2 is a schematic diagram for explaining a state in which light emitted from the light emitting layer is extracted to the outside in the LED shown in FIG.

発光層3から放出され、観測面方向である上方向に進行する光線L1は、透光性のp側全面電極6aを透過して、LED100の外部に取り出される。   The light beam L1 emitted from the light emitting layer 3 and traveling upward, which is the observation surface direction, is transmitted through the translucent p-side full surface electrode 6a and extracted outside the LED 100.

発光層3から放出され、基板面1a側である下方向に進行する光線L2は、半導体発光素子構造30の相対的に高屈折率な積層構造10と基板1等との界面で全反射を繰り返し、光線L3、光線L4、光線L5のように積層構造10内を横方向に伝播する。積層構造10内を伝播し、半導体構造の端部、ここでは半導体発光素子構造30の外周に到達した光線L5は、外周に傾斜して設けられた第2の側面7によって観測面方向に反射され、光線L6としてp側全面電極6aを透過して外部に取り出される。   The light beam L2 emitted from the light emitting layer 3 and traveling downward on the substrate surface 1a side is repeatedly totally reflected at the interface between the semiconductor light emitting element structure 30 having the relatively high refractive index laminated structure 10 and the substrate 1 or the like. , The light beam L3, the light beam L4, and the light beam L5 propagate in the lateral direction in the laminated structure 10. The light beam L5 propagating through the laminated structure 10 and reaching the edge of the semiconductor structure, here the outer periphery of the semiconductor light emitting device structure 30, is reflected in the observation surface direction by the second side surface 7 provided inclined at the outer periphery. , Light L6 is transmitted through the p-side full surface electrode 6a and extracted to the outside.

また、発光層3から横方向に放出され、あるいは積層構造10内を導波して、凹部20に向かって進行する光は、凹部20において発光層3若しくは基板面1aに対して略垂直に形成された第1の側面20aに到達する。第1の側面20aに到達した光の一部は、光線L7のように第1の側面20aから凹部20の空間に出射される。凹部20内を進行する光線L7の一部はn側電極5によって吸収・散乱されるが、n側電極5の干渉を受けない光線L7は、光線L7が出射した第1の側面20aと対向する、他の第1の側面20aから再び積層構造10内に入射する。積層構造10に入射した光線L8は、積層構造10内を外周方向に導波し、外周に設けられた第2の側面7によって観測面方向に反射され、光線L9としてp側全面電極6aを透過して外部に取り出される。   Further, light emitted from the light emitting layer 3 in the lateral direction or guided in the laminated structure 10 and traveling toward the recess 20 is formed in the recess 20 substantially perpendicular to the light emitting layer 3 or the substrate surface 1a. It reaches the first side surface 20a. A part of the light reaching the first side surface 20a is emitted from the first side surface 20a to the space of the recess 20 like a light beam L7. A part of the light beam L7 that travels in the recess 20 is absorbed and scattered by the n-side electrode 5, but the light beam L7 that does not receive interference from the n-side electrode 5 faces the first side surface 20a from which the light beam L7 has been emitted. Then, the light enters the laminated structure 10 again from the other first side face 20a. The light beam L8 incident on the laminated structure 10 is guided in the outer circumferential direction in the laminated structure 10, reflected in the observation surface direction by the second side surface 7 provided on the outer circumference, and transmitted through the p-side full-surface electrode 6a as the light beam L9. And taken out to the outside.

他方、第1の側面20aに到達した光で、凹部20に出射されずに、第1の側面20aによって反射された光は、積層構造10内を外周方向に向かって導波し、前記した光線L2と同様に、第2の側面7に到達すると観測面方向に反射され、外部に取り出される。   On the other hand, the light that has reached the first side surface 20a and is not emitted to the recess 20 but reflected by the first side surface 20a is guided in the outer circumferential direction in the laminated structure 10, and the light beam described above. Similar to L2, when it reaches the second side surface 7, it is reflected in the direction of the observation surface and taken out to the outside.

また、第1の側面20aを発光層3若しくは基板面1aに対して略垂直若しくは順傾斜に形成することによる他の利点について説明する。
第2の側面7は横方向に伝播する光を観測面方向に反射する機能を有する。また、第1の側面20aは、発光層3若しくは基板面1aに対して略垂直若しくは順傾斜に、かつ少なくとも一部が互いに対向するように形成されているため、第1の側面20aから出射した光が、一部は反射されるが、再び対向する第1の側面20aから積層構造10内に入射する光もあり、積層構造10内に再入射した光は、第2の側面7によって観測面方向に反射される。
In addition, another advantage of forming the first side surface 20a substantially perpendicularly or forwardly with respect to the light emitting layer 3 or the substrate surface 1a will be described.
The second side surface 7 has a function of reflecting light propagating in the lateral direction in the observation plane direction. Further, the first side surface 20a is formed so as to be substantially perpendicular or forwardly inclined with respect to the light emitting layer 3 or the substrate surface 1a and so as to be at least partially opposed to each other. Although some of the light is reflected, there is also light that enters the stacked structure 10 again from the first side surface 20a that is opposed again, and the light that is re-entered into the stacked structure 10 is observed by the second side surface 7. Reflected in the direction.

<製造方法>
次に、図3を参照して、本実施の形態に係るLED100の製造方法について説明する。ここで、図3は、実施の形態に係るLEDの製造工程を説明するための模式図(断面図)であり、(a)から(e)は、各製造工程におけるLEDの加工の様子を示す図である。
なお、本実施の形態では、図1等に示すLED100が二次元的に配列されたウエハ状態で各工程が実施され、図3(e)に示す工程においてチップ状に分割されたLED素子が得られる。したがって、図3に示す図面においては、複数のLEDの加工の様子が描かれている。
<Manufacturing method>
Next, with reference to FIG. 3, the manufacturing method of LED100 which concerns on this Embodiment is demonstrated. Here, FIG. 3 is a schematic diagram (cross-sectional view) for explaining the manufacturing process of the LED according to the embodiment, and (a) to (e) show the processing of the LED in each manufacturing process. FIG.
In this embodiment, each process is performed in a wafer state in which the LEDs 100 shown in FIG. 1 and the like are two-dimensionally arranged, and an LED element divided into chips in the process shown in FIG. 3E is obtained. It is done. Therefore, in the drawing shown in FIG. 3, a state of processing a plurality of LEDs is depicted.

(半導体発光素子構造を形成する工程)
半導体発光素子構造30を形成する工程は、基板1上に積層構造10(半導体構造)を形成する工程と、凹部20を形成する工程と、n側電極5を形成する工程と、p側電極6を形成する工程と、を含む。
(Process for forming a semiconductor light emitting device structure)
The step of forming the semiconductor light emitting element structure 30 includes the step of forming the laminated structure 10 (semiconductor structure) on the substrate 1, the step of forming the recess 20, the step of forming the n-side electrode 5, and the p-side electrode 6 Forming a step.

(積層構造(半導体構造)を形成する工程)
図3(a)は、基板1上に半導体構造である半導体の積層構造10を形成した状態を示す図である。図3(a)に示すように、まずサファイア、SiC等からなる基板1上に、MOCVD法等により、例えば、下地層などを介して、SiをドープしたGaNからなるn型半導体層2、InGaNからなる発光層3、MgをドープしたGaNからなるp型半導体層4を順次積層し、窒化物半導体であるGaN系化合物半導体からなる積層構造10を形成する。
(Process for forming a laminated structure (semiconductor structure))
FIG. 3A is a diagram showing a state in which a semiconductor stacked structure 10 which is a semiconductor structure is formed on the substrate 1. As shown in FIG. 3A, first, an n-type semiconductor layer 2 made of GaN doped with Si, for example, via an underlayer or the like on a substrate 1 made of sapphire, SiC, or the like by an MOCVD method or the like. A light emitting layer 3 made of GaN and a p-type semiconductor layer 4 made of GaN doped with Mg are sequentially laminated to form a laminated structure 10 made of a GaN compound semiconductor that is a nitride semiconductor.

半導体構造の内、素子機能を有する半導体構造は、前記した通り、基板上にバッファ層などの下地層を介して、第1導電型半導体層及び第2導電型半導体層と、その間に発光層とを設けた構造などが形成される。なお、下地層は基板と半導体材料の組み合わせによっては省略でき、また各導電型半導体層の積層順序は特に限定されない。各半導体層は、異種基板、好ましくは、サファイア基板上に、MOCVD法により、c軸成長の窒化物半導体を用いて形成する。
n型半導体層2は、n型不純物であるSiをドープしたGaNからなる結晶を成長させて形成する。また、n型半導体層2は、n型コンタクト層とn型クラッド層との2層構造にして形成してもよい。
Among the semiconductor structures, as described above, the semiconductor structure having an element function includes a first conductive type semiconductor layer and a second conductive type semiconductor layer on a substrate via a base layer such as a buffer layer, and a light emitting layer therebetween. A structure provided with is formed. The underlayer can be omitted depending on the combination of the substrate and the semiconductor material, and the stacking order of the conductive semiconductor layers is not particularly limited. Each semiconductor layer is formed on a heterogeneous substrate, preferably a sapphire substrate, using a c-axis grown nitride semiconductor by MOCVD.
The n-type semiconductor layer 2 is formed by growing a crystal made of GaN doped with Si, which is an n-type impurity. The n-type semiconductor layer 2 may be formed in a two-layer structure of an n-type contact layer and an n-type cladding layer.

発光層3は、各導電型半導体層間に設けられ、具体的にはn型半導体層2上に、MOCVD法により、InGaNなどを積層して形成する。なお、本実施の形態では、発光層3としてInGaNからなる活性層を形成し、ダブルへテロ構造の発光層3としたが、n型半導体層2とp型半導体層4との間に異なる材料の活性層を設けずに、n型半導体層2とp型半導体層4とを直接に接合し、このpn接合面(界面)を発光層3とした構造としてもよい。また、発光層3として、障壁層と井戸層とを交互に積層した量子井戸構造、好ましくはInGaN/GaNの多重量子井戸構造よりなる活性層を形成してもよい。   The light emitting layer 3 is provided between the conductive semiconductor layers, and specifically, is formed by laminating InGaN or the like on the n-type semiconductor layer 2 by MOCVD. In the present embodiment, an active layer made of InGaN is formed as the light emitting layer 3 to form the light emitting layer 3 having a double hetero structure, but different materials are used between the n-type semiconductor layer 2 and the p-type semiconductor layer 4. The n-type semiconductor layer 2 and the p-type semiconductor layer 4 may be directly joined without providing the active layer, and the pn junction surface (interface) may be the light emitting layer 3. Further, as the light emitting layer 3, an active layer having a quantum well structure in which barrier layers and well layers are alternately stacked, preferably an InGaN / GaN multiple quantum well structure may be formed.

p型半導体層4は、発光層3上に、MOCVD法により、p型不純物であるMgをドープしたGaNからなる結晶を成長させて形成する。p型半導体層4も、n型半導体層2と同様に、p型クラッド層とp型コンタクト層との2層構造にして形成してもよい。   The p-type semiconductor layer 4 is formed on the light emitting layer 3 by growing a crystal made of GaN doped with Mg, which is a p-type impurity, by MOCVD. Similarly to the n-type semiconductor layer 2, the p-type semiconductor layer 4 may be formed in a two-layer structure of a p-type cladding layer and a p-type contact layer.

(凹部(凹状に形成された部位)を形成する工程)
図3(b)は、積層構造10に凹部20を形成し、その底面20bにn側電極5を形成すると共に、p型半導体層4上にp側全面電極6aを形成し、さらにp側全面電極6aの一部にp側パッド電極6bを形成した状態を示す。すなわち、第1導電型半導体層及び第2導電型半導体層を有する半導体構造、具体的にはそれらを順次積層した積層構造10において、下方に位置する導電型の半導体層(第1導電型半導体層)に電極を設けるために、その一部領域が露出される。
凹部20は、例えば、フォトリソグラフィ法により形成し、具体的には、凹部20を形成する領域を除く領域にフォトレジストを用いてマスクを形成、若しくはマスクをパターニングしてレジストを除去し、塩素系ガスを用いたRIE(反応性イオンエッチング)によって積層構造10を、n型半導体層2が露出するまで異方性エッチングをする。RIEを用いた異方性エッチングにより、マスクからn型半導体層2の露出面まで略垂直な、若しくは順傾斜した第1の側面20aを有する凹部20が形成される。この後、マスクを除去する。
(Process for forming a recess (part formed in a recess))
In FIG. 3B, a recess 20 is formed in the laminated structure 10, an n-side electrode 5 is formed on the bottom surface 20b, a p-side full electrode 6a is formed on the p-type semiconductor layer 4, and the p-side full surface is further formed. A state in which the p-side pad electrode 6b is formed on a part of the electrode 6a is shown. That is, in a semiconductor structure having a first conductive type semiconductor layer and a second conductive type semiconductor layer, specifically, in a stacked structure 10 in which they are sequentially stacked, a conductive type semiconductor layer (first conductive type semiconductor layer located below) ), A partial region thereof is exposed.
The recess 20 is formed by, for example, a photolithography method. Specifically, a mask is formed using a photoresist in a region other than the region where the recess 20 is to be formed, or the resist is removed by patterning the mask. The stacked structure 10 is anisotropically etched until the n-type semiconductor layer 2 is exposed by RIE (reactive ion etching) using a gas. By anisotropic etching using RIE, the concave portion 20 having the first side surface 20a that is substantially perpendicular or forwardly inclined from the mask to the exposed surface of the n-type semiconductor layer 2 is formed. Thereafter, the mask is removed.

(電極を形成する工程)
前記した各導電型半導体層には、電極が形成される。n側電極5は、蒸着法、スパッタリング法などによりn型半導体層2側から順にW、Pt、Auを全面に積層する。そして、この金属層を所望の形状にパターニングすることによってn側電極5が形成される。他の金属や合金を用いることもできる。p側電極6を形成する工程は、p型半導体層4上にp側全面電極6aを形成する工程と、p側全面電極6aの一部にp側パッド電極6bを形成する工程とを含む。p側電極6の形成は、積層構造10の上にスパッタリング法によりITOを成膜し、p側全面電極6aを形成する領域に、フォトレジスト等を用いてマスクを形成し、ITOをエッチングした後に、有機溶剤を用いた洗浄等によってマスクを除去することにより、p側全面電極6aが形成される。次に、蒸着法、スパッタリング法等により、p側全面電極6a側から順にW、Pt、Auを全面に積層する。その後、フォトリソグラフィ法によって、この金属層を所望の形状にパターニングすることでp側パッド電極6bが形成される。電極材料として用いる材料は、Ni/Auを積層して形成してもよいし、他の金属や合金を用いることもできる。なお、p側パッド電極6bとn側電極5とに同じ材料を用いる場合には、p側パッド電極6bとn側電極5とを同じ工程において形成することもできる。
(Process for forming electrodes)
An electrode is formed on each conductive semiconductor layer described above. The n-side electrode 5 is formed by laminating W, Pt, and Au over the entire surface sequentially from the n-type semiconductor layer 2 side by vapor deposition, sputtering, or the like. Then, the n-side electrode 5 is formed by patterning this metal layer into a desired shape. Other metals and alloys can also be used. The step of forming the p-side electrode 6 includes the step of forming the p-side full surface electrode 6a on the p-type semiconductor layer 4 and the step of forming the p-side pad electrode 6b on a part of the p-side full surface electrode 6a. The p-side electrode 6 is formed by depositing ITO on the laminated structure 10 by sputtering, forming a mask using a photoresist or the like in the region where the p-side full surface electrode 6a is to be formed, and etching the ITO. Then, the p-side full surface electrode 6a is formed by removing the mask by washing with an organic solvent or the like. Next, W, Pt, and Au are stacked on the entire surface in this order from the p-side full surface electrode 6a side by vapor deposition, sputtering, or the like. Thereafter, the p-side pad electrode 6b is formed by patterning this metal layer into a desired shape by photolithography. The material used as the electrode material may be formed by stacking Ni / Au, or other metals or alloys can be used. When the same material is used for the p-side pad electrode 6b and the n-side electrode 5, the p-side pad electrode 6b and the n-side electrode 5 can be formed in the same process.

(積層構造(半導体構造)の上端面と異なる結晶面を露出する工程)
前記した通り、ウェットエッチングは、主に基板との界面から進行させるようにする。このため、エッチング時のマスクから露出された露出部の半導体結晶面が、基板との界面における結晶面よりもエッチングレートが小さくなるように、互いに異なる結晶面とする。例えば、半導体発光素子構造30の外周部に相当する部位の積層構造10を、積層構造10の上端面4a及びマスクから露出した端面(外周側面)と異なる結晶面を露出するまでエッチングによって積層構造10を除去する。好ましくは、半導体発光素子構造30の外周部に相当する部位の積層構造10を基板面1a(図1参照)までエッチングし、積層構造10の基板との界面を露出する。このように、積層構造10(半導体構造)において、エッチングレートが互いに異なる結晶面を露出させ、積層構造10の基板面側の結晶面のエッチングレートが大きいことで、基板面側の半導体が上端面側及び端面(側面)の半導体よりも優先的に、好適には選択的にエッチングされて、逆傾斜面が積層構造10の端面(側面)に形成される。
(Step of exposing a crystal plane different from the upper end surface of the laminated structure (semiconductor structure))
As described above, the wet etching proceeds mainly from the interface with the substrate. For this reason, the semiconductor crystal planes of the exposed portions exposed from the mask at the time of etching are made different from each other so that the etching rate is lower than the crystal plane at the interface with the substrate. For example, the laminated structure 10 in a portion corresponding to the outer peripheral portion of the semiconductor light emitting element structure 30 is etched by etching until a crystal plane different from the upper end face 4a of the laminated structure 10 and the end face (outer peripheral side face) exposed from the mask is exposed. Remove. Preferably, the laminated structure 10 corresponding to the outer peripheral portion of the semiconductor light emitting element structure 30 is etched to the substrate surface 1a (see FIG. 1) to expose the interface of the laminated structure 10 with the substrate. As described above, in the stacked structure 10 (semiconductor structure), the crystal planes having different etching rates are exposed, and the etching rate of the crystal surface on the substrate surface side of the stacked structure 10 is large, so that the semiconductor on the substrate surface side is the upper end surface. The reverse inclined surface is formed on the end surface (side surface) of the stacked structure 10 by preferably selectively etching over the side and end surface (side surface) semiconductors.

図3(c)を参照して本工程について説明する。まずエッチングのマスク材料となるSiO等を、例えばスパッタリング法などにより全面に形成し、その上にレジストを設けて、フォトリソグラフィ法によりレジスト膜をパターニングして、次にマスクをパターニングしてレジスト膜を除去し、半導体発光素子構造30の外周部に相当する部位21を除く領域にマスク50を形成する。次に塩素系ガスを用いたRIEにより半導体発光素子構造30の外周部に相当する部位21を、所望の結晶面が露出するまでエッチングする。好ましくは、基板面1aが露出するまでエッチングする。RIEによる異方性エッチングのため、半導体発光素子構造30の外周部に相当する部位21は積層構造10の上端面4aから、マスク50の形状を保って略垂直にエッチングされるため、半導体発光素子構造30の外周に形成された側面は、積層構造10の上端面4a、すなわち基板面1aに略垂直な面である。図3(c)は、半導体発光素子構造30の外周に基板面1aに略垂直な側面が形成された状態を示している。 This process will be described with reference to FIG. First, SiO 2 or the like as an etching mask material is formed on the entire surface by, for example, a sputtering method, a resist is provided thereon, the resist film is patterned by a photolithography method, and then the mask is patterned to form a resist film Then, a mask 50 is formed in a region excluding the portion 21 corresponding to the outer peripheral portion of the semiconductor light emitting element structure 30. Next, the portion 21 corresponding to the outer peripheral portion of the semiconductor light emitting element structure 30 is etched by RIE using a chlorine-based gas until a desired crystal plane is exposed. Preferably, etching is performed until the substrate surface 1a is exposed. Due to the anisotropic etching by RIE, the portion 21 corresponding to the outer peripheral portion of the semiconductor light emitting element structure 30 is etched substantially vertically from the upper end surface 4a of the laminated structure 10 while maintaining the shape of the mask 50. Therefore, the semiconductor light emitting element The side surface formed on the outer periphery of the structure 30 is a top surface 4a of the laminated structure 10, that is, a surface substantially perpendicular to the substrate surface 1a. FIG. 3C shows a state in which a side surface substantially perpendicular to the substrate surface 1 a is formed on the outer periphery of the semiconductor light emitting element structure 30.

(第2の側面(傾斜した側面)を形成する工程)
次に、図3(d)を参照して、第2の側面7を形成する工程について説明する。
前の工程におけるマスク50を除去せずに残したまま、作製中の基板1及び半導体発光素子構造30の全体を、ピロリン酸液、水酸化カリウム水溶液等を用いたエッチング液に浸漬することにより、マスク50の形成されていない半導体発光素子構造30の外周側面がウェットエッチングされ、第2の側面7として積層構造10を構成する半導体結晶の結晶性に応じた結晶面が形成される。
(Step of forming second side surface (inclined side surface))
Next, with reference to FIG.3 (d), the process of forming the 2nd side surface 7 is demonstrated.
By immersing the entire substrate 1 and the semiconductor light emitting device structure 30 under fabrication in an etching solution using a pyrophosphoric acid solution, a potassium hydroxide aqueous solution, or the like while leaving the mask 50 in the previous step without being removed, The outer peripheral side surface of the semiconductor light emitting element structure 30 in which the mask 50 is not formed is wet-etched, and a crystal plane corresponding to the crystallinity of the semiconductor crystal constituting the stacked structure 10 is formed as the second side surface 7.

半導体としてGaN系化合物半導体を用い、基板1と接する界面側を(000−1)面、すなわちN極性面として形成した半導体の積層構造10を用いた場合には、ウェットエッチングによって積層構造10のN極性面側からエッチングが進行するため、半導体発光素子構造30の積層構造10の上端面4aよりも、この上端面4aと異なる結晶面として露出させた基板1との界面側の結晶面(下端面)の方が、エッチングレートが大きくなる。したがって、エッチングが進行するほど、積層構造10の下端面の方が内側に削られ、積層構造10の側面には逆傾斜面が形成される。   In the case of using a semiconductor laminated structure 10 in which a GaN-based compound semiconductor is used as a semiconductor and the interface side in contact with the substrate 1 is formed as a (000-1) plane, that is, an N-polar plane, N of the laminated structure 10 is obtained by wet etching. Since etching proceeds from the polar face side, the crystal face (lower end face) on the interface side with the substrate 1 exposed as a different crystal face from the upper end face 4a rather than the upper end face 4a of the stacked structure 10 of the semiconductor light emitting element structure 30. ) Has a higher etching rate. Therefore, as the etching progresses, the lower end surface of the laminated structure 10 is scraped inward, and an inversely inclined surface is formed on the side surface of the laminated structure 10.

さらに、エッチングを進めることにより、エッチング面は{1−102}面、30°回転R面を形成するようになる。ここでエッチングを終了することにより、{1−102}面からなる第2の側面7が形成される。エッチングの後、フッ酸を用いたエッチング等によりマスク50を除去することで、図3(d)に示すように、半導体発光素子構造30が基板1上に形成される。   Further, by proceeding with the etching, the etched surface forms a {1-102} plane and a 30 ° rotation R plane. Here, the second side surface 7 composed of the {1-102} plane is formed by finishing the etching. After etching, the mask 50 is removed by etching using hydrofluoric acid or the like, whereby the semiconductor light emitting element structure 30 is formed on the substrate 1 as shown in FIG.

(LEDチップに分割する工程)
最後に、図3(e)に示すように、必要に応じて基板1の裏面を研磨して薄肉化し、ダイシング、スクライブなどによって切断し、個々のLED100をチップ状に分割する。
また、前記した第2の側面を形成する工程により、図3(d)に示すように、隣接する半導体発光素子構造30間において、積層構造10(半導体構造)の上端面側と基板面側とで距離が異なり、基板面側において隣接する端部の幅が広くなっている。このため、各半導体発光素子構造30の間隔を狭くして、ウエハ当たりに形成する半導体発光素子構造30の数を多くしても、基板面側の半導体発光素子構造30の間隔を広くすることができ、基板分割における切り代を確保することができる。また、各半導体発光素子構造30間で上端面側の幅が狭く、基板面側で広くなるため、基板の切り代幅を従来と同じにしても、発光領域を大きくした半導体発光素子構造30を作製でき、ウエハ当たりの半導体発光素子構造30の数を多くすることができる。また、図8に示す比較例のように、半導体発光素子構造の外周部をn型半導体層302の露出部とする場合に比して、実施の形態1のように発光層3の端面を半導体発光素子構造30の外周側面である第2の側面7に設けた構造の方が、発光領域を広くでき、積層構造10(半導体構造)の端面の逆傾斜面による光反射効果を高めることができる。このとき、積層構造10の上端面における端部が、素子毎に分割した後の基板の端部に最も近く配置される。すなわち、発光層3の端部よりも、上端面の端部の方が素子の外側に突出した構造であるため、逆傾斜面における好適な光反射、指向性の制御を実現することができる。
(Step of dividing into LED chips)
Finally, as shown in FIG. 3E, the back surface of the substrate 1 is polished and thinned as necessary, and cut by dicing, scribing, etc., and the individual LEDs 100 are divided into chips.
Further, by the step of forming the second side surface, as shown in FIG. 3D, between the adjacent semiconductor light emitting element structures 30, the upper end surface side and the substrate surface side of the stacked structure 10 (semiconductor structure) And the distance is different, and the width of the adjacent end portion on the substrate surface side is wide. Therefore, even if the interval between the semiconductor light emitting element structures 30 is reduced and the number of semiconductor light emitting element structures 30 formed per wafer is increased, the interval between the semiconductor light emitting element structures 30 on the substrate surface side can be increased. It is possible to secure a cutting allowance in dividing the substrate. In addition, since the width on the upper end surface side is narrow and wide on the substrate surface side between the semiconductor light emitting element structures 30, the semiconductor light emitting element structure 30 having a large light emitting region can be obtained even if the cutting margin width of the substrate is the same as the conventional one. The number of semiconductor light emitting device structures 30 per wafer can be increased. Further, as in the comparative example shown in FIG. 8, the end face of the light emitting layer 3 is made of a semiconductor as in the first embodiment as compared with the case where the outer peripheral portion of the semiconductor light emitting element structure is the exposed portion of the n-type semiconductor layer 302. The structure provided on the second side surface 7 which is the outer peripheral side surface of the light emitting element structure 30 can widen the light emitting region, and can enhance the light reflection effect by the reverse inclined surface of the end surface of the stacked structure 10 (semiconductor structure). . At this time, the end portion on the upper end surface of the laminated structure 10 is disposed closest to the end portion of the substrate after being divided for each element. That is, since the end portion of the upper end surface protrudes outside the element rather than the end portion of the light emitting layer 3, it is possible to realize suitable light reflection and directivity control on the reversely inclined surface.

以上、説明した製造方法によって、図1に示した実施の形態1のLED100を製造することができる。なお、以上は、一実施形態に係る製造工程を順に説明するものであり、他の実施形態として、半導体構造の上端面と異なる結晶面を露出させる工程・第2の側面を形成する工程と、p側電極を形成する工程・n側電極を形成する工程・凹部を形成する工程とは、順序が入れ替わってもよく、例えば、半導体構造の上端面と異なる結晶面を露出させる工程・第2の側面を形成する工程を実施した後に、凹部を形成する工程・p側電極を形成する工程・n側電極を形成る工程を実施するようにしてもよい。 As described above, the LED 100 of Embodiment 1 shown in FIG. 1 can be manufactured by the manufacturing method described above. Note that the above describes the manufacturing process according to one embodiment in order, and as another embodiment, a process of exposing a crystal plane different from the upper end face of the semiconductor structure, a process of forming a second side surface, The order of the step of forming the p-side electrode, the step of forming the n-side electrode, and the step of forming the recesses may be reversed. For example, a step of exposing a crystal plane different from the upper end surface of the semiconductor structure after the step of forming a side surface, it may be carried a step that form a step · n-side electrodes forming step · p-side electrode forming the recess.

(実施の形態2)
<構成>
次に、図4を参照して、実施の形態2のLED100の構成について説明する。ここで、図4(a)は、実施の形態2のLEDを電極配置面側からみた平面図であり、図4(b)は、図4(a)のB−B線における断面図である。実施の形態2のLED100は、図1に示した実施の形態1とは、主に凹部20を形成した位置及び凹部20の側面20aの形状が異なる以外は、同様の構成であるので、同じ構成の箇所については説明を省略する。
(Embodiment 2)
<Configuration>
Next, with reference to FIG. 4, the structure of LED100 of Embodiment 2 is demonstrated. Here, FIG. 4A is a plan view of the LED according to the second embodiment as viewed from the electrode arrangement surface side, and FIG. 4B is a cross-sectional view taken along the line BB in FIG. . The LED 100 according to the second embodiment has the same configuration as the first embodiment shown in FIG. 1 except that the position where the recess 20 is formed and the shape of the side surface 20a of the recess 20 are different. The description of this part is omitted.

実施の形態2のLED100においては、実施の形態1に比して、凹部20の内壁面の一部が半導体発光素子構造30の外側に開口されており、具体的にはn側電極5を配置するための凹部20が、電極配置面側からみて略正方形の半導体発光素子構造30の一辺の一部を削るように形成され、外周方向に向かって開口している。そのため、凹部20の略正方形の底面20bを囲む第1の側面20aは、略3面から構成され、このうち外周方向を向く1面は対向面を有さないが、他の2面は互いに対向する。
実施の形態1に係るLEDと同様に、実施の形態2に係るLED100は、第2の側面7に到達した光の経路は、実施の形態1のLEDと同様であるので説明を省略する。
In the LED 100 of the second embodiment, as compared with the first embodiment, a part of the inner wall surface of the recess 20 is opened to the outside of the semiconductor light emitting element structure 30, and specifically, the n-side electrode 5 is disposed. A recess 20 is formed so as to scrape a part of one side of the substantially square semiconductor light emitting element structure 30 when viewed from the electrode arrangement surface side, and is open toward the outer peripheral direction. Therefore, the first side surface 20a surrounding the substantially square bottom surface 20b of the recess 20 is composed of approximately three surfaces, of which one surface facing the outer peripheral direction does not have a facing surface, but the other two surfaces are facing each other. To do.
Similar to the LED according to the first embodiment, the LED 100 according to the second embodiment has the same light path reaching the second side surface 7 as that of the LED according to the first embodiment, and a description thereof will be omitted.

対向面を有さない第1の側面20aから出射された光は、観測面方向に向かうことができず、指向性の低下につながる。一方、第2の側面20aの一部に対向面を有さない部位を設けることで、凹部20の底面20bに配置されるn側電極5とリードフレームを接続するワイヤは、観測面方向である半導体発光素子構造30の発光領域の上面を跨ぐことなく、配線することができる。実施の形態1のように、凹部20の底面20bが積層構造10(半導体構造)に囲まれた構成の場合は、n側電極5とリードフレームを接続するワイヤはLED100の観測面上を跨ぐことになり、観測面方向に進行する光の一部がワイヤによって吸収又は散乱され、光出力を下げる原因ともなる。   The light emitted from the first side surface 20a that does not have the facing surface cannot travel in the observation surface direction, leading to a decrease in directivity. On the other hand, the wire that connects the n-side electrode 5 disposed on the bottom surface 20b of the recess 20 and the lead frame is in the observation plane direction by providing a portion that does not have a facing surface in a part of the second side surface 20a. Wiring can be performed without straddling the upper surface of the light emitting region of the semiconductor light emitting element structure 30. When the bottom surface 20b of the recess 20 is surrounded by the laminated structure 10 (semiconductor structure) as in the first embodiment, the wire connecting the n-side electrode 5 and the lead frame straddles the observation surface of the LED 100. Therefore, a part of the light traveling in the direction of the observation surface is absorbed or scattered by the wire, which causes a decrease in light output.

したがって、凹部20をどのように設けるかは、前記長所・短所を勘案し、第1の側面20aにおいて互いに対向する面の面積を多くするように設計することができる。   Accordingly, how to provide the recess 20 can be designed to increase the area of the surfaces facing each other on the first side surface 20a in consideration of the advantages and disadvantages.

<製造方法>
実施の形態2のLED100は、図3(b)に示す凹部20を形成する位置及びn側電極5及びp側電極6を形成する位置が異なる他は、実施の形態1と同様の製造工程によって製造することができる。
<Manufacturing method>
The LED 100 of the second embodiment is manufactured by the same manufacturing process as that of the first embodiment except that the position for forming the recess 20 shown in FIG. 3B and the position for forming the n-side electrode 5 and the p-side electrode 6 are different. Can be manufactured.

(実施の形態3)
<構成>
次に、図5及び図6を参照して、実施の形態3のLED100の構造について説明する。ここで、図5(a)は、実施の形態3のLEDを電極配置面側からみた平面図であり、図5(b)は、図5(a)のB−B線における断面図である。また、図6は実施の形態3のLEDの第2の側面の形状を説明するための斜視図である。
(Embodiment 3)
<Configuration>
Next, the structure of the LED 100 of Embodiment 3 will be described with reference to FIGS. Here, FIG. 5A is a plan view of the LED of Embodiment 3 as viewed from the electrode arrangement surface side, and FIG. 5B is a cross-sectional view taken along the line BB of FIG. . FIG. 6 is a perspective view for explaining the shape of the second side surface of the LED of the third embodiment.

実施の形態3のLED100は、第2の側面7に前記した結晶面の多面体による凹凸形状7a(凸部7bと凹部7cとからなる形状)を設けたことを特徴とする。第2の側面7に凹凸形状7aを設けた以外の構成は、図4に示した実施の形態2のLED100と同じ構成であるから、同じ構成の箇所については説明を省略する。   The LED 100 according to the third embodiment is characterized in that the second side surface 7 is provided with a concavo-convex shape 7a (a shape composed of a convex portion 7b and a concave portion 7c) formed of a polyhedron having a crystal plane as described above. Since the configuration other than providing the concave-convex shape 7a on the second side surface 7 is the same as that of the LED 100 of the second embodiment shown in FIG.

実施の形態3の第2の側面7は、図6に示すように、積層構造10の厚さ方向に平行に、かつ周期的に凸部7b及び凹部7cからなる凹凸形状7aが形成されている。なお、この凹凸形状7aをならした平均面は、実施の形態2における第2の側面7と同様に、積層構造10の上端面4aから下端面(基板面1a)に向かって内側に傾斜した逆傾斜面である。   As shown in FIG. 6, the second side surface 7 of the third embodiment is formed with a concavo-convex shape 7 a including a convex portion 7 b and a concave portion 7 c periodically and parallel to the thickness direction of the laminated structure 10. . In addition, the average surface which leveled this uneven | corrugated shape 7a was reversely inclined inward toward the lower end surface (substrate surface 1a) from the upper end surface 4a of the laminated structure 10 similarly to the 2nd side surface 7 in Embodiment 2. It is an inclined surface.

このような凹凸形状を有する傾斜面は、ウェットエッチング時のマスクの端部形状を起点として多面体のエッチング面として形成することができる。具体的には、基板面の平面視で、マスクの一辺を直線状から、波状、ジグザグ状などの端部形状として、基板面露出時の積層構造10の端部に凹凸形状を設ける。端部の凹凸形状は、エッチング法により半導体結晶を加工することにより形成することができ、ウェットエッチング法によって結晶面の多面体に加工することができる。実施の形態1において説明したものと同様に、半導体として六方晶の結晶構造を有する窒化物半導体であるGaN系化合物半導体を用いた場合は、第2の側面7を半導体結晶の結晶面として形成することができる。基板面を露出させるエッチングの際に、マスクの端部形状を凹凸状として、積層構造10の、例えば、その半導体発光素子構造30の平面視の構造辺の一辺に、凹凸形状の端部を形成する。次に、ウェットエッチング法によるエッチングで、図6に示すような{1−102}面の多面体からなる凹凸形状が現れる。一方で、半導体発光素子構造30の端部、例えば、その半導体発光素子構造30の平面視の構成辺の一辺の端部を、略均一な1つの面で構成させるには、基板面を露出させる際に、積層構造10の端部を略平坦とすること、すなわち、基板面を露出させる際に用いるマスクの端部形状を直線状とすること、である。この凹凸形状は結晶構造によって規制される面であるから、精度の安定した面を形成することができる。   Such an inclined surface having a concavo-convex shape can be formed as an etching surface of a polyhedron starting from the shape of the edge of the mask during wet etching. Specifically, in a plan view of the substrate surface, one side of the mask is changed from a straight shape to an end shape such as a wave shape or a zigzag shape, and an uneven shape is provided at the end portion of the laminated structure 10 when the substrate surface is exposed. The uneven shape at the end can be formed by processing a semiconductor crystal by an etching method, and can be processed into a polyhedron of a crystal plane by a wet etching method. In the same manner as described in the first embodiment, when a GaN-based compound semiconductor that is a nitride semiconductor having a hexagonal crystal structure is used as the semiconductor, the second side surface 7 is formed as a crystal plane of the semiconductor crystal. be able to. When etching to expose the substrate surface, the edge shape of the mask is made uneven, and an edge having an uneven shape is formed, for example, on one side of the structure side of the semiconductor light emitting device structure 30 in plan view of the laminated structure 10 To do. Next, an uneven shape formed of a polyhedron having a {1-102} plane as shown in FIG. 6 appears by etching using a wet etching method. On the other hand, in order to configure an end portion of the semiconductor light emitting element structure 30, for example, an end portion of one side of the semiconductor light emitting element structure 30 in a plan view, with a substantially uniform surface, the substrate surface is exposed. At this time, the end portion of the laminated structure 10 is made substantially flat, that is, the end portion shape of the mask used when exposing the substrate surface is made linear. Since this uneven shape is a surface regulated by the crystal structure, a surface with stable accuracy can be formed.

第2の側面7における多面体の凹凸形状7aの凸部7b及び凹部7cの周期としては、第2の側面7における光の外部取り出しの効率から0.1〜0.3μm程度とすることが好ましい。   The period of the convex portions 7b and the concave portions 7c of the polyhedral concavo-convex shape 7a on the second side surface 7 is preferably about 0.1 to 0.3 μm from the efficiency of external extraction of light on the second side surface 7.

図7は、実施の形態3に係るLEDを用いたLED装置の構成を示す断面図である。LED100は、基板1を下側として、外部から電流を供給するための正電極側のリードフレーム111のカップ状に形成された凹部111a内に接着剤115によって固定されている。凹部111aの内部の側面は上方に向かって外側に傾斜した傾斜面である。p側パッド電極6bは、正電極側のリードフレーム111の一部とAu線等からなるワイヤ113で接続されている。n側電極5は負電極側のリードフレーム112とAu線等からなるワイヤ114で接続されている。全体は樹脂116で封止され、砲弾型の外観を有するLED装置110を構成している。   FIG. 7 is a cross-sectional view illustrating a configuration of an LED device using the LED according to the third embodiment. The LED 100 is fixed by an adhesive 115 in a recess 111a formed in a cup shape of a lead frame 111 on the positive electrode side for supplying current from the outside with the substrate 1 as a lower side. The inner side surface of the recess 111a is an inclined surface that is inclined outwardly upward. The p-side pad electrode 6b is connected to a part of the lead frame 111 on the positive electrode side by a wire 113 made of Au wire or the like. The n-side electrode 5 is connected to the lead frame 112 on the negative electrode side by a wire 114 made of Au wire or the like. The whole is sealed with a resin 116 to constitute an LED device 110 having a bullet-shaped appearance.

<動作>
次に、図5を参照して、実施の形態3に係るLED100の動作について説明する。第2の側面7に凹凸形状7aを有さない実施の形態1及び実施の形態2のような構成について考える。第2の側面7に到達した光は、第2の側面7によって観測面方向である上方向に反射される。実施の形態3では、第2の側面7に凹凸形状7aを設けることにより、半導体発光素子構造30の積層構造10内を横方向に伝播して第2の側面7に到達した光の一部を、凹凸形状7aによって散乱し、外部に取り出すように構成した。図5(b)を参照して、実施の形態3のLED100における光の外部取り出しの様子を説明する。発光層3から観測面方向である上方向に放出された光線L1は、透光性のp側全面電極6aを透過して外部に取り出される。積層構造10内を横方向に伝播する光線L2は、積層構造10の界面で全反射を繰り返し光線L3のように第2の側面7に到達する。光線L3は、第2の側面7によって、その一部が上方向に反射される。第2の側面7で上方向に反射された光線L4は、半導体発光素子構造30の積層構造10の上端面4aに対して、全反射の臨界角以下の角度で入射すると、積層構造10から外部に取り出される。しかし、臨界角以上の角度で入射すると、積層構造10の上端面4aによって全反射され、外部に取り出されることなく、再び積層構造10内を伝播する。
<Operation>
Next, the operation of the LED 100 according to Embodiment 3 will be described with reference to FIG. Consider a configuration as in the first and second embodiments in which the second side surface 7 does not have the uneven shape 7a. The light that reaches the second side surface 7 is reflected by the second side surface 7 in the upward direction, which is the observation surface direction. In the third embodiment, by providing the concave and convex shape 7 a on the second side surface 7, a part of the light that has propagated in the lateral direction in the stacked structure 10 of the semiconductor light emitting element structure 30 and reached the second side surface 7 is obtained. The light is scattered by the uneven shape 7a and taken out to the outside. With reference to FIG.5 (b), the mode of the external extraction of the light in LED100 of Embodiment 3 is demonstrated. The light beam L1 emitted from the light emitting layer 3 in the upward direction, which is the observation surface direction, is transmitted through the translucent p-side full-surface electrode 6a and extracted outside. The light beam L2 propagating in the lateral direction in the laminated structure 10 repeats total reflection at the interface of the laminated structure 10 and reaches the second side surface 7 like the light beam L3. A part of the light beam L3 is reflected upward by the second side surface 7. When the light beam L4 reflected upward by the second side surface 7 is incident on the upper end surface 4a of the stacked structure 10 of the semiconductor light emitting device structure 30 at an angle equal to or less than the critical angle of total reflection, the light beam L4 is externally transmitted from the stacked structure 10 to the outside. To be taken out. However, when incident at an angle greater than the critical angle, the light is totally reflected by the upper end surface 4a of the laminated structure 10 and propagates through the laminated structure 10 again without being taken out.

他方、第2の側面7に到達した光線L3の一部は、第2の側面7に設けられた凹凸形状7aによって散乱され、光線L5のように一部は第2の側面7から外部に取り出され、積層構造10の内部へ反射される一部の光も、散乱により反射角が変化する。特に半導体発光素子構造30の構成辺に沿う方向、すなわち図5(b)の紙面に垂直な方向に伝播する光において、このような第2の側面7での散乱による光取り出し、内部への反射が好適に機能する。第2の側面7から、光線の一部を外部に取り出すことにより、LED100全体としてみれば、外部への取り出し光量を増加することができる。   On the other hand, a part of the light beam L3 reaching the second side surface 7 is scattered by the uneven shape 7a provided on the second side surface 7, and a part of the light beam L5 is taken out from the second side surface 7 like the light beam L5. In addition, the reflection angle of some of the light reflected into the laminated structure 10 changes due to scattering. In particular, in the light propagating in the direction along the constituent side of the semiconductor light emitting element structure 30, that is, in the direction perpendicular to the paper surface of FIG. 5B, the light is extracted by the scattering on the second side surface 7 and reflected to the inside. Works well. By extracting a part of the light beam from the second side surface 7 to the outside, the amount of light extracted to the outside can be increased when viewed as the LED 100 as a whole.

図7を参照して、実施の形態3に係るLEDを用いたLED装置による光の外部への取り出しについて説明する。実施の形態3に係るLED100は、第2の側面7からも光が出射されるため、この第2の側面7から出射された光を観測面方向に向けるためのカップ状に形成された凹部111aをリードフレーム111に設けた。凹部111aの内部の側面は上方に向かって外側に傾斜した傾斜面であり、LED100の第2の側面7から出射される光を観測面方向である上方向に反射する。このように構成することで、LED装置110として、観測面方向に有効に取り出される光量を増加することができる。   With reference to FIG. 7, extraction of light to the outside by the LED device using the LED according to the third embodiment will be described. Since the LED 100 according to the third embodiment emits light from the second side surface 7 as well, a concave portion 111a formed in a cup shape for directing the light emitted from the second side surface 7 in the observation surface direction. Was provided on the lead frame 111. The inner side surface of the recess 111a is an inclined surface that is inclined outward toward the upper side, and reflects light emitted from the second side surface 7 of the LED 100 in the upward direction, which is the observation surface direction. With this configuration, the LED device 110 can increase the amount of light that is effectively extracted in the observation plane direction.

(実施例1)
直径2インチのC面サファイア基板上に、GaNを用いたバッファ層(下地層)を設けて、その上に、GaN系化合物半導体を用いた発光層を含む積層構造を形成する。
次に、積層構造の表面からn型半導体層が露出する深さで、フォトリソグラフィ法により、図1に示す凹部を形成する。
積層構造の表面にはITOによるp側全面電極を形成し、さらに蒸着法及びフォトリソグラフィ法を用いて、p側全面電極の一部に金属からなるp側パッド電極を、凹部の底面に金属からなるn側電極を形成する。
続いて、フォトリソグラフィ法により積層構造の上端面及び電極を覆うマスクを、SiOを用いて形成し、各半導体発光素子構造の構成単位の外周部を、基板表面が露出する深さまで、塩素系ガスを用いたRIEによる異方性エッチングによってエッチングし、基板上で互いに分離された半導体発光素子構造を形成する。このとき、それぞれのエッチング端面は、基板面(発光層)にほぼ垂直な面となる。
半導体発光素子構造の表面のSiOマスクを用いて、エッチング液である約200℃のピロリン酸溶液に浸漬し、半導体発光素子構造を囲む外周側面に、逆傾斜したエッチング面を形成する。
SiOマスクを、フッ酸を用いて除去し、基板をダイシングによって割断して、LEDチップを得る。
Example 1
A buffer layer (underlayer) using GaN is provided on a C-plane sapphire substrate having a diameter of 2 inches, and a laminated structure including a light emitting layer using a GaN-based compound semiconductor is formed thereon.
Next, the recess shown in FIG. 1 is formed by photolithography at a depth at which the n-type semiconductor layer is exposed from the surface of the stacked structure.
A p-side full surface electrode made of ITO is formed on the surface of the laminated structure, and a p-side pad electrode made of metal is formed on a part of the p-side full surface electrode and a bottom surface of the recess is made of metal by vapor deposition and photolithography. An n-side electrode is formed.
Subsequently, a mask covering the upper end surface and the electrode of the stacked structure is formed using SiO 2 by photolithography, and the outer peripheral portion of the constituent unit of each semiconductor light emitting element structure is chlorinated to a depth at which the substrate surface is exposed. Etching is performed by anisotropic etching by RIE using gas to form semiconductor light emitting device structures separated from each other on the substrate. At this time, each etching end surface is a surface substantially perpendicular to the substrate surface (light emitting layer).
An SiO 2 mask on the surface of the semiconductor light emitting device structure is used to immerse in an approximately 200 ° C. pyrophosphoric acid solution, which is an etching solution, to form a reverse inclined etching surface on the outer peripheral side surface surrounding the semiconductor light emitting device structure.
The SiO 2 mask is removed using hydrofluoric acid, and the substrate is cleaved by dicing to obtain an LED chip.

(実施例2)
ウェットエッチング法のエッチング液として、実施例1におけるピロリン酸溶液の代わりに水酸化カリウム水溶液を用い、半導体発光素子構造の端部であるその外周に逆傾斜面を形成し、LEDチップを作製する。他の条件は、実施例1と同じとする。
(Example 2)
As an etchant for the wet etching method, an aqueous potassium hydroxide solution is used instead of the pyrophosphoric acid solution in Example 1, and a reversely inclined surface is formed on the outer periphery, which is an end of the semiconductor light emitting device structure, to produce an LED chip. Other conditions are the same as those in the first embodiment.

(実施例3)
図4に示すように、凹部が部分的に外部に開口する形状の半導体発光素子構造を有するLEDチップを作製する。他の条件は、実施例1と同じとする。
(Example 3)
As shown in FIG. 4, an LED chip having a semiconductor light emitting element structure in which a concave portion partially opens to the outside is manufactured. Other conditions are the same as those in the first embodiment.

(実施例4)
実施例1において、積層構造を形成後に、各半導体発光素子構造部をマスクで覆い、基板面が露出するまでエッチングで除去して、ウェットエッチング法により、逆傾斜面を形成する。続いて、マスクを除去し、実施例1と同様にして、積層構造に凹部を形成し、n型半導体層及びp型半導体層の上に、それぞれn側電極及びp側電極を形成して、チップに割断してLEDチップを得る。このように、積層構造の端部に逆傾斜面を形成する工程(第2の側面を形成する工程)を、積層構造の加工(凹部を形成する工程)及びn側電極・p側電極を形成する工程よりも前に実施することで、ウェットエッチングによる侵食などの問題が発生せず、好ましい。
Example 4
In Example 1, after forming the laminated structure, each semiconductor light emitting element structure is covered with a mask, removed by etching until the substrate surface is exposed, and an inversely inclined surface is formed by wet etching. Subsequently, the mask was removed, and a concave portion was formed in the stacked structure in the same manner as in Example 1, and an n-side electrode and a p-side electrode were formed on the n-type semiconductor layer and the p-type semiconductor layer, respectively. The LED chip is obtained by cutting into chips. As described above, the step of forming the reverse inclined surface (the step of forming the second side surface) at the end of the laminated structure is the same as the processing of the laminated structure (the step of forming the recess) and the formation of the n-side electrode and the p-side electrode. It is preferable to carry out the process before the step, since problems such as erosion due to wet etching do not occur.

(比較例)
比較例として、図8に示すLEDチップを作製する。
基板301、n型半導体層302、発光層303、p型半導体層304、凹部320、n側電極305、p側全面電極306a及びp側パッド電極306bからなるp側電極6は、実施例3と同様であるが、凹部320を形成するエッチング工程において、n側電極305の形成部と、発光層303の外周部をマスクから露出させ、RIEによりn型半導体層が露出するまでエッチングする。その結果、発光層を含む積層構造の外周に、発光層に略垂直な側面307bが形成される。
その後、半導体発光素子構造の外周部を、RIEによって基板面が露出するまで除去することで発光層に略垂直な外周測面を形成し、凹部形成時に露出したn型半導体層の露出面より下の部分をウェットエッチングし、積層構造の下部の外周に逆傾斜面からなる側面307aを形成する。
(Comparative example)
As a comparative example, an LED chip shown in FIG. 8 is manufactured.
The p-side electrode 6 including the substrate 301, the n-type semiconductor layer 302, the light emitting layer 303, the p-type semiconductor layer 304, the recess 320, the n-side electrode 305, the p-side full surface electrode 306a, and the p-side pad electrode 306b is Similarly, in the etching process for forming the recess 320, the formation part of the n-side electrode 305 and the outer peripheral part of the light emitting layer 303 are exposed from the mask, and etching is performed until the n-type semiconductor layer is exposed by RIE. As a result, a side surface 307b substantially perpendicular to the light emitting layer is formed on the outer periphery of the stacked structure including the light emitting layer.
Thereafter, the outer peripheral portion of the semiconductor light emitting element structure is removed by RIE until the substrate surface is exposed, thereby forming an outer peripheral measurement surface substantially perpendicular to the light emitting layer, and below the exposed surface of the n-type semiconductor layer exposed when the recess is formed. This portion is wet-etched to form a side surface 307a having a reverse inclined surface on the outer periphery of the lower portion of the laminated structure.

実施例によるLEDは、発光層を含む積層構造の外周に逆傾斜した側面を形成したため、発光層から離れたn型半導体層の下方の側面307aにしか傾斜面が設けられていない比較例によるLEDに対して、光の取り出し効率が良好である。また、発光層の面積、引いては発光出力を増加させることができる。   Since the LED according to the example has a side surface that is reversely inclined on the outer periphery of the laminated structure including the light emitting layer, the LED according to the comparative example in which the inclined surface is provided only on the side surface 307a below the n-type semiconductor layer away from the light emitting layer. On the other hand, the light extraction efficiency is good. Further, the area of the light emitting layer, that is, the light emission output can be increased.

本発明の半導体発光素子は、各種照明器具、車両搭載用照明、ディスプレイ、インジケータ等の発光素子を用いるものに利用することができ、また、可視光だけでなく紫外光などの可視光域外の電磁波の素子にも応用でき、本発明の素子構造は、受光素子などの他の光素子にも応用することができる。更に、本発明の窒化物半導体の結晶面の構成以外に係るその他の本発明の構成、態様については、他の材料、例えば、AlGaAsなどのGaAs系半導体、AlInGaPなどのGaP系半導体、他の波長の光素子にも応用することができる。加えて、本発明の窒化物半導体の結晶面に係る構成及びその素子構造を、HEMTなどのパワー半導体、電子デバイス素子など、他の半導体素子などにも応用することができる。   The semiconductor light-emitting device of the present invention can be used for various lighting devices, vehicle-mounted lighting, displays, indicators, and other light-emitting devices, and not only visible light but also electromagnetic waves outside the visible light region such as ultraviolet light. The element structure of the present invention can also be applied to other optical elements such as a light receiving element. In addition to the configuration of the crystal surface of the nitride semiconductor of the present invention, other configurations and aspects of the present invention include other materials such as GaAs-based semiconductors such as AlGaAs, GaP-based semiconductors such as AlInGaP, and other wavelengths. It can be applied to other optical elements. In addition, the structure related to the crystal plane of the nitride semiconductor of the present invention and its element structure can be applied to other semiconductor elements such as power semiconductors such as HEMTs and electronic device elements.

実施の形態1に係るLEDの構成を示す模式図であり、(a)はLEDを電極配置面側からみた平面図、(b)は図1(a)のA−A線における断面図である。It is a schematic diagram which shows the structure of LED which concerns on Embodiment 1, (a) is the top view which looked at LED from the electrode arrangement surface side, (b) is sectional drawing in the AA line of Fig.1 (a). . 実施の形態1に係るLEDにおいて、光の外部取り出しの様子を説明するための図である。FIG. 5 is a diagram for explaining how light is extracted outside in the LED according to the first embodiment. 実施の形態に係るLEDの製造工程を説明する図であり、(a)は基板上に半導体の積層構造を形成する工程、(b)は凹部の底面を囲む第1の側面を形成する工程、(c)は半導体積層構造の外周を、基板面が露出するまでエッチングする工程、(d)はウェットエッチングによって第2の側面を形成する工程、(e)は基板を切断し、LED(半導体発光素子)チップに分割する工程、を説明するためのLEDの断面図である。It is a figure explaining the manufacturing process of LED which concerns on embodiment, (a) is the process of forming the laminated structure of a semiconductor on a board | substrate, (b) is the process of forming the 1st side surface surrounding the bottom face of a recessed part, (C) is a step of etching the outer periphery of the semiconductor multilayer structure until the substrate surface is exposed, (d) is a step of forming the second side surface by wet etching, (e) is a step of cutting the substrate, and LED (semiconductor light emission) It is sectional drawing of LED for demonstrating the process divided | segmented into an element | device chip | tip. 実施の形態2に係るLEDの構成を示す模式図であり、(a)はLEDを電極配置面側からみた平面図、(b)は、(a)のB−B線における断面図である。It is a schematic diagram which shows the structure of LED which concerns on Embodiment 2, (a) is the top view which looked at LED from the electrode arrangement surface side, (b) is sectional drawing in the BB line of (a). 実施の形態3に係るLEDの構成及び光の外部取り出しの様子を説明するた めの模式図であり、(a)はLEDを電極配置面側からみた平面図、(b)は、(a)のB−B線における断面図である。 Is a schematic diagram order to explain the manner of taking out the outside of the LED structure and the light pertaining to the third embodiment, (a) shows the plan view of the LED from the electrode arrangement surface, (b) is, (a) It is sectional drawing in the BB line. 実施の形態3に係るLEDの第2の側面の形状を説明するための斜視図であ る。 Ru perspective view der for explaining the shape of the second side of the LED according to the third embodiment. 実施の形態3に係るLEDを用いたLED装置の構成を示す模式図(断面図)である。It is a schematic diagram (sectional drawing) which shows the structure of the LED apparatus using LED which concerns on Embodiment 3. FIG. 比較例のLEDの構成を示す模式図であり、(a)はLEDを電極配置面側からみた平面図、(b)は、(a)のA−A線における断面図である。It is a schematic diagram which shows the structure of LED of a comparative example, (a) is the top view which looked at LED from the electrode arrangement | positioning surface side, (b) is sectional drawing in the AA of (a).

符号の説明Explanation of symbols

1 基板
1a 基板面(積層構造の下端面)
2 n型半導体層
3 発光層
4 p型半導体層
4a p型半導体層の上端面(積層構造の上端面)
5 n側電極
6 p側電極
6a p側全面電極
6b p側パッド電極
7 第2の側面(外周側面)
10 積層構造(半導体構造)
20 凹部(凹状に形成された部位)
20a 第1の側面
20b 底面
30 半導体発光素子構造
100 LED(半導体発光素子)
1 Substrate 1a Substrate surface (lower end surface of laminated structure)
2 n-type semiconductor layer 3 light emitting layer 4 p-type semiconductor layer 4a upper end surface of p-type semiconductor layer (upper end surface of laminated structure)
5 n-side electrode 6 p-side electrode 6a p-side full surface electrode 6b p-side pad electrode 7 second side surface (outer peripheral side surface)
10 Laminated structure (semiconductor structure)
20 Recessed part (part formed in a concave shape)
20a First side surface 20b Bottom surface 30 Semiconductor light emitting device structure 100 LED (semiconductor light emitting device)

Claims (3)

窒化ガリウム系化合物半導体からなるn型半導体層と、発光層と、p型半導体層とがこの順で積層してなる半導体構造を有する半導体発光素子構造を、サファイアからなりサファイア結晶のC面を基板面とする基板上に設けた半導体発光素子であって、
前記半導体構造は、上端面に開口部を有する前記n型半導体層が露出した凹部を有し、
上面視で、前記p型半導体層が前記凹部の全周を囲み、
前記半導体発光素子構造は、当該半導体発光素子構造の外周の全域に形成された側面を有し、
前記側面は、前記半導体構造の上端面と前記基板面に接する前記半導体構造の下端面とを接続し、前記上端面から前記下端面に向かって内側に傾斜する傾斜面として形成され、
凹凸形状を有し、当該凹凸形状を構成する凹部又は凸部の少なくとも一方が、前記半導体構造と前記基板との界面である前記窒化ガリウム系化合物半導体の(000−1)面(N極性面)からウェットエッチングされて形成された{1−102}面の多面体によって構成されたことを特徴とする半導体発光素子。
A semiconductor light emitting device structure having a semiconductor structure in which an n-type semiconductor layer made of a gallium nitride-based compound semiconductor , a light emitting layer, and a p-type semiconductor layer are laminated in this order, and a C surface of a sapphire crystal made of sapphire as a substrate A semiconductor light emitting device provided on a substrate as a surface,
The semiconductor structure has a recess in which the n-type semiconductor layer having an opening on an upper end surface is exposed,
In top view, the p-type semiconductor layer surrounds the entire circumference of the recess,
The semiconductor light emitting device structure has side surfaces formed over the entire periphery of the semiconductor light emitting device structure,
The side surface connects the upper end surface of the semiconductor structure and the lower end surface of the semiconductor structure in contact with the substrate surface, and is formed as an inclined surface inclined inward from the upper end surface toward the lower end surface,
The (000-1) plane (N-polar plane) of the gallium nitride compound semiconductor that has an irregular shape and at least one of the concave portion or the convex portion constituting the irregular shape is an interface between the semiconductor structure and the substrate A semiconductor light emitting device comprising a polyhedron having a {1-102} plane formed by wet etching.
窒化ガリウム系化合物半導体を積層してなる半導体構造を有する半導体発光素子構造を、サファイアからなりサファイア結晶のC面を基板面とする基板上に設けた請求項1に記載の半導体発光素子の製造方法であって、
前記基板のC面上に窒化ガリウム系化合物半導体からなるn型半導体層と、発光層と、p型半導体層とをこの順で積層した半導体構造を有する半導体発光素子構造を形成する工程と、
前記半導体発光素子構造の端部における前記半導体構造を、上面視で凹凸形状を有するように前記基板面に略垂直に除去して、前記基板面を露出する工程と、
前記基板面が露出した前記半導体発光素子構造の端部を、当該半導体構造と前記基板との界面である前記窒化ガリウム系化合物半導体の(000−1)面(N極性面)からウェットエッチングして、前記半導体構造の上端面から前記基板面に向かって内側に傾斜する側面を形成する工程と、
をこの順で含み、
さらに、前記半導体構造の一部を上端面側から除去して前記n型半導体層が露出する凹部を、上面視で、前記p型半導体層が前記凹部の全周を囲むように形成する工程前記内側に傾斜する側面を形成する工程より後に含むことを特徴とする半導体発光素子の製造方法。
2. The method of manufacturing a semiconductor light-emitting element according to claim 1, wherein the semiconductor light-emitting element structure having a semiconductor structure formed by stacking gallium nitride compound semiconductors is provided on a substrate made of sapphire and having a C-plane of the sapphire crystal as a substrate surface. Because
Forming a semiconductor light-emitting element structure having a semiconductor structure in which an n-type semiconductor layer made of a gallium nitride-based compound semiconductor , a light-emitting layer, and a p-type semiconductor layer are stacked in this order on the C-plane of the substrate;
Removing the semiconductor structure at an end of the semiconductor light emitting element structure substantially perpendicularly to the substrate surface so as to have a concavo-convex shape when viewed from above, and exposing the substrate surface;
The edge of the semiconductor light emitting device structure with the substrate surface exposed is wet etched from the (000-1) plane (N-polar plane) of the gallium nitride compound semiconductor, which is the interface between the semiconductor structure and the substrate. Forming a side surface inclined inward from the upper end surface of the semiconductor structure toward the substrate surface;
In this order ,
A step of removing a part of the semiconductor structure from the upper end surface side to form a recess in which the n-type semiconductor layer is exposed so that the p-type semiconductor layer surrounds the entire periphery of the recess in a top view; The manufacturing method of the semiconductor light-emitting device characterized by including after the process of forming the side surface inclined inside .
前記半導体構造を形成する工程において、有機金属化学気相成長法(MOCVD法)によって前記半導体構造を形成することを特徴とする請求項に記載の半導体発光素子の製造方法。 3. The method of manufacturing a semiconductor light emitting device according to claim 2 , wherein in the step of forming the semiconductor structure, the semiconductor structure is formed by metal organic chemical vapor deposition (MOCVD).
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